OpenCores
URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sgmii
    from Rev 22 to Rev 23
    ↔ Reverse comparison
  •

Rev 22 → Rev 23

/trunk/src/mTransmit.v
102,7 → 102,7
.i_Clk(i_Clk),
.i_ARst_L(i_ARst_L));
//END FIFO
assign w_FifoRd = ((w_FifoTxEn && (r13_State==stXMIT_DATA||r13_State==stTX_IDLE)))?1'b0:1'b1;
assign w_FifoRd = ((w_FifoTxEn && (r13_State==stXMIT_DATA||r13_State==stIDLE_DATA)))?1'b0:1'b1;
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
/trunk/src/mSGMII.v
63,6 → 63,8
output o_SGMIIDuplex,
//GMII Interface
output o_TxClk,
output o_RxClk,
input [07:00] i8_TxD,
input i_TxEN,
input i_TxER,
74,6 → 76,7
output o_Col,
output o_Crs);
wire w_ClkTx,w_ClkRx;
wire w_ClkSys;
wire w_Loopback;
reg r_RestartAN;
140,6 → 143,8
assign o_Linkup = w_SyncStatus;
assign o_ANDone = w_ANComplete;
assign o_TxClk = w_ClkTx;
assign o_RxClk = w_ClkRx;
mRateAdapter u0RateAdapter(
//MAC Side signal
186,7 → 191,7
assign w_CheckEndRRK = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];
assign w_CheckEndRRS = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsSSet[0];
always@(posedge w_ClkSys)
always@(posedge w_ClkRx)
begin
r8_RxCodeGroup[0] <= w8_RxCode;
r_RxCgCtrl[0] <= w_RxCodeCtrl;
242,7 → 247,7
.i16_LpAdvAbility (w16_LpAdvAbility));
mSyncCtrl u0SyncCtrl(
.i_Clk (w_ClkSys ),
.i_Clk (w_ClkRx ),
.i_Cke ((~w_GxBPowerDown) ),
.i_ARst_L (w_ARstLogic_L ),
.i_CtrlLoopBack (w_Loopback ),
269,7 → 274,7
.o_IsSSet (w_IsSSet ),
.o_IsRSet (w_IsRSet ));
always@(posedge w_ClkSys)
always@(posedge w_ClkRx)
begin
r_CheckEndKDK <= w_CheckEndKDK;
r_CheckEndKD21_5D0_0 <= w_CheckEndKD21_5D0_0;
319,11 → 324,11
.o8_RxD (w8_RxD ),
.o_Invalid (w_Invalid),
.o_Receiving (w_Receiving),
.i_Clk (w_ClkSys),
.i_Clk (w_ClkRx),
.i_ARst_L (w_ARstLogic_L));
mANCtrl u0ANCtrl(
.i_Clk (w_ClkSys ),
.i_Clk (w_ClkRx ),
.i_ARst_L (w_ARstLogic_L ),
.i_Cke ((~w_GxBPowerDown) ),
.i_RestartAN (w_ANRestart ),
356,7 → 361,7
.o_TxCodeCtrl (w_TxCodeCtrl ),
.i_CurrentParity (w_CurrentParity ),
.i_Clk (w_ClkSys ),
.i_Clk (w_ClkTx ),
.i_ARst_L (w_ARstLogic_L ));
assign w_SignalDetect=~w_RxCodeInvalid;
384,12 → 389,14
.i_TxForceNegDisp (w_TxForceNegDisp ),
.o_RunningDisparity (w_CurrentParity));*/
mAltA5GXlvds u0Xcverlvds(
.i_SerRx (i_SerRx ),
.o_SerTx (o_SerTx ),
.i_RefClk125M (i_RefClk125M ),
.o_CoreClk (w_ClkSys ),
.o_TxClk (w_ClkTx ),
.o_RxClk (w_ClkRx ),
.i_GxBPwrDwn (w_GxBPowerDown ),
.i_XcverDigitalRst (~i_ARstHardware_L ),
.o_PllLocked (w_PllLocked ),
406,6 → 413,7
.i_TxForceNegDisp (1'b0 ),
.o_RunningDisparity (w_CurrentParity));
assign w_ClkSys = w_ClkTx;
assign o_GMIIClk = w_ClkSys;
always@(posedge w_ClkSys or negedge i_ARstHardware_L )
/trunk/src/mAltGX/mAltA5GXlvds.v
5,7 → 5,8
output o_SerTx,
input i_RefClk125M,
output o_CoreClk,
output o_RxClk,
output o_TxClk,
input i_GxBPwrDwn,
input i_XcverDigitalRst,
output o_PllLocked,
39,7 → 40,7
.o10_Dout (w10_txdata), //abcdeifghj
.o_Rd (o_RunningDisparity),
.o_KErr (),
.i_Clk (w_RxClk),
.i_Clk (w_TxClk),
.i_ARst_L (~i_XcverDigitalRst));
mDec8b10bMem u8b10bDec(
91,7 → 92,7
.tx_out (o_SerTx));
mAltLvdsPll uAltTxPll(
.refclk (w_RxClk), // refclk.clk
.refclk (i_RefClk125M), // refclk.clk
.rst (w_PorRst), // reset.reset
.outclk_0 (w_TxSerClk), // outclk0.clk
.outclk_1 (w_TxEnClk), // outclk1.clk
99,10 → 100,12
.locked (w_TxLocked) // locked.export
);
reg [9:0] r10_txdata0;
always@(posedge w_TxClk)
r10_txdata <= w10_txdata;
r10_txdata <= w10_txdata;
assign o_CoreClk = w_RxClk;
assign o_RxClk = w_RxClk;
assign o_TxClk = w_TxClk;
reg [7:0] r8_PorTmr;
assign w_PorRst = ~(&r8_PorTmr);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.