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/trunk/build/mMdioMstr.v
0,0 → 1,132
/*
Copyright � 2012 JeffLieu-lieumychuong@gmail.com
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
File :
Description :
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
 
module mMdioMstr(
input i_Clk,
input i_ARst_L,
//Wishbone interface
input i_Cyc,i_Stb,i_WEn,
output reg o_Ack,
input [1:0] i2_Addr,
input [31:0] i32_WrData,
output reg [31:0] o32_RdData,
//MDIO Interface
output o_Mdc,
inout io_Mdio);
reg [15:0] r16_WrData;
reg [15:0] r16_RdData;
reg [15:0] r16_Cmd;
reg [4:0] r5_BitCnt;
reg [3:0] rv_ClkDiv;
reg r_Mdc;
reg r_Mdo;
reg r_Frame;
wire w_NewCmd;
reg r_NewCmd;
wire w_ReadFrame;
//Bus Interface
always@(posedge i_Clk or negedge i_ARst_L)
if(~i_ARst_L) begin
r16_Cmd <= 16'h0;
r16_WrData <= 16'h0;
r_NewCmd <= 1'b0;
end else begin
if(i_Cyc & i_Stb & i_WEn)
case(i2_Addr)
2'b00: r16_Cmd <= i32_WrData[15:0];
2'b01: r16_WrData <= i32_WrData[15:0];
endcase
case(i2_Addr)
2'b00: o32_RdData <= {16'h0,r16_Cmd};
2'b01: o32_RdData <= {16'h0,r16_WrData};
2'b10: o32_RdData <= {16'h0,r16_RdData};
2'b11: o32_RdData <= {16'h0,r16_RdData};
endcase
o_Ack <= (~o_Ack) & i_Cyc & i_Stb;
if(r_Frame)//Reset
r_NewCmd <= 1'b0;
else if(w_NewCmd) //Set
r_NewCmd <= 1'b1;
end
assign w_NewCmd = i_Cyc & i_Stb & i_WEn & o_Ack & (i2_Addr==2'b00);
assign w_ReadFrame = (r16_Cmd[13:12]==2'b10)?1'b1:1'b0;
assign o_Mdc = r_Mdc?1'bz:1'b0; //OpenDrain
assign io_Mdio = (r_Mdo|(~r_Frame))?1'bz:1'b0;
always@(posedge i_Clk or negedge i_ARst_L)
if(~i_ARst_L)
begin
rv_ClkDiv <= 4'b0;
r_Mdc<=1'b0;
end
else begin
rv_ClkDiv <= rv_ClkDiv+4'b1;
if(&rv_ClkDiv) r_Mdc<=~r_Mdc;
end
always@(posedge i_Clk or negedge i_ARst_L)
if(~i_ARst_L)
begin
r_Frame <= 1'b0;
r5_BitCnt <= 5'b11111;
r_Mdo <= 1'b1;
r16_RdData <= 16'h0;
end
else
begin
if((&rv_ClkDiv) && ~r_Mdc)
begin //At the rising edge of MDC clock
if(r_NewCmd) //If New Command Available Start Frame Half a clock earlier by
r_Frame<=1'b1;
else
if(~(|r5_BitCnt))
r_Frame<=1'b0;
end
if(~r_Frame) r_Mdo <= 1'b1;
else
if(r_Frame && (&rv_ClkDiv) && r_Mdc) //AT the Falling edge and
begin
r_Mdo <= r5_BitCnt[4]?r16_Cmd[r5_BitCnt[3:0]]:(w_ReadFrame?1'b1:r16_WrData[r5_BitCnt[3:0]]);
end
if(~r_Frame) //Load Bit Count
r5_BitCnt <= 5'b11111;
else if(r_Frame && (&rv_ClkDiv) && ~r_Mdc) //At the rising edge count down
r5_BitCnt<=r5_BitCnt-5'b1;
if((r_Frame && (&rv_ClkDiv) && ~r_Mdc))
r16_RdData[r5_BitCnt[3:0]]<=io_Mdio;
end
 
endmodule
/trunk/build/mPacketGenerator.sv
0,0 → 1,279
module pkt_gen32 (
clk,
rst,
 
control,
status,
config_1,
config_2,
i32_Payload1,
i32_Payload2,
i32_Payload3,
i32_Payload4,
 
pkt_rdy,
pkt_dv,
pkt_sop,
pkt_eop,
pkt_data,
pkt_BE,
pkt_rd,
pkt_len_rdy,
pkt_len,
pkt_len_rd);
 
input clk;
input rst;
input [15:00] control;
output reg [31:00] status;
input [31:00] config_1;
input [31:00] config_2;
input [31:00] i32_Payload1;
input [31:00] i32_Payload2;
input [31:00] i32_Payload3;
input [31:00] i32_Payload4;
 
output pkt_rdy;
output pkt_dv;
output pkt_sop;
output pkt_eop;
output [31:00] pkt_data;
input pkt_rd;
output [1:0] pkt_BE;
 
input pkt_len_rd;
output pkt_len_rdy;
output [15:00] pkt_len;
 
typedef enum {IDLE, RDY, END, WAIT} state_type;
 
parameter MAC_SRC = 48'h00_1F_02_03_AA_BB;
parameter MAC_DST = 48'h00_27_0E_1A_46_03;
parameter IP_SRC = 32'hC0_A8_00_01;
parameter IP_DST = 32'hC0_A8_01_B0;
 
reg [15:0] polynomial[16];
 
state_type st;
wire enable;
wire sw_rst;
wire [31:0] src_ip;
wire [31:0] dst_ip;
reg [31:00] mux_data;
reg [31:00] random_data;
reg [15:00] word_cnt;
reg [15:00] byte_cnt;
reg [31:00] timer;
reg [15:00] i_pkt_length;
reg [15:00] ip_rand;
 
wire [31:00] shift_random_data;
 
wire sop;
wire eop;
wire dv;
wire time_exp;
 
reg pkt_rd_d;
reg one_sec_clk;
reg [31:00] one_sec_tmr;
localparam ONE_SEC_CYCLES = 124_999_999;
reg [31:00] datarate;
reg tmr_en;
 
assign enable = control[0];
assign sw_rst = control[1];
 
always@(posedge clk or posedge rst)
begin
if(rst) begin
one_sec_tmr <= 0;
one_sec_clk <= 0;
datarate <= 0;
end
else begin
if(one_sec_tmr==ONE_SEC_CYCLES) begin
one_sec_tmr <= 0;
one_sec_clk <= 1'b1;
end
else
begin
one_sec_tmr <= one_sec_tmr+1;
one_sec_clk <= 1'b0;
end
if(one_sec_clk) begin
datarate <= 0;
status <= datarate; end
else if(dv)
datarate <= datarate+1;
end
end
 
always@(posedge clk or posedge rst)
if(rst)
st <= IDLE;
else
begin
if((sw_rst) || (~enable))
st<= IDLE;
else
case(st)
IDLE: st <= RDY;
RDY : if(eop) st<= END;
END : st <= WAIT;
WAIT: if(time_exp) st <= IDLE;
endcase
end
assign pkt_rdy = (st==RDY);
assign pkt_len_rdy = enable;
assign pkt_len = i_pkt_length;
assign eop = (byte_cnt<=4 && byte_cnt>0 && dv ==1'b1);
assign sop = (byte_cnt == i_pkt_length && dv == 1'b1);
assign pkt_eop = eop;
assign pkt_dv = dv;
assign pkt_sop = sop;
assign dv = pkt_rd_d && (st==RDY);
assign pkt_BE = byte_cnt[1:0];
always@(posedge clk)
begin
if(st==IDLE||st==END) begin
word_cnt <= 0;
byte_cnt <= config_1[15:0];
i_pkt_length <= config_1[15:0];
end
else
if(dv) begin
word_cnt <= word_cnt+1;
if(byte_cnt>4)
byte_cnt <= byte_cnt-4;
else
byte_cnt <= 0;
end
if(st==IDLE)
tmr_en <= 1'b0;
else if(sop)
tmr_en <= 1'b1;
if(st==IDLE)
timer <= config_2;
else if(tmr_en && (timer!=0)) timer <= timer - 1;
if(st==RDY)
pkt_rd_d <= pkt_rd; else
pkt_rd_d <= 1'b0;
end
/*always@(*)
begin
case(word_cnt)
0: mux_data <= MAC_DST[47:16];
1: mux_data <= {MAC_DST[15:00], MAC_SRC[47:32]};
2: mux_data <= MAC_SRC[31:00];
3: mux_data <= {config_1[15:0],16'h0000};//{16'h0800,16'h0000};
4: mux_data <= 32'h00;//{config_1[15:0],16'h0000};
5: mux_data <= {16'h0000,16'h0000};
6: mux_data <= {16'h0000,src_ip[31:16]};
7: mux_data <= {src_ip[15:0],IP_DST[31:16]};
8: mux_data <= {IP_DST[15:0],16'h0000};
default: mux_data <= {byte_cnt,byte_cnt};//random_data;
endcase
end*/
always@(*)
begin
case(word_cnt)
0: mux_data <= MAC_DST[47:16];
1: mux_data <= {MAC_DST[15:00], MAC_SRC[47:32]};
2: mux_data <= MAC_SRC[31:00];
3: mux_data <= {(config_1[15:0]-16'd14),16'h0000};//{16'h0800,16'h0000};
4: mux_data <= i32_Payload1;
5: mux_data <= i32_Payload2;
6: mux_data <= i32_Payload3;
7: mux_data <= i32_Payload4;
default: mux_data <= {32'h0102_0304};//random_data;
endcase
end
assign time_exp = (timer==0);
assign pkt_data = mux_data;
//random data generation
assign shift_random_data = {random_data[30:0],^(random_data&32'h1034_BCFE)};
always@(posedge clk)
begin
if(word_cnt==3 && dv==1'b1)
random_data <= MAC_DST[31:00];
else
if(dv) begin
random_data <= random_data[31]?shift_random_data:(~shift_random_data);
end
end
always@(posedge clk or posedge rst)
begin
if(rst) begin
ip_rand <= 16'h1;
//For this polynomial, look for maxim-ic.com/app-notes/index.mvp/id/1743
polynomial[00] = 16'h0;
polynomial[01] = 16'h0;
polynomial[02] = 16'h0005;
polynomial[03] = 16'h0009;
polynomial[04] = 16'h0012;
polynomial[05] = 16'h0021;
polynomial[06] = 16'h0041;
polynomial[07] = 16'h008E;
polynomial[08] = 16'h0108;
polynomial[09] = 16'h0204;
polynomial[10] = 16'h0402;
polynomial[11] = 16'h0829;
polynomial[12] = 16'h100D;
polynomial[13] = 16'h2015;
polynomial[14] = 16'h4001;
polynomial[15] = 16'h8016;
end
else
begin
if(eop & dv) begin
ip_rand = {ip_rand[15:0],^(ip_rand&(polynomial[config_1[19:16]]))};
ip_rand[(config_1[19:16]+1)] = 1'b0;
//synthesis_off
$display("IPRAND = %d",ip_rand);
//synthesis_on
end
end
end
assign src_ip = {IP_SRC[31:16],ip_rand};
//synthesis_off
/*
always@(posedge clk or posedge rst)
begin
integer found[];
integer i;
integer cnt;
if(rst) begin
cnt = 0;
for(i=0;i<5000;i++)
begin
found[i]=0;
end
end
else
begin
if(sop & dv) begin
if(found[ip_rand]==0) begin
cnt++;
found[ip_rand]=1;
$display("Total Streams %d",cnt);
end
end
end
end*/
//synthesis_on
 
endmodule
/trunk/build/mWishboneMaster88E1111.v
0,0 → 1,191
/*
Copyright © 2012 JeffLieu-lieumychuong@gmail.com
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
 
File : sgmii_demo.v
Description : This file implements top-level file to test SGMII core
 
Remarks :
 
Revision :
Date Author Description
 
*/
`define CMD_NOP 3'b000
`define CMD_RD 3'b001
`define CMD_WR 3'b010
`define CMD_WT 3'b011
`define CMD_JMP 3'b100
`define CMD_JEQ 3'b101
`define CMD_END 3'b111
`define MDIO_RD 2'b10
`define MDIO_WR 2'b01
`define MDIO_RD_FRAME(RDWR,PHYADDR,REGADDR) {16'h0,2'b01,RDWR,PHYADDR,REGADDR,2'b11}
`define MDIO_WR_FRAME(RDWR,PHYADDR,REGADDR) {16'h0,2'b01,RDWR,PHYADDR,REGADDR,2'b10}
`define MDIO_RD_REG27 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd27)}
`define MDIO_RD_REG17 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd17)}
`define MDIO_RD_REG00 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_RD,5'b0,5'd0)}
`define MDIO_RD_REG01 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd01)}
`define MDIO_RD_REG04 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd04)}
`define MDIO_RD_REG22 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_RD_FRAME(`MDIO_RD,5'b0,5'd22)}
`define MDIO_WR_REG27 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_WR,5'b0,5'd27)}
`define MDIO_WR_REG00 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_WR,5'b0,5'd0)}
`define MDIO_WR_REG22 {2'b10,8'hFF,`CMD_WR ,8'h00 ,`MDIO_WR_FRAME(`MDIO_WR,5'b0,5'd22)}
 
 
module mWishboneMaster88E1111#(parameter pCommands=32,pAddrW=8,pChipSelect=2)
(
output [pChipSelect-1:0] ov_CSel,
output o_Cyc,
output o_Stb,
output o_WEn,
output [31:0] o32_WrData,
input [31:0] i32_RdData,
output [pAddrW-1:0] ov_Addr,
input i_Ack,
input i_ARst_L,
input i_Clk);
localparam pInstrWidth = pAddrW+32+3+8+pChipSelect;
localparam pFETCH = 4'b0001,
pEXECU = 4'b0010,
pNEXTI = 4'b0100,
pWAIT = 4'b1000;
reg [3:0] r4_State;
reg [pInstrWidth-1:0] rv_InstrReg;
reg [pInstrWidth-1:0] rv_MicroCodes[0:pCommands-1];
reg [31:0] r32_ReadData;
reg [7:0] r8_InstrCnt;
reg [31:0] r32_WaitTmr;
wire [2:0] w3_Opcode;
wire [7:0] w8_WaitTime;
/*Instruction Format
y-bit chipslect, 8-bit WaitTime, 3bit-Opcode, x-bit Address, 32-bit Data
*/
assign ov_CSel = rv_InstrReg[pInstrWidth-1-:pChipSelect];
assign w8_WaitTime = rv_InstrReg[pInstrWidth-1-pChipSelect-:8];
assign w3_Opcode = rv_InstrReg[pInstrWidth-1-pChipSelect-8-:3];
assign ov_Addr = rv_InstrReg[pInstrWidth-1-pChipSelect-8-3-:pAddrW];
assign o32_WrData = rv_InstrReg[31:0];
always@(posedge i_Clk or negedge i_ARst_L)
if(!i_ARst_L) begin
r8_InstrCnt <= 8'h0;
r4_State <= pFETCH;
r32_WaitTmr <= 32'h0;
end
else begin
case(r4_State)
pFETCH : begin
rv_InstrReg <= rv_MicroCodes[r8_InstrCnt];
r4_State <= pEXECU;
end
pEXECU : begin
if(w3_Opcode==`CMD_WT)
begin
r4_State<=pWAIT;
r32_WaitTmr <= o32_WrData[31:0];
end
else if(w3_Opcode==`CMD_RD||w3_Opcode==`CMD_WR) begin
if(i_Ack)
begin
r4_State<=pWAIT;
r32_WaitTmr <= {24'h0,w8_WaitTime};
if(w3_Opcode==`CMD_RD) r32_ReadData <= i32_RdData;
end
end
else begin
r4_State<=pWAIT;
r32_WaitTmr <= {24'h0,w8_WaitTime};
end
end
pNEXTI : begin
if(w3_Opcode==`CMD_JMP)
r8_InstrCnt <= ov_Addr;
else
if(w3_Opcode==`CMD_JEQ) begin
if(r32_ReadData==o32_WrData)
r8_InstrCnt <= ov_Addr;
else
r8_InstrCnt <= r8_InstrCnt+8'h1;
end
else
r8_InstrCnt <= r8_InstrCnt+8'h1;
r4_State <= pFETCH;
end
pWAIT : if(w3_Opcode==`CMD_END)
r4_State <= pWAIT;
else
if(r32_WaitTmr==0) r4_State <= pNEXTI; else r32_WaitTmr<=r32_WaitTmr-16'h1;
endcase
end
assign o_Cyc = (r4_State==pEXECU)?1'b1:1'b0;
assign o_Stb = (r4_State==pEXECU)?1'b1:1'b0;
assign o_WEn = (r4_State==pEXECU&&w3_Opcode==`CMD_WR)?1'b1:1'b0;
 
always@(posedge i_Clk)
begin
rv_MicroCodes[0] <={2'b01,8'h4,`CMD_RD ,8'h28 ,32'h0 };
rv_MicroCodes[1] <={2'b01,8'h4,`CMD_WR ,8'h20 ,32'hFFFF };//Set link timer to 1.6ms
rv_MicroCodes[2] <={2'b01,8'h4,`CMD_WR ,8'h24 ,32'h001F };//
rv_MicroCodes[3] <={2'b01,8'h4,`CMD_WR ,8'h7C ,32'h0001 };//Enable SGMII Mode, MAC Side
rv_MicroCodes[4] <={2'b01,8'h4,`CMD_WR ,8'h00 ,32'h1340 };//Restart
rv_MicroCodes[5] <=`MDIO_RD_REG27;
rv_MicroCodes[6] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
rv_MicroCodes[7] <={2'b10,8'h4,`CMD_RD ,8'h02 ,32'h1340 };//Read MDIO Registers
rv_MicroCodes[8] <={2'b10,8'h4,`CMD_WR ,8'h01 ,{r32_ReadData[31:4],4'h4}};//Write to Register 27 to change mode
rv_MicroCodes[9] <=`MDIO_WR_REG27;
rv_MicroCodes[10] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
 
rv_MicroCodes[11] <=`MDIO_RD_REG22;
rv_MicroCodes[12] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
rv_MicroCodes[13] <={2'b10,8'h4,`CMD_RD ,8'h02 ,32'h1340 };//Read MDIO Registers
rv_MicroCodes[14] <={2'b10,8'h4,`CMD_WR ,8'h01 ,{r32_ReadData[31:8],8'h01} };//Switch Page
rv_MicroCodes[15] <=`MDIO_WR_REG22;
rv_MicroCodes[16] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
rv_MicroCodes[17] <={2'b10,8'h4,`CMD_WR ,8'h01 ,32'h0000_9000 };//Soft Reset, Disable Auto Negotiation
rv_MicroCodes[18] <=`MDIO_WR_REG00;
rv_MicroCodes[19] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd125_000_000};
rv_MicroCodes[20] <=`MDIO_RD_REG04;
rv_MicroCodes[21] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
rv_MicroCodes[22] <=`MDIO_RD_REG00;
rv_MicroCodes[23] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048 };
rv_MicroCodes[24] <=`MDIO_RD_REG01;
rv_MicroCodes[25] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048};
rv_MicroCodes[26] <=`MDIO_RD_REG17;
rv_MicroCodes[27] <={2'b00,8'hFF,`CMD_WT ,8'h00 ,32'd2048};
rv_MicroCodes[28] <={2'b00,8'hFF,`CMD_JMP ,8'd20 ,32'b0 };
end
endmodule
/trunk/build/mPshBtnDbnce.v
0,0 → 1,52
/*
Copyright © 2012 JeffLieu-lieumychuong@gmail.com
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
 
File : sgmii_demo.v
Description : This file implements top-level file to test SGMII core
 
Remarks :
 
Revision :
Date Author Description
 
*/
 
module mPshBtnDbnce #(parameter pDbncePeriod=8191,pDbncerWidth=13)(
input i_Clk,
input i_PshBtn,
output reg o_Dbnced);
 
reg r_PshBtnIn_D1;
reg r_PshBtnIn_D2;
reg r_PshBtnIn_D3;
reg [pDbncerWidth-1:0] rv_Dbncer;
always@(posedge i_Clk)
begin
r_PshBtnIn_D1 <= i_PshBtn;
r_PshBtnIn_D2 <= r_PshBtnIn_D1;
r_PshBtnIn_D3 <= r_PshBtnIn_D2;
if(r_PshBtnIn_D3^r_PshBtnIn_D2) rv_Dbncer <= pDbncePeriod;
else begin
if(~(|rv_Dbncer)) rv_Dbncer<=rv_Dbncer-1;
else o_Dbnced <= r_PshBtnIn_D3;
end
end
endmodule
 

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