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URL https://opencores.org/ocsvn/sha256_hash_core/sha256_hash_core/trunk

Subversion Repositories sha256_hash_core

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  • This comparison shows the changes necessary to convert path 
    /sha256_hash_core
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/trunk/doc/src/GV_SHA256_core.png Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/GV_SHA256_core.png
trunk/doc/src/GV_SHA256_core.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/syn/sha256/isim.log =================================================================== --- trunk/syn/sha256/isim.log (nonexistent) +++ trunk/syn/sha256/isim.log (revision 8) @@ -0,0 +1,20 @@ +ISim log file +Running: Z:\Dropbox\develop\fpga\sha256_hash_core\sha256_hash_core\trunk\syn\sha256\testbench_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/testbench_isim_beh.wdb +ISim P.20131013 (signature 0x7708f090) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +Time resolution is 1 ps +# onerror resume +# wave add / +# run all +Simulator is doing circuit initialization process. +at 0 ps, Instance /testbench/Inst_sha_256_dut/Inst_sha256_kt_rom/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 +Finished circuit initialization process. + +** Failure:End Simulation +User(VHDL) Code Called Simulation Stop +In process sha256_test.vhd:tb1 + +INFO: Simulator is stopped. Index: trunk/syn/sha256/gv_sha256_summary.html =================================================================== --- trunk/syn/sha256/gv_sha256_summary.html (revision 7) +++ trunk/syn/sha256/gv_sha256_summary.html (revision 8) @@ -72,8 +72,9 @@  
+
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri Jul 22 12:10:37 2016
-
Date Generated: 07/20/2016 - 02:07:46
+
Date Generated: 07/22/2016 - 12:10:43
\ No newline at end of file
/trunk/syn/sha256/sha256_Ki_rom.vhd
55,14 → 55,14
 
entity sha256_ki_rom is
port (
K0_o : out std_logic_vector (31 downto 0) := (others => 'X');
K1_o : out std_logic_vector (31 downto 0) := (others => 'X');
K2_o : out std_logic_vector (31 downto 0) := (others => 'X');
K3_o : out std_logic_vector (31 downto 0) := (others => 'X');
K4_o : out std_logic_vector (31 downto 0) := (others => 'X');
K5_o : out std_logic_vector (31 downto 0) := (others => 'X');
K6_o : out std_logic_vector (31 downto 0) := (others => 'X');
K7_o : out std_logic_vector (31 downto 0) := (others => 'X')
K0_o : out std_logic_vector (31 downto 0) := (others => 'U');
K1_o : out std_logic_vector (31 downto 0) := (others => 'U');
K2_o : out std_logic_vector (31 downto 0) := (others => 'U');
K3_o : out std_logic_vector (31 downto 0) := (others => 'U');
K4_o : out std_logic_vector (31 downto 0) := (others => 'U');
K5_o : out std_logic_vector (31 downto 0) := (others => 'U');
K6_o : out std_logic_vector (31 downto 0) := (others => 'U');
K7_o : out std_logic_vector (31 downto 0) := (others => 'U')
);
end sha256_ki_rom;
 
/trunk/syn/sha256/iseconfig/sha256.projectmgr
52,7 → 52,7
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000300000000010001000100000000000000000000000064ffffffff000000810000000000000001000003000000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000009a000000010001000100000000000000000000000064ffffffff0000008100000000000000010000009a0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
67,7 → 67,7
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000bc000000010000000100000000000000000000000064ffffffff000000810000000000000001000000bc0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000064000000010000000100000000000000000000000064ffffffff000000810000000000000001000000640000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Programming File</CurrentItem>
</ItemView>
110,7 → 110,7
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000300000000010000000100000000000000000000000064ffffffff000000810000000000000001000003000000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000039c000000010000000100000000000000000000000064ffffffff0000008100000000000000010000039c0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
/trunk/syn/sha256/iseconfig/gv_sha256.xreport
1,7 → 1,7
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2016-07-20T02:07:46</DateModified>
<DateModified>2016-07-22T12:10:44</DateModified>
<ModuleName>gv_sha256</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/iseconfig/gv_sha256.xreport</SavedFilePath>
/trunk/syn/sha256/sha256_regs.vhd
54,41 → 54,41
 
entity sha256_regs is
port (
clk_i : in std_logic := 'X'; -- system clock
ce_i : in std_logic := 'X'; -- clock enable from control logic
ld_i : in std_logic := 'X'; -- internal mux selection from control logic
A_i : in std_logic_vector (31 downto 0) := (others => 'X');
B_i : in std_logic_vector (31 downto 0) := (others => 'X');
C_i : in std_logic_vector (31 downto 0) := (others => 'X');
D_i : in std_logic_vector (31 downto 0) := (others => 'X');
E_i : in std_logic_vector (31 downto 0) := (others => 'X');
F_i : in std_logic_vector (31 downto 0) := (others => 'X');
G_i : in std_logic_vector (31 downto 0) := (others => 'X');
H_i : in std_logic_vector (31 downto 0) := (others => 'X');
K0_i : in std_logic_vector (31 downto 0) := (others => 'X');
K1_i : in std_logic_vector (31 downto 0) := (others => 'X');
K2_i : in std_logic_vector (31 downto 0) := (others => 'X');
K3_i : in std_logic_vector (31 downto 0) := (others => 'X');
K4_i : in std_logic_vector (31 downto 0) := (others => 'X');
K5_i : in std_logic_vector (31 downto 0) := (others => 'X');
K6_i : in std_logic_vector (31 downto 0) := (others => 'X');
K7_i : in std_logic_vector (31 downto 0) := (others => 'X');
N0_o : out std_logic_vector (31 downto 0) := (others => 'X');
N1_o : out std_logic_vector (31 downto 0) := (others => 'X');
N2_o : out std_logic_vector (31 downto 0) := (others => 'X');
N3_o : out std_logic_vector (31 downto 0) := (others => 'X');
N4_o : out std_logic_vector (31 downto 0) := (others => 'X');
N5_o : out std_logic_vector (31 downto 0) := (others => 'X');
N6_o : out std_logic_vector (31 downto 0) := (others => 'X');
N7_o : out std_logic_vector (31 downto 0) := (others => 'X');
H0_o : out std_logic_vector (31 downto 0) := (others => 'X');
H1_o : out std_logic_vector (31 downto 0) := (others => 'X');
H2_o : out std_logic_vector (31 downto 0) := (others => 'X');
H3_o : out std_logic_vector (31 downto 0) := (others => 'X');
H4_o : out std_logic_vector (31 downto 0) := (others => 'X');
H5_o : out std_logic_vector (31 downto 0) := (others => 'X');
H6_o : out std_logic_vector (31 downto 0) := (others => 'X');
H7_o : out std_logic_vector (31 downto 0) := (others => 'X')
clk_i : in std_logic := 'U'; -- system clock
ce_i : in std_logic := 'U'; -- clock enable from control logic
ld_i : in std_logic := 'U'; -- internal mux selection from control logic
A_i : in std_logic_vector (31 downto 0) := (others => 'U');
B_i : in std_logic_vector (31 downto 0) := (others => 'U');
C_i : in std_logic_vector (31 downto 0) := (others => 'U');
D_i : in std_logic_vector (31 downto 0) := (others => 'U');
E_i : in std_logic_vector (31 downto 0) := (others => 'U');
F_i : in std_logic_vector (31 downto 0) := (others => 'U');
G_i : in std_logic_vector (31 downto 0) := (others => 'U');
H_i : in std_logic_vector (31 downto 0) := (others => 'U');
K0_i : in std_logic_vector (31 downto 0) := (others => 'U');
K1_i : in std_logic_vector (31 downto 0) := (others => 'U');
K2_i : in std_logic_vector (31 downto 0) := (others => 'U');
K3_i : in std_logic_vector (31 downto 0) := (others => 'U');
K4_i : in std_logic_vector (31 downto 0) := (others => 'U');
K5_i : in std_logic_vector (31 downto 0) := (others => 'U');
K6_i : in std_logic_vector (31 downto 0) := (others => 'U');
K7_i : in std_logic_vector (31 downto 0) := (others => 'U');
N0_o : out std_logic_vector (31 downto 0) := (others => 'U');
N1_o : out std_logic_vector (31 downto 0) := (others => 'U');
N2_o : out std_logic_vector (31 downto 0) := (others => 'U');
N3_o : out std_logic_vector (31 downto 0) := (others => 'U');
N4_o : out std_logic_vector (31 downto 0) := (others => 'U');
N5_o : out std_logic_vector (31 downto 0) := (others => 'U');
N6_o : out std_logic_vector (31 downto 0) := (others => 'U');
N7_o : out std_logic_vector (31 downto 0) := (others => 'U');
H0_o : out std_logic_vector (31 downto 0) := (others => 'U');
H1_o : out std_logic_vector (31 downto 0) := (others => 'U');
H2_o : out std_logic_vector (31 downto 0) := (others => 'U');
H3_o : out std_logic_vector (31 downto 0) := (others => 'U');
H4_o : out std_logic_vector (31 downto 0) := (others => 'U');
H5_o : out std_logic_vector (31 downto 0) := (others => 'U');
H6_o : out std_logic_vector (31 downto 0) := (others => 'U');
H7_o : out std_logic_vector (31 downto 0) := (others => 'U')
);
end sha256_regs;
 
103,23 → 103,23
signal reg_H6 : unsigned (31 downto 0) := (others => '0');
signal reg_H7 : unsigned (31 downto 0) := (others => '0');
-- word shifter wires
signal next_reg_H0 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H1 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H2 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H3 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H4 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H5 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H6 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H7 : unsigned (31 downto 0) := (others => '0');
signal next_reg_H0 : unsigned (31 downto 0);
signal next_reg_H1 : unsigned (31 downto 0);
signal next_reg_H2 : unsigned (31 downto 0);
signal next_reg_H3 : unsigned (31 downto 0);
signal next_reg_H4 : unsigned (31 downto 0);
signal next_reg_H5 : unsigned (31 downto 0);
signal next_reg_H6 : unsigned (31 downto 0);
signal next_reg_H7 : unsigned (31 downto 0);
-- internal modulo adders
signal sum0 : unsigned (31 downto 0) := (others => '0');
signal sum1 : unsigned (31 downto 0) := (others => '0');
signal sum2 : unsigned (31 downto 0) := (others => '0');
signal sum3 : unsigned (31 downto 0) := (others => '0');
signal sum4 : unsigned (31 downto 0) := (others => '0');
signal sum5 : unsigned (31 downto 0) := (others => '0');
signal sum6 : unsigned (31 downto 0) := (others => '0');
signal sum7 : unsigned (31 downto 0) := (others => '0');
signal sum0 : unsigned (31 downto 0);
signal sum1 : unsigned (31 downto 0);
signal sum2 : unsigned (31 downto 0);
signal sum3 : unsigned (31 downto 0);
signal sum4 : unsigned (31 downto 0);
signal sum5 : unsigned (31 downto 0);
signal sum6 : unsigned (31 downto 0);
signal sum7 : unsigned (31 downto 0);
begin
--=============================================================================================
-- OUTPUT RESULT REGISTERS LOGIC
/trunk/syn/sha256/sha256_padding.vhd
57,11 → 57,11
 
entity sha256_padding is
port (
words_sel_i : in std_logic_vector (1 downto 0) := (others => 'X'); -- selector for bitcnt insertion at the last block
words_sel_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- selector for bitcnt insertion at the last block
one_insert_i : in std_logic; -- insert a leading one in the padding
bytes_ena_i : in std_logic_vector (3 downto 0) := (others => 'X'); -- byte lane selector lines
bitlen_i : in std_logic_vector (63 downto 0) := (others => 'X'); -- 64bit message bit length
di_i : in std_logic_vector (31 downto 0) := (others => 'X'); -- big endian input message words
bytes_ena_i : in std_logic_vector (3 downto 0) := (others => 'U'); -- byte lane selector lines
bitlen_i : in std_logic_vector (63 downto 0) := (others => 'U'); -- 64bit message bit length
di_i : in std_logic_vector (31 downto 0) := (others => 'U'); -- big endian input message words
do_o : out std_logic_vector (31 downto 0); -- padded output words
error_o : out std_logic -- '1' if error in the byte_ena selectors
);

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