URL
https://opencores.org/ocsvn/sincos/sincos/trunk
Subversion Repositories sincos
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Rev 25 → Rev 26
/trunk/vhdl/arith/sincos/sincos_tc.vhd
0,0 → 1,56
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-- (c) 2010.. Hoffmann RF & DSP opencores@hoffmann-hochfrequenz.de |
-- V1.0 published under BSD license |
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-- file name: sincos_tc.vhd |
-- tool version: ISE12.3 Modelsim 6.1, 6.5 |
-- description: test chip for portable sine table |
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library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
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entity sincos_tc is |
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port ( |
clk: in std_logic; |
ce: in std_logic := '1'; |
rst: in std_logic := '0'; |
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theta: in unsigned(17 downto 0); |
sine: out signed(17 downto 0); |
cosine: out signed(17 downto 0) |
); |
end entity sincos_tc; |
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architecture rtl of sincos_tc is |
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signal verbose: boolean := true; |
constant pipestages: integer :=5; |
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---------------------------------------------------------------------------------------------------- |
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BEGIN |
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u_sin: entity work.sincostab -- convert phase to sine |
generic map ( |
pipestages => pipestages |
) |
port map ( |
clk => clk, |
ce => ce, |
rst => rst, |
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theta => theta, |
sine => sine, |
cosine => cosine |
); |
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END ARCHITECTURE rtl; |