URL https://opencores.org/ocsvn/sockit_owm/sockit_owm/trunk

Subversion Repositories sockit_owm

Compare Revisions

This comparison shows the changes necessary to convert path
```
/sockit_owm
```
from Rev 2 to Rev 3
↔ Reverse comparison
Compare Path: Rev

With Path: Rev

Rev 2 → Rev 3

/trunk/onewire.odt Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/trunk/onewire.odt

trunk/onewire.odt Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/iverilog_gtkwave.scr =================================================================== --- trunk/iverilog_gtkwave.scr (revision 2) +++ trunk/iverilog_gtkwave.scr (nonexistent) @@ -1,14 +0,0 @@ -#!/bin/bash - -# cleanup first -rm onewire.out -rm onewire.vcd - -# compile the verilog sources (testbench and RTL) -iverilog -o onewire.out onewire_tb.v sockit_owm.v onewire_slave_model.v - -# run the simulation -vvp onewire.out - -# open the waveform and detach it -gtkwave onewire.vcd gtkwave.sav &

trunk/iverilog_gtkwave.scr Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/onewire.odg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/onewire.odg =================================================================== --- trunk/onewire.odg (revision 2) +++ trunk/onewire.odg (nonexistent)

trunk/onewire.odg Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/onewire_tb.v =================================================================== --- trunk/onewire_tb.v (revision 2) +++ trunk/onewire_tb.v (nonexistent) @@ -1,231 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// // -// Minimalistic 1-wire (onewire) master with Avalon MM bus interface // -// testbench // -// // -// Copyright (C) 2010 Iztok Jeras // -// // -////////////////////////////////////////////////////////////////////////////// -// // -// This RTL is free hardware: you can redistribute it and/or modify // -// it under the terms of the GNU Lesser General Public License // -// as published by the Free Software Foundation, either // -// version 3 of the License, or (at your option) any later version. // -// // -// This RTL is distributed in the hope that it will be useful, // -// but WITHOUT ANY WARRANTY; without even the implied warranty of // -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // -// GNU General Public License for more details. // -// // -// You should have received a copy of the GNU General Public License // -// along with this program. If not, see . // -// // -////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -module onewire_tb; - -// system clock parameters -localparam real FRQ = 4_000_000; // 24MHz // realistic option -localparam real CP = 1*(10**9)/FRQ; // clock period - -localparam MTP_N = 7500; // divider number normal mode -localparam MTP_O = 750; // divider number overdrive mode - -localparam CDR_N = MTP_N / CP; // divider number normal mode -localparam CDR_O = MTP_O / CP; // divider number overdrive mode - -// onewire parameters -localparam OWN = 3; // number of ports - -// Avalon MM parameters -localparam AAW = 1; // address width -localparam ADW = 32; // data width -localparam ABW = ADW/8; // byte enable width - -// system_signals -reg clk; // clock -reg rst; // reset (asynchronous) -// Avalon MM interface -reg avalon_read; -reg avalon_write; -reg [AAW-1:0] avalon_address; -reg [ABW-1:0] avalon_byteenable; -reg [ADW-1:0] avalon_writedata; -wire [ADW-1:0] avalon_readdata; -wire avalon_waitrequest; -wire avalon_interrupt; - -// Avalon MM local signals -wire avalon_transfer; -reg [ADW-1:0] data; - -// onewire -wire [OWN-1:0] owr; // bidirectional -wire [OWN-1:0] owr_p; // output power enable from master -wire [OWN-1:0] owr_e; // output pull down enable from master -wire [OWN-1:0] owr_i; // input into master - -// request for a dumpfile -initial begin - $dumpfile("onewire.vcd"); - $dumpvars(0, onewire_tb); -end - -////////////////////////////////////////////////////////////////////////////// -// clock and reset -////////////////////////////////////////////////////////////////////////////// - -// clock generation -initial clk = 1'b1; -always #(CP/2) clk = ~clk; - -// reset generation -initial begin - rst = 1'b1; - repeat (2) @(posedge clk); - rst = 1'b0; -end - -////////////////////////////////////////////////////////////////////////////// -// Avalon write and read transfers -////////////////////////////////////////////////////////////////////////////// - -initial begin - // Avalon MM interface is idle - avalon_read = 1'b0; - avalon_write = 1'b0; - - // long delay to skip presence pulse - #1000_000; - - // generate a reset pulse - avalon_cycle (1, 0, 4'hf, 32'b00000010, data); - avalon_pulling (8); - // write '0' - avalon_cycle (1, 0, 4'hf, 32'b00000000, data); - avalon_pulling (8); - // write '1' - avalon_cycle (1, 0, 4'hf, 32'b00000001, data); - avalon_pulling (8); - - // switch to overdrive mode - - // generate a reset pulse - avalon_cycle (1, 0, 4'hf, 32'b00000110, data); - avalon_pulling (8); - // write '0' - avalon_cycle (1, 0, 4'hf, 32'b00000100, data); - avalon_pulling (8); - // write '1' - avalon_cycle (1, 0, 4'hf, 32'b00000101, data); - avalon_pulling (8); - - // test power supply - - // generate a delay pulse with power supply enabled - avalon_cycle (1, 0, 4'hf, 32'h00010003, data); - avalon_pulling (8); - - // test breaking a delay sequence with an idle transfer - - // generate a delay pulse and break it, before it finishes - repeat (10) @(posedge clk); - avalon_cycle (1, 0, 4'hf, 32'h00000003, data); - repeat (10) @(posedge clk); - avalon_cycle (1, 0, 4'hf, 32'h00000007, data); - - // wait a few cycles and finish - repeat (10) @(posedge clk); - $finish(); -end - -// wait for the onewire cycle completion -task avalon_pulling (input integer d); -begin - data = 32'h02; - while (data & 32'h02) begin - repeat (d) @ (posedge clk); - avalon_cycle (0, 0, 4'hf, 32'hxxxx_xxxx, data); - end -end endtask - -////////////////////////////////////////////////////////////////////////////// -// Avalon transfer cycle generation task -////////////////////////////////////////////////////////////////////////////// - -task automatic avalon_cycle ( - input r_w, // 0-read or 1-write cycle - input [AAW-1:0] adr, - input [ABW-1:0] ben, - input [ADW-1:0] wdt, - output [ADW-1:0] rdt -); -begin - $display ("Avalon MM cycle start: T=%10tns, %s address=%08x byteenable=%04b writedata=%08x", $time/1000.0, r_w?"write":"read ", adr, ben, wdt); - // start an Avalon cycle - avalon_read <= ~r_w; - avalon_write <= r_w; - avalon_address <= adr; - avalon_byteenable <= ben; - avalon_writedata <= wdt; - // wait for waitrequest to be retracted - @ (posedge clk); while (~avalon_transfer) @ (posedge clk); - // end Avalon cycle - avalon_read <= 1'b0; - avalon_write <= 1'b0; - // read data - rdt = avalon_readdata; - $display ("Avalon MM cycle end : T=%10tns, readdata=%08x", $time/1000.0, rdt); -end -endtask - -// avalon cycle transfer cycle end status -assign avalon_transfer = (avalon_read | avalon_write) & ~avalon_waitrequest; - -assign avalon_waitrequest = 1'b0; - -////////////////////////////////////////////////////////////////////////////// -// RTL instance -////////////////////////////////////////////////////////////////////////////// - -sockit_owm #( - .CDR_N (CDR_N), - .CDR_O (CDR_O), - .OWN (OWN) -) onewire_master ( - // system - .clk (clk), - .rst (rst), - // Avalon - .bus_read (avalon_read), - .bus_write (avalon_write), - .bus_writedata (avalon_writedata), - .bus_readdata (avalon_readdata), - .bus_interrupt (avalon_interrupt), - // onewire - .onewire_p (owr_p), - .onewire_e (owr_e), - .onewire_i (owr_i) -); - -// onewire -pullup onewire_pullup [OWN-1:0] (owr); - -genvar i; -generate for (i=0; i

trunk/iverilog_gtkwave.cmd Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/onewire_slave_model.v =================================================================== --- trunk/onewire_slave_model.v (revision 2) +++ trunk/onewire_slave_model.v (nonexistent) @@ -1,186 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// // -// 1-wire (owr) slave model // -// // -// Copyright (C) 2010 Iztok Jeras // -// // -////////////////////////////////////////////////////////////////////////////// -// // -// This RTL is free hardware: you can redistribute it and/or modify // -// it under the terms of the GNU Lesser General Public License // -// as published by the Free Software Foundation, either // -// version 3 of the License, or (at your option) any later version. // -// // -// This RTL is distributed in the hope that it will be useful, // -// but WITHOUT ANY WARRANTY; without even the implied warranty of // -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // -// GNU General Public License for more details. // -// // -// You should have received a copy of the GNU General Public License // -// along with this program. If not, see . // -// // -////////////////////////////////////////////////////////////////////////////// - -`timescale 1us / 1ns - -module onewire_slave_model #( - // identification - parameter FAMILY_CODE = 8'h01, - parameter SERIAL_NUMBER = 48'hba98_7654_3210, - parameter CRC_CODE = 8'hff, - // time slot (min=15, typ=30, max=60) - parameter TS = 30 -)( - inout wire owr -); - -// commands -localparam Read_ROM = 8'h33; -localparam Search_ROM = 8'hf0; -localparam Overdrive_Skip_ROM = 8'h3C; - -// IO -reg pull; - -// status registers -reg [23:0] state; // chip state in ASCII -reg [23:0] cycle; // cycle status in ASCII -reg [7:0] cmd; // received command -reg od; // overdrive mode status -integer cnt; // transfer bit counter - -// data registers -reg [7:0] drx; -reg [7:0] dtx; - -// events -event transfer; -event clock; -event sample; -event reset; - -////////////////////////////////////////////////////////////////////////////// -// IO -////////////////////////////////////////////////////////////////////////////// - -assign owr = pull ? 1'b0 : 1'bz; - -////////////////////////////////////////////////////////////////////////////// -// events inside a cycle -////////////////////////////////////////////////////////////////////////////// - -always @ (negedge owr) begin - fork - begin : slot_data - #((od?TS/10:TS)*1) -> sample; - end - begin : slot_reset - #((od?TS/10:TS)*8) -> reset; - end - begin : slot_reset_all - #((od?TS/10:TS)*8*8) begin - od = 1'b0; - -> reset; - end - end - begin : slot_end - @ (posedge owr) begin - disable slot_data; - disable slot_reset; - disable slot_reset_all; - end - end - join -end - -// // bit transfer -// always @ (negedge owr) begin -// //task trn (); begin -// -> transfer; -// cycle <= dtx[0] ? "OPN" : "PUL"; -// pull <= ~dtx[0]; -// cnt <= cnt + 1; -// fork -// // transmit -// begin : trn_tx -// #(TS*1); -// pull <= 1'b0; -// end -// // receive -// begin : trn_rx -// #(TS*1); -// drx = {owr, drx[7:1]}; -// -> sample; -// end -// // reset -// begin : trn_rst -// #(TS*16) -// state <= "RST"; -// cnt <= 0; -// end -// // wait for owr posedge -// begin : trn_pdg -// @ (posedge owr) -// disable trn_rst; -// end -// join -// cycle <= "IDL"; -// end -// //endtask - -////////////////////////////////////////////////////////////////////////////// -// logic -////////////////////////////////////////////////////////////////////////////// - -// power up state -initial begin - pull <= 1'b0; - #1 -> reset; -end - -// reset event -always @ (reset) begin - // IO state - pull <= 1'b0; - dtx <= 0; - cnt <= 0; - cycle <= "OPN"; - // power-up chip state - state <= "RST"; - od <= 1'b0; - if (~owr) @ (posedge owr); - // issue presence pulse - #((od?TS/10:TS)*1); - state <= "PRS"; - pull <= 1'b1; - #((od?TS/10:TS)*4); - pull <= 1'b0; - state <= "IDL"; -end - -// // reset -// always @ (negedge owr) -// if (state == "RST") begin -// trn (); -// state <= "IDL"; -// end - -// // bit transfer -// always @ (negedge owr) -// case (state) -// "IDL": begin -// state <= "CMD"; -// trn (); -// end -// "CMD": begin -// trn (); -// if (cnt == 8) -// cmd <= drx; -// if (cmd == Read_ROM) -// state <= "DTX"; -// dtx <= FAMILY_CODE; -// end -// endcase - - -endmodule Index: trunk/sockit_owm.v =================================================================== --- trunk/sockit_owm.v (revision 2) +++ trunk/sockit_owm.v (nonexistent) @@ -1,327 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// // -// Minimalistic 1-wire (onewire) master with Avalon MM bus interface // -// // -// Copyright (C) 2010 Iztok Jeras // -// // -////////////////////////////////////////////////////////////////////////////// -// // -// This RTL is free hardware: you can redistribute it and/or modify // -// it under the terms of the GNU Lesser General Public License // -// as published by the Free Software Foundation, either // -// version 3 of the License, or (at your option) any later version. // -// // -// This RTL is distributed in the hope that it will be useful, // -// but WITHOUT ANY WARRANTY; without even the implied warranty of // -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // -// GNU General Public License for more details. // -// // -// You should have received a copy of the GNU General Public License // -// along with this program. If not, see . // -// // -////////////////////////////////////////////////////////////////////////////// - - -////////////////////////////////////////////////////////////////////////////// -// // -// The clock divider parameter is computed with the next formula: // -// // -// CDR_N = f_CLK * BTP_N (example: CDR_N = 2MHz * 7.5us = 15) // -// CDR_O = f_CLK * BTP_O (example: CDR_O = 2MHz * 1.0us = 2) // -// // -// If the dividing factor is not a round integer, than the timing of the // -// controller will be slightly off, and would support only a subset of // -// 1-wire devices with timing closer to the typical 30us slot. // -// // -// Base time periods BTP_N = "7.5" and BTP_O = "1.0" are optimized for // -// logic consumption and optimal onewire timing. // -// Since the default timing might shrink the range of available frequences // -// to multiples of 2MHz, a less restrictive timing is offered, // -// BTP_N = "5.0" and BTP_O = "1.0", this limits the frequency to multiples // -// of 1MHz. // -// If even this restrictions are too strict use timing BTP_N = "6.0" and // -// BTP_O = "0.5", where the actual periods can be in the range: // -// 6.0us <= BTP_N <= 7.5us // -// 0.5us <= BTP_O <= 0.66us // -// // -////////////////////////////////////////////////////////////////////////////// - -module sockit_owm #( - // interface parameters - parameter BDW = 32, // bus data width - parameter OWN = 1, // number of 1-wire ports - // implementation of overdrive enable - parameter OVD_E = 1, // overdrive functionality is implemented by default - // clock divider ratios (defaults are for a 2MHz clock) - parameter CDR_N = 15, // normal mode - parameter CDR_O = 2, // overdrive mode - // base time period - parameter BTP_N = "7.5", // normal mode (7.5us, options are "7.5", "5.0" and "6.0") - parameter BTP_O = "1.0", // overdrive mode (1.0us, options are "1.0", and "0.5") - // normal mode timing - parameter T_RSTH_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset high - parameter T_RSTL_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset low - parameter T_RSTP_N = (BTP_N == "7.5") ? 10 : (BTP_N == "5.0") ? 15 : 10, // reset presence pulse - parameter T_DAT0_N = (BTP_N == "7.5") ? 8 : (BTP_N == "5.0") ? 12 : 10, // bit 0 low - parameter T_DAT1_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // bit 1 low - parameter T_BITS_N = (BTP_N == "7.5") ? 2 : (BTP_N == "5.0") ? 3 : 2, // bit sample - parameter T_RCVR_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // recovery - parameter T_IDLE_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 104 : 1, // recovery - // overdrive mode timing - parameter T_RSTH_O = (BTP_N == "1.0") ? 48 : 96, // reset high - parameter T_RSTL_O = (BTP_N == "1.0") ? 48 : 96, // reset low - parameter T_RSTP_O = (BTP_N == "1.0") ? 10 : 15, // reset presence pulse - parameter T_DAT0_O = (BTP_N == "1.0") ? 6 : 12, // bit 0 low - parameter T_DAT1_O = (BTP_N == "1.0") ? 1 : 2, // bit 1 low - parameter T_BITS_O = (BTP_N == "1.0") ? 2 : 3, // bit sample - parameter T_RCVR_O = (BTP_N == "1.0") ? 1 : 2, // recovery - parameter T_IDLE_O = (BTP_N == "1.0") ? 48 : 96 // recovery -)( - // system signals - input clk, - input rst, - // bus interface - input bus_read, - input bus_write, - input [BDW-1:0] bus_writedata, - output [BDW-1:0] bus_readdata, - output bus_interrupt, - // onewire - output [OWN-1:0] onewire_p, // output power enable - output [OWN-1:0] onewire_e, // output pull down enable - input [OWN-1:0] onewire_i // input from bidirectional wire -); - -////////////////////////////////////////////////////////////////////////////// -// local parameters -////////////////////////////////////////////////////////////////////////////// - -// size of boudrate generator counter (divider for normal mode is largest) -localparam CDW = $clog2(CDR_N); - -// size of port select signal -localparam SDW = $clog2(OWN); - -// size of cycle timing counter -localparam TDW = (T_RSTH_O+T_RSTL_O) > (T_RSTH_N+T_RSTL_N) - ? $clog2(T_RSTH_O+T_RSTL_O) : $clog2(T_RSTH_N+T_RSTL_N); - -////////////////////////////////////////////////////////////////////////////// -// local signals -////////////////////////////////////////////////////////////////////////////// - -// clock divider -//generate if (CDR>1) begin : div_declaration -reg [CDW-1:0] div; -//end endgenerate -wire pls; - -// transfer control -reg owr_trn; // transfer status -reg [TDW-1:0] cnt; // transfer counter - -// port select -//generate if (OWN>1) begin : sel_declaration -reg [SDW-1:0] owr_sel; -//end endgenerate - -// onewire signals -reg [OWN-1:0] owr_pwr; // power -reg owr_ovd; // overdrive -reg owr_rst; // reset -reg owr_dtx; // data bit transmit -reg owr_drx; // data bit receive - -wire owr_p; // output -reg owr_oen; // output enable -wire owr_i; // input - -// interrupt signals -reg irq_etx; // interrupt enable transmit -reg irq_erx; // interrupt enable receive -reg irq_stx; // interrupt status transmit -reg irq_srx; // interrupt status receive - -// timing signals -wire [TDW-1:0] t_idl ; // idle cycle time -wire [TDW-1:0] t_rst ; // reset cycle time -wire [TDW-1:0] t_bit ; // data bit transfer cycle time -wire [TDW-1:0] t_rstp; // reset presence pulse sampling time -wire [TDW-1:0] t_rsth; // reset release time -wire [TDW-1:0] t_dat0; // data bit 0 release time -wire [TDW-1:0] t_dat1; // data bit 1 release time -wire [TDW-1:0] t_bits; // data bit transfer sampling time -wire [TDW-1:0] t_zero; // end of cycle time - -////////////////////////////////////////////////////////////////////////////// -// cycle timing -////////////////////////////////////////////////////////////////////////////// - -// idle time -assign t_idl = owr_ovd ? T_IDLE_O : T_IDLE_N ; -// reset cycle time (reset low + reset hight) -assign t_rst = owr_ovd ? T_RSTL_O + T_RSTH_O : T_RSTL_N + T_RSTH_N ; -// data bit transfer cycle time (write 0 + recovery) -assign t_bit = owr_ovd ? T_DAT0_O + + T_RCVR_N : T_DAT0_N + T_RCVR_O; - -// reset presence pulse sampling time (reset high - reset presence) -assign t_rstp = owr_ovd ? T_RSTH_O - T_RSTP_O : T_RSTH_N - T_RSTP_N ; -// reset release time (reset high) -assign t_rsth = owr_ovd ? T_RSTH_O : T_RSTH_N ; - -// data bit 0 release time (write bit 0 - write bit 0 + recovery) -assign t_dat0 = owr_ovd ? T_DAT0_O - T_DAT0_O + T_RCVR_O : T_DAT0_N - T_DAT0_N + T_RCVR_N; -// data bit 1 release time (write bit 0 - write bit 1 + recovery) -assign t_dat1 = owr_ovd ? T_DAT0_O - T_DAT1_O + T_RCVR_O : T_DAT0_N - T_DAT1_N + T_RCVR_N; -// data bit transfer sampling time (write bit 0 - write bit 1 + recovery) -assign t_bits = owr_ovd ? T_DAT0_O - T_BITS_O + T_RCVR_O : T_DAT0_N - T_BITS_N + T_RCVR_N; - -// end of cycle time -assign t_zero = 'd0; - -////////////////////////////////////////////////////////////////////////////// -// clock divider -////////////////////////////////////////////////////////////////////////////// - -// clock division ratio depends on overdrive mode status, -generate if ((CDR_N>1) | (CDR_O>1)) begin : div_implementation - // clock divider - always @ (posedge clk, posedge rst) - if (rst) div <= 'd0; - else begin - if (bus_write) div <= 'd0; - else div <= pls ? 'd0 : div + owr_trn; - end - // divided clock pulse - assign pls = (div == (owr_ovd ? CDR_O : CDR_N) - 1); -end else begin - // clock period is same as the onewire period - assign pls = 1'b1; -end endgenerate - -////////////////////////////////////////////////////////////////////////////// -// bus logic -////////////////////////////////////////////////////////////////////////////// - -// bus read data -generate if (OWN>1) begin : sel_readdata - assign bus_readdata = {{BDW-OWN-16{1'b0}}, owr_pwr, {8-SDW{1'b0}}, owr_sel, - irq_erx, irq_etx, irq_srx, irq_stx, - owr_i , owr_ovd, owr_trn, owr_drx}; -end else begin - assign bus_readdata = {irq_erx, irq_etx, irq_srx, irq_stx, - owr_i , owr_ovd, owr_trn, owr_drx}; -end endgenerate - -generate if (OWN>1) begin : sel_implementation - // port select - always @ (posedge clk, posedge rst) - if (rst) owr_sel <= {SDW{1'b0}}; - else if (bus_write) owr_sel <= bus_writedata[8+:SDW]; - - // power delivery - always @ (posedge clk, posedge rst) - if (rst) owr_pwr <= {SDW{1'b0}}; - else if (bus_write) owr_pwr <= bus_writedata[16+:SDW]; -end else begin - // port select - always @ (*) owr_sel <= {SDW{1'b0}}; - // power delivery - always @ (posedge clk, posedge rst) - if (rst) owr_pwr <= 1'b0; - else if (bus_write) owr_pwr <= bus_writedata[3]; -end endgenerate - -// bus interrupt -assign bus_interrupt = irq_erx & irq_srx - | irq_etx & irq_stx; - -// interrupt enable -always @ (posedge clk, posedge rst) -if (rst) {irq_erx, irq_etx} <= 2'b00; -else if (bus_write) {irq_erx, irq_etx} <= bus_writedata[7:6]; - -// transmit status (active after onewire transfer cycle ends) -always @ (posedge clk, posedge rst) -if (rst) irq_stx <= 1'b0; -else begin - if (bus_write) irq_stx <= 1'b0; - else if (pls & (cnt == t_zero)) irq_stx <= 1'b1; - else if (bus_read) irq_stx <= 1'b0; -end - -// receive status (active after wire sampling point inside the transfer cycle) -always @ (posedge clk, posedge rst) -if (rst) irq_srx <= 1'b0; -else begin - if (bus_write) irq_srx <= 1'b0; - else if (pls) begin - if (cnt == t_rstp) irq_srx <= owr_rst & ~owr_dtx; // presence detect - else if (cnt == t_bits) irq_srx <= ~owr_rst & owr_dtx; // read data bit - end else if (bus_read) irq_srx <= 1'b0; -end - -////////////////////////////////////////////////////////////////////////////// -// onewire state machine -////////////////////////////////////////////////////////////////////////////// - -// transmit data, reset, overdrive -generate if (OVD_E) begin : ctrl_writedata - always @ (posedge clk, posedge rst) - if (rst) {owr_ovd, owr_rst, owr_dtx} <= 3'b000; - else if (bus_write) {owr_ovd, owr_rst, owr_dtx} <= bus_writedata[2:0]; -end else begin - always @ (posedge clk, posedge rst) - if (rst) {owr_ovd, owr_rst, owr_dtx} <= 3'b000; - else if (bus_write) { owr_rst, owr_dtx} <= bus_writedata[1:0]; -end endgenerate - -// onewire transfer status -always @ (posedge clk, posedge rst) -if (rst) owr_trn <= 1'b0; -else begin - if (bus_write) owr_trn <= ~&bus_writedata[2:0]; - else if (pls & (cnt == t_zero)) owr_trn <= 1'b0; -end - -// state counter (initial value depends whether the cycle is reset or data) -always @ (posedge clk, posedge rst) -if (rst) cnt <= 0; -else begin - if (bus_write) cnt <= (&bus_writedata[1:0] ? t_idl : bus_writedata[1] ? t_rst : t_bit) - 'd1; - else if (pls) cnt <= cnt - 'd1; -end - -// receive data (sampling point depends whether the cycle is reset or data) -always @ (posedge clk) -if (pls) begin - if ( owr_rst & (cnt == t_rstp)) owr_drx <= owr_i; // presence detect - else if (~owr_rst & (cnt == t_bits)) owr_drx <= owr_i; // read data bit -end - -// output register (switch point depends whether the cycle is reset or data) -always @ (posedge clk, posedge rst) -if (rst) owr_oen <= 1'b0; -else begin - if (bus_write) owr_oen <= ~&bus_writedata[1:0]; - else if (pls) begin - if (owr_rst & (cnt == t_rsth)) owr_oen <= 1'b0; // reset - else if (owr_dtx & (cnt == t_dat1)) owr_oen <= 1'b0; // write 1, read - else if ( (cnt == t_dat0)) owr_oen <= 1'b0; // write 0 - end -end - -////////////////////////////////////////////////////////////////////////////// -// IO -////////////////////////////////////////////////////////////////////////////// - -// only one 1-wire line cn be accessed at the same time -assign onewire_e = owr_oen << owr_sel; -// all 1-wire lines can be powered independently -assign onewire_p = owr_pwr; - -// 1-wire line status read multiplexer -assign owr_i = onewire_i [owr_sel]; -assign owr_p = onewire_p [owr_sel]; - -endmodule Index: trunk/LICENSE =================================================================== --- trunk/LICENSE (nonexistent) +++ trunk/LICENSE (revision 3) @@ -0,0 +1,27 @@ +Verilog RTL and testbench files are licensed under LGPL 3. +Bash and Windows cmd scripts are licensed under LGPL 3. +lic/lgpl.txt + +TCL scripts for integration into Altera tools are licensed under LGPL 3. This +files were at first based on Altera demos, but are now entirely rewritten +according requirements described in SOPC Builder documentation. +lic/lgpl.txt + +The glue code for the Nios II HAL is licensed with the original public domain +like license by Altera. This files were at first based on Altera demos, but +are now almost entirely rewritten according requirements described in Nios II +documentation. + +The license for the "public domain kit" has not been changed. The modified code +is also public domain. +lic/license_pub.txt + +The documentation (including all drawings except the PS/2 connector) is +licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported +(CC BY-SA 3.0) License. +http://creativecommons.org/licenses/by-sa/3.0/ +http://creativecommons.org/licenses/by-sa/3.0/legalcode + +The PS/2 connector SVG drawing is from Wikipedia, and its copyright holder +released it into the public domain. +http://en.wikipedia.org/wiki/File:MiniDIN-6_Connector_Pinout.svg Index: trunk/HAL/src/owerr.c =================================================================== --- trunk/HAL/src/owerr.c (revision 2) +++ trunk/HAL/src/owerr.c (revision 3) @@ -30,17 +30,12 @@ // #include -#ifndef _WIN32_WCE #include -#endif -#ifdef _WIN64 -#include -#endif #include "ownet.h" #ifndef SIZE_OWERROR_STACK - #ifdef SMALL_MEMORY_TARGET - //for small memory, only hole 1 error + #ifdef SOCKIT_OWM_ERR_SMALL + //for small memory, only hold 1 error #define SIZE_OWERROR_STACK 1 #else #define SIZE_OWERROR_STACK 10 @@ -81,7 +76,7 @@ #else void owRaiseError(int); #endif -#ifndef SMALL_MEMORY_TARGET +#ifndef SOCKIT_OWM_ERR_SMALL void owPrintErrorMsg(FILE *); void owPrintErrorMsgStd(); char *owGetErrorMsg(int); @@ -163,9 +158,9 @@ #endif -// SMALL_MEMORY_TARGET - embedded microcontrollers, where these +// SOCKIT_OWM_ERR_SMALL - embedded microcontrollers, where these // messaging functions might not make any sense. -#ifndef SMALL_MEMORY_TARGET +#ifndef SOCKIT_OWM_ERR_SMALL //Array of meaningful error messages to associate with codes. //Not used on targets with low memory (i.e. PIC). static char *owErrorMsg[125] = @@ -302,7 +297,6 @@ return owErrorMsg[err]; } -#ifndef __C51__ //-------------------------------------------------------------------------- // The 'owPrintErrorMsg' is the method for printing an error from the stack. // The destination for the print is specified by the argument, fileno, which @@ -329,7 +323,6 @@ fprintf(filenum,"Error %d: %s\r\n",err,owErrorMsg[err]); #endif } -#endif //__C51__ // Same as above, except uses default printf output void owPrintErrorMsgStd()

/trunk/HAL/src/sockit_owm.c

1,5 → 1,9

29,30 → 33,6

80,14 → 60,13

105,7 → 84,7

/trunk/HAL/src/temp28.c

0,0 → 1,129

trunk/HAL/src/temp28.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/HAL/src/temp10.c =================================================================== --- trunk/HAL/src/temp10.c (nonexistent) +++ trunk/HAL/src/temp10.c (revision 3) @@ -0,0 +1,139 @@ +//--------------------------------------------------------------------------- +// Copyright (C) 2000 Dallas Semiconductor Corporation, All Rights Reserved. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL DALLAS SEMICONDUCTOR BE LIABLE FOR ANY CLAIM, DAMAGES +// OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +// OTHER DEALINGS IN THE SOFTWARE. +// +// Except as contained in this notice, the name of Dallas Semiconductor +// shall not be used except as stated in the Dallas Semiconductor +// Branding Policy. +// --------------------------------------------------------------------------- +// +// temp10.C - Module to read the DS1920/DS1820 - temperature measurement. +// +// --------------------------------------------------------------------------- +// +// +#include "ownet.h" +#include "temp10.h" + +//---------------------------------------------------------------------- +// Read the temperature of a DS1920/DS1820 (family code 0x10) +// +// 'portnum' - number 0 to MAX_PORTNUM-1. This number was provided to +// OpenCOM to indicate the port number. +// 'SerialNum' - Serial Number of DS1920/DS1820 to read temperature from +// 'Temp ' - pointer to variable where that temperature will be +// returned +// +// Returns: TRUE(1) temperature has been read and verified +// FALSE(0) could not read the temperature, perhaps device is not +// in contact +// +int ReadTemperature10(int portnum, uchar *SerialNum, float *Temp) +{ + uchar rt=FALSE; + uchar send_block[30],lastcrc8; + int send_cnt, tsht, i, loop=0; + float tmp,cr,cpc; + int power; + + // set the device serial number to the counter device + owSerialNum(portnum,SerialNum,FALSE); + + for (loop = 0; loop < 2; loop ++) + { + // check if the chip is connected to VDD + if (owAccess(portnum)) + { + owWriteByte(portnum,0xB4); + power = owReadByte(portnum); + } + + // access the device + if (owAccess(portnum)) + { + // send the convert command and if nesessary start power delivery + if (power) { + if (!owWriteBytePower(portnum,0x44)) + return FALSE; + } else { + if (!owWriteByte(portnum,0x44)) + return FALSE; + } + + // sleep for 1 second + msDelay(1000); + + // turn off the 1-Wire Net strong pull-up + if (power) { + if (owLevel(portnum,MODE_NORMAL) != MODE_NORMAL) + return FALSE; + } + + // access the device + if (owAccess(portnum)) + { + // create a block to send that reads the temperature + // read scratchpad command + send_cnt = 0; + send_block[send_cnt++] = 0xBE; + // now add the read bytes for data bytes and crc8 + for (i = 0; i < 9; i++) + send_block[send_cnt++] = 0xFF; + + // now send the block + if (owBlock(portnum,FALSE,send_block,send_cnt)) + { + // initialize the CRC8 + setcrc8(portnum,0); + // perform the CRC8 on the last 8 bytes of packet + for (i = send_cnt - 9; i < send_cnt; i++) + lastcrc8 = docrc8(portnum,send_block[i]); + + // verify CRC8 is correct + if (lastcrc8 == 0x00) + { + // calculate the high-res temperature + tsht = send_block[1]/2; + if (send_block[2] & 0x01) + tsht |= -128; + tmp = (float)(tsht); + cr = send_block[7]; + cpc = send_block[8]; + if (((cpc - cr) == 1) && (loop == 0)) + continue; + if (cpc == 0) + return FALSE; + else + tmp = tmp - (float)0.25 + (cpc - cr)/cpc; + + *Temp = tmp; + // success + rt = TRUE; + break; + } + } + } + } + + } + + // return the result flag rt + return rt; +}

trunk/HAL/src/temp10.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/HAL/src/owlnk.c =================================================================== --- trunk/HAL/src/owlnk.c (revision 2) +++ trunk/HAL/src/owlnk.c (revision 3) @@ -76,25 +76,26 @@ int ovd = (sockit_owm.ovd >> portnum) & 0x1; // lock transfer - ALT_SEM_PEND (sockit_owm.trn, 0); + ALT_SEM_PEND (sockit_owm.cyc, 0); - // write RST - IOWR_SOCKIT_OWM (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_POWER_OFST) - | (portnum << SOCKIT_OWM_SEL_OFST) - | (sockit_owm.ena << SOCKIT_OWM_ETX_OFST) - | (ovd << SOCKIT_OWM_OVD_OFST) - | SOCKIT_OWM_RST_MSK); + // reset pulse + IOWR_SOCKIT_OWM_CTL (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_CTL_POWER_OFST ) + | (portnum << SOCKIT_OWM_CTL_SEL_OFST ) + | (sockit_owm.ien ? SOCKIT_OWM_CTL_IEN_MSK : 0x00) + | ( SOCKIT_OWM_CTL_CYC_MSK ) + | (ovd ? SOCKIT_OWM_CTL_OVD_MSK : 0x00) + | ( SOCKIT_OWM_CTL_RST_MSK )); // wait for irq to set the transfer end flag ALT_FLAG_PEND (sockit_owm.irq, 0x1, OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, 0); // wait for STX (end of transfer cycle) and read the presence status - while ((reg = IORD_SOCKIT_OWM (sockit_owm.base)) & SOCKIT_OWM_TRN_MSK); + while ((reg = IORD_SOCKIT_OWM_CTL (sockit_owm.base)) & SOCKIT_OWM_CTL_CYC_MSK); // release transfer lock - ALT_SEM_POST (sockit_owm.trn); + ALT_SEM_POST (sockit_owm.cyc); - // return DRX (presence detect) - return (~reg >> SOCKIT_OWM_DAT_OFST) & 0x1; + // return negated DAT (presence detect) + return (~reg & SOCKIT_OWM_CTL_DAT_MSK); // NOTE the shortcut } //-------------------------------------------------------------------------- @@ -116,25 +117,26 @@ int ovd = (sockit_owm.ovd >> portnum) & 0x1; // lock transfer - ALT_SEM_PEND (sockit_owm.trn, 0); + ALT_SEM_PEND (sockit_owm.cyc, 0); - // write RST - IOWR_SOCKIT_OWM (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_POWER_OFST) - | (portnum << SOCKIT_OWM_SEL_OFST) - | (sockit_owm.ena << SOCKIT_OWM_ETX_OFST) - | (ovd << SOCKIT_OWM_OVD_OFST) - | ((sendbit & 0x1) << SOCKIT_OWM_DAT_OFST)); + // read/write data + IOWR_SOCKIT_OWM_CTL (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_CTL_POWER_OFST ) + | (portnum << SOCKIT_OWM_CTL_SEL_OFST ) + | (sockit_owm.ien ? SOCKIT_OWM_CTL_IEN_MSK : 0x00) + | ( SOCKIT_OWM_CTL_CYC_MSK ) + | (ovd ? SOCKIT_OWM_CTL_OVD_MSK : 0x00) + | (sendbit & SOCKIT_OWM_CTL_DAT_MSK )); // NOTE the shortcut // wait for irq to set the transfer end flag ALT_FLAG_PEND (sockit_owm.irq, 0x1, OS_FLAG_WAIT_SET_ANY + OS_FLAG_CONSUME, 0); // wait for STX (end of transfer cycle) and read the read data bit - while ((reg = IORD_SOCKIT_OWM (sockit_owm.base)) & SOCKIT_OWM_TRN_MSK); + while ((reg = IORD_SOCKIT_OWM_CTL (sockit_owm.base)) & SOCKIT_OWM_CTL_CYC_MSK); // release transfer lock - ALT_SEM_POST (sockit_owm.trn); + ALT_SEM_POST (sockit_owm.cyc); - // return DRX (read bit) - return (reg >> SOCKIT_OWM_DAT_OFST) & 0x1; + // return DAT (read bit) + return (reg & SOCKIT_OWM_CTL_DAT_MSK); // NOTE the shortcut } //-------------------------------------------------------------------------- @@ -205,10 +207,15 @@ // SMALLINT owSpeed(int portnum, SMALLINT new_speed) { - if (new_speed == MODE_OVERDRIVE) sockit_owm.ovd |= (1 << portnum); - if (new_speed == MODE_NORMAL ) sockit_owm.ovd &= ~(1 << portnum); + int select; + select = 0x1 << portnum; + // if overdrive is implemented use it + if (sockit_owm.ovd_e) { + if (new_speed == MODE_OVERDRIVE) sockit_owm.ovd |= select; + if (new_speed == MODE_NORMAL ) sockit_owm.ovd &= ~select; + } // return the current port state - return ((sockit_owm.ovd >> portnum) & 0x1) ? MODE_OVERDRIVE : MODE_NORMAL; + return (sockit_owm.ovd & select) ? MODE_OVERDRIVE : MODE_NORMAL; } //-------------------------------------------------------------------------- @@ -230,15 +237,12 @@ if (new_level == MODE_STRONG5) { // set the power bit sockit_owm.pwr |= (1 << portnum); - IOWR_SOCKIT_OWM (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_POWER_OFST) - | SOCKIT_OWM_PWR_MSK - | SOCKIT_OWM_IDL_MSK); + IOWR_SOCKIT_OWM_CTL (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_CTL_POWER_OFST) | SOCKIT_OWM_CTL_PWR_MSK); } if (new_level == MODE_NORMAL) { // clear the power bit sockit_owm.pwr &= ~(1 << portnum); - IOWR_SOCKIT_OWM (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_POWER_OFST) - | SOCKIT_OWM_IDL_MSK); + IOWR_SOCKIT_OWM_CTL (sockit_owm.base, (sockit_owm.pwr << SOCKIT_OWM_CTL_POWER_OFST)); } // return the current port state return ((sockit_owm.pwr >> portnum) & 0x1) ? MODE_STRONG5 : MODE_NORMAL; @@ -268,23 +272,27 @@ #if SOCKIT_OWM_HW_DLY int i; + // compute the number delay cycles depending on delay time + len = (len * sockit_owm.f_dly) >> 16; + // lock transfer - ALT_SEM_PEND (sockit_owm.trn, 0); + ALT_SEM_PEND (sockit_owm.cyc, 0); for (i=0; i

/trunk/HAL/src/temp42.c

0,0 → 1,129

trunk/HAL/src/temp42.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/HAL/inc/temp42.h =================================================================== --- trunk/HAL/inc/temp42.h (nonexistent) +++ trunk/HAL/inc/temp42.h (revision 3) @@ -0,0 +1,31 @@ +//--------------------------------------------------------------------------- +// Copyright (C) 2000 Dallas Semiconductor Corporation, All Rights Reserved. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL DALLAS SEMICONDUCTOR BE LIABLE FOR ANY CLAIM, DAMAGES +// OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +// OTHER DEALINGS IN THE SOFTWARE. +// +// Except as contained in this notice, the name of Dallas Semiconductor +// shall not be used except as stated in the Dallas Semiconductor +// Branding Policy. +// --------------------------------------------------------------------------- +// +// temp42.h - Header to read the DS28EA00 - temperature measurement. +// +// --------------------------------------------------------------------------- + +int ReadTemperature42(int,uchar *,float *);

trunk/HAL/inc/temp42.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/HAL/inc/ownet.h =================================================================== --- trunk/HAL/inc/ownet.h (revision 2) +++ trunk/HAL/inc/ownet.h (revision 3) @@ -43,64 +43,17 @@ // Common Includes to ownet applications //--------------------------------------------------------------// #include +#include - //--------------------------------------------------------------// // Target Specific Information //--------------------------------------------------------------// -//--------------------------------------------------------------// -// Handhelds (PalmOS, WinCE) -//--------------------------------------------------------------// -#ifdef __MC68K__ - //MC68K is the type of processor in the PILOT - //Metrowerk's CodeWarrior defines this symbol - #include - #ifndef strcmp - #include - #define strcmp StrCompare - #endif - #include -#endif -#ifdef _WIN32_WCE - //All of our projects had this flag defined by default (_WIN32_WCE), - //but I'm not 100% positive that this is _the_ definitive - //flag to use to identify a WinCE system. - #include "WinCElnk.h" - #ifndef FILE - #define FILE int - extern int sprintf(char *buffer, char *format,...); - extern void fprintf(FILE *fp, char *format,...); - extern void printf(char *format,...); - #endif -#endif +// Altera Nios II + uCOS II +// configuration options available in: sockit_owm_sw.tcl +//#define SOCKIT_OWM_ERR_ENABLE +//#define SOCKIT_OWM_ERR_SMALL -#if !defined(_WIN32_WCE) && !defined(__MC68K__) - #include -#endif - -#ifdef __C51__ - #define FILE int - #define exit(c) return - typedef unsigned int ushort; - typedef unsigned long ulong; - #define SMALLINT uchar -#endif - -#ifdef __ICCMAXQ__ - #define FILE int - #define stdout 0 - #define stdin 1 - #define stderr 2 - typedef unsigned int ushort; - typedef unsigned long ulong; - #define SMALLINT short - #define main micro_main - #define real_main main - #define SMALL_MEMORY_TARGET -#endif - - //--------------------------------------------------------------// // Typedefs //--------------------------------------------------------------// @@ -128,15 +81,6 @@ #define SMALLINT int #endif -// setting max baud -#ifdef _WINDOWS - // 0x02 = PARAMSET_19200 -#define MAX_BAUD 0x02 -#else - // 0x06 = PARMSET_115200 -#define MAX_BAUD 0x06 -#endif - #ifndef OW_UCHAR #define OW_UCHAR typedef unsigned char uchar; @@ -197,6 +141,9 @@ //--------------------------------------------------------------// // Error handling //--------------------------------------------------------------// + +#ifdef SOCKIT_OWM_ERR_ENABLE + extern int owGetErrorNum(void); extern int owHasErrors(void); @@ -215,7 +162,7 @@ #define OWASSERT(s,err,ret) if(!(s)){owRaiseError((err));return (ret);} #endif -#ifdef SMALL_MEMORY_TARGET +#ifdef SOCKIT_OWM_ERR_SMALL #define OWERROR_DUMP(fileno) /*no-op*/; #else //Prints the stack out to the given file. @@ -225,6 +172,14 @@ extern char *owGetErrorMsg(int); #endif +#else + +#define OWERROR_CLEAR() /*no-op*/; +#define OWERROR(err) /*no-op*/; +#define OWERROR_DUMP(fileno) /*no-op*/; + +#endif + #define OWERROR_NO_ERROR_SET 0 #define OWERROR_NO_DEVICES_ON_NET 1 #define OWERROR_RESET_FAILED 2

/trunk/HAL/inc/sockit_owm.h

1,5 → 1,9

29,30 → 33,6

67,63 → 47,63

130,11 → 110,11

147,6 → 127,6

/trunk/HAL/inc/temp28.h

0,0 → 1,31

trunk/HAL/inc/temp28.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/HAL/inc/temp10.h =================================================================== --- trunk/HAL/inc/temp10.h (nonexistent) +++ trunk/HAL/inc/temp10.h (revision 3) @@ -0,0 +1,31 @@ +//--------------------------------------------------------------------------- +// Copyright (C) 2000 Dallas Semiconductor Corporation, All Rights Reserved. +// +// Permission is hereby granted, free of charge, to any person obtaining a +// copy of this software and associated documentation files (the "Software"), +// to deal in the Software without restriction, including without limitation +// the rights to use, copy, modify, merge, publish, distribute, sublicense, +// and/or sell copies of the Software, and to permit persons to whom the +// Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included +// in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +// OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +// IN NO EVENT SHALL DALLAS SEMICONDUCTOR BE LIABLE FOR ANY CLAIM, DAMAGES +// OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +// OTHER DEALINGS IN THE SOFTWARE. +// +// Except as contained in this notice, the name of Dallas Semiconductor +// shall not be used except as stated in the Dallas Semiconductor +// Branding Policy. +// --------------------------------------------------------------------------- +// +// temp10.h - Header to read the DS1920/DS1820 - temperature measurement. +// +// --------------------------------------------------------------------------- + +int ReadTemperature10(int,uchar *,float *);

trunk/HAL/inc/temp10.h Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/demo/Terasic_DE1/DE1_soc_nios2.qsf =================================================================== --- trunk/demo/Terasic_DE1/DE1_soc_nios2.qsf (nonexistent) +++ trunk/demo/Terasic_DE1/DE1_soc_nios2.qsf (revision 3) @@ -0,0 +1,706 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + +set_global_assignment -name TOP_LEVEL_ENTITY DE1_soc_nios2 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:21:40 APRIL 17, 2010" +set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1" + +# Terasic DE1 board FPGA +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 + +# pinout +set_location_assignment PIN_A13 -to GPIO_0[0] +set_location_assignment PIN_B13 -to GPIO_0[1] +set_location_assignment PIN_A14 -to GPIO_0[2] +set_location_assignment PIN_B14 -to GPIO_0[3] +set_location_assignment PIN_A15 -to GPIO_0[4] +set_location_assignment PIN_B15 -to GPIO_0[5] +set_location_assignment PIN_A16 -to GPIO_0[6] +set_location_assignment PIN_B16 -to GPIO_0[7] +set_location_assignment PIN_A17 -to GPIO_0[8] +set_location_assignment PIN_B17 -to GPIO_0[9] +set_location_assignment PIN_A18 -to GPIO_0[10] +set_location_assignment PIN_B18 -to GPIO_0[11] +set_location_assignment PIN_A19 -to GPIO_0[12] +set_location_assignment PIN_B19 -to GPIO_0[13] +set_location_assignment PIN_A20 -to GPIO_0[14] +set_location_assignment PIN_B20 -to GPIO_0[15] +set_location_assignment PIN_C21 -to GPIO_0[16] +set_location_assignment PIN_C22 -to GPIO_0[17] +set_location_assignment PIN_D21 -to GPIO_0[18] +set_location_assignment PIN_D22 -to GPIO_0[19] +set_location_assignment PIN_E21 -to GPIO_0[20] +set_location_assignment PIN_E22 -to GPIO_0[21] +set_location_assignment PIN_F21 -to GPIO_0[22] +set_location_assignment PIN_F22 -to GPIO_0[23] +set_location_assignment PIN_G21 -to GPIO_0[24] +set_location_assignment PIN_G22 -to GPIO_0[25] +set_location_assignment PIN_J21 -to GPIO_0[26] +set_location_assignment PIN_J22 -to GPIO_0[27] +set_location_assignment PIN_K21 -to GPIO_0[28] +set_location_assignment PIN_K22 -to GPIO_0[29] +set_location_assignment PIN_J19 -to GPIO_0[30] +set_location_assignment PIN_J20 -to GPIO_0[31] +set_location_assignment PIN_J18 -to GPIO_0[32] +set_location_assignment PIN_K20 -to GPIO_0[33] +set_location_assignment PIN_L19 -to GPIO_0[34] +set_location_assignment PIN_L18 -to GPIO_0[35] +set_location_assignment PIN_H12 -to GPIO_1[0] +set_location_assignment PIN_H13 -to GPIO_1[1] +set_location_assignment PIN_H14 -to GPIO_1[2] +set_location_assignment PIN_G15 -to GPIO_1[3] +set_location_assignment PIN_E14 -to GPIO_1[4] +set_location_assignment PIN_E15 -to GPIO_1[5] +set_location_assignment PIN_F15 -to GPIO_1[6] +set_location_assignment PIN_G16 -to GPIO_1[7] +set_location_assignment PIN_F12 -to GPIO_1[8] +set_location_assignment PIN_F13 -to GPIO_1[9] +set_location_assignment PIN_C14 -to GPIO_1[10] +set_location_assignment PIN_D14 -to GPIO_1[11] +set_location_assignment PIN_D15 -to GPIO_1[12] +set_location_assignment PIN_D16 -to GPIO_1[13] +set_location_assignment PIN_C17 -to GPIO_1[14] +set_location_assignment PIN_C18 -to GPIO_1[15] +set_location_assignment PIN_C19 -to GPIO_1[16] +set_location_assignment PIN_C20 -to GPIO_1[17] +set_location_assignment PIN_D19 -to GPIO_1[18] +set_location_assignment PIN_D20 -to GPIO_1[19] +set_location_assignment PIN_E20 -to GPIO_1[20] +set_location_assignment PIN_F20 -to GPIO_1[21] +set_location_assignment PIN_E19 -to GPIO_1[22] +set_location_assignment PIN_E18 -to GPIO_1[23] +set_location_assignment PIN_G20 -to GPIO_1[24] +set_location_assignment PIN_G18 -to GPIO_1[25] +set_location_assignment PIN_G17 -to GPIO_1[26] +set_location_assignment PIN_H17 -to GPIO_1[27] +set_location_assignment PIN_J15 -to GPIO_1[28] +set_location_assignment PIN_H18 -to GPIO_1[29] +set_location_assignment PIN_N22 -to GPIO_1[30] +set_location_assignment PIN_N21 -to GPIO_1[31] +set_location_assignment PIN_P15 -to GPIO_1[32] +set_location_assignment PIN_N15 -to GPIO_1[33] +set_location_assignment PIN_P17 -to GPIO_1[34] +set_location_assignment PIN_P18 -to GPIO_1[35] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34] +set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35] +set_location_assignment PIN_L22 -to SW[0] +set_location_assignment PIN_L21 -to SW[1] +set_location_assignment PIN_M22 -to SW[2] +set_location_assignment PIN_V12 -to SW[3] +set_location_assignment PIN_W12 -to SW[4] +set_location_assignment PIN_U12 -to SW[5] +set_location_assignment PIN_U11 -to SW[6] +set_location_assignment PIN_M2 -to SW[7] +set_location_assignment PIN_M1 -to SW[8] +set_location_assignment PIN_L2 -to SW[9] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[0] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[1] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[2] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[3] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[4] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[5] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[6] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[7] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[8] +set_instance_assignment -name IO_STANDARD LVTTL -to SW[9] +set_location_assignment PIN_J2 -to HEX0[0] +set_location_assignment PIN_J1 -to HEX0[1] +set_location_assignment PIN_H2 -to HEX0[2] +set_location_assignment PIN_H1 -to HEX0[3] +set_location_assignment PIN_F2 -to HEX0[4] +set_location_assignment PIN_F1 -to HEX0[5] +set_location_assignment PIN_E2 -to HEX0[6] +set_location_assignment PIN_E1 -to HEX1[0] +set_location_assignment PIN_H6 -to HEX1[1] +set_location_assignment PIN_H5 -to HEX1[2] +set_location_assignment PIN_H4 -to HEX1[3] +set_location_assignment PIN_G3 -to HEX1[4] +set_location_assignment PIN_D2 -to HEX1[5] +set_location_assignment PIN_D1 -to HEX1[6] +set_location_assignment PIN_G5 -to HEX2[0] +set_location_assignment PIN_G6 -to HEX2[1] +set_location_assignment PIN_C2 -to HEX2[2] +set_location_assignment PIN_C1 -to HEX2[3] +set_location_assignment PIN_E3 -to HEX2[4] +set_location_assignment PIN_E4 -to HEX2[5] +set_location_assignment PIN_D3 -to HEX2[6] +set_location_assignment PIN_F4 -to HEX3[0] +set_location_assignment PIN_D5 -to HEX3[1] +set_location_assignment PIN_D6 -to HEX3[2] +set_location_assignment PIN_J4 -to HEX3[3] +set_location_assignment PIN_L8 -to HEX3[4] +set_location_assignment PIN_F3 -to HEX3[5] +set_location_assignment PIN_D4 -to HEX3[6] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5] +set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6] +set_location_assignment PIN_R22 -to KEY[0] +set_location_assignment PIN_R21 -to KEY[1] +set_location_assignment PIN_T22 -to KEY[2] +set_location_assignment PIN_T21 -to KEY[3] +set_location_assignment PIN_R20 -to LEDR[0] +set_location_assignment PIN_R19 -to LEDR[1] +set_location_assignment PIN_U19 -to LEDR[2] +set_location_assignment PIN_Y19 -to LEDR[3] +set_location_assignment PIN_T18 -to LEDR[4] +set_location_assignment PIN_V19 -to LEDR[5] +set_location_assignment PIN_Y18 -to LEDR[6] +set_location_assignment PIN_U18 -to LEDR[7] +set_location_assignment PIN_R18 -to LEDR[8] +set_location_assignment PIN_R17 -to LEDR[9] +set_location_assignment PIN_U22 -to LEDG[0] +set_location_assignment PIN_U21 -to LEDG[1] +set_location_assignment PIN_V22 -to LEDG[2] +set_location_assignment PIN_V21 -to LEDG[3] +set_location_assignment PIN_W22 -to LEDG[4] +set_location_assignment PIN_W21 -to LEDG[5] +set_location_assignment PIN_Y22 -to LEDG[6] +set_location_assignment PIN_Y21 -to LEDG[7] +set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0] +set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1] +set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2] +set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6] +set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7] +set_location_assignment PIN_D12 -to CLOCK_27[0] +set_location_assignment PIN_E12 -to CLOCK_27[1] +set_location_assignment PIN_B12 -to CLOCK_24[0] +set_location_assignment PIN_A12 -to CLOCK_24[1] +set_location_assignment PIN_L1 -to CLOCK_50 +set_location_assignment PIN_M21 -to EXT_CLOCK +set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1] +set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0] +set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1] +set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50 +set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK +set_location_assignment PIN_V20 -to SD_CLK +set_location_assignment PIN_Y20 -to SD_CMD +set_location_assignment PIN_W20 -to SD_DAT +set_location_assignment PIN_U20 -to SD_DAT3 +set_instance_assignment -name IO_STANDARD LVTTL -to SD_CLK +set_instance_assignment -name IO_STANDARD LVTTL -to SD_CMD +set_instance_assignment -name IO_STANDARD LVTTL -to SD_DAT +set_instance_assignment -name IO_STANDARD LVTTL -to SD_DAT3 +set_location_assignment PIN_H15 -to PS2_CLK +set_location_assignment PIN_J14 -to PS2_DAT +set_location_assignment PIN_F14 -to UART_RXD +set_location_assignment PIN_G12 -to UART_TXD +set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK +set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT +set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD +set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD +set_location_assignment PIN_E8 -to TDI +set_location_assignment PIN_D8 -to TCS +set_location_assignment PIN_C7 -to TCK +set_location_assignment PIN_D7 -to TDO +set_instance_assignment -name IO_STANDARD LVTTL -to TDI +set_instance_assignment -name IO_STANDARD LVTTL -to TCS +set_instance_assignment -name IO_STANDARD LVTTL -to TCK +set_instance_assignment -name IO_STANDARD LVTTL -to TDO +set_location_assignment PIN_D9 -to VGA_R[0] +set_location_assignment PIN_C9 -to VGA_R[1] +set_location_assignment PIN_A7 -to VGA_R[2] +set_location_assignment PIN_B7 -to VGA_R[3] +set_location_assignment PIN_B8 -to VGA_G[0] +set_location_assignment PIN_C10 -to VGA_G[1] +set_location_assignment PIN_B9 -to VGA_G[2] +set_location_assignment PIN_A8 -to VGA_G[3] +set_location_assignment PIN_A9 -to VGA_B[0] +set_location_assignment PIN_D11 -to VGA_B[1] +set_location_assignment PIN_A10 -to VGA_B[2] +set_location_assignment PIN_B10 -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_HS +set_location_assignment PIN_B11 -to VGA_VS +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3] +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS +set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS +set_location_assignment PIN_A3 -to I2C_SCLK +set_location_assignment PIN_B3 -to I2C_SDAT +set_location_assignment PIN_A6 -to AUD_ADCLRCK +set_location_assignment PIN_B6 -to AUD_ADCDAT +set_location_assignment PIN_A5 -to AUD_DACLRCK +set_location_assignment PIN_B5 -to AUD_DACDAT +set_location_assignment PIN_B4 -to AUD_XCK +set_location_assignment PIN_A4 -to AUD_BCLK +set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK +set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT +set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK +set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK +set_location_assignment PIN_W4 -to DRAM_ADDR[0] +set_location_assignment PIN_W5 -to DRAM_ADDR[1] +set_location_assignment PIN_Y3 -to DRAM_ADDR[2] +set_location_assignment PIN_Y4 -to DRAM_ADDR[3] +set_location_assignment PIN_R6 -to DRAM_ADDR[4] +set_location_assignment PIN_R5 -to DRAM_ADDR[5] +set_location_assignment PIN_P6 -to DRAM_ADDR[6] +set_location_assignment PIN_P5 -to DRAM_ADDR[7] +set_location_assignment PIN_P3 -to DRAM_ADDR[8] +set_location_assignment PIN_N4 -to DRAM_ADDR[9] +set_location_assignment PIN_W3 -to DRAM_ADDR[10] +set_location_assignment PIN_N6 -to DRAM_ADDR[11] +set_location_assignment PIN_U3 -to DRAM_BA[0] +set_location_assignment PIN_V4 -to DRAM_BA[1] +set_location_assignment PIN_T3 -to DRAM_CAS_N +set_location_assignment PIN_N3 -to DRAM_CKE +set_location_assignment PIN_U4 -to DRAM_CLK +set_location_assignment PIN_T6 -to DRAM_CS_N +set_location_assignment PIN_U1 -to DRAM_DQ[0] +set_location_assignment PIN_U2 -to DRAM_DQ[1] +set_location_assignment PIN_V1 -to DRAM_DQ[2] +set_location_assignment PIN_V2 -to DRAM_DQ[3] +set_location_assignment PIN_W1 -to DRAM_DQ[4] +set_location_assignment PIN_W2 -to DRAM_DQ[5] +set_location_assignment PIN_Y1 -to DRAM_DQ[6] +set_location_assignment PIN_Y2 -to DRAM_DQ[7] +set_location_assignment PIN_N1 -to DRAM_DQ[8] +set_location_assignment PIN_N2 -to DRAM_DQ[9] +set_location_assignment PIN_P1 -to DRAM_DQ[10] +set_location_assignment PIN_P2 -to DRAM_DQ[11] +set_location_assignment PIN_R1 -to DRAM_DQ[12] +set_location_assignment PIN_R2 -to DRAM_DQ[13] +set_location_assignment PIN_T1 -to DRAM_DQ[14] +set_location_assignment PIN_T2 -to DRAM_DQ[15] +set_location_assignment PIN_R7 -to DRAM_DQM[0] +set_location_assignment PIN_M5 -to DRAM_DQM[1] +set_location_assignment PIN_T5 -to DRAM_RAS_N +set_location_assignment PIN_R8 -to DRAM_WE_N +set_location_assignment PIN_AB20 -to FL_ADDR[0] +set_location_assignment PIN_AA14 -to FL_ADDR[1] +set_location_assignment PIN_Y16 -to FL_ADDR[2] +set_location_assignment PIN_R15 -to FL_ADDR[3] +set_location_assignment PIN_T15 -to FL_ADDR[4] +set_location_assignment PIN_U15 -to FL_ADDR[5] +set_location_assignment PIN_V15 -to FL_ADDR[6] +set_location_assignment PIN_W15 -to FL_ADDR[7] +set_location_assignment PIN_R14 -to FL_ADDR[8] +set_location_assignment PIN_Y13 -to FL_ADDR[9] +set_location_assignment PIN_R12 -to FL_ADDR[10] +set_location_assignment PIN_T12 -to FL_ADDR[11] +set_location_assignment PIN_AB14 -to FL_ADDR[12] +set_location_assignment PIN_AA13 -to FL_ADDR[13] +set_location_assignment PIN_AB13 -to FL_ADDR[14] +set_location_assignment PIN_AA12 -to FL_ADDR[15] +set_location_assignment PIN_AB12 -to FL_ADDR[16] +set_location_assignment PIN_AA20 -to FL_ADDR[17] +set_location_assignment PIN_U14 -to FL_ADDR[18] +set_location_assignment PIN_V14 -to FL_ADDR[19] +set_location_assignment PIN_U13 -to FL_ADDR[20] +set_location_assignment PIN_R13 -to FL_ADDR[21] +set_location_assignment PIN_AB16 -to FL_DQ[0] +set_location_assignment PIN_AA16 -to FL_DQ[1] +set_location_assignment PIN_AB17 -to FL_DQ[2] +set_location_assignment PIN_AA17 -to FL_DQ[3] +set_location_assignment PIN_AB18 -to FL_DQ[4] +set_location_assignment PIN_AA18 -to FL_DQ[5] +set_location_assignment PIN_AB19 -to FL_DQ[6] +set_location_assignment PIN_AA19 -to FL_DQ[7] +set_location_assignment PIN_AA15 -to FL_OE_N +set_location_assignment PIN_W14 -to FL_RST_N +set_location_assignment PIN_Y14 -to FL_WE_N +set_location_assignment PIN_AA3 -to SRAM_ADDR[0] +set_location_assignment PIN_AB3 -to SRAM_ADDR[1] +set_location_assignment PIN_AA4 -to SRAM_ADDR[2] +set_location_assignment PIN_AB4 -to SRAM_ADDR[3] +set_location_assignment PIN_AA5 -to SRAM_ADDR[4] +set_location_assignment PIN_AB10 -to SRAM_ADDR[5] +set_location_assignment PIN_AA11 -to SRAM_ADDR[6] +set_location_assignment PIN_AB11 -to SRAM_ADDR[7] +set_location_assignment PIN_V11 -to SRAM_ADDR[8] +set_location_assignment PIN_W11 -to SRAM_ADDR[9] +set_location_assignment PIN_R11 -to SRAM_ADDR[10] +set_location_assignment PIN_T11 -to SRAM_ADDR[11] +set_location_assignment PIN_Y10 -to SRAM_ADDR[12] +set_location_assignment PIN_U10 -to SRAM_ADDR[13] +set_location_assignment PIN_R10 -to SRAM_ADDR[14] +set_location_assignment PIN_T7 -to SRAM_ADDR[15] +set_location_assignment PIN_Y6 -to SRAM_ADDR[16] +set_location_assignment PIN_Y5 -to SRAM_ADDR[17] +set_location_assignment PIN_AB5 -to SRAM_CE_N +set_location_assignment PIN_AA6 -to SRAM_DQ[0] +set_location_assignment PIN_AB6 -to SRAM_DQ[1] +set_location_assignment PIN_AA7 -to SRAM_DQ[2] +set_location_assignment PIN_AB7 -to SRAM_DQ[3] +set_location_assignment PIN_AA8 -to SRAM_DQ[4] +set_location_assignment PIN_AB8 -to SRAM_DQ[5] +set_location_assignment PIN_AA9 -to SRAM_DQ[6] +set_location_assignment PIN_AB9 -to SRAM_DQ[7] +set_location_assignment PIN_Y9 -to SRAM_DQ[8] +set_location_assignment PIN_W9 -to SRAM_DQ[9] +set_location_assignment PIN_V9 -to SRAM_DQ[10] +set_location_assignment PIN_U9 -to SRAM_DQ[11] +set_location_assignment PIN_R9 -to SRAM_DQ[12] +set_location_assignment PIN_W8 -to SRAM_DQ[13] +set_location_assignment PIN_V8 -to SRAM_DQ[14] +set_location_assignment PIN_U8 -to SRAM_DQ[15] +set_location_assignment PIN_Y7 -to SRAM_B_N[0] +set_location_assignment PIN_T8 -to SRAM_OE_N +set_location_assignment PIN_W7 -to SRAM_B_N[1] +set_location_assignment PIN_AA10 -to SRAM_WE_N +set_location_assignment PIN_AB15 -to FL_CE_N + +# Quartus configuration + +# file list + + + + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name VERILOG_FILE DE1_soc_nios2.v +set_global_assignment -name VERILOG_FILE debouncer.v +set_global_assignment -name QIP_FILE soc.qip + +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE DE1_soc_nios2.stp +set_global_assignment -name SIGNALTAP_FILE DE1_soc_nios2.stp +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "soc:soc_i|onewire:the_onewire|clk" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "soc:soc_i|onewire:the_onewire|bus_adr" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "soc:soc_i|onewire:the_onewire|bus_irq" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "soc:soc_i|onewire:the_onewire|bus_rdt[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "soc:soc_i|onewire:the_onewire|bus_rdt[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "soc:soc_i|onewire:the_onewire|bus_rdt[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "soc:soc_i|onewire:the_onewire|bus_rdt[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "soc:soc_i|onewire:the_onewire|bus_rdt[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "soc:soc_i|onewire:the_onewire|bus_rdt[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "soc:soc_i|onewire:the_onewire|bus_rdt[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "soc:soc_i|onewire:the_onewire|bus_rdt[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "soc:soc_i|onewire:the_onewire|bus_rdt[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "soc:soc_i|onewire:the_onewire|bus_rdt[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "soc:soc_i|onewire:the_onewire|bus_rdt[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "soc:soc_i|onewire:the_onewire|bus_rdt[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "soc:soc_i|onewire:the_onewire|bus_rdt[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "soc:soc_i|onewire:the_onewire|bus_rdt[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "soc:soc_i|onewire:the_onewire|bus_rdt[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "soc:soc_i|onewire:the_onewire|bus_rdt[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "soc:soc_i|onewire:the_onewire|bus_rdt[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "soc:soc_i|onewire:the_onewire|bus_rdt[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "soc:soc_i|onewire:the_onewire|bus_rdt[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "soc:soc_i|onewire:the_onewire|bus_rdt[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "soc:soc_i|onewire:the_onewire|bus_rdt[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "soc:soc_i|onewire:the_onewire|bus_rdt[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "soc:soc_i|onewire:the_onewire|bus_rdt[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "soc:soc_i|onewire:the_onewire|bus_rdt[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "soc:soc_i|onewire:the_onewire|bus_rdt[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "soc:soc_i|onewire:the_onewire|bus_rdt[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "soc:soc_i|onewire:the_onewire|bus_rdt[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "soc:soc_i|onewire:the_onewire|bus_rdt[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "soc:soc_i|onewire:the_onewire|bus_rdt[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "soc:soc_i|onewire:the_onewire|bus_rdt[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "soc:soc_i|onewire:the_onewire|bus_rdt[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "soc:soc_i|onewire:the_onewire|bus_rdt[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "soc:soc_i|onewire:the_onewire|bus_ren" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "soc:soc_i|onewire:the_onewire|bus_wdt[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "soc:soc_i|onewire:the_onewire|bus_wdt[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "soc:soc_i|onewire:the_onewire|bus_wdt[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "soc:soc_i|onewire:the_onewire|bus_wdt[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "soc:soc_i|onewire:the_onewire|bus_wdt[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "soc:soc_i|onewire:the_onewire|bus_wdt[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "soc:soc_i|onewire:the_onewire|bus_wdt[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "soc:soc_i|onewire:the_onewire|bus_wdt[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "soc:soc_i|onewire:the_onewire|bus_wdt[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "soc:soc_i|onewire:the_onewire|bus_wdt[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "soc:soc_i|onewire:the_onewire|bus_wdt[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "soc:soc_i|onewire:the_onewire|bus_wdt[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "soc:soc_i|onewire:the_onewire|bus_wdt[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "soc:soc_i|onewire:the_onewire|bus_wdt[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "soc:soc_i|onewire:the_onewire|bus_wdt[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "soc:soc_i|onewire:the_onewire|bus_wdt[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "soc:soc_i|onewire:the_onewire|bus_wdt[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "soc:soc_i|onewire:the_onewire|bus_wdt[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "soc:soc_i|onewire:the_onewire|bus_wdt[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "soc:soc_i|onewire:the_onewire|bus_wdt[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "soc:soc_i|onewire:the_onewire|bus_wdt[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "soc:soc_i|onewire:the_onewire|bus_wdt[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "soc:soc_i|onewire:the_onewire|bus_wdt[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "soc:soc_i|onewire:the_onewire|bus_wdt[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "soc:soc_i|onewire:the_onewire|bus_wdt[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "soc:soc_i|onewire:the_onewire|bus_wdt[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "soc:soc_i|onewire:the_onewire|bus_wdt[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "soc:soc_i|onewire:the_onewire|bus_wdt[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "soc:soc_i|onewire:the_onewire|bus_wdt[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "soc:soc_i|onewire:the_onewire|bus_wdt[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "soc:soc_i|onewire:the_onewire|bus_wdt[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "soc:soc_i|onewire:the_onewire|bus_wdt[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "soc:soc_i|onewire:the_onewire|bus_wen" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "soc:soc_i|onewire:the_onewire|owr_e" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "soc:soc_i|onewire:the_onewire|owr_i" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "soc:soc_i|onewire:the_onewire|owr_p" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "soc:soc_i|onewire:the_onewire|rst" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[0] -to "soc:soc_i|onewire:the_onewire|bus_adr" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[1] -to "soc:soc_i|onewire:the_onewire|bus_irq" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[2] -to "soc:soc_i|onewire:the_onewire|bus_rdt[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[3] -to "soc:soc_i|onewire:the_onewire|bus_rdt[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[4] -to "soc:soc_i|onewire:the_onewire|bus_rdt[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[5] -to "soc:soc_i|onewire:the_onewire|bus_rdt[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[6] -to "soc:soc_i|onewire:the_onewire|bus_rdt[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[7] -to "soc:soc_i|onewire:the_onewire|bus_rdt[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[8] -to "soc:soc_i|onewire:the_onewire|bus_rdt[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[9] -to "soc:soc_i|onewire:the_onewire|bus_rdt[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[10] -to "soc:soc_i|onewire:the_onewire|bus_rdt[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[11] -to "soc:soc_i|onewire:the_onewire|bus_rdt[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[12] -to "soc:soc_i|onewire:the_onewire|bus_rdt[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[13] -to "soc:soc_i|onewire:the_onewire|bus_rdt[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[14] -to "soc:soc_i|onewire:the_onewire|bus_rdt[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[15] -to "soc:soc_i|onewire:the_onewire|bus_rdt[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[16] -to "soc:soc_i|onewire:the_onewire|bus_rdt[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[17] -to "soc:soc_i|onewire:the_onewire|bus_rdt[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[18] -to "soc:soc_i|onewire:the_onewire|bus_rdt[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[19] -to "soc:soc_i|onewire:the_onewire|bus_rdt[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[20] -to "soc:soc_i|onewire:the_onewire|bus_rdt[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[21] -to "soc:soc_i|onewire:the_onewire|bus_rdt[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[22] -to "soc:soc_i|onewire:the_onewire|bus_rdt[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[23] -to "soc:soc_i|onewire:the_onewire|bus_rdt[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[24] -to "soc:soc_i|onewire:the_onewire|bus_rdt[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[25] -to "soc:soc_i|onewire:the_onewire|bus_rdt[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[26] -to "soc:soc_i|onewire:the_onewire|bus_rdt[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[27] -to "soc:soc_i|onewire:the_onewire|bus_rdt[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[28] -to "soc:soc_i|onewire:the_onewire|bus_rdt[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[29] -to "soc:soc_i|onewire:the_onewire|bus_rdt[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[30] -to "soc:soc_i|onewire:the_onewire|bus_rdt[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[31] -to "soc:soc_i|onewire:the_onewire|bus_rdt[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[32] -to "soc:soc_i|onewire:the_onewire|bus_rdt[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[33] -to "soc:soc_i|onewire:the_onewire|bus_rdt[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[34] -to "soc:soc_i|onewire:the_onewire|bus_ren" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[35] -to "soc:soc_i|onewire:the_onewire|bus_wdt[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[36] -to "soc:soc_i|onewire:the_onewire|bus_wdt[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[37] -to "soc:soc_i|onewire:the_onewire|bus_wdt[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[38] -to "soc:soc_i|onewire:the_onewire|bus_wdt[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[39] -to "soc:soc_i|onewire:the_onewire|bus_wdt[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[40] -to "soc:soc_i|onewire:the_onewire|bus_wdt[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[41] -to "soc:soc_i|onewire:the_onewire|bus_wdt[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[42] -to "soc:soc_i|onewire:the_onewire|bus_wdt[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[43] -to "soc:soc_i|onewire:the_onewire|bus_wdt[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[44] -to "soc:soc_i|onewire:the_onewire|bus_wdt[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[45] -to "soc:soc_i|onewire:the_onewire|bus_wdt[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[46] -to "soc:soc_i|onewire:the_onewire|bus_wdt[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[47] -to "soc:soc_i|onewire:the_onewire|bus_wdt[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[48] -to "soc:soc_i|onewire:the_onewire|bus_wdt[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[49] -to "soc:soc_i|onewire:the_onewire|bus_wdt[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[50] -to "soc:soc_i|onewire:the_onewire|bus_wdt[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[51] -to "soc:soc_i|onewire:the_onewire|bus_wdt[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[52] -to "soc:soc_i|onewire:the_onewire|bus_wdt[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[53] -to "soc:soc_i|onewire:the_onewire|bus_wdt[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[54] -to "soc:soc_i|onewire:the_onewire|bus_wdt[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[55] -to "soc:soc_i|onewire:the_onewire|bus_wdt[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[56] -to "soc:soc_i|onewire:the_onewire|bus_wdt[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[57] -to "soc:soc_i|onewire:the_onewire|bus_wdt[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[58] -to "soc:soc_i|onewire:the_onewire|bus_wdt[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[59] -to "soc:soc_i|onewire:the_onewire|bus_wdt[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[60] -to "soc:soc_i|onewire:the_onewire|bus_wdt[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[61] -to "soc:soc_i|onewire:the_onewire|bus_wdt[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[62] -to "soc:soc_i|onewire:the_onewire|bus_wdt[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[63] -to "soc:soc_i|onewire:the_onewire|bus_wdt[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[64] -to "soc:soc_i|onewire:the_onewire|bus_wdt[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[65] -to "soc:soc_i|onewire:the_onewire|bus_wdt[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[66] -to "soc:soc_i|onewire:the_onewire|bus_wdt[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[67] -to "soc:soc_i|onewire:the_onewire|bus_wen" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[68] -to "soc:soc_i|onewire:the_onewire|owr_e" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[69] -to "soc:soc_i|onewire:the_onewire|owr_i" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[70] -to "soc:soc_i|onewire:the_onewire|owr_p" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[71] -to "soc:soc_i|onewire:the_onewire|rst" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_GAP_RECORD=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "soc:soc_i|onewire:the_onewire|bus_ren" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "soc:soc_i|onewire:the_onewire|bus_wen" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=2" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_MODE=TRANSITIONAL" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[72] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[73] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[74] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[75] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[76] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[77] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[78] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_n[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[79] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[80] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[81] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[82] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[83] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[84] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_storage_qualifier_in[85] -to "soc:soc_i|onewire:the_onewire|sockit_owm:onewire|cdr_o[6]" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=86" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=86" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=116" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=87" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=56357" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=33129" -section_id auto_signaltap_0 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: trunk/demo/Terasic_DE1/soc.sopcinfo =================================================================== --- trunk/demo/Terasic_DE1/soc.sopcinfo (nonexistent) +++ trunk/demo/Terasic_DE1/soc.sopcinfo (revision 3) @@ -0,0 +1,12260 @@ + + + + + + + com.altera.entityinterfaces.moduleext.IDeviceFamily$EDeviceFamily + CYCLONEII + false + true + true + true + + + com.altera.sopcmodel.ensemble.Ensemble$EFabricMode + SOPC + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage + VERILOG + false + true + true + true + + + java.lang.String + DE1_soc_nios2.qpf + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 30150066089 + false + true + true + true + + + long + 1294693433376 + false + true + true + true + + + + + long + 24000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + clk_in + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + false + true + + + long + 24000000 + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + cpu + clk + cpu.clk + + + false + jtag_uart + clk + jtag_uart.clk + + + false + uart + clk + uart.clk + + + false + onchip_ram + clk1 + onchip_ram.clk1 + + + false + sdram + clk + sdram.clk + + + false + pio_7seg + clk + pio_7seg.clk + + + false + pio_ledg + clk + pio_ledg.clk + + + false + pio_ledr + clk + pio_ledr.clk + + + false + epcs_flash + clk + epcs_flash.clk + + + false + cfi_flash + clk + cfi_flash.clk + + + false + tri_state_bridge_flash + clk + tri_state_bridge_flash.clk + + + false + sysid + clk + sysid.clk + + + false + timer + clk + timer.clk + + + false + onewire + clock_reset + onewire.clock_reset + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + embeddedsw.configuration.cpuArchitecture + Nios II + + + embeddedsw.configuration.HDLSimCachesCleared + 1 + + + embeddedsw.CMacro.CPU_IMPLEMENTATION + "tiny" + + + embeddedsw.CMacro.BIG_ENDIAN + 0 + + + embeddedsw.CMacro.CPU_FREQ + 24000000u + + + embeddedsw.CMacro.ICACHE_LINE_SIZE + 0 + + + embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2 + 0 + + + embeddedsw.CMacro.ICACHE_SIZE + 0 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE + 0 + + + embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2 + 0 + + + embeddedsw.CMacro.DCACHE_SIZE + 0 + + + embeddedsw.CMacro.FLUSHDA_SUPPORTED + + + + embeddedsw.CMacro.HAS_JMPI_INSTRUCTION + + + + embeddedsw.configuration.resetSlave + onchip_ram.s1 + + + embeddedsw.configuration.resetOffset + 0 + + + embeddedsw.configuration.exceptionSlave + onchip_ram.s1 + + + embeddedsw.configuration.exceptionOffset + 32 + + + embeddedsw.configuration.breakSlave + cpu.jtag_debug_module + + + embeddedsw.configuration.breakOffset + 32 + + + embeddedsw.CMacro.EXCEPTION_ADDR + 0x1804020 + + + embeddedsw.CMacro.RESET_ADDR + 0x1804000 + + + embeddedsw.CMacro.BREAK_ADDR + 0x1809020 + + + embeddedsw.CMacro.HAS_DEBUG_STUB + + + + embeddedsw.CMacro.HAS_DEBUG_CORE + 1 + + + embeddedsw.CMacro.CPU_ID_SIZE + 1 + + + embeddedsw.CMacro.CPU_ID_VALUE + 0x0 + + + embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_MULX_PRESENT + 0 + + + embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT + 0 + + + embeddedsw.CMacro.INST_ADDR_WIDTH + 25 + + + embeddedsw.CMacro.DATA_ADDR_WIDTH + 25 + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptPerfCounterWidth + _32 + false + false + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptInterruptControllerType + Internal + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptBranchPredictionType + Automatic + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.nios2.components.Nios2InternalSettings$OptBhtPtrSz + _8 + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + onchip_ram.s1 + false + true + true + true + + + long + 0 + false + true + true + true + + + com.altera.nios2.components.Nios2MultiplierDivider$OptMultiplier + EmbeddedMulFast + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + false + false + false + true + true + + + int + 8 + false + false + true + true + + + int + 8 + false + false + true + true + + + com.altera.nios2.components.Nios2MPU$OptRegionSize + _12 + false + false + true + true + + + com.altera.nios2.components.Nios2MPU$OptRegionSize + _12 + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbNumEntries + _4 + false + false + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbNumEntries + _6 + false + false + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbPtrSz + _7 + false + false + true + true + + + com.altera.nios2.components.Nios2MMU$OptTlbNumWays + _16 + false + false + true + true + + + com.altera.nios2.components.Nios2MMU$OptProcessIDNumBits + _8 + false + false + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + false + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + false + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + true + true + + + long + 31 + false + true + true + true + + + java.lang.String + ]]> + false + true + true + true + + + int + 25 + false + true + true + true + + + com.altera.nios2.components.INios2Component$Impl + Tiny + false + true + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptBytes + _4096 + false + false + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptRamBlockType + Automatic + false + false + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptNumTCM + _0 + false + false + true + true + + + com.altera.nios2.components.Nios2ICache$OptBurstType + None + false + false + true + true + + + com.altera.entityinterfaces.IConnectionPoint + onchip_ram.s1 + false + true + true + true + + + long + 32 + false + true + true + true + + + java.lang.String + M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 + false + true + true + true + + + java.lang.String + Cyclone II + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.nios2.components.Nios2Debug$OptLevel + Level1 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + true + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.nios2.components.Nios2Debug$OptOCIOnchipTrace + _128 + false + false + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptBytes + _2048 + false + false + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptRamBlockType + Automatic + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.nios2.components.Nios2AbstractCache$OptNumTCM + _0 + false + false + true + true + + + com.altera.nios2.components.Nios2DCache$OptLineSize + _32 + false + false + true + true + + + boolean + false + false + false + true + true + + + java.lang.String + ]]> + false + true + true + true + + + int + 25 + false + true + true + true + + + boolean + false + false + true + true + true + + + long + 0 + false + false + true + true + + + long + 24000000 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + cpu.jtag_debug_module + false + false + true + true + + + long + 32 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + i_address + Output + 25 + address + + + i_read + Output + 1 + read + + + i_readdata + Input + 32 + readdata + + + i_readdatavalid + Input + 1 + readdatavalid + + + i_waitrequest + Input + 1 + waitrequest + + + false + cpu + jtag_debug_module + cpu.jtag_debug_module + 25202688 + 2048 + + + false + onchip_ram + s1 + onchip_ram.s1 + 25182208 + 4096 + + + false + sdram + s1 + sdram.s1 + 8388608 + 8388608 + + + false + epcs_flash + epcs_control_port + epcs_flash.epcs_control_port + 25204736 + 2048 + + + false + cfi_flash + s1 + cfi_flash.s1 + 20971520 + 4194304 + + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 1 + false + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + SYMBOLS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + false + true + + + int + 0 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + true + + d_address + Output + 25 + address + + + d_byteenable + Output + 4 + byteenable + + + d_read + Output + 1 + read + + + d_readdata + Input + 32 + readdata + + + d_readdatavalid + Input + 1 + readdatavalid + + + d_waitrequest + Input + 1 + waitrequest + + + d_write + Output + 1 + write + + + d_writedata + Output + 32 + writedata + + + jtag_debug_module_debugaccess_to_roms + Output + 1 + debugaccess + + + false + cpu + jtag_debug_module + cpu.jtag_debug_module + 25202688 + 2048 + + + false + jtag_uart + avalon_jtag_slave + jtag_uart.avalon_jtag_slave + 25206784 + 8 + + + false + uart + s1 + uart.s1 + 25206816 + 32 + + + false + onchip_ram + s1 + onchip_ram.s1 + 25182208 + 4096 + + + false + sdram + s1 + sdram.s1 + 8388608 + 8388608 + + + false + pio_7seg + s1 + pio_7seg.s1 + 25206848 + 16 + + + false + pio_ledg + s1 + pio_ledg.s1 + 25206864 + 16 + + + false + pio_ledr + s1 + pio_ledr.s1 + 25206880 + 16 + + + false + epcs_flash + epcs_control_port + epcs_flash.epcs_control_port + 25204736 + 2048 + + + false + cfi_flash + s1 + cfi_flash.s1 + 20971520 + 4194304 + + + false + sysid + control_slave + sysid.control_slave + 25206912 + 8 + + + false + timer + s1 + timer.s1 + 25206944 + 32 + + + false + onewire + s1 + onewire.s1 + 1575536 + 8 + + + + + + com.altera.entityinterfaces.IConnectionPoint + cpu.data_master + false + true + true + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + INDIVIDUAL_REQUESTS + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + true + + d_irq + Input + 32 + irq + + + false + jtag_uart + irq + jtag_uart.irq + 1 + + + false + uart + irq + uart.irq + 2 + + + false + epcs_flash + irq + epcs_flash.irq + 0 + + + false + timer + irq + timer.irq + 4 + + + false + onewire + irq + onewire.irq + 3 + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.hideDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + jtag_debug_module_address + Input + 9 + address + + + jtag_debug_module_begintransfer + Input + 1 + begintransfer + + + jtag_debug_module_byteenable + Input + 4 + byteenable + + + jtag_debug_module_debugaccess + Input + 1 + debugaccess + + + jtag_debug_module_readdata + Output + 32 + readdata + + + jtag_debug_module_resetrequest + Output + 1 + resetrequest + + + jtag_debug_module_select + Input + 1 + chipselect + + + jtag_debug_module_write + Input + 1 + write + + + jtag_debug_module_writedata + Input + 32 + writedata + + + + + + java.lang.String + + true + true + false + true + + + int + 8 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 0 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + nios_custom_instruction + true + + dataa + Output + 32 + dataa + + + datab + Output + 32 + datab + + + result + Input + 32 + result + + + clk_en + Output + 1 + clk_en + + + reset + Output + 1 + reset + + + start + Output + 1 + start + + + done + Input + 1 + done + + + n + Output + 8 + n + + + a + Output + 5 + a + + + b + Output + 5 + b + + + c + Output + 5 + c + + + readra + Output + 1 + readra + + + readrb + Output + 1 + readrb + + + writerc + Output + 1 + writerc + + + + + + + embeddedsw.CMacro.WRITE_DEPTH + 16 + + + embeddedsw.CMacro.READ_DEPTH + 16 + + + embeddedsw.CMacro.WRITE_THRESHOLD + 8 + + + embeddedsw.CMacro.READ_THRESHOLD + 8 + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonJtagUART.AlteraAvalonJtagUART$JtagSimulationOptions + INTERACTIVE_ASCII_OUTPUT + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 16 + false + true + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + rst_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + av_chipselect + Input + 1 + chipselect + + + av_address + Input + 1 + address + + + av_read_n + Input + 1 + read_n + + + av_readdata + Output + 32 + readdata + + + av_write_n + Input + 1 + write_n + + + av_writedata + Input + 32 + writedata + + + av_waitrequest + Output + 1 + waitrequest + + + dataavailable + Output + 1 + dataavailable + + + readyfordata + Output + 1 + readyfordata + + + + + + com.altera.entityinterfaces.IConnectionPoint + jtag_uart.avalon_jtag_slave + false + true + true + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + av_irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.BAUD + 115200 + + + embeddedsw.CMacro.DATA_BITS + 8 + + + embeddedsw.CMacro.FIXED_BAUD + 1 + + + embeddedsw.CMacro.PARITY + 'N' + + + embeddedsw.CMacro.STOP_BITS + 1 + + + embeddedsw.CMacro.SYNC_REG_DEPTH + 2 + + + embeddedsw.CMacro.USE_CTS_RTS + 0 + + + embeddedsw.CMacro.USE_EOP_REGISTER + 0 + + + embeddedsw.CMacro.SIM_TRUE_BAUD + 0 + + + embeddedsw.CMacro.SIM_CHAR_STREAM + "" + + + embeddedsw.CMacro.FREQ + 24000000u + + + int + 115200 + false + true + true + true + + + double + 0.16 + true + true + true + true + + + long + 24000000 + false + true + true + true + + + int + 8 + false + true + true + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonUART.AlteraAvalonUART$UartParity + NONE + false + true + true + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 2 + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isPrintableDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + true + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + begintransfer + Input + 1 + begintransfer + + + chipselect + Input + 1 + chipselect + + + read_n + Input + 1 + read_n + + + write_n + Input + 1 + write_n + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + dataavailable + Output + 1 + dataavailable + + + readyfordata + Output + 1 + readyfordata + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + rxd + Input + 1 + export + + + txd + Output + 1 + export + + + + + + com.altera.entityinterfaces.IConnectionPoint + uart.s1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE + 0 + + + embeddedsw.CMacro.INIT_CONTENTS_FILE + "onchip_ram" + + + embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED + 0 + + + embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE + "Automatic" + + + embeddedsw.CMacro.WRITABLE + 1 + + + embeddedsw.CMacro.DUAL_PORT + 0 + + + embeddedsw.CMacro.SIZE_VALUE + 4096u + + + embeddedsw.CMacro.SIZE_MULTIPLE + 1 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.CMacro.RAM_BLOCK_TYPE + "Auto" + + + embeddedsw.CMacro.INIT_MEM_CONTENT + 1 + + + embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR + 0 + + + embeddedsw.CMacro.INSTANCE_ID + "NONE" + + + embeddedsw.CMacro.READ_DURING_WRITE_MODE + "DONT_CARE" + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + QPF_DIR + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$BlockType + AUTO + false + true + true + true + + + int + 32 + false + true + true + true + + + java.lang.String + Cyclone II + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + java.lang.String + onchip_ram + false + false + true + true + + + java.lang.String + NONE + false + false + true + true + + + long + 4096 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonOnchipMemory.AlteraAvalonOnchipMemory$ReadDuringWriteMode + DONT_CARE + false + false + true + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 4096 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk1 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 4096 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 10 + address + + + chipselect + Input + 1 + chipselect + + + clken + Input + 1 + clken + + + readdata + Output + 32 + readdata + + + write + Input + 1 + write + + + writedata + Input + 32 + writedata + + + byteenable + Input + 4 + byteenable + + + + + + + embeddedsw.CMacro.REGISTER_DATA_IN + 1 + + + embeddedsw.CMacro.SIM_MODEL_BASE + 1 + + + embeddedsw.CMacro.SDRAM_DATA_WIDTH + 16 + + + embeddedsw.CMacro.SDRAM_ADDR_WIDTH + 22 + + + embeddedsw.CMacro.SDRAM_ROW_WIDTH + 12 + + + embeddedsw.CMacro.SDRAM_COL_WIDTH + 8 + + + embeddedsw.CMacro.SDRAM_NUM_CHIPSELECTS + 1 + + + embeddedsw.CMacro.SDRAM_NUM_BANKS + 4 + + + embeddedsw.CMacro.REFRESH_PERIOD + 15.625 + + + embeddedsw.CMacro.POWERUP_DELAY + 100.0 + + + embeddedsw.CMacro.CAS_LATENCY + 3 + + + embeddedsw.CMacro.T_RFC + 70.0 + + + embeddedsw.CMacro.T_RP + 20.0 + + + embeddedsw.CMacro.T_MRD + 3 + + + embeddedsw.CMacro.T_RCD + 20.0 + + + embeddedsw.CMacro.T_AC + 5.5 + + + embeddedsw.CMacro.T_WR + 14.0 + + + embeddedsw.CMacro.INIT_REFRESH_COMMANDS + 2 + + + embeddedsw.CMacro.INIT_NOP_DELAY + 0.0 + + + embeddedsw.CMacro.SHARED_DATA + 0 + + + embeddedsw.CMacro.STARVATION_INDICATOR + 0 + + + embeddedsw.CMacro.TRISTATE_BRIDGE_SLAVE + "" + + + embeddedsw.CMacro.IS_INITIALIZED + 1 + + + embeddedsw.CMacro.SDRAM_BANK_WIDTH + 2 + + + embeddedsw.CMacro.CONTENTS_INFO + "" + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 16 + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + double + 5.5 + false + true + true + true + + + long + 3 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 70.0 + false + true + true + true + + + double + 20.0 + false + true + true + true + + + double + 14.0 + false + true + true + true + + + int + 3 + false + true + true + true + + + long + 24000000 + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 16 + false + true + true + true + + + boolean + true + false + true + true + true + + + double + 0.0 + false + true + true + true + + + int + 2 + false + true + true + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonSDRAMController.ModelMangler$PresetModels + custom + false + true + true + true + + + int + 4 + false + true + true + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 100.0 + false + true + true + true + + + double + 15.625 + false + true + true + true + + + boolean + true + false + true + true + true + + + int + 12 + false + true + true + true + + + long + 8388608 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isMemoryDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8388608 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 7 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + false + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + false + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + az_addr + Input + 22 + address + + + az_be_n + Input + 2 + byteenable_n + + + az_cs + Input + 1 + chipselect + + + az_data + Input + 16 + writedata + + + az_rd_n + Input + 1 + read_n + + + az_wr_n + Input + 1 + write_n + + + za_data + Output + 16 + readdata + + + za_valid + Output + 1 + readdatavalid + + + za_waitrequest + Output + 1 + waitrequest + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + zs_addr + Output + 12 + export + + + zs_ba + Output + 2 + export + + + zs_cas_n + Output + 1 + export + + + zs_cke + Output + 1 + export + + + zs_cs_n + Output + 1 + export + + + zs_dq + Bidir + 16 + export + + + zs_dqm + Output + 2 + export + + + zs_ras_n + Output + 1 + export + + + zs_we_n + Output + 1 + export + + + + + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0x0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 32 + + + embeddedsw.CMacro.RESET_VALUE + 0x0 + + + embeddedsw.CMacro.EDGE_TYPE + "NONE" + + + embeddedsw.CMacro.IRQ_TYPE + "NONE" + + + embeddedsw.CMacro.FREQ + 24000000u + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 24000000 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$Direction + Output + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$EdgeType + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$IrqType + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 32 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 32 + readdata + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 32 + export + + + + + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0x0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 8 + + + embeddedsw.CMacro.RESET_VALUE + 0x0 + + + embeddedsw.CMacro.EDGE_TYPE + "NONE" + + + embeddedsw.CMacro.IRQ_TYPE + "NONE" + + + embeddedsw.CMacro.FREQ + 24000000u + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 24000000 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$Direction + Output + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$EdgeType + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$IrqType + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 8 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 8 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 8 + readdata + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 8 + export + + + + + + + embeddedsw.CMacro.DO_TEST_BENCH_WIRING + 0 + + + embeddedsw.CMacro.DRIVEN_SIM_VALUE + 0x0 + + + embeddedsw.CMacro.HAS_TRI + 0 + + + embeddedsw.CMacro.HAS_OUT + 1 + + + embeddedsw.CMacro.HAS_IN + 0 + + + embeddedsw.CMacro.CAPTURE + 0 + + + embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER + 0 + + + embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER + 0 + + + embeddedsw.CMacro.DATA_WIDTH + 10 + + + embeddedsw.CMacro.RESET_VALUE + 0x0 + + + embeddedsw.CMacro.EDGE_TYPE + "NONE" + + + embeddedsw.CMacro.IRQ_TYPE + "NONE" + + + embeddedsw.CMacro.FREQ + 24000000u + + + boolean + false + false + false + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 24000000 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$Direction + Output + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$EdgeType + RISING + false + false + true + true + + + boolean + false + false + false + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonPIO.AlteraAvalonPIO$IrqType + LEVEL + false + false + true + true + + + long + 0 + false + true + true + true + + + boolean + false + false + false + true + true + + + long + 0 + false + false + true + true + + + int + 10 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 4 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 2 + address + + + write_n + Input + 1 + write_n + + + writedata + Input + 10 + writedata + + + chipselect + Input + 1 + chipselect + + + readdata + Output + 10 + readdata + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + out_port + Output + 10 + export + + + + + + + embeddedsw.CMacro.REGISTER_OFFSET + 512 + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 32 + + + embeddedsw.memoryInfo.MEM_INIT_FILENAME + epcs_flash_boot_rom + + + embeddedsw.memoryInfo.IS_EPCS + 1 + + + embeddedsw.memoryInfo.IS_FLASH + 1 + + + embeddedsw.memoryInfo.GENERATE_HEX + 1 + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_FLASH + 1 + + + embeddedsw.memoryInfo.HEX_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.FLASH_INSTALL_DIR + APP_DIR + + + boolean + true + false + true + true + true + + + java.lang.String + Cyclone II + false + true + false + true + + + boolean + true + false + false + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isNonVolatileStorage + 1 + + + embeddedsw.configuration.isFlash + 1 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2048 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 9 + address + + + chipselect + Input + 1 + chipselect + + + dataavailable + Output + 1 + dataavailable + + + endofpacket + Output + 1 + endofpacket + + + read_n + Input + 1 + read_n + + + readdata + Output + 32 + readdata + + + readyfordata + Output + 1 + readyfordata + + + write_n + Input + 1 + write_n + + + writedata + Input + 32 + writedata + + + + + + com.altera.entityinterfaces.IConnectionPoint + epcs_flash.epcs_control_port + false + true + true + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.SETUP_VALUE + 90 + + + embeddedsw.CMacro.WAIT_VALUE + 0 + + + embeddedsw.CMacro.HOLD_VALUE + 0 + + + embeddedsw.CMacro.TIMING_UNITS + "ns" + + + embeddedsw.CMacro.SIZE + 4194304u + + + embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH + 8 + + + embeddedsw.memoryInfo.HAS_BYTE_LANE + 0 + + + embeddedsw.memoryInfo.IS_FLASH + 1 + + + embeddedsw.memoryInfo.GENERATE_DAT_SYM + 1 + + + embeddedsw.memoryInfo.GENERATE_FLASH + 1 + + + embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR + SIM_DIR + + + embeddedsw.memoryInfo.FLASH_INSTALL_DIR + APP_DIR + + + double + 0.0 + true + true + true + true + + + double + 125.0 + true + true + true + true + + + double + 0.0 + true + true + true + true + + + int + 22 + false + true + true + true + + + long + 24000000 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonCommonFlashInterface.FlashCorePresets + CUSTOM + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 90 + false + true + true + true + + + [Ljava.lang.String; + + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonCommonFlashInterface.FlashTimingUnits + NS + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + + + + embeddedsw.configuration.isNonVolatileStorage + 1 + + + embeddedsw.configuration.isFlash + 1 + + + embeddedsw.configuration.isMemoryDevice + 1 + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + long + 4194304 + true + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 90 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Nanoseconds + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_tristate + false + + data + Bidir + 8 + data + + + address + Input + 22 + address + + + read_n + Input + 1 + read_n + + + write_n + Input + 1 + write_n + + + select_n + Input + 1 + chipselect_n + + + + + + + boolean + true + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 1 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + tri_state_bridge_flash.tristate_master + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + true + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + true + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 32 + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_tristate + true + + false + cfi_flash + s1 + cfi_flash.s1 + 20971520 + 4194304 + + + + + + + embeddedsw.CMacro.ID + 85295031u + + + embeddedsw.CMacro.TIMESTAMP + 1294693433u + + + long + 85295031 + true + true + true + true + + + long + 1294693433 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clock + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 2 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 1 + address + + + readdata + Output + 32 + readdata + + + + + + + embeddedsw.CMacro.ALWAYS_RUN + 0 + + + embeddedsw.CMacro.FIXED_PERIOD + 0 + + + embeddedsw.CMacro.SNAPSHOT + 1 + + + embeddedsw.CMacro.PERIOD + 1 + + + embeddedsw.CMacro.PERIOD_UNITS + "ms" + + + embeddedsw.CMacro.RESET_OUTPUT + 0 + + + embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT + 0 + + + embeddedsw.CMacro.FREQ + 24000000u + + + embeddedsw.CMacro.LOAD_VALUE + 23999ULL + + + embeddedsw.CMacro.COUNTER_SIZE + 32 + + + embeddedsw.CMacro.MULT + 0.0010 + + + embeddedsw.CMacro.TICKS_PER_SEC + 1000u + + + boolean + false + false + true + true + true + + + int + 32 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.AlteraAvalonTimer$TimerPeriodUnit + MSEC + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 24000000 + false + true + true + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.components.avalon.AlteraAvalonTimer.TimerPresets + CUSTOM + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + reset_n + Input + 1 + reset_n + + + + + + embeddedsw.configuration.isTimerDevice + 1 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + NATIVE + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + writedata + Input + 16 + writedata + + + readdata + Output + 16 + readdata + + + chipselect + Input + 1 + chipselect + + + write_n + Input + 1 + write_n + + + + + + com.altera.entityinterfaces.IConnectionPoint + timer.s1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + irq + Output + 1 + irq + + + + + + + embeddedsw.CMacro.BTP_N + "5.0" + + + embeddedsw.CMacro.BTP_O + "1.0" + + + embeddedsw.CMacro.CDR_E + 0 + + + embeddedsw.CMacro.CDR_N + 119 + + + embeddedsw.CMacro.CDR_O + 23 + + + embeddedsw.CMacro.F_DLY + 65536 + + + embeddedsw.CMacro.OVD_E + 1 + + + embeddedsw.CMacro.OWN + 2 + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 32 + false + false + false + true + + + int + 1 + false + false + false + true + + + int + 2 + false + true + true + true + + + java.lang.String + 5.0 + false + true + true + true + + + java.lang.String + 1.0 + false + true + true + true + + + int + 24000000 + false + true + true + true + + + int + 119 + true + true + true + true + + + int + 23 + true + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 24000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clock_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + rst + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + true + true + + + int + 0 + false + true + false + true + + + long + 8 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + false + false + true + false + true + + + java.lang.String + clock_reset + false + true + false + true + + + java.lang.String + clock_reset_reset + false + true + false + true + + + int + 8 + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + false + true + + + boolean + true + false + true + false + true + + + long + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + bus_ren + Input + 1 + read + + + bus_wen + Input + 1 + write + + + bus_adr + Input + 1 + address + + + bus_wdt + Input + 32 + writedata + + + bus_rdt + Output + 32 + readdata + + + + + + com.altera.entityinterfaces.IConnectionPoint + onewire.s1 + false + true + true + true + + + java.lang.String + clock_reset + false + true + false + true + + + java.lang.String + clock_reset_reset + false + true + false + true + + + com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme + NONE + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + interrupt + false + + bus_irq + Output + 1 + irq + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + owr_p + Output + 2 + export + + + owr_e + Output + 2 + export + + + owr_i + Input + 2 + export + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + cpu + clk + + + + int + 1 + false + true + true + true + + + long + 0x01809000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + cpu + jtag_debug_module + + + + int + 1 + false + true + true + true + + + long + 0x01809000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + cpu + jtag_debug_module + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + jtag_uart + clk + + + + int + 1 + false + true + true + true + + + long + 0x0180a000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + jtag_uart + avalon_jtag_slave + + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + jtag_uart + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + uart + clk + + + + int + 1 + false + true + true + true + + + long + 0x0180a020 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + uart + s1 + + + + int + 2 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + uart + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + onchip_ram + clk1 + + + + int + 1 + false + true + true + true + + + long + 0x01804000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + onchip_ram + s1 + + + + int + 1 + false + true + true + true + + + long + 0x01804000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + onchip_ram + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + sdram + clk + + + + int + 1 + false + true + true + true + + + long + 0x00800000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + sdram + s1 + + + + int + 1 + false + true + true + true + + + long + 0x00800000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sdram + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + pio_7seg + clk + + + + int + 1 + false + true + true + true + + + long + 0x0180a040 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + pio_7seg + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + pio_ledg + clk + + + + int + 1 + false + true + true + true + + + long + 0x0180a050 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + pio_ledg + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + pio_ledr + clk + + + + int + 1 + false + true + true + true + + + long + 0x0180a060 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + pio_ledr + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + epcs_flash + clk + + + + int + 1 + false + true + true + true + + + long + 0x01809800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + epcs_flash + epcs_control_port + + + + int + 1 + false + true + true + true + + + long + 0x01809800 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + epcs_flash + epcs_control_port + + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + epcs_flash + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + cfi_flash + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + tri_state_bridge_flash + clk + + + + int + 1 + false + true + true + true + + + long + 0x0000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + instruction_master + tri_state_bridge_flash + avalon_slave + + + + int + 1 + false + true + true + true + + + long + 0x0000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + tri_state_bridge_flash + avalon_slave + + + + int + 1 + false + true + true + true + + + long + 0x01400000 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + tri_state_bridge_flash + tristate_master + cfi_flash + s1 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + sysid + clk + + + + int + 1 + false + true + true + true + + + long + 0x0180a080 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + sysid + control_slave + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + timer + clk + + + + int + 1 + false + true + true + true + + + long + 0x0180a0a0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + timer + s1 + + + + int + 4 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + timer + irq + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk + clk + onewire + clock_reset + + + + int + 1 + false + true + true + true + + + long + 0x00180a70 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + data_master + onewire + s1 + + + + int + 3 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + cpu + d_irq + onewire + irq + + + 1 + altera_nios2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Nios II Processor + 10.0 + + + 1 + avalon_tristate_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Slave + 10.0 + + + 1 + altera_avalon_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + UART (RS-232 Serial Port) + 10.0 + + + 1 + altera_avalon_sysid + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + System ID Peripheral + 10.0 + + + 1 + avalon_tristate_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Tristate Master + 10.0 + + + 5 + interrupt + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Interrupt Connection + 10.0 + + + 14 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 10.0 + + + 5 + conduit + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit Endpoint + 7.1 + + + 3 + altera_avalon_pio + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + PIO (Parallel I/O) + 10.0 + + + 14 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 10.0 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 10.0 + + + 1 + altera_avalon_jtag_uart + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + JTAG UART + 10.0 + + + 1 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 10.0 + + + 1 + altera_avalon_tri_state_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Avalon-MM Tristate Bridge + 10.0 + + + 1 + sockit_owm + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + 1-wire (onewire) master + 1.3 + + + 2 + avalon_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Master + 10.0 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 10.0 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 10.0 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 10.0 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 10.0 + + + 1 + altera_avalon_new_sdram_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + SDRAM Controller + 10.0 + + + 1 + nios_custom_instruction_master + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Custom Instruction Master + 10.0 + + + 1 + altera_avalon_epcs_flash_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + EPCS Serial Flash Controller + 10.0 + + + 1 + avalon_tristate + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Tristate Connection + 10.0 + + + 1 + altera_avalon_onchip_memory2 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + On-Chip Memory (RAM or ROM) + 10.0 + + + 1 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 10.0 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 10.0 + + + 1 + interrupt_receiver + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Receiver + 10.0 + + + 1 + altera_avalon_cfi_flash + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Flash Memory Interface (CFI) + 10.0 + + + 12 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 10.0 + + + 18 + avalon + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Avalon Memory Mapped Connection + 6.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 10.0 + + + 4 + interrupt_sender + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Interrupt Sender + 10.0 + + + 1 + altera_avalon_timer + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Interval Timer + 10.0 + + 10.0sp1 262 + 0022FB59BE740000012D71BDE49D + Index: trunk/demo/Terasic_DE1/soc.sopc =================================================================== --- trunk/demo/Terasic_DE1/soc.sopc (nonexistent) +++ trunk/demo/Terasic_DE1/soc.sopc (revision 3) @@ -0,0 +1,868 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + M512_MEMORY 0 M4K_MEMORY 1 M9K_MEMORY 0 M20K_MEMORY 0 M144K_MEMORY 0 MRAM_MEMORY 0 MLAB_MEMORY 0 ESB 0 EPCS 1 DSP 0 EMUL 1 HARDCOPY 0 LVDS_IO 0 ADDRESS_STALL 1 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 DSP_SHIFTER_BLOCK 0 + + + + + + + + + + + + + + + ]]> + + + + + cpu.jtag_debug_module + + + + + + + + + INTERACTIVE_ASCII_OUTPUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/demo/Terasic_DE1/software/onewire_ucosii/onewire_ucosii.c =================================================================== --- trunk/demo/Terasic_DE1/software/onewire_ucosii/onewire_ucosii.c (nonexistent) +++ trunk/demo/Terasic_DE1/software/onewire_ucosii/onewire_ucosii.c (revision 3) @@ -0,0 +1,202 @@ +/************************************************************************* +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. All use of this software and documentation is * +* subject to the License Agreement located at the end of this file below.* +************************************************************************** +* Description: * +* The following is a simple hello world program running MicroC/OS-II.The * +* purpose of the design is to be a very simple application that just * +* demonstrates MicroC/OS-II running on NIOS II.The design doesn't account* +* for issues such as checking system call return codes. etc. * +* * +* Requirements: * +* -Supported Example Hardware Platforms * +* Standard * +* Full Featured * +* Low Cost * +* -Supported Development Boards * +* Nios II Development Board, Stratix II Edition * +* Nios Development Board, Stratix Professional Edition * +* Nios Development Board, Stratix Edition * +* Nios Development Board, Cyclone Edition * +* -System Library Settings * +* RTOS Type - MicroC/OS-II * +* Periodic System Timer * +* -Know Issues * +* If this design is run on the ISS, terminal output will take several* +* minutes per iteration. * +**************************************************************************/ + + +#include +#include "includes.h" + +#include "ownet.h" +#include "temp10.h" +#include "findtype.h" + +// defines +#define MAXDEVICES 20 +#define ONEWIRE_P 0 + +// local functions +void DisplaySerialNum(uchar sn[8]); + +/* Definition of Task Stacks */ +#define TASK_STACKSIZE 2048 +OS_STK task1_stk[TASK_STACKSIZE]; +OS_STK task2_stk[TASK_STACKSIZE]; + +/* Definition of Task Priorities */ + +#define TASK1_PRIORITY 1 +#define TASK2_PRIORITY 2 + +/* Prints "Hello World" and sleeps for three seconds */ +void task1(void* pdata) +{ + uchar FamilySN[MAXDEVICES][8]; + float current_temp; + int i = 0; + int j = 0; + int NumDevices = 0; + SMALLINT didRead = 0; + + //use port number for 1-wire + uchar portnum = ONEWIRE_P; + + //---------------------------------------- + // Introduction header + printf("\r\nTemperature\r\n"); + + // attempt to acquire the 1-Wire Net + if (!owAcquire(portnum,NULL)) + { + printf("Acquire failed\r\n"); + while(owHasErrors()) + printf(" - Error %d\r\n", owGetErrorNum()); + return; + } + printf("Acquire done\r\n"); + + do + { + j = 0; + // Find the device(s) + NumDevices = FindDevices(portnum, FamilySN, 0x28, MAXDEVICES); + if (NumDevices>0) + { + printf("\r\n"); + // read the temperature and print serial number and temperature + for (i = NumDevices; i; i--) + { + printf("(%d) ", j++); + DisplaySerialNum(FamilySN[i-1]); + didRead = ReadTemperature(portnum, FamilySN[i-1],¤t_temp); + + if (didRead) + { + printf(" %5.1f Celsius\r\n", current_temp); + } + else + { + printf(" Convert failed. Device is"); + if(!owVerify(portnum, FALSE)) + printf(" not"); + printf(" present.\r\n"); + while(owHasErrors()) + printf(" - Error %d\r\n", owGetErrorNum()); + } + + } + } + else + printf("No temperature devices found!\r\n"); + + printf("\r\nPress any key to continue\r\n"); + i = getchar(); + } + while (i!='q'); + + // release the 1-Wire Net + owRelease(portnum); +} + +/* Prints "Hello World" and sleeps for three seconds */ +void task2(void* pdata) +{ + while (1) + { + printf("Hello from task2\n"); + OSTimeDlyHMSM(0, 0, 3, 0); + } +} +/* The main function creates two task and starts multi-tasking */ +int main(void) +{ + printf("Hello before OS\n"); + + OSTaskCreateExt(task1, + NULL, + (void *)&task1_stk[TASK_STACKSIZE-1], + TASK1_PRIORITY, + TASK1_PRIORITY, + task1_stk, + TASK_STACKSIZE, + NULL, + 0); + + + OSTaskCreateExt(task2, + NULL, + (void *)&task2_stk[TASK_STACKSIZE-1], + TASK2_PRIORITY, + TASK2_PRIORITY, + task2_stk, + TASK_STACKSIZE, + NULL, + 0); + OSStart(); + return 0; +} + +/****************************************************************************** +* * +* License Agreement * +* * +* Copyright (c) 2004 Altera Corporation, San Jose, California, USA. * +* All rights reserved. * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included in * +* all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +* This agreement shall be governed in all respects by the laws of the State * +* of California and by the laws of the United States of America. * +* Altera does not recommend, suggest or require that this reference design * +* file be used in conjunction or combination with any other product. * +******************************************************************************/ + +// ------------------------------------------------------------------------------- +// Read and print the serial number. +// +void DisplaySerialNum(uchar sn[8]) +{ + int i; + for (i = 7; i>=0; i--) + printf("%02X", (int)sn[i]); +}

trunk/demo/Terasic_DE1/software/onewire_ucosii/onewire_ucosii.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/demo/Terasic_DE1/software/onewire/onewire.c =================================================================== --- trunk/demo/Terasic_DE1/software/onewire/onewire.c (nonexistent) +++ trunk/demo/Terasic_DE1/software/onewire/onewire.c (revision 3) @@ -0,0 +1,122 @@ +/* + * "Hello World" example. + * + * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on + * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example + * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT + * device in your system's hardware. + * The memory footprint of this hosted application is ~69 kbytes by default + * using the standard reference design. + * + * For a reduced footprint version of this template, and an explanation of how + * to reduce the memory footprint for a given application, see the + * "small_hello_world" template. + * + */ + +#include +#include "system.h" + +#include "ownet.h" +#include "findtype.h" +#include "temp10.h" +#include "temp28.h" +#include "temp42.h" + +// defines +#define MAXDEVICES 20 +#define ONEWIRE_P 0 + +// local functions +void DisplaySerialNum(uchar sn[8]); + +int main() +{ + uchar FamilySN[MAXDEVICES][8]; + float current_temp; + int i = 0; + int j = 0; + int NumDevices = 0; + SMALLINT didRead = 0; + + //use port number for 1-wire + uchar portnum = ONEWIRE_P; + + //---------------------------------------- + // Introduction header + printf("\r\nTemperature device demo:\r\n"); + + // attempt to acquire the 1-Wire Net + if (!owAcquire(portnum,NULL)) + { + printf("Acquire failed\r\n"); +#ifdef SOCKIT_OWM_ERR_ENABLE + while(owHasErrors()) + printf(" - Error %d\r\n", owGetErrorNum()); + return 1; +#endif + } + + do + { + j = 0; + // Find the device(s) + NumDevices = 0; + NumDevices += FindDevices(portnum, &FamilySN[NumDevices], 0x10, MAXDEVICES-NumDevices); + NumDevices += FindDevices(portnum, &FamilySN[NumDevices], 0x28, MAXDEVICES-NumDevices); + NumDevices += FindDevices(portnum, &FamilySN[NumDevices], 0x42, MAXDEVICES-NumDevices); + if (NumDevices) + { + printf("\r\n"); + // read the temperature and print serial number and temperature + for (i = NumDevices; i; i--) + { + printf("(%d) ", j++); + DisplaySerialNum(FamilySN[i-1]); + if (FamilySN[i-1][0] == 0x10) + didRead = ReadTemperature10(portnum, FamilySN[i-1],¤t_temp); + if (FamilySN[i-1][0] == 0x28) + didRead = ReadTemperature28(portnum, FamilySN[i-1],¤t_temp); + if (FamilySN[i-1][0] == 0x42) + didRead = ReadTemperature42(portnum, FamilySN[i-1],¤t_temp); + + if (didRead) + { + printf(" %5.1f Celsius\r\n", current_temp); + } + else + { + printf(" Convert failed. Device is"); + if(!owVerify(portnum, FALSE)) + printf(" not"); + printf(" present.\r\n"); +#ifdef SOCKIT_OWM_ERR_ENABLE + while(owHasErrors()) + printf(" - Error %d\r\n", owGetErrorNum()); +#endif + } + + } + } + else + printf("No temperature devices found!\r\n"); + + printf("\r\nPress any key to continue\r\n"); + i = getchar(); + } + while (i!='q'); + + // release the 1-Wire Net + owRelease(portnum); + + return 0; +} +// ------------------------------------------------------------------------------- +// Read and print the serial number. +// +void DisplaySerialNum(uchar sn[8]) +{ + int i; + for (i = 7; i>=0; i--) + printf("%02X", (int)sn[i]); +}

trunk/demo/Terasic_DE1/software/onewire/onewire.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/demo/Terasic_DE1/debouncer.v =================================================================== --- trunk/demo/Terasic_DE1/debouncer.v (nonexistent) +++ trunk/demo/Terasic_DE1/debouncer.v (revision 3) @@ -0,0 +1,29 @@ +module debouncer #( + parameter CN = 8, // counter number (sequence length) + parameter CW = $clog2(CN) // counter width in bits +)( + input clk, // clock + input d_i, // debouncer input + output reg d_o // debouncer output +); + +reg [CW-1:0] cnt; // counter +reg d_r; // input register + +// TODO, check if this is done acording to Altera specifications +initial cnt <= 0; + +// prevention of metastability problems +always @ (posedge clk) +d_r <= d_i; + +// the counter should start running on a change +always @ (posedge clk) +if (|cnt) cnt <= cnt - 1; +else if (d_r^d_o) cnt <= CN; + +// when the counter is zero the output should follow the input +always @ (posedge clk) +if (~|cnt) d_o <= d_r; + +endmodule Index: trunk/demo/Terasic_DE1/DE1_soc_nios2.v =================================================================== --- trunk/demo/Terasic_DE1/DE1_soc_nios2.v (nonexistent) +++ trunk/demo/Terasic_DE1/DE1_soc_nios2.v (revision 3) @@ -0,0 +1,171 @@ +////////////////////////////////////////////////////////////////////////////// +// Copyright 2010 by Iztok Jeras (based on code by Terasic Technologies Inc.) +////////////////////////////////////////////////////////////////////////////// + +module DE1_soc_nios2 ( +// Clock Input +input [1:0] CLOCK_24, // 24 MHz +input [1:0] CLOCK_27, // 27 MHz +input CLOCK_50, // 50 MHz +input EXT_CLOCK, // External Clock +// Push Button +input [3:0] KEY, // Pushbutton[3:0] +// DPDT Switch +input [9:0] SW, // Toggle Switch[9:0] +// 7-SEG Dispaly +output [6:0] HEX0, // Seven Segment Digit 0 +output [6:0] HEX1, // Seven Segment Digit 1 +output [6:0] HEX2, // Seven Segment Digit 2 +output [6:0] HEX3, // Seven Segment Digit 3 +// LED +output [7:0] LEDG, // LED Green[7:0] +output [9:0] LEDR, // LED Red[9:0] +// UART +output UART_TXD, // UART Transmitter +input UART_RXD, // UART Receiver +// SDRAM Interface +output DRAM_CLK, // SDRAM Clock +output DRAM_CKE, // SDRAM Clock Enable +output DRAM_CS_N, // SDRAM Chip Select +output DRAM_WE_N, // SDRAM Write Enable +output DRAM_CAS_N, // SDRAM Column Address Strobe +output DRAM_RAS_N, // SDRAM Row Address Strobe +output [1:0] DRAM_BA, // SDRAM Bank Address +output [11:0] DRAM_ADDR, // SDRAM Address bus 12 Bits +inout [15:0] DRAM_DQ, // SDRAM Data bus 16 Bits +output [1:0] DRAM_DQM, // SDRAM Byte Data Mask +// Flash Interface +output FL_RST_N, // FLASH Reset +output FL_CE_N, // FLASH Chip Enable +output FL_WE_N, // FLASH Write Enable +output FL_OE_N, // FLASH Output Enable +output [21:0] FL_ADDR, // FLASH Address bus 22 Bits +inout [7:0] FL_DQ, // FLASH Data bus 8 Bits +// SRAM Interface +output SRAM_CE_N, // SRAM Chip Enable +output SRAM_WE_N, // SRAM Write Enable +output SRAM_OE_N, // SRAM Output Enable +output [17:0] SRAM_ADDR, // SRAM Address bus 18 Bits +output [1:0] SRAM_B_N, // SRAM Byte Data Mask +inout [15:0] SRAM_DQ, // SRAM Data bus 16 Bits +// SD_Card Interface +inout SD_DAT, // SD Card Data +inout SD_DAT3, // SD Card Data 3 +inout SD_CMD, // SD Card Command Signal +output SD_CLK, // SD Card Clock +// USB JTAG link +input TDI, // CPLD -> FPGA (data in) +input TCK, // CPLD -> FPGA (clk) +input TCS, // CPLD -> FPGA (CS) +output TDO, // FPGA -> CPLD (data out) +// I2C +inout I2C_SDAT, // I2C Data +output I2C_SCLK, // I2C Clock +// PS2 +inout PS2_DAT, // PS2 Data +inout PS2_CLK, // PS2 Clock +// VGA +output VGA_HS, // VGA H_SYNC +output VGA_VS, // VGA V_SYNC +output [3:0] VGA_R, // VGA Red[3:0] +output [3:0] VGA_G, // VGA Green[3:0] +output [3:0] VGA_B, // VGA Blue[3:0] +// Audio CODEC +inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock +input AUD_ADCDAT, // Audio CODEC ADC Data +inout AUD_DACLRCK, // Audio CODEC DAC LR Clock +output AUD_DACDAT, // Audio CODEC DAC Data +inout AUD_BCLK, // Audio CODEC Bit-Stream Clock +output AUD_XCK, // Audio CODEC Chip Clock +// GPIO +inout [35:0] GPIO_0, // GPIO Connection 0 +inout [35:0] GPIO_1 // GPIO Connection 1 +); + +localparam FRQ = 24000000; // 24MHz + +// system clock and reset +wire clk, rst; + +// debounced button signals +wire [3:0] btn; + +// 7 segment display negated signals +wire [31:0] seg7; + +// 1-wire +wire [1:0] owr_p; +wire [1:0] owr_e; +wire [1:0] owr_i; + +// All inout port turn to tri-state +assign SD_DAT = 1'bz; +//assign I2C_SDAT = 1'bz; +assign AUD_ADCLRCK = 1'bz; +assign AUD_DACLRCK = 1'bz; +assign AUD_BCLK = 1'bz; +assign GPIO_0 = 36'hzzzzzzzzz; +assign GPIO_1 = 36'hzzzzzzzzz; + +// set system clock to 24MHz +assign clk = CLOCK_24[0]; +assign rst = btn[0]; + +// debouncing of command buttons (buttons are active low) +debouncer #(.CN (FRQ/100)) debouncer_i [3:0] (.clk (clk), .d_i (~KEY), .d_o (btn)); + +// soc_nios RTL instance +soc soc_i ( + // 1) global signals: + .clk (clk), + .reset_n (~rst), + // the_epcs_flash + .ds_MISO_from_the_epcs_flash (), + // the_pio_7seg + .out_port_from_the_pio_7seg (seg7), + // the_pio_ledg + .out_port_from_the_pio_ledg (LEDG), + // the_pio_ledr + .out_port_from_the_pio_ledr (LEDR), + // the_sdram + .zs_cke_from_the_sdram (DRAM_CKE), + .zs_cs_n_from_the_sdram (DRAM_CS_N), + .zs_we_n_from_the_sdram (DRAM_WE_N), + .zs_cas_n_from_the_sdram (DRAM_CAS_N), + .zs_ras_n_from_the_sdram (DRAM_RAS_N), + .zs_ba_from_the_sdram (DRAM_BA), + .zs_addr_from_the_sdram (DRAM_ADDR), + .zs_dq_to_and_from_the_sdram (DRAM_DQ), + .zs_dqm_from_the_sdram (DRAM_DQM), + // the_tri_state_bridge_flash_avalon_slave + .select_n_to_the_cfi_flash (FL_CE_N), + .write_n_to_the_cfi_flash (FL_WE_N), + .read_n_to_the_cfi_flash (FL_OE_N), + .address_to_the_cfi_flash (FL_ADDR), + .data_to_and_from_the_cfi_flash (FL_DQ), + // the_uart + .rxd_to_the_uart (UART_TXD), + .txd_from_the_uart (UART_RXD), + // onewire + .owr_p_from_the_onewire (owr_p), + .owr_e_from_the_onewire (owr_e), + .owr_i_to_the_onewire (owr_i) +); + +// 1-wire +assign PS2_DAT = (owr_p [0] | owr_e [0]) ? owr_p [0] : 1'bz; +assign PS2_CLK = (owr_p [1] | owr_e [1]) ? owr_p [1] : 1'bz; +assign owr_i = {PS2_CLK, PS2_DAT}; + +// SDRAM Interface +assign DRAM_CLK = ~clk; // SDRAM Clock +// Flash Interface +assign FL_RST_N = ~rst; // FLASH Reset + +// active low 7 segment outputs +assign HEX0 = ~seg7[0*8+:7]; +assign HEX1 = ~seg7[1*8+:7]; +assign HEX2 = ~seg7[2*8+:7]; +assign HEX3 = ~seg7[3*8+:7]; + +endmodule

trunk/demo/Terasic_DE1/DE1_soc_nios2.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/demo/Terasic_DE1/DE1_soc_nios2.qpf =================================================================== --- trunk/demo/Terasic_DE1/DE1_soc_nios2.qpf (nonexistent) +++ trunk/demo/Terasic_DE1/DE1_soc_nios2.qpf (revision 3) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "9.1" +DATE = "14:33:53 April 27, 2006" + + +# Revisions + +PROJECT_REVISION = "DE1_soc_nios2" Index: trunk/demo/Terasic_DE1/DE1_soc_nios2.stp =================================================================== --- trunk/demo/Terasic_DE1/DE1_soc_nios2.stp (nonexistent) +++ trunk/demo/Terasic_DE1/DE1_soc_nios2.stp (revision 3) @@ -0,0 +1,451 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 'soc:soc_i|onewire:the_onewire|bus_wen' == either edge + + + + + + + + + + + + + + + + 11111111111111111111111111111111111111111111111111111111111111111111111100000000000000 + 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + + 'soc:soc_i|onewire:the_onewire|bus_ren' == high && 'soc:soc_i|onewire:the_onewire|bus_wen' == high && 'soc:soc_i|onewire:the_onewire|owr_e' == either edge && 'soc:soc_i|onewire:the_onewire|owr_i' == either edge && 'soc:soc_i|onewire:the_onewire|owr_p' == either edge + + + + + + + + + + + + + + + + + + + 0010000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000001010100000000100000000001000111111000100000001010000000000000111001000000000000000000010101000000001000000000010001111110001000000010100000000000001110010000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000001010100000000100000000001000111111000100000001010000000000000111001000000000000000000010101000000001000000000010001111110001000000010100000000000001110010000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000001010100000000100000000001000111111000100000001010000000000000111001000000000000000000010101000000001000000000010001111110001000000010100000000000001110010000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000001010100000000100000000001000111111000100000001010000000000000111001000000000000000000010101000000001000000000010001111110001000000010100000000000001110010000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000001010100000000100000000001000111111000100000001010000000000000111001000000000000000000010101000000001000000000010001111110001000000010100000000000001110010000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000001010100000000100000000001000111111000100000001010000000000000111001000000000000000000010101000000001000000000010001111110001000000010100000000000001110010000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000001010100000000100000000001000111111000100000001010000000000000111001000000000000000000010101000000001000000000010001111110001000000010100000000000001110010000000000000000000101010000000010000000000100011111100010000000101000000000000011100100000000000000000000010000000000000000000000000000000000000000000100000000000001000000000000000000000000000100000000000000000000000000000000000000000001000000000000010000001000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000001001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000101100000000000001000000000000000000000000000000000000001000000000000010000000000000001011000000000000010000000000000000000000000000000000000010000000000000100000000000000010110000000000000100000000000000000000000000000000000000100000000000001000000000000000101100000000000001000000000000000000000000000000000000001000000000000010000000000000001011000000000000010000000000000000000000000000000000000010000000000000100000000000000000100000000000000100000000000000000000000000000000000000100000000000001000000000000000001000000000000001000000000000000000000000000000000000001000000000000010000000000000000010000000000000010000000000000000000000000000000000000010000000000000100000000000000000100000000000000100000000000000000000000000000000000000100000000000001000000000000000001000000000000001000000000000000000000000000000000000001000000000000010000000000000000010000000000000010000000000000000000000000000000000000010000000000000100000000000000000100000000000000100000000000000000000000000000000000000100000000000001000000000000000001000000000000001000000000000000000000000000000000000001000000000000010000000000000000010000000000000010000000000000000000000000000000000000010000000000000100000000000000000100000000000000100000000000000000000000000000000000000100000000000001000000000000000001000000000000001000000000000000000000000000000000000001000000000000010000000000000000010000000000000010000000000000000000000000000000000000010000000000000100000000000000000100000000000000100000000000000000000000000000000000000100000000000001000000000000000001000000000000001000000000000000000000000000000000000001000000000000010000000000000000010000000000000010000000000000000000000000000000000000010000000000000100000000000000000000000000000000100000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000100000000000000000000000000000000000000000000000000000000000000010000000000000100000001000000000000000000000000000000000000000000000000000000000000000100000000000001000000010000000000000000000000000000000000000000000000000000000000000001000000000000010000000100000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000100000001000000000000000000000000000000000000000000000000100000000000001000000000000001000000010000000000000000000000000000000000000000000000001000000000000010000000000000010000000100000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000000000000000000000000000000000000000000000000000000000000000000010000000000000100000000000000000000000000000000000000000000000000000000000000000000000100000000000001000000000000000000000000000000000000000000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000001111100010111100011101111111000000000000000000000000000000000010000000000000100000000011111000101111000111011111110000000000000000000000000000000000100000000000001000000000111110001011110001110111111100000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000100110100000001000000000111111000000000000000000000000000000000100000000000001000000001001101000000010000000001111110000000000000000000000000000000001000000000000010000000010011010000000100000000011111100000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000001001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000100000001010000000000000111001000000000000000000000000000000001000000000000010000000001000000010100000000000001110010000000000000000000000000000000010000000000000100000000010000000101000000000000011100100000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000000000000000001000000000000010000000000000000001000000000000010000000000000000000000000000000000000010000000000000100000000000000000010000000000000100000000000000000000000000000000000000100000000000001000000000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000101010000000010000000000100011111100000000000010000000000000100000000000000000000000001010100000000100000000001000111111000000000000100000000000001000000000000000000000000010101000000001000000000010001111110000000000001000000000000010000000000000000000000000 + 1111111111111111111111111111111111111111111111111111111111111111T111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 + + + + + + + + + + + Index: trunk/doc/sockit_owr.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/sockit_owr.odt =================================================================== --- trunk/doc/sockit_owr.odt (nonexistent) +++ trunk/doc/sockit_owr.odt (revision 3)

trunk/doc/sockit_owr.odt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/sockit_owr.odg =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/sockit_owr.odg =================================================================== --- trunk/doc/sockit_owr.odg (nonexistent) +++ trunk/doc/sockit_owr.odg (revision 3)

trunk/doc/sockit_owr.odg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/TODO =================================================================== --- trunk/TODO (nonexistent) +++ trunk/TODO (revision 3) @@ -0,0 +1,5 @@ +TODO: +1. check the delay code (why is usleep longer than 1us), find macro for detecting OS +2. run some more uCOS-II tests +2. write Linux kernel driver +3. port owfs Index: trunk/hdl/onewire_tb.v =================================================================== --- trunk/hdl/onewire_tb.v (nonexistent) +++ trunk/hdl/onewire_tb.v (revision 3) @@ -0,0 +1,542 @@ +////////////////////////////////////////////////////////////////////////////// +// // +// Minimalistic 1-wire (onewire) master with Avalon MM bus interface // +// testbench // +// // +// Copyright (C) 2010 Iztok Jeras // +// // +////////////////////////////////////////////////////////////////////////////// +// // +// This RTL is free hardware: you can redistribute it and/or modify // +// it under the terms of the GNU Lesser General Public License // +// as published by the Free Software Foundation, either // +// version 3 of the License, or (at your option) any later version. // +// // +// This RTL is distributed in the hope that it will be useful, // +// but WITHOUT ANY WARRANTY; without even the implied warranty of // +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // +// GNU General Public License for more details. // +// // +// You should have received a copy of the GNU General Public License // +// along with this program. If not, see . // +// // +////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +module onewire_tb; + +localparam DEBUG = 1'b0; + +// system clock parameters +localparam real FRQ = 6_000_000; // frequency 6MHz +localparam real TCP = (10.0**9)/FRQ; // time clock period in ns + +`ifdef CDR_E +localparam CDR_E = 1; +`else +localparam CDR_E = 0; +`endif + +`ifdef PRESET_50_10 +localparam OVD_E = 1'b1; // overdrive functionality enable +localparam BTP_N = "5.0"; // normal mode +localparam BTP_O = "1.0"; // overdrive mode +`elsif PRESET_60_05 +localparam OVD_E = 1'b1; // overdrive functionality enable +localparam BTP_N = "6.0"; // normal mode +localparam BTP_O = "0.5"; // overdrive mode +`elsif PRESET_75 +localparam OVD_E = 1'b0; // overdrive functionality enable +localparam BTP_N = "7.5"; // normal mode +localparam BTP_O = "1.0"; // overdrive mode +`else // default +localparam OVD_E = 1'b1; // overdrive functionality enable +localparam BTP_N = "5.0"; // normal mode +localparam BTP_O = "1.0"; // overdrive mode +`endif + +// port width parameters +`ifdef BDW_32 +localparam BDW = 32; // 32bit bus data width +`elsif BDW_8 +localparam BDW = 8; // 8bit bus data width +`else // default +localparam BDW = 32; // bus data width +`endif + +// number of wires +`ifdef OWN +localparam OWN = `OWN; // number of wires +`else +localparam OWN = 3; // slaves with different timing (min, typ, max) +`endif + +// computed bus address port width +localparam BAW = (BDW==32) ? 1 : 2; + +// clock dividers for normal and overdrive mode +// NOTE! must be round integer values +`ifdef PRESET_60_05 +// there is no way to cast a real value into an integer +localparam integer CDR_N = 45 - 1; +localparam integer CDR_O = 4 - 1; +`else +localparam integer CDR_N = ((BTP_N == "5.0") ? 5.0 : 7.5 ) * FRQ / 1_000_000 - 1; +localparam integer CDR_O = ((BTP_O == "1.0") ? 1.0 : 0.67) * FRQ / 1_000_000 - 1; +`endif + +// Avalon MM parameters +localparam AAW = BAW; // address width +localparam ADW = BDW; // data width +localparam ABW = ADW/8; // byte enable width + +// system_signals +reg clk; // clock +reg rst; // reset (asynchronous) +// Avalon MM interface +reg avalon_read; +reg avalon_write; +reg [AAW-1:0] avalon_address; +reg [ABW-1:0] avalon_byteenable; +reg [ADW-1:0] avalon_writedata; +wire [ADW-1:0] avalon_readdata; +wire avalon_waitrequest; +wire avalon_interrupt; + +// Avalon MM local signals +wire avalon_transfer; +reg [BDW-1:0] data; + +// onewire +wire [OWN-1:0] owr; // bidirectional +wire [OWN-1:0] owr_p; // output power enable from master +wire [OWN-1:0] owr_e; // output pull down enable from master +wire [OWN-1:0] owr_i; // input into master + +// slave conviguration +reg slave_ena; // slave enable (connect/disconnect from wire) +reg [3:0] slave_sel; // 1-wire slave select +reg slave_ovd; // overdrive mode enable +reg slave_dat_r; // read data +wire [OWN-1:0] slave_dat_w; // write data + +// error checking +integer error; +integer n; + +// overdrive enable loop +integer i; + +////////////////////////////////////////////////////////////////////////////// +// configuration printout and waveforms +////////////////////////////////////////////////////////////////////////////// + +// request for a dumpfile +initial begin + $dumpfile("onewire.vcd"); + $dumpvars(0, onewire_tb); +end + +// print configuration +initial begin + $display ("NOTE: Ports : BDW=%0d, BAW=%0d, OWN=%0d", BDW, BAW, OWN); + $display ("NOTE: Clock : FRQ=%3.2fMHz, TCP=%3.2fns", FRQ/1_000_000.0, TCP); + $display ("NOTE: Divide: CDR_E=%0b, CDR_N=%0d, CDR_O=%0d", CDR_E, CDR_N, CDR_O); + $display ("NOTE: Config: OVD_E=%0b, BTP_N=%1.2fus, BTP_O=%1.2fus", + OVD_E, (CDR_N+1)*1_000_000/FRQ, (CDR_O+1)*1_000_000/FRQ); +end + +////////////////////////////////////////////////////////////////////////////// +// clock and reset +////////////////////////////////////////////////////////////////////////////// + +// clock generation +initial clk = 1'b1; +always #(TCP/2) clk = ~clk; + +// reset generation +initial begin + rst = 1'b1; + repeat (2) @(posedge clk); + rst = 1'b0; +end + +////////////////////////////////////////////////////////////////////////////// +// Avalon write and read transfers +////////////////////////////////////////////////////////////////////////////// + +initial begin + // reset error counter + error = 0; + + // Avalon MM interface is idle + avalon_read = 1'b0; + avalon_write = 1'b0; + + // long delay to skip presence pulse + slave_ena = 1'b0; + #1000_000; + + // set clock divider ratios + if (CDR_E) begin + if (BDW==32) begin + avalon_cycle (1, 1, 4'hf, { 16'h0001, 16'h0001}, data); + avalon_cycle (1, 1, 4'hf, {CDR_O[15:0], CDR_N[15:0]}, data); + end else if (BDW==8) begin + avalon_cycle (1, 2, 1'b1, 8'h01, data); + avalon_cycle (1, 3, 1'b1, 8'h01, data); + avalon_cycle (1, 2, 1'b1, CDR_N[7:0], data); + avalon_cycle (1, 3, 1'b1, CDR_O[7:0], data); + end + end + + // test with slaves with different timing (each slave one one of the wires) + for (slave_sel=0; slave_sel1) begin + $display("ERROR: (t=%0t) Non ideal idle cycle time, should be around zero.", $time); + end + + // generate a delay pulse and break it with an idle pulse, before it finishes + repeat (10) @(posedge clk); + avalon_request (16'd0, 4'h0, 3'b011); + repeat (10) @(posedge clk); + avalon_request (16'd0, 4'h0, 3'b111); + + // wait a few cycles and finish + repeat (10) @(posedge clk); + $finish(); +end + +// avalon request cycle +task avalon_request ( + input [15:0] pwr, // power enable + input [3:0] sel, // onewire slave select + input [2:0] cmd // command {ovd, rst, dat} +); + reg [BDW-1:0] data; // read data +begin + if (BDW==32) begin + avalon_cycle (1, 0, 4'hf, {pwr<. // +// // +////////////////////////////////////////////////////////////////////////////// + + +////////////////////////////////////////////////////////////////////////////// +// // +// The clock divider parameter is computed with the next formula: // +// // +// CDR_N = f_CLK * BTP_N - 1 (example: CDR_N = 1MHz * 5.0us - 1 = 5-1) // +// CDR_O = f_CLK * BTP_O - 1 (example: CDR_O = 1MHz * 1.0us - 1 = 1-1) // +// // +// If the dividing factor is not a round integer, than the timing of the // +// controller will be slightly off, and would support only a subset of // +// 1-wire devices with timing closer to the typical 30us slot. // +// // +// Base time periods BTP_N = "5.0" and BTP_O = "1.0" are optimized for // +// onewire timing. The default timing restricts the range of available // +// frequences to multiples of 1MHz. // +// // +// If even this restrictions are too strict use timing BTP_N = "6.0" and // +// BTP_O = "0.5", where the actual periods can be in the range: // +// 6.0us <= BTP_N <= 7.5us // +// 0.5us <= BTP_O <= 0.66us // +// // +// A third timing option is available for normal mode BTP_N = "7.5", this // +// option is optimized for logic size. // +// // +////////////////////////////////////////////////////////////////////////////// + +module sockit_owm #( + // enable implementation of optional functionality + parameter OVD_E = 1, // overdrive functionality is implemented by default + parameter CDR_E = 1, // clock divider register is implemented by default + // interface parameters + parameter BDW = 32, // bus data width + parameter OWN = 1, // number of 1-wire ports + // computed bus address port width +`ifdef __ICARUS__ + parameter BAW = (BDW==32) ? 1 : 2, +`else + parameter BAW = 1, // TODO, the above is correct, but does not work well with Altera SOPC Builder +`endif + // base time period + parameter BTP_N = "5.0", // normal mode (5.0us, options are "7.5", "5.0" and "6.0") + parameter BTP_O = "1.0", // overdrive mode (1.0us, options are "1.0", and "0.5") + // normal mode timing + parameter T_RSTH_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset high + parameter T_RSTL_N = (BTP_N == "7.5") ? 64 : (BTP_N == "5.0") ? 96 : 80, // reset low + parameter T_RSTP_N = (BTP_N == "7.5") ? 10 : (BTP_N == "5.0") ? 15 : 10, // reset presence pulse + parameter T_DAT0_N = (BTP_N == "7.5") ? 8 : (BTP_N == "5.0") ? 12 : 10, // bit 0 low + parameter T_DAT1_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // bit 1 low + parameter T_BITS_N = (BTP_N == "7.5") ? 2 : (BTP_N == "5.0") ? 3 : 2, // bit sample + parameter T_RCVR_N = (BTP_N == "7.5") ? 1 : (BTP_N == "5.0") ? 1 : 1, // recovery + parameter T_IDLE_N = (BTP_N == "7.5") ? 128 : (BTP_N == "5.0") ? 200 : 160, // idle timer + // overdrive mode timing + parameter T_RSTH_O = (BTP_O == "1.0") ? 48 : 96, // reset high + parameter T_RSTL_O = (BTP_O == "1.0") ? 48 : 96, // reset low + parameter T_RSTP_O = (BTP_O == "1.0") ? 10 : 15, // reset presence pulse + parameter T_DAT0_O = (BTP_O == "1.0") ? 6 : 12, // bit 0 low + parameter T_DAT1_O = (BTP_O == "1.0") ? 1 : 2, // bit 1 low + parameter T_BITS_O = (BTP_O == "1.0") ? 2 : 3, // bit sample + parameter T_RCVR_O = (BTP_O == "1.0") ? 2 : 4, // recovery + parameter T_IDLE_O = (BTP_O == "1.0") ? 96 : 192, // idle timer + // clock divider ratios (defaults are for a 2MHz clock) + parameter CDR_N = 5-1, // normal mode + parameter CDR_O = 1-1 // overdrive mode +)( + // system signals + input clk, + input rst, + // CPU bus interface + input bus_ren, // read enable + input bus_wen, // write enable + input [BAW-1:0] bus_adr, // address + input [BDW-1:0] bus_wdt, // write data + output [BDW-1:0] bus_rdt, // read data + output bus_irq, // interrupt request + // 1-wire interface + output [OWN-1:0] owr_p, // output power enable + output [OWN-1:0] owr_e, // output pull down enable + input [OWN-1:0] owr_i // input from bidirectional wire +); + +////////////////////////////////////////////////////////////////////////////// +// local parameters +////////////////////////////////////////////////////////////////////////////// + +// size of combined power and select registers +localparam PDW = (BDW==32) ? 24 : 8; + +// size of boudrate generator counter (divider for normal mode is largest) +localparam CDW = CDR_E ? ((BDW==32) ? 16 : 8) : $clog2(CDR_N); + +// size of port select signal +localparam SDW = $clog2(OWN); + +// size of cycle timing counter +localparam TDW = (T_RSTH_O+T_RSTL_O) > (T_RSTH_N+T_RSTL_N) + ? $clog2(T_RSTH_O+T_RSTL_O) : $clog2(T_RSTH_N+T_RSTL_N); + +////////////////////////////////////////////////////////////////////////////// +// local signals +////////////////////////////////////////////////////////////////////////////// + +// address dependent write enable +wire bus_ren_ctl_sts; +wire bus_wen_ctl_sts; +wire bus_wen_pwr_sel; +wire bus_wen_cdr_n; +wire bus_wen_cdr_o; + +// read data bus segments +wire [7:0] bus_rdt_ctl_sts; +wire [PDW-1:0] bus_rdt_pwr_sel; + +// clock divider +reg [CDW-1:0] div; +reg [CDW-1:0] cdr_n; +reg [CDW-1:0] cdr_o; +wire pls; + +// cycle control and status +reg owr_cyc; // cycle status +reg [TDW-1:0] cnt; // cycle counter + +// port select +//generate if (OWN>1) begin : sel_declaration +reg [SDW-1:0] owr_sel; +//end endgenerate + +// modified input data for overdrive +wire req_ovd; + +// onewire signals +reg [OWN-1:0] owr_pwr; // power +reg owr_ovd; // overdrive +reg owr_rst; // reset +reg owr_dat; // data bit +reg owr_smp; // sample bit + +reg owr_oen; // output enable +wire owr_iln; // input line + +// interrupt signals +reg irq_ena; // interrupt enable +reg irq_sts; // interrupt status + +// timing signals +wire [TDW-1:0] t_idl ; // idle cycle time +wire [TDW-1:0] t_rst ; // reset cycle time +wire [TDW-1:0] t_bit ; // data bit cycle time +wire [TDW-1:0] t_rstp; // reset presence pulse sampling time +wire [TDW-1:0] t_rsth; // reset release time +wire [TDW-1:0] t_dat0; // data bit 0 release time +wire [TDW-1:0] t_dat1; // data bit 1 release time +wire [TDW-1:0] t_bits; // data bit sampling time +wire [TDW-1:0] t_zero; // end of cycle time + +////////////////////////////////////////////////////////////////////////////// +// cycle timing +////////////////////////////////////////////////////////////////////////////// + +// idle time +assign t_idl = req_ovd ? T_IDLE_O : T_IDLE_N ; +// reset cycle time (reset low + reset hight) +assign t_rst = req_ovd ? T_RSTL_O + T_RSTH_O : T_RSTL_N + T_RSTH_N ; +// data bit cycle time (write 0 + recovery) +assign t_bit = req_ovd ? T_DAT0_O + + T_RCVR_O : T_DAT0_N + T_RCVR_N; + +// reset presence pulse sampling time (reset high - reset presence) +assign t_rstp = owr_ovd ? T_RSTH_O - T_RSTP_O : T_RSTH_N - T_RSTP_N ; +// reset release time (reset high) +assign t_rsth = owr_ovd ? T_RSTH_O : T_RSTH_N ; + +// data bit 0 release time (write bit 0 - write bit 0 + recovery) +assign t_dat0 = owr_ovd ? T_DAT0_O - T_DAT0_O + T_RCVR_O : T_DAT0_N - T_DAT0_N + T_RCVR_N; +// data bit 1 release time (write bit 0 - write bit 1 + recovery) +assign t_dat1 = owr_ovd ? T_DAT0_O - T_DAT1_O + T_RCVR_O : T_DAT0_N - T_DAT1_N + T_RCVR_N; +// data bit sampling time (write bit 0 - write bit 1 + recovery) +assign t_bits = owr_ovd ? T_DAT0_O - T_BITS_O + T_RCVR_O : T_DAT0_N - T_BITS_N + T_RCVR_N; + +// end of cycle time +assign t_zero = 'd0; + +////////////////////////////////////////////////////////////////////////////// +// bus read +////////////////////////////////////////////////////////////////////////////// + +// bus segnemt - controll/status register +assign bus_rdt_ctl_sts = {irq_ena, irq_sts, 1'b0, owr_pwr[0], owr_cyc, owr_ovd, owr_rst, owr_dat}; + +// bus segnemt - power and select register +generate + if (BDW==32) begin + if (OWN>1) begin + assign bus_rdt_pwr_sel = {{16-OWN{1'b0}}, owr_pwr, 4'h0, {4-SDW{1'b0}}, owr_sel}; + end else begin + assign bus_rdt_pwr_sel = 24'h0000_00; + end + end else if (BDW==8) begin + if (OWN>1) begin + assign bus_rdt_pwr_sel = {{ 4-OWN{1'b0}}, owr_pwr, {4-SDW{1'b0}}, owr_sel}; + end else begin + assign bus_rdt_pwr_sel = 8'hxx; + end + end +endgenerate + +// bus read data +generate if (BDW==32) begin + assign bus_rdt = (bus_adr[0]==1'b0) ? {bus_rdt_pwr_sel, bus_rdt_ctl_sts} : (cdr_o << 16 | cdr_n); +end else if (BDW==8) begin + assign bus_rdt = (bus_adr[1]==1'b0) ? ((bus_adr[0]==1'b0) ? bus_rdt_ctl_sts + : bus_rdt_pwr_sel) + : ((bus_adr[0]==1'b0) ? cdr_n + : cdr_o ); +end endgenerate + +////////////////////////////////////////////////////////////////////////////// +// bus write +////////////////////////////////////////////////////////////////////////////// + +// combined write/read enable and address decoder +generate if (BDW==32) begin + assign bus_ren_ctl_sts = bus_ren & bus_adr[0] == 1'b0; + assign bus_wen_ctl_sts = bus_wen & bus_adr[0] == 1'b0; + assign bus_wen_pwr_sel = bus_wen & bus_adr[0] == 1'b0; + assign bus_wen_cdr_n = bus_wen & bus_adr[0] == 1'b1; + assign bus_wen_cdr_o = bus_wen & bus_adr[0] == 1'b1; +end else if (BDW==8) begin + assign bus_ren_ctl_sts = bus_ren & bus_adr[1:0] == 2'b00; + assign bus_wen_ctl_sts = bus_wen & bus_adr[1:0] == 2'b00; + assign bus_wen_pwr_sel = bus_wen & bus_adr[1:0] == 2'b01; + assign bus_wen_cdr_n = bus_wen & bus_adr[1:0] == 2'b10; + assign bus_wen_cdr_o = bus_wen & bus_adr[1:0] == 2'b11; +end endgenerate + +////////////////////////////////////////////////////////////////////////////// +// clock divider +////////////////////////////////////////////////////////////////////////////// + +// clock divider ratio registers +generate + if (CDR_E) begin + if (BDW==32) begin + always @ (posedge clk, posedge rst) + if (rst) begin + cdr_n <= CDR_N; + cdr_o <= CDR_O; + end else begin + if (bus_wen_cdr_n) cdr_n <= bus_wdt[15: 0]; + if (bus_wen_cdr_o) cdr_o <= bus_wdt[31:16]; + end + end else if (BDW==8) begin + always @ (posedge clk, posedge rst) + if (rst) begin + cdr_n <= CDR_N; + cdr_o <= CDR_O; + end else begin + if (bus_wen_cdr_n) cdr_n <= bus_wdt; + if (bus_wen_cdr_o) cdr_o <= bus_wdt; + end + end + end else begin + initial begin + cdr_n = CDR_N; + cdr_o = CDR_O; + end + end +endgenerate + +// clock divider +always @ (posedge clk, posedge rst) +if (rst) div <= 'd0; +else begin + if (bus_wen) div <= 'd0; + else div <= pls ? 'd0 : div + owr_cyc; +end + +// divided clock pulse +assign pls = (div == (owr_ovd ? cdr_o : cdr_n)); + +////////////////////////////////////////////////////////////////////////////// +// power and select register +////////////////////////////////////////////////////////////////////////////// + +// select and power register implementation +generate if (OWN>1) begin : sel_implementation + // port select + always @ (posedge clk, posedge rst) + if (rst) owr_sel <= {SDW{1'b0}}; + else if (bus_wen_pwr_sel) owr_sel <= bus_wdt[(BDW==32 ? 8 : 0)+:SDW]; + + // power delivery + always @ (posedge clk, posedge rst) + if (rst) owr_pwr <= {OWN{1'b0}}; + else if (bus_wen_pwr_sel) owr_pwr <= bus_wdt[(BDW==32 ? 16 : 4)+:OWN]; +end else begin + // port select + initial owr_sel <= 'd0; + // power delivery + always @ (posedge clk, posedge rst) + if (rst) owr_pwr <= 1'b0; + else if (bus_wen_ctl_sts) owr_pwr <= bus_wdt[4]; +end endgenerate + +////////////////////////////////////////////////////////////////////////////// +// interrupt logic +////////////////////////////////////////////////////////////////////////////// + +// bus interrupt +assign bus_irq = irq_ena & irq_sts; + +// interrupt enable +always @ (posedge clk, posedge rst) +if (rst) irq_ena <= 1'b0; +else if (bus_wen_ctl_sts) irq_ena <= bus_wdt[7]; + +// transmit status (active after onewire cycle ends) +always @ (posedge clk, posedge rst) +if (rst) irq_sts <= 1'b0; +else begin + if (bus_wen_ctl_sts) irq_sts <= 1'b0; + else if (pls & (cnt == t_zero)) irq_sts <= 1'b1; + else if (bus_ren_ctl_sts) irq_sts <= 1'b0; +end + +////////////////////////////////////////////////////////////////////////////// +// onewire state machine +////////////////////////////////////////////////////////////////////////////// + +assign req_ovd = OVD_E ? bus_wen_ctl_sts & bus_wdt[2] : 1'b0; + +// overdrive +always @ (posedge clk, posedge rst) +if (rst) owr_ovd <= 1'b0; +else if (bus_wen_ctl_sts) owr_ovd <= req_ovd; + +// reset +always @ (posedge clk, posedge rst) +if (rst) owr_rst <= 1'b0; +else if (bus_wen_ctl_sts) owr_rst <= bus_wdt[1]; + +// transmit data, reset, overdrive +always @ (posedge clk, posedge rst) +if (rst) owr_dat <= 1'b0; +else begin + if (bus_wen_ctl_sts) owr_dat <= bus_wdt[0]; + else if (pls & (cnt == t_zero)) owr_dat <= owr_smp; +end + +// onewire cycle status +always @ (posedge clk, posedge rst) +if (rst) owr_cyc <= 1'b0; +else begin + if (bus_wen_ctl_sts) owr_cyc <= bus_wdt[3] & ~&bus_wdt[2:0]; + else if (pls & (cnt == t_zero)) owr_cyc <= 1'b0; +end + +// state counter (initial value depends whether the cycle is reset or data) +always @ (posedge clk, posedge rst) +if (rst) cnt <= 0; +else begin + if (bus_wen_ctl_sts) cnt <= (&bus_wdt[1:0] ? t_idl : bus_wdt[1] ? t_rst : t_bit) - 'd1; + else if (pls) cnt <= cnt - 'd1; +end + +// receive data (sampling point depends whether the cycle is reset or data) +always @ (posedge clk) +if (pls) begin + if ( owr_rst & (cnt == t_rstp)) owr_smp <= owr_iln; // presence detect + else if (~owr_rst & (cnt == t_bits)) owr_smp <= owr_iln; // read data bit +end + +// output register (switch point depends whether the cycle is reset or data) +always @ (posedge clk, posedge rst) +if (rst) owr_oen <= 1'b0; +else begin + if (bus_wen_ctl_sts) owr_oen <= ~&bus_wdt[1:0]; + else if (pls) begin + if (owr_rst & (cnt == t_rsth)) owr_oen <= 1'b0; // reset + else if (owr_dat & (cnt == t_dat1)) owr_oen <= 1'b0; // write 1, read + else if ( (cnt == t_dat0)) owr_oen <= 1'b0; // write 0 + end +end + +////////////////////////////////////////////////////////////////////////////// +// IO +////////////////////////////////////////////////////////////////////////////// + +// only one 1-wire line cn be accessed at the same time +assign owr_e = owr_oen << owr_sel; +// all 1-wire lines can be powered independently +assign owr_p = owr_pwr; + +// 1-wire line status read multiplexer +assign owr_iln = owr_i [owr_sel]; + +endmodule Index: trunk/hdl/onewire_slave_model.v =================================================================== --- trunk/hdl/onewire_slave_model.v (nonexistent) +++ trunk/hdl/onewire_slave_model.v (revision 3) @@ -0,0 +1,115 @@ +////////////////////////////////////////////////////////////////////////////// +// // +// 1-wire (owr) slave model // +// // +// Copyright (C) 2010 Iztok Jeras // +// // +////////////////////////////////////////////////////////////////////////////// +// // +// This RTL is free hardware: you can redistribute it and/or modify // +// it under the terms of the GNU Lesser General Public License // +// as published by the Free Software Foundation, either // +// version 3 of the License, or (at your option) any later version. // +// // +// This RTL is distributed in the hope that it will be useful, // +// but WITHOUT ANY WARRANTY; without even the implied warranty of // +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the // +// GNU General Public License for more details. // +// // +// You should have received a copy of the GNU General Public License // +// along with this program. If not, see . // +// // +////////////////////////////////////////////////////////////////////////////// + +`timescale 1us / 1ns + +module onewire_slave_model #( + // time slot (min=15.0, typ=30.0, max=60.0) + parameter TS = 30.0 +)( + // configuration + input wire ena, // response enable + input wire ovd, // overdrive mode select + input wire dat_r, // read data + output wire dat_w, // write data + // 1-wire + inout wire owr +); + +// IO +reg pul; +reg dat; + +// events +event sample_dat; +event sample_rst; + +////////////////////////////////////////////////////////////////////////////// +// IO +////////////////////////////////////////////////////////////////////////////// + +// onewire open collector signal +assign owr = pul & ena ? 1'b0 : 1'bz; + +// read data output +assign dat_w = ena ? dat : 1'bz; + +////////////////////////////////////////////////////////////////////////////// +// events inside a cycle +////////////////////////////////////////////////////////////////////////////// + +// power up state +initial pul <= 1'b0; + +always @ (negedge owr) if (ena) transfer (ovd, dat_r, dat); + +task automatic transfer ( + input ovd, + input dat_r, + output dat_w +); begin + // provide read data response + pul = ~dat_r; + // wait 1 time slot + if (ovd) #(1*TS/8); + else #(1*TS); + // write data is sampled here + -> sample_dat; + dat_w = owr; + // release the wire + pul = 1'b0; + // fork into data or reset cycle + fork + // transfer data + begin : transfer_dat + // if cycle ends before reset is detected + if (~owr) @ (posedge owr); + // disable reset path + disable transfer_rst; + end + // transfer reset + begin : transfer_rst + // wait 7 time slots + if (ovd) #(7*TS/8); + else #(7*TS); + // reset is sampled here + -> sample_rst; + // if reset is detected disable data path + if (~owr) disable transfer_dat; + // wait for reset low to end + @ (posedge owr) + // wait 1 time slot + if (ovd) #(1*TS/8); + else #(1*TS); + // provide presence pulse + pul = 1'b1; + // wait 4 time slot + if (ovd) #(4*TS/8); + else #(4*TS); + // release the wire + pul = 1'b0; + end + join +end endtask + +endmodule Index: trunk/hdl/wishbone2bus.v =================================================================== --- trunk/hdl/wishbone2bus.v (nonexistent) +++ trunk/hdl/wishbone2bus.v (revision 3) @@ -0,0 +1,43 @@ +module wishbone2bus #( + parameter AW = 2, // address width + parameter DW = 32, // data width + parameter SW = DW/8 // select width +)( + // Wishbone master port + input wire wb_cyc, // cycle + input wire wb_stb, // strobe + input wire wb_we, // write enable + input wire [AW-1:0] wb_adr, // address + input wire [SW-1:0] wb_sel, // byte select + input wire [DW-1:0] wb_dat_w, // write data + output wire [DW-1:0] wb_dat_r, // read data + output wire wb_ack, // acknowledge + output wire wb_err, // error + output wire wb_rty, // retry + // Avalon slave port + output wire bus_wen, // write enable + output wire bus_ren, // read enable + output wire [AW-1:0] bus_adr, // address + output wire [DW-1:0] bus_wdt, // write data + input wire [DW-1:0] bus_rdt // read data +); + +// bus write and read enable +assign bus_wen = wb_cyc & wb_stb & wb_we; +assign bus_ren = wb_cyc & wb_stb & ~wb_we; + +// address +assign bus_adr = wb_adr; + +// write data +assign bus_wdt = wb_dat_w; + +// read data +assign wb_dat_r = bus_rdt; + +// error if not full width access else acknowledge +assign wb_ack = &wb_sel; +assign wb_err = ~&wb_sel; +assign wb_rty = 1'b0; + +endmodule Index: trunk/lic/license_pub.txt =================================================================== --- trunk/lic/license_pub.txt (nonexistent) +++ trunk/lic/license_pub.txt (revision 3) @@ -0,0 +1,24 @@ +Copyright (C) 1998 Dallas Semiconductor Corporation, All Rights Reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included +in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL DALLAS SEMICONDUCTOR BE LIABLE FOR ANY CLAIM, DAMAGES +OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +Except as contained in this notice, the name of Dallas Semiconductor +shall not be used except as stated in the Dallas Semiconductor +Branding Policy. + Index: trunk/lic/lgpl.txt =================================================================== --- trunk/lic/lgpl.txt (nonexistent) +++ trunk/lic/lgpl.txt (revision 3) @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. Additional Definitions. + + As used herein, "this License" refers to version 3 of the GNU Lesser +General Public License, and the "GNU GPL" refers to version 3 of the GNU +General Public License. + + "The Library" refers to a covered work governed by this License, +other than an Application or a Combined Work as defined below. + + An "Application" is any work that makes use of an interface provided +by the Library, but which is not otherwise based on the Library. +Defining a subclass of a class defined by the Library is deemed a mode +of using an interface provided by the Library. + + A "Combined Work" is a work produced by combining or linking an +Application with the Library. The particular version of the Library +with which the Combined Work was made is also called the "Linked +Version". + + The "Minimal Corresponding Source" for a Combined Work means the +Corresponding Source for the Combined Work, excluding any source code +for portions of the Combined Work that, considered in isolation, are +based on the Application, and not on the Linked Version. + + The "Corresponding Application Code" for a Combined Work means the +object code and/or source code for the Application, including any data +and utility programs needed for reproducing the Combined Work from the +Application, but excluding the System Libraries of the Combined Work. + + 1. Exception to Section 3 of the GNU GPL. + + You may convey a covered work under sections 3 and 4 of this License +without being bound by section 3 of the GNU GPL. + + 2. Conveying Modified Versions. + + If you modify a copy of the Library, and, in your modifications, a +facility refers to a function or data to be supplied by an Application +that uses the facility (other than as an argument passed when the +facility is invoked), then you may convey a copy of the modified +version: + + a) under this License, provided that you make a good faith effort to + ensure that, in the event an Application does not supply the + function or data, the facility still operates, and performs + whatever part of its purpose remains meaningful, or + + b) under the GNU GPL, with none of the additional permissions of + this License applicable to that copy. + + 3. Object Code Incorporating Material from Library Header Files. + + The object code form of an Application may incorporate material from +a header file that is part of the Library. You may convey such object +code under terms of your choice, provided that, if the incorporated +material is not limited to numerical parameters, data structure +layouts and accessors, or small macros, inline functions and templates +(ten or fewer lines in length), you do both of the following: + + a) Give prominent notice with each copy of the object code that the + Library is used in it and that the Library and its use are + covered by this License. + + b) Accompany the object code with a copy of the GNU GPL and this license + document. + + 4. Combined Works. + + You may convey a Combined Work under terms of your choice that, +taken together, effectively do not restrict modification of the +portions of the Library contained in the Combined Work and reverse +engineering for debugging such modifications, if you also do each of +the following: + + a) Give prominent notice with each copy of the Combined Work that + the Library is used in it and that the Library and its use are + covered by this License. + + b) Accompany the Combined Work with a copy of the GNU GPL and this license + document. + + c) For a Combined Work that displays copyright notices during + execution, include the copyright notice for the Library among + these notices, as well as a reference directing the user to the + copies of the GNU GPL and this license document. + + d) Do one of the following: + + 0) Convey the Minimal Corresponding Source under the terms of this + License, and the Corresponding Application Code in a form + suitable for, and under terms that permit, the user to + recombine or relink the Application with a modified version of + the Linked Version to produce a modified Combined Work, in the + manner specified by section 6 of the GNU GPL for conveying + Corresponding Source. + + 1) Use a suitable shared library mechanism for linking with the + Library. A suitable mechanism is one that (a) uses at run time + a copy of the Library already present on the user's computer + system, and (b) will operate properly with a modified version + of the Library that is interface-compatible with the Linked + Version. + + e) Provide Installation Information, but only if you would otherwise + be required to provide such information under section 6 of the + GNU GPL, and only to the extent that such information is + necessary to install and execute a modified version of the + Combined Work produced by recombining or relinking the + Application with a modified version of the Linked Version. (If + you use option 4d0, the Installation Information must accompany + the Minimal Corresponding Source and Corresponding Application + Code. If you use option 4d1, you must provide the Installation + Information in the manner specified by section 6 of the GNU GPL + for conveying Corresponding Source.) + + 5. Combined Libraries. + + You may place library facilities that are a work based on the +Library side by side in a single library together with other library +facilities that are not Applications and are not covered by this +License, and convey such a combined library under terms of your +choice, if you do both of the following: + + a) Accompany the combined library with a copy of the same work based + on the Library, uncombined with any other library facilities, + conveyed under the terms of this License. + + b) Give prominent notice with the combined library that part of it + is a work based on the Library, and explaining where to find the + accompanying uncombined form of the same work. + + 6. Revised Versions of the GNU Lesser General Public License. + + The Free Software Foundation may publish revised and/or new versions +of the GNU Lesser General Public License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. Index: trunk/sockit_owm_sw.tcl =================================================================== --- trunk/sockit_owm_sw.tcl (revision 2) +++ trunk/sockit_owm_sw.tcl (revision 3) @@ -1,6 +1,25 @@ -# -# sockit_owm_sw.tcl -# +############################################################################### +# # +# Minimalistic 1-wire (onewire) master with Avalon MM bus interface # +# # +# Copyright (C) 2010 Iztok Jeras # +# # +############################################################################### +# # +# This script is free software: you can redistribute it and/or modify # +# it under the terms of the GNU Lesser General Public License # +# as published by the Free Software Foundation, either # +# version 3 of the License, or (at your option) any later version. # +# # +# This RTL is distributed in the hope that it will be useful, # +# but WITHOUT ANY WARRANTY; without even the implied warranty of # +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # +# GNU General Public License for more details. # +# # +# You should have received a copy of the GNU General Public License # +# along with this program. If not, see . # +# # +############################################################################### # Create a new driver create_driver sockit_owm_driver @@ -9,16 +28,12 @@ set_sw_property hw_class_name sockit_owm # Driver version -set_sw_property version 1.1 +set_sw_property version 1.3 -# This driver is proclaimed to be compatible with sockit_owm hardware -# as old as version "1.0". If the hardware component version number is not -# equal or greater than the min_compatable_hw_version number, the driver -# source files will not be copied over to the BSP drivers subdirectory -set_sw_property min_compatible_hw_version 1.1 +# This driver is compatible with version 1.3 and above +set_sw_property min_compatible_hw_version 1.3 -# Interrupt properties: This driver supports both legacy and enhanced -# interrupt APIs, as well as ISR preemption. +# Interrupt properties set_sw_property isr_preemption_supported true set_sw_property supported_interrupt_apis "legacy_interrupt_api enhanced_interrupt_api" @@ -28,37 +43,41 @@ # Location in generated BSP that above sources will be copied into set_sw_property bsp_subdirectory drivers -# -# Source file listings... -# +# C source files +add_sw_property c_source HAL/src/sockit_owm.c +add_sw_property c_source HAL/src/ownet.c +add_sw_property c_source HAL/src/owtran.c +add_sw_property c_source HAL/src/owlnk.c +add_sw_property c_source HAL/src/owses.c -# C/C++ source files -add_sw_property c_source HAL/src/ownet.c -add_sw_property c_source HAL/src/owtran.c -add_sw_property c_source HAL/src/owlnk.c -add_sw_property c_source HAL/src/owses.c -add_sw_property c_source HAL/src/owerr.c -add_sw_property c_source HAL/src/crcutil.c -add_sw_property c_source HAL/src/sockit_owm.c - # Include files +add_sw_property include_source inc/sockit_owm_regs.h +add_sw_property include_source HAL/inc/sockit_owm.h add_sw_property include_source HAL/inc/ownet.h -add_sw_property include_source HAL/inc/sockit_owm.h -add_sw_property include_source inc/sockit_owm_regs.h # Common files +add_sw_property c_source HAL/src/owerr.c +add_sw_property c_source HAL/src/crcutil.c add_sw_property include_source HAL/inc/findtype.h add_sw_property c_source HAL/src/findtype.c +# device files (thermometer) +add_sw_property include_source HAL/inc/temp10.h +add_sw_property c_source HAL/src/temp10.c +add_sw_property include_source HAL/inc/temp28.h +add_sw_property c_source HAL/src/temp28.c +add_sw_property include_source HAL/inc/temp42.h +add_sw_property c_source HAL/src/temp42.c + # This driver supports HAL & UCOSII BSP (OS) types add_sw_property supported_bsp_type HAL add_sw_property supported_bsp_type UCOSII # Driver configuration options -add_sw_setting boolean_define_only public_mk_define enable_polling_driver SOCKIT_OWM_POLLING false "Small-footprint (polled mode) driver" -add_sw_setting boolean_define_only public_mk_define enable_hardware_delay SOCKIT_OWM_HW_DLY false "Mili second delay implemented in hardware" +add_sw_setting boolean_define_only public_mk_define polling_driver_enable SOCKIT_OWM_POLLING false "Small-footprint (polled mode) driver" +add_sw_setting boolean_define_only public_mk_define hardware_delay_enable SOCKIT_OWM_HW_DLY true "Mili second delay implemented in hardware" +add_sw_setting boolean_define_only public_mk_define error_detection_enable SOCKIT_OWM_ERR_ENABLE true "Implement error detection support" +add_sw_setting boolean_define_only public_mk_define error_detection_small SOCKIT_OWM_ERR_SMALL true "Reduced memory consumption for error detection" # Enable application layer code #add_sw_setting boolean_define_only public_mk_define enable_A SOCKIT_OWM_A false "Enable driver A" - -# End of file

/trunk/sim/gtkwave.sav

0,0 → 1,60

/trunk/sim/iverilog_gtkwave.cmd

0,0 → 1,14

trunk/sim/iverilog_gtkwave.cmd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/readme.txt =================================================================== --- trunk/sim/readme.txt (nonexistent) +++ trunk/sim/readme.txt (revision 3) @@ -0,0 +1,15 @@ +Instructions for running the testbench + +Files: +- sim/gtkwave.sav (GTKWave waveform save file) +- sim/iverilog_gtkwave.scr (Bash script) +- sim/iverilog_gtkwave.cmd (Windows cmd script) + +Requirements: +- Icarus Verilog simulator +- GTKWave waveform viewer (not essential) + +Procedure: +1. First CD into the sim/ directory. +2. modify the test parameters in the script (the loop can be commented out) +3. run the script ./iverilog_gtkwave.scr Index: trunk/sim/iverilog_gtkwave.scr =================================================================== --- trunk/sim/iverilog_gtkwave.scr (nonexistent) +++ trunk/sim/iverilog_gtkwave.scr (revision 3) @@ -0,0 +1,32 @@ +#!/bin/bash + +# cleanup first +rm onewire.out +rm onewire.vcd + +# list of source files +sources="../hdl/onewire_tb.v ../hdl/onewire_slave_model.v ../hdl/sockit_owm.v" + +# compile verilog sources (testbench and RTL) and run simulation + +# data bus widths +for buswdth in "BDW_32" "BDW_8" +do + # clock divider implementation + for divider in "CDR_NONE" "CDR_E" + do + # timing options + for preset in "PRESET_50_10" "PRESET_60_05" "PRESET_75" + do + iverilog -o onewire.out $sources -D$preset -D$divider -D$buswdth + vvp onewire.out -none + done + done +done + +# test a single 1-wire line configuration (waveform generation is enabled) +iverilog -o onewire.out $sources -DPRESET_50_10 -DCDR_NONE -DBDW_32 -DOWN=1 +vvp onewire.out + +# open the waveform and detach it +gtkwave onewire.vcd gtkwave.sav &

trunk/sim/iverilog_gtkwave.scr Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/inc/sockit_owm_regs.h =================================================================== --- trunk/inc/sockit_owm_regs.h (revision 2) +++ trunk/inc/sockit_owm_regs.h (revision 3) @@ -27,38 +27,55 @@ #include -#define SOCKIT_OWM_REG 0 -#define IOADDR_SOCKIT_OWM(base) __IO_CALC_ADDRESS_NATIVE(base, SOCKIT_OWM_REG) -#define IORD_SOCKIT_OWM(base) IORD(base, SOCKIT_OWM_REG) -#define IOWR_SOCKIT_OWM(base, data) IOWR(base, SOCKIT_OWM_REG, data) +////////////////////////////////////////////////////////////////////////////// +// control status register // +////////////////////////////////////////////////////////////////////////////// -#define SOCKIT_OWM_DAT_MSK (0x01) // data bit -#define SOCKIT_OWM_DAT_OFST (0) -#define SOCKIT_OWM_RST_MSK (0x02) // reset (write only) -#define SOCKIT_OWM_RST_OFST (1) -#define SOCKIT_OWM_TRN_MSK (0x02) // transfer (read only) -#define SOCKIT_OWM_TRN_OFST (1) -#define SOCKIT_OWM_OVD_MSK (0x04) // overdrive -#define SOCKIT_OWM_OVD_OFST (2) -#define SOCKIT_OWM_PWR_MSK (0x08) // power (strong pull-up) -#define SOCKIT_OWM_PWR_OFST (3) // if there is a single port -#define SOCKIT_OWM_STX_MSK (0x10) // status TX -#define SOCKIT_OWM_STX_OFST (4) -#define SOCKIT_OWM_SRX_MSK (0x20) // status RX -#define SOCKIT_OWM_SRX_OFST (5) -#define SOCKIT_OWM_ETX_MSK (0x40) // irq enable TX -#define SOCKIT_OWM_ETX_OFST (6) -#define SOCKIT_OWM_ERX_MSK (0x80) // irq enable RX -#define SOCKIT_OWM_ERX_OFST (7) +#define SOCKIT_OWM_CTL_REG 0 +#define IOADDR_SOCKIT_OWM_CTL(base) IO_CALC_ADDRESS_NATIVE(base, SOCKIT_OWM_CTL_REG) +#define IORD_SOCKIT_OWM_CTL(base) IORD(base, SOCKIT_OWM_CTL_REG) +#define IOWR_SOCKIT_OWM_CTL(base, data) IOWR(base, SOCKIT_OWM_CTL_REG, data) -#define SOCKIT_OWM_SEL_MSK (0x0f00) // port select number -#define SOCKIT_OWM_SEL_OFST (8) +#define SOCKIT_OWM_CTL_DAT_MSK (0x00000001) // data bit +#define SOCKIT_OWM_CTL_DAT_OFST (0) +#define SOCKIT_OWM_CTL_RST_MSK (0x00000002) // reset +#define SOCKIT_OWM_CTL_RST_OFST (1) +#define SOCKIT_OWM_CTL_OVD_MSK (0x00000004) // overdrive +#define SOCKIT_OWM_CTL_OVD_OFST (2) +#define SOCKIT_OWM_CTL_CYC_MSK (0x00000008) // cycle +#define SOCKIT_OWM_CTL_CYC_OFST (3) +#define SOCKIT_OWM_CTL_PWR_MSK (0x00000010) // power (strong pull-up), if there is a single 1-wire line +#define SOCKIT_OWM_CTL_PWR_OFST (5) +#define SOCKIT_OWM_CTL_RSV_MSK (0x00000020) // reserved +#define SOCKIT_OWM_CTL_RSV_OFST (5) +#define SOCKIT_OWM_CTL_IRQ_MSK (0x00000040) // irq status +#define SOCKIT_OWM_CTL_IRQ_OFST (6) +#define SOCKIT_OWM_CTL_IEN_MSK (0x00000080) // irq enable +#define SOCKIT_OWM_CTL_IEN_OFST (7) -#define SOCKIT_OWM_POWER_MSK (0xffff0000) // power (strong pull-up) -#define SOCKIT_OWM_POWER_OFST (16) // if there is more than one port +#define SOCKIT_OWM_CTL_SEL_MSK (0x00000f00) // port select number +#define SOCKIT_OWM_CTL_SEL_OFST (8) +#define SOCKIT_OWM_CTL_POWER_MSK (0xffff0000) // power (strong pull-up), if there is more than one 1-wire line +#define SOCKIT_OWM_CTL_POWER_OFST (16) + // two common commands -#define SOCKIT_OWM_DLY_MSK ( SOCKIT_OWM_RST_MSK | SOCKIT_OWM_DAT_MSK) -#define SOCKIT_OWM_IDL_MSK (SOCKIT_OWM_OVD_MSK | SOCKIT_OWM_RST_MSK | SOCKIT_OWM_DAT_MSK) +#define SOCKIT_OWM_CTL_DLY_MSK ( SOCKIT_OWM_CTL_RST_MSK | SOCKIT_OWM_CTL_DAT_MSK) +#define SOCKIT_OWM_CTL_IDL_MSK (SOCKIT_OWM_CTL_OVD_MSK | SOCKIT_OWM_CTL_RST_MSK | SOCKIT_OWM_CTL_DAT_MSK) +////////////////////////////////////////////////////////////////////////////// +// clock divider ratio register // +////////////////////////////////////////////////////////////////////////////// + +#define SOCKIT_OWM_CDR_REG 1 +#define IOADDR_SOCKIT_OWM_CDR(base) IO_CALC_ADDRESS_NATIVE(base, SOCKIT_OWM_CDR_REG) +#define IORD_SOCKIT_OWM_CDR(base) IORD(base, SOCKIT_OWM_CDR_REG) +#define IOWR_SOCKIT_OWM_CDR(base, data) IOWR(base, SOCKIT_OWM_CDR_REG, data) + +#define SOCKIT_OWM_CDR_N_MSK (0x0000ffff) // normal mode +#define SOCKIT_OWM_CDR_N_OFST (0) +#define SOCKIT_OWM_CDR_O_MSK (0xffff0000) // overdrive mode +#define SOCKIT_OWM_CDR_O_OFST (16) + + #endif /* __SOCKIT_OWM_REGS_H__ */

/trunk/README

10,8 → 10,7

/trunk/sockit_owm_hw.tcl

1,37 → 1,72

39,18 → 74,19

81,7 → 117,7

89,7 → 125,7

99,9 → 135,9

108,7 → 144,7

133,10 → 169,11

146,7 → 183,7

153,20 → 190,20

178,11 → 215,13

192,16 → 231,18

213,7 → 254,26

Browse

Tools

Subversion Repositories sockit_owm

Compare Revisions

Rev 2 → Rev 3