URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk/altera_work/spw_fifo_ulight/db
- from Rev 35 to Rev 40
- ↔ Reverse comparison
Rev 35 → Rev 40
/.cmp.kpt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/ddio_out_uqe.tdf
1,5 → 1,5
--altddio_out CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" INVERT_OUTPUT="OFF" POWER_UP_HIGH="OFF" WIDTH=1 datain_h datain_l dataout outclock |
--VERSION_BEGIN 17.0 cbx_altddio_out 2017:06:01:09:22:16:SJ cbx_cycloneii 2017:06:01:09:22:16:SJ cbx_maxii 2017:06:01:09:22:16:SJ cbx_mgl 2017:06:01:10:52:00:SJ cbx_stratix 2017:06:01:09:22:16:SJ cbx_stratixii 2017:06:01:09:22:16:SJ cbx_stratixiii 2017:06:01:09:22:16:SJ cbx_stratixv 2017:06:01:09:22:16:SJ cbx_util_mgl 2017:06:01:09:22:16:SJ VERSION_END |
--VERSION_BEGIN 17.1 cbx_altddio_out 2017:12:05:11:11:27:SJ cbx_cycloneii 2017:12:05:11:11:27:SJ cbx_maxii 2017:12:05:11:11:27:SJ cbx_mgl 2017:12:05:12:41:31:SJ cbx_stratix 2017:12:05:11:11:27:SJ cbx_stratixii 2017:12:05:11:11:27:SJ cbx_stratixiii 2017:12:05:11:11:27:SJ cbx_stratixv 2017:12:05:11:11:27:SJ cbx_util_mgl 2017:12:05:11:11:27:SJ VERSION_END |
|
|
-- Copyright (C) 2017 Intel Corporation. All rights reserved. |
10,12 → 10,11
-- associated documentation or information are expressly subject |
-- to the terms and conditions of the Intel Program License |
-- Subscription Agreement, the Intel Quartus Prime License Agreement, |
-- the Intel MegaCore Function License Agreement, or other |
-- applicable license agreement, including, without limitation, |
-- that your use is for the sole purpose of programming logic |
-- devices manufactured by Intel and sold by Intel or its |
-- authorized distributors. Please refer to the applicable |
-- agreement for further details. |
-- the Intel FPGA IP License Agreement, or other applicable license |
-- agreement, including, without limitation, that your use is for |
-- the sole purpose of programming logic devices manufactured by |
-- Intel and sold by Intel or its authorized distributors. Please |
-- refer to the applicable agreement for further details. |
|
|
FUNCTION cyclonev_ddio_out (areset, clk, clkhi, clklo, datainhi, datainlo, ena, hrbypass, muxsel, sreset) |
/prev_cmp_spw_fifo_ulight.qmsg
1,231 → 1,455
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1503605346490 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1503605346525 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 24 17:09:06 2017 " "Processing started: Thu Aug 24 17:09:06 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1503605346525 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605346525 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605346527 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1503605356357 ""} |
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1503605356357 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" { } { { "../rtl/fpga_debug/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/detector_tokens.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376205 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376205 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" { } { { "../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376207 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376207 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376208 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376208 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" { } { { "../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376209 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376209 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376211 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376211 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" { } { { "../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376215 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376215 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376217 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376217 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" { } { { "../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/tx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376222 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376222 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" { } { { "../rtl/fpga_debug/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/clock_reduce.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376224 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376224 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" { } { { "../rtl/fpga_debug/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/fpga_debug/debounce.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376226 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376226 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376231 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376231 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376233 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376233 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376235 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376235 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376269 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376270 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376270 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376271 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376274 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376274 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376275 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376275 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376275 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376276 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376276 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376278 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376278 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376282 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376282 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376286 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376286 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376287 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376294 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376302 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376303 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376303 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376306 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376308 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376309 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376309 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376311 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376311 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376315 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376315 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376319 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376319 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376321 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376321 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376325 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376328 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376328 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376328 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376332 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376332 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376334 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376334 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376335 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376335 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376335 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376336 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1503605376336 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376338 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376338 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376338 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376342 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376345 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376345 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376352 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376352 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376356 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376356 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376358 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376360 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376360 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376362 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376362 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376364 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376364 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376366 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376366 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376368 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376368 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376371 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376371 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376377 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376377 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376379 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376379 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376454 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376454 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376457 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376461 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376463 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376465 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376467 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376470 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376474 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376476 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376478 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376478 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376481 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376481 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376483 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376483 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376493 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376495 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376495 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376508 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376508 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376510 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376510 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376511 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376513 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376515 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376517 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376517 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376519 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376519 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376521 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376521 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376523 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376523 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376525 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376525 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376527 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376527 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605376530 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376530 ""} |
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(96) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(96): created implicit net for \"top_tx_ready_tick\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 96 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376532 ""} |
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376533 ""} |
{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1503605376809 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376811 "|SPW_ULIGHT_FIFO"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" { } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376816 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376829 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376834 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376838 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376843 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376847 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376853 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376880 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376896 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376914 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376927 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376937 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376944 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376945 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376945 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376950 ""} |
{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } } } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605376960 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "umemphy" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 573 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376962 ""} |
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "reset_n_seq_clk hps_sdram_p0_acv_hard_memphy.v(420) " "Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 hps_sdram_p0_acv_hard_memphy.v(557) " "Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 557 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "reset_n_seq_clk 0 hps_sdram_p0_acv_hard_memphy.v(420) " "Net \"reset_n_seq_clk\" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0'" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ctl_reset_export_n hps_sdram_p0_acv_hard_memphy.v(222) " "Output port \"ctl_reset_export_n\" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 222 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376969 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_ldc ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc " "Elaborating entity \"hps_sdram_p0_acv_ldc\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "memphy_ldc" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 554 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376971 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dq hps_sdram_p0_acv_ldc.v(45) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object \"phy_clk_dq\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 45 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376974 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dqs_2x hps_sdram_p0_acv_ldc.v(47) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object \"phy_clk_dqs_2x\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1503605376974 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_io_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_io_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "uio_pads" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 780 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376978 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ddio_phy_dqdin\[179..32\] hps_sdram_p0_acv_hard_io_pads.v(191) " "Output port \"ddio_phy_dqdin\[179..32\]\" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 191 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605376982 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_addr_cmd_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_addr_cmd_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "uaddr_cmd_pads" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605376985 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "uaddress_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377094 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ubank_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 166 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377115 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ucmd_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377125 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ureset_n_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 198 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377142 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altddio_out\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377201 ""} |
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377202 ""} |
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Parameter \"extend_oe_disable\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invert_output OFF " "Parameter \"invert_output\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Parameter \"lpm_type\" = \"altddio_out\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Parameter \"oe_reg\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_high OFF " "Parameter \"power_up_high\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Parameter \"width\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377203 ""} } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1503605377203 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_uqe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_uqe " "Found entity 1: ddio_out_uqe" { } { { "db/ddio_out_uqe.tdf" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/db/ddio_out_uqe.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1503605377273 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605377273 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_uqe ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated " "Elaborating entity \"ddio_out_uqe\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated\"" { } { { "altddio_out.tdf" "auto_generated" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altddio_out.tdf" 101 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377274 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_clock_pair_generator ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator " "Elaborating entity \"hps_sdram_p0_clock_pair_generator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].uclk_generator" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 337 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377284 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_altdqdqs ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs " "Elaborating entity \"hps_sdram_p0_altdqdqs\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "dq_ddio\[0\].ubidir_dq_dqs" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377290 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdq_dqs2_acv_connect_to_hard_phy_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst " "Elaborating entity \"altdq_dqs2_acv_connect_to_hard_phy_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "altdq_dqs2_inst" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 146 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377294 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hhp_qseq_synth_top ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq " "Elaborating entity \"altera_mem_if_hhp_qseq_synth_top\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377365 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hard_memory_controller_top_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0 " "Elaborating entity \"altera_mem_if_hard_memory_controller_top_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "c0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377372 ""} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377380 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377381 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1503605377382 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_oct_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct " "Elaborating entity \"altera_mem_if_oct_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "oct" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377388 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_dll_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll " "Elaborating entity \"altera_mem_if_dll_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "dll" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 814 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377392 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_led_pio_test ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test " "Elaborating entity \"ulight_fifo_led_pio_test\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "led_pio_test" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 339 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377397 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_pll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0 " "Elaborating entity \"ulight_fifo_pll_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "pll_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377407 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborating entity \"altera_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "altera_pll_i" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377454 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvds_clk altera_pll.v(320) " "Output port \"lvds_clk\" at altera_pll.v(320) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 320 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_pll.v(321) " "Output port \"loaden\" at altera_pll.v(321) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 321 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk_out altera_pll.v(322) " "Output port \"extclk_out\" at altera_pll.v(322) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 322 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "wire_to_nowhere_64 " "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 ""} |
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377458 ""} |
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "fractional_vco_multiplier false " "Parameter \"fractional_vco_multiplier\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "reference_clock_frequency 100.0 MHz " "Parameter \"reference_clock_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_cout 32 " "Parameter \"pll_fractional_cout\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_dsm_out_sel 1st_order " "Parameter \"pll_dsm_out_sel\" = \"1st_order\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode direct " "Parameter \"operation_mode\" = \"direct\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_clocks 1 " "Parameter \"number_of_clocks\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency0 400.000000 MHz " "Parameter \"output_clock_frequency0\" = \"400.000000 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift0 0 ps " "Parameter \"phase_shift0\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle0 50 " "Parameter \"duty_cycle0\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency1 0 MHz " "Parameter \"output_clock_frequency1\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift1 0 ps " "Parameter \"phase_shift1\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle1 50 " "Parameter \"duty_cycle1\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency2 0 MHz " "Parameter \"output_clock_frequency2\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift2 0 ps " "Parameter \"phase_shift2\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle2 50 " "Parameter \"duty_cycle2\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency3 0 MHz " "Parameter \"output_clock_frequency3\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift3 0 ps " "Parameter \"phase_shift3\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle3 50 " "Parameter \"duty_cycle3\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency4 0 MHz " "Parameter \"output_clock_frequency4\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift4 0 ps " "Parameter \"phase_shift4\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle4 50 " "Parameter \"duty_cycle4\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency5 0 MHz " "Parameter \"output_clock_frequency5\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift5 0 ps " "Parameter \"phase_shift5\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle5 50 " "Parameter \"duty_cycle5\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency6 0 MHz " "Parameter \"output_clock_frequency6\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift6 0 ps " "Parameter \"phase_shift6\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle6 50 " "Parameter \"duty_cycle6\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency7 0 MHz " "Parameter \"output_clock_frequency7\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift7 0 ps " "Parameter \"phase_shift7\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle7 50 " "Parameter \"duty_cycle7\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency8 0 MHz " "Parameter \"output_clock_frequency8\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift8 0 ps " "Parameter \"phase_shift8\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle8 50 " "Parameter \"duty_cycle8\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency9 0 MHz " "Parameter \"output_clock_frequency9\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift9 0 ps " "Parameter \"phase_shift9\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle9 50 " "Parameter \"duty_cycle9\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency10 0 MHz " "Parameter \"output_clock_frequency10\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift10 0 ps " "Parameter \"phase_shift10\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle10 50 " "Parameter \"duty_cycle10\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency11 0 MHz " "Parameter \"output_clock_frequency11\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift11 0 ps " "Parameter \"phase_shift11\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle11 50 " "Parameter \"duty_cycle11\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency12 0 MHz " "Parameter \"output_clock_frequency12\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift12 0 ps " "Parameter \"phase_shift12\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle12 50 " "Parameter \"duty_cycle12\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency13 0 MHz " "Parameter \"output_clock_frequency13\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift13 0 ps " "Parameter \"phase_shift13\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle13 50 " "Parameter \"duty_cycle13\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency14 0 MHz " "Parameter \"output_clock_frequency14\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift14 0 ps " "Parameter \"phase_shift14\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle14 50 " "Parameter \"duty_cycle14\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency15 0 MHz " "Parameter \"output_clock_frequency15\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift15 0 ps " "Parameter \"phase_shift15\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle15 50 " "Parameter \"duty_cycle15\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency16 0 MHz " "Parameter \"output_clock_frequency16\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift16 0 ps " "Parameter \"phase_shift16\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle16 50 " "Parameter \"duty_cycle16\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency17 0 MHz " "Parameter \"output_clock_frequency17\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift17 0 ps " "Parameter \"phase_shift17\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle17 50 " "Parameter \"duty_cycle17\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type Cyclone V " "Parameter \"pll_type\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_subtype General " "Parameter \"pll_subtype\" = \"General\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_hi_div 2 " "Parameter \"m_cnt_hi_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_lo_div 2 " "Parameter \"m_cnt_lo_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_hi_div 256 " "Parameter \"n_cnt_hi_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_lo_div 256 " "Parameter \"n_cnt_lo_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_bypass_en false " "Parameter \"m_cnt_bypass_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_bypass_en true " "Parameter \"n_cnt_bypass_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_odd_div_duty_en false " "Parameter \"m_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_odd_div_duty_en false " "Parameter \"n_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div0 256 " "Parameter \"c_cnt_hi_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div0 256 " "Parameter \"c_cnt_lo_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst0 1 " "Parameter \"c_cnt_prst0\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst0 0 " "Parameter \"c_cnt_ph_mux_prst0\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src0 ph_mux_clk " "Parameter \"c_cnt_in_src0\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en0 true " "Parameter \"c_cnt_bypass_en0\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en0 false " "Parameter \"c_cnt_odd_div_duty_en0\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div1 1 " "Parameter \"c_cnt_hi_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div1 1 " "Parameter \"c_cnt_lo_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst1 1 " "Parameter \"c_cnt_prst1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst1 0 " "Parameter \"c_cnt_ph_mux_prst1\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src1 ph_mux_clk " "Parameter \"c_cnt_in_src1\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en1 true " "Parameter \"c_cnt_bypass_en1\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en1 false " "Parameter \"c_cnt_odd_div_duty_en1\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div2 1 " "Parameter \"c_cnt_hi_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div2 1 " "Parameter \"c_cnt_lo_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst2 1 " "Parameter \"c_cnt_prst2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst2 0 " "Parameter \"c_cnt_ph_mux_prst2\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src2 ph_mux_clk " "Parameter \"c_cnt_in_src2\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en2 true " "Parameter \"c_cnt_bypass_en2\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en2 false " "Parameter \"c_cnt_odd_div_duty_en2\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div3 1 " "Parameter \"c_cnt_hi_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div3 1 " "Parameter \"c_cnt_lo_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst3 1 " "Parameter \"c_cnt_prst3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst3 0 " "Parameter \"c_cnt_ph_mux_prst3\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src3 ph_mux_clk " "Parameter \"c_cnt_in_src3\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en3 true " "Parameter \"c_cnt_bypass_en3\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en3 false " "Parameter \"c_cnt_odd_div_duty_en3\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div4 1 " "Parameter \"c_cnt_hi_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div4 1 " "Parameter \"c_cnt_lo_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst4 1 " "Parameter \"c_cnt_prst4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst4 0 " "Parameter \"c_cnt_ph_mux_prst4\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src4 ph_mux_clk " "Parameter \"c_cnt_in_src4\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en4 true " "Parameter \"c_cnt_bypass_en4\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en4 false " "Parameter \"c_cnt_odd_div_duty_en4\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div5 1 " "Parameter \"c_cnt_hi_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div5 1 " "Parameter \"c_cnt_lo_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst5 1 " "Parameter \"c_cnt_prst5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst5 0 " "Parameter \"c_cnt_ph_mux_prst5\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src5 ph_mux_clk " "Parameter \"c_cnt_in_src5\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en5 true " "Parameter \"c_cnt_bypass_en5\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en5 false " "Parameter \"c_cnt_odd_div_duty_en5\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div6 1 " "Parameter \"c_cnt_hi_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div6 1 " "Parameter \"c_cnt_lo_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst6 1 " "Parameter \"c_cnt_prst6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst6 0 " "Parameter \"c_cnt_ph_mux_prst6\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src6 ph_mux_clk " "Parameter \"c_cnt_in_src6\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en6 true " "Parameter \"c_cnt_bypass_en6\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en6 false " "Parameter \"c_cnt_odd_div_duty_en6\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div7 1 " "Parameter \"c_cnt_hi_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div7 1 " "Parameter \"c_cnt_lo_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst7 1 " "Parameter \"c_cnt_prst7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst7 0 " "Parameter \"c_cnt_ph_mux_prst7\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src7 ph_mux_clk " "Parameter \"c_cnt_in_src7\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en7 true " "Parameter \"c_cnt_bypass_en7\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en7 false " "Parameter \"c_cnt_odd_div_duty_en7\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div8 1 " "Parameter \"c_cnt_hi_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div8 1 " "Parameter \"c_cnt_lo_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst8 1 " "Parameter \"c_cnt_prst8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst8 0 " "Parameter \"c_cnt_ph_mux_prst8\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src8 ph_mux_clk " "Parameter \"c_cnt_in_src8\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en8 true " "Parameter \"c_cnt_bypass_en8\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en8 false " "Parameter \"c_cnt_odd_div_duty_en8\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div9 1 " "Parameter \"c_cnt_hi_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div9 1 " "Parameter \"c_cnt_lo_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst9 1 " "Parameter \"c_cnt_prst9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst9 0 " "Parameter \"c_cnt_ph_mux_prst9\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src9 ph_mux_clk " "Parameter \"c_cnt_in_src9\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en9 true " "Parameter \"c_cnt_bypass_en9\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en9 false " "Parameter \"c_cnt_odd_div_duty_en9\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div10 1 " "Parameter \"c_cnt_hi_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div10 1 " "Parameter \"c_cnt_lo_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst10 1 " "Parameter \"c_cnt_prst10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst10 0 " "Parameter \"c_cnt_ph_mux_prst10\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src10 ph_mux_clk " "Parameter \"c_cnt_in_src10\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en10 true " "Parameter \"c_cnt_bypass_en10\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en10 false " "Parameter \"c_cnt_odd_div_duty_en10\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div11 1 " "Parameter \"c_cnt_hi_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div11 1 " "Parameter \"c_cnt_lo_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst11 1 " "Parameter \"c_cnt_prst11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst11 0 " "Parameter \"c_cnt_ph_mux_prst11\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src11 ph_mux_clk " "Parameter \"c_cnt_in_src11\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en11 true " "Parameter \"c_cnt_bypass_en11\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en11 false " "Parameter \"c_cnt_odd_div_duty_en11\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div12 1 " "Parameter \"c_cnt_hi_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div12 1 " "Parameter \"c_cnt_lo_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst12 1 " "Parameter \"c_cnt_prst12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst12 0 " "Parameter \"c_cnt_ph_mux_prst12\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src12 ph_mux_clk " "Parameter \"c_cnt_in_src12\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en12 true " "Parameter \"c_cnt_bypass_en12\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en12 false " "Parameter \"c_cnt_odd_div_duty_en12\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div13 1 " "Parameter \"c_cnt_hi_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div13 1 " "Parameter \"c_cnt_lo_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst13 1 " "Parameter \"c_cnt_prst13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst13 0 " "Parameter \"c_cnt_ph_mux_prst13\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src13 ph_mux_clk " "Parameter \"c_cnt_in_src13\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en13 true " "Parameter \"c_cnt_bypass_en13\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en13 false " "Parameter \"c_cnt_odd_div_duty_en13\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div14 1 " "Parameter \"c_cnt_hi_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div14 1 " "Parameter \"c_cnt_lo_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst14 1 " "Parameter \"c_cnt_prst14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst14 0 " "Parameter \"c_cnt_ph_mux_prst14\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src14 ph_mux_clk " "Parameter \"c_cnt_in_src14\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en14 true " "Parameter \"c_cnt_bypass_en14\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en14 false " "Parameter \"c_cnt_odd_div_duty_en14\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div15 1 " "Parameter \"c_cnt_hi_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div15 1 " "Parameter \"c_cnt_lo_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst15 1 " "Parameter \"c_cnt_prst15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst15 0 " "Parameter \"c_cnt_ph_mux_prst15\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src15 ph_mux_clk " "Parameter \"c_cnt_in_src15\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en15 true " "Parameter \"c_cnt_bypass_en15\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en15 false " "Parameter \"c_cnt_odd_div_duty_en15\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div16 1 " "Parameter \"c_cnt_hi_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div16 1 " "Parameter \"c_cnt_lo_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst16 1 " "Parameter \"c_cnt_prst16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst16 0 " "Parameter \"c_cnt_ph_mux_prst16\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src16 ph_mux_clk " "Parameter \"c_cnt_in_src16\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en16 true " "Parameter \"c_cnt_bypass_en16\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en16 false " "Parameter \"c_cnt_odd_div_duty_en16\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div17 1 " "Parameter \"c_cnt_hi_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div17 1 " "Parameter \"c_cnt_lo_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst17 1 " "Parameter \"c_cnt_prst17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst17 0 " "Parameter \"c_cnt_ph_mux_prst17\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src17 ph_mux_clk " "Parameter \"c_cnt_in_src17\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en17 true " "Parameter \"c_cnt_bypass_en17\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en17 false " "Parameter \"c_cnt_odd_div_duty_en17\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_vco_div 2 " "Parameter \"pll_vco_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_cp_current 30 " "Parameter \"pll_cp_current\" = \"30\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_bwctrl 2000 " "Parameter \"pll_bwctrl\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_output_clk_frequency 400.0 MHz " "Parameter \"pll_output_clk_frequency\" = \"400.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_division 1 " "Parameter \"pll_fractional_division\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "mimic_fbclk_type none " "Parameter \"mimic_fbclk_type\" = \"none\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_1 glb " "Parameter \"pll_fbclk_mux_1\" = \"glb\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_2 m_cnt " "Parameter \"pll_fbclk_mux_2\" = \"m_cnt\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_m_cnt_in_src ph_mux_clk " "Parameter \"pll_m_cnt_in_src\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_slf_rst false " "Parameter \"pll_slf_rst\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "refclk1_frequency 100.0 MHz " "Parameter \"refclk1_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_loss_sw_en true " "Parameter \"pll_clk_loss_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_manu_clk_sw_en false " "Parameter \"pll_manu_clk_sw_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_auto_clk_sw_en true " "Parameter \"pll_auto_clk_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clkin_1_src clk_1 " "Parameter \"pll_clkin_1_src\" = \"clk_1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_sw_dly 0 " "Parameter \"pll_clk_sw_dly\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1503605377460 ""} } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1503605377460 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dps_extra_kick ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst " "Elaborating entity \"dps_extra_kick\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\"" { } { { "altera_pll.v" "dps_extra_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377471 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377473 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dprio_init ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst " "Elaborating entity \"dprio_init\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\"" { } { { "altera_pll.v" "dprio_init_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377476 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377477 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\"" { } { { "altera_pll.v" "lcell_cntsel_int_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377486 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377488 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\"" { } { { "altera_pll.v" "lcell_cntsel_int_1" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377493 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377494 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\"" { } { { "altera_pll.v" "lcell_cntsel_int_2" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377496 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377497 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\"" { } { { "altera_pll.v" "lcell_cntsel_int_3" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377499 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377500 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\"" { } { { "altera_pll.v" "lcell_cntsel_int_4" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377503 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377504 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll " "Elaborating entity \"altera_cyclonev_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\"" { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377524 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk altera_cyclonev_pll.v(632) " "Output port \"extclk\" at altera_cyclonev_pll.v(632) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 632 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377531 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "clkout\[0\] altera_cyclonev_pll.v(637) " "Output port \"clkout\[0\]\" at altera_cyclonev_pll.v(637) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 637 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_cyclonev_pll.v(641) " "Output port \"loaden\" at altera_cyclonev_pll.v(641) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 641 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvdsclk altera_cyclonev_pll.v(642) " "Output port \"lvdsclk\" at altera_cyclonev_pll.v(642) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 642 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377532 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll_base ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 " "Elaborating entity \"altera_cyclonev_pll_base\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\"" { } { { "altera_cyclonev_pll.v" "fpll_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377537 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377542 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_rx ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx " "Elaborating entity \"ulight_fifo_timecode_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_rx" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 385 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377548 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_tx_data ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data " "Elaborating entity \"ulight_fifo_timecode_tx_data\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_tx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 396 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377551 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_write_data_fifo_tx ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx " "Elaborating entity \"ulight_fifo_write_data_fifo_tx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "write_data_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377560 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "mm_interconnect_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377564 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_translator" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 1962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377760 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_axi_master_ni ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent " "Elaborating entity \"altera_merlin_axi_master_ni\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_agent" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3434 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377814 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377819 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3518 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377824 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377828 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rsp_fifo" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3559 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377833 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rdata_fifo" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3600 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605377839 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378122 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378129 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router_002" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378140 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378144 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_wr_limiter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7520 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378244 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7620 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378254 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_13_1 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter_13_1\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_13_1.burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378259 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 778 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378271 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_burstwrap_increment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment " "Elaborating entity \"altera_merlin_burst_adapter_burstwrap_increment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_burstwrap_increment" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378276 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_min ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min " "Elaborating entity \"altera_merlin_burst_adapter_min\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_min" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 1004 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378281 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_subtractor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub " "Elaborating entity \"altera_merlin_burst_adapter_subtractor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "ab_sub" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378285 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract " "Elaborating entity \"altera_merlin_burst_adapter_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "subtract" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 88 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605378290 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_demux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8813 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379228 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_mux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379239 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 287 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379243 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379246 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_demux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379398 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_mux" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10111 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379438 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 630 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379456 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379459 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "avalon_st_adapter" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10283 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379473 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379476 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller ulight_fifo:u0\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "rst_controller" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 616 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379595 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379600 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379604 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spw_ulight_con_top_x spw_ulight_con_top_x:A_SPW_TOP " "Elaborating entity \"spw_ulight_con_top_x\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\"" { } { { "top_rtl/spw_fifo_ulight.v" "A_SPW_TOP" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 143 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379619 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top_spw_ultra_light spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW " "Elaborating entity \"top_spw_ultra_light\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "SPW" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 101 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379622 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM " "Elaborating entity \"FSM_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\"" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "FSM" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 113 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379624 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX " "Elaborating entity \"RX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\"" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "RX" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379628 ""} |
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "rx_spw.v(508) " "Verilog HDL Case Statement information at rx_spw.v(508): all case item expressions in this case statement are onehot" { } { { "../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/rx_spw.v" 508 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1503605379632 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX " "Elaborating entity \"TX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\"" { } { { "../rtl/RTL_VB/top_spw_ultra_light.v" "TX" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/top_spw_ultra_light.v" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379638 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_rx spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data " "Elaborating entity \"fifo_rx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "rx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 116 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379644 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_tx spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Elaborating entity \"fifo_tx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 130 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379648 ""} |
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "counter fifo_tx.v(59) " "Verilog HDL Always Construct warning at fifo_tx.v(59): inferring latch(es) for variable \"counter\", which holds its previous value in one or more paths through the always construct" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1503605379651 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"} |
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[0\] fifo_tx.v(59) " "Inferred latch for \"counter\[0\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"} |
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[1\] fifo_tx.v(59) " "Inferred latch for \"counter\[1\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"} |
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[2\] fifo_tx.v(59) " "Inferred latch for \"counter\[2\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"} |
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[3\] fifo_tx.v(59) " "Inferred latch for \"counter\[3\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"} |
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[4\] fifo_tx.v(59) " "Inferred latch for \"counter\[4\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"} |
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "counter\[5\] fifo_tx.v(59) " "Inferred latch for \"counter\[5\]\" at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379657 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data"} |
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[5\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[5\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""} |
{ "Error" "EVRFX_VDB_NET_ANOTHER_DRIVER" "fifo_tx.v(59) " "Constant driver at fifo_tx.v(59)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 59 0 0 } } } 0 10029 "Constant driver at %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""} |
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[4\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[4\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""} |
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[3\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[3\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""} |
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[2\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[2\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""} |
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[1\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[1\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""} |
{ "Error" "EVRFX_VDB_NET_MULTIPLE_DRIVERS" "counter\[0\] fifo_tx.v(93) " "Can't resolve multiple constant drivers for net \"counter\[0\]\" at fifo_tx.v(93)" { } { { "../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/fifo_tx.v" 93 0 0 } } } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605379659 ""} |
{ "Error" "ESGN_USER_HIER_ELABORATION_FAILURE" "spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Can't elaborate user hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" { } { { "../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/rtl/RTL_VB/spw_ulight_con_top_x.v" 130 0 0 } } } 0 12152 "Can't elaborate user hierarchy \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1503605379660 ""} |
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/SPW_SC/TESTSTRESS/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1503605380524 ""} |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1516735621447 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Shell Quartus Prime " "Running Quartus Prime Shell" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 23 17:27:00 2018 " "Processing started: Tue Jan 23 17:27:00 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1516735621464 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight " "Command: quartus_sh --ip_upgrade -variation_files ulight_fifo.qsys spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""} |
{ "Info" "IQEXE_START_BANNER_TCL_ARGS" "-variation_files ulight_fifo.qsys spw_fifo_ulight " "Quartus(args): -variation_files ulight_fifo.qsys spw_fifo_ulight" { } { } 0 0 "Quartus(args): %1!s!" 0 0 "Shell" 0 -1 1516735621464 ""} |
{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo.qsys ulight_fifo.BAK.qsys " "Backing up file \"ulight_fifo.qsys\" to \"ulight_fifo.BAK.qsys\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653410 ""} |
{ "Info" "IIPMAN_IPRGEN_BACKUP_FILE" "ulight_fifo/synthesis/ulight_fifo.v ulight_fifo.BAK.v " "Backing up file \"ulight_fifo/synthesis/ulight_fifo.v\" to \"ulight_fifo.BAK.v\"" { } { } 0 11902 "Backing up file \"%1!s!\" to \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653455 ""} |
{ "Info" "IIPMAN_IPRGEN_START" "Qsys ulight_fifo.qsys " "Started upgrading IP component Qsys with file \"ulight_fifo.qsys\"" { } { } 0 11837 "Started upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735653457 ""} |
{ "Info" "" "" "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" { } { } 0 0 "2018.01.23.17:28:24 Info: Starting to upgrade the IP cores in the Platform Designer system" 0 0 "Shell" 0 -1 1516735704060 ""} |
{ "Info" "" "" "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" { } { } 0 0 "2018.01.23.17:28:24 Info: Finished upgrading the ip cores" 0 0 "Shell" 0 -1 1516735704118 ""} |
{ "Info" "ulight_fifo_generation.rpt" "" "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Saving generation log to /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo" 0 0 "Shell" 0 -1 1516735739162 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Starting: Create simulation model" { } { } 0 0 "2018.01.23.17:28:59 Info: Starting: Create simulation model" 0 0 "Shell" 0 -1 1516735739163 ""} |
{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:28:59 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735739395 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Reading input file" { } { } 0 0 "2018.01.23.17:28:59 Info: Reading input file" 0 0 "Shell" 0 -1 1516735739472 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739501 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735739502 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735739503 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735739503 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739504 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735739505 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739506 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735739510 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739513 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735739515 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739516 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735739520 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739522 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735739523 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739525 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735739527 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739528 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735739543 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739544 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735739544 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739546 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735739546 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739547 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735739548 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739548 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735739549 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735739550 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735739564 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739586 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735739586 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739588 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735739589 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739590 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735739598 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735739599 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735739600 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739604 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735739605 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739606 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735739612 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739614 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735739615 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739616 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_enable" 0 0 "Shell" 0 -1 1516735739625 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739627 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735739627 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739628 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735739629 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:28:59 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735739630 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735739631 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Building connections" { } { } 0 0 "2018.01.23.17:28:59 Info: Building connections" 0 0 "Shell" 0 -1 1516735739632 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Parameterizing connections" { } { } 0 0 "2018.01.23.17:28:59 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735739642 ""} |
{ "Info" "" "" "2018.01.23.17:28:59 Info: Validating" { } { } 0 0 "2018.01.23.17:28:59 Info: Validating" 0 0 "Shell" 0 -1 1516735739645 ""} |
{ "Info" "" "" "2018.01.23.17:29:08 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:29:08 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735748747 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752187 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.\n2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735752190 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735752190 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735752196 ""} |
{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735752197 ""} |
{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735752198 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735752198 ""} |
{ "Warning" "" "" "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:29:12 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735752198 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752199 ""} |
{ "Info" "" "" "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:29:12 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735752200 ""} |
{ "Info" "" "" "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" { } { } 0 0 "2018.01.23.17:29:16 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for SIM_VERILOG" 0 0 "Shell" 0 -1 1516735756855 ""} |
{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" { } { } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735775279 ""} |
{ "Warning" "" "" "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" { } { } 0 0 "2018.01.23.17:29:35 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735775279 ""} |
{ "Info" "" "" "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:29:39 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735779023 ""} |
{ "Info" " ]" "" "2018.01.23.17:29:39 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" { } { } 0 0 "2018.01.23.17:29:39 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0002_auto_start_gen" 0 0 "Shell" 0 -1 1516735779023 ""} |
{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:29:40 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735780647 ""} |
{ "Info" "" "" "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" { } { } 0 0 "2018.01.23.17:29:40 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735780650 ""} |
{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780733 ""} |
{ "Info" " ]" "" "2018.01.23.17:29:40 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0003_clock_sel_gen" 0 0 "Shell" 0 -1 1516735780733 ""} |
{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735780886 ""} |
{ "Info" "" "" "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" { } { } 0 0 "2018.01.23.17:29:40 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735780888 ""} |
{ "Info" "" "" "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735780972 ""} |
{ "Info" " ]" "" "2018.01.23.17:29:40 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" { } { } 0 0 "2018.01.23.17:29:40 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0004_counter_rx_fifo_gen" 0 0 "Shell" 0 -1 1516735780972 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" { } { } 0 0 "2018.01.23.17:29:41 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'\n2018.01.23.17:29:41 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735781099 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735781242 ""} |
{ "Info" " ]" "" "2018.01.23.17:29:41 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0005_data_flag_rx_gen" 0 0 "Shell" 0 -1 1516735781242 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" { } { } 0 0 "2018.01.23.17:29:41 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'\n2018.01.23.17:29:41 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735781379 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781502 ""} |
{ "Info" " ]" "" "2018.01.23.17:29:41 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0006_data_info_gen" 0 0 "Shell" 0 -1 1516735781502 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735781634 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" { } { } 0 0 "2018.01.23.17:29:41 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735781635 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781751 ""} |
{ "Info" " ]" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0007_fifo_empty_rx_status_gen" 0 0 "Shell" 0 -1 1516735781752 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735781904 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" { } { } 0 0 "2018.01.23.17:29:41 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735781906 ""} |
{ "Info" "" "" "2018.01.23.17:29:41 Info: hps_0: \"Running for module: hps_0\"" { } { } 0 0 "2018.01.23.17:29:41 Info: hps_0: \"Running for module: hps_0\"" 0 0 "Shell" 0 -1 1516735781908 ""} |
{ "Info" "" "" "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:29:42 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735782735 ""} |
{ "Info" "" "" "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:29:43 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735783333 ""} |
{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735783343 ""} |
{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735783636 ""} |
{ "Warning" "" "" "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:29:43 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735783757 ""} |
{ "Info" "" "" "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" { } { } 0 0 "2018.01.23.17:29:44 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735784424 ""} |
{ "Info" " ]" "" "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" { } { } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0008_led_pio_test_gen" 0 0 "Shell" 0 -1 1516735784521 ""} |
{ "Info" "" "" "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" { } { } 0 0 "2018.01.23.17:29:44 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'\n2018.01.23.17:29:44 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735784720 ""} |
{ "Info" "" "" "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" { } { } 0 0 "2018.01.23.17:29:44 Info: pll_0: Generating simgen model" 0 0 "Shell" 0 -1 1516735784779 ""} |
{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" { } { } 0 0 "2018.01.23.17:30:12 Info: pll_0: Simgen was successful" 0 0 "Shell" 0 -1 1516735812813 ""} |
{ "Info" "" "" "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" { } { } 0 0 "2018.01.23.17:30:12 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735812815 ""} |
{ "Info" "" "" "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:30:12 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735812969 ""} |
{ "Info" " ]" "" "2018.01.23.17:30:12 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" { } { } 0 0 "2018.01.23.17:30:12 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0010_timecode_rx_gen" 0 0 "Shell" 0 -1 1516735812970 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735813142 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735813144 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813212 ""} |
{ "Info" " ]" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0011_timecode_tx_data_gen" 0 0 "Shell" 0 -1 1516735813212 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735813329 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" { } { } 0 0 "2018.01.23.17:30:13 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735813330 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813400 ""} |
{ "Info" " ]" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=1 --sim_dir=/tmp/alt7554_7831099621877055177.dir/0012_write_data_fifo_tx_gen" 0 0 "Shell" 0 -1 1516735813401 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735813531 ""} |
{ "Info" "" "" "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" { } { } 0 0 "2018.01.23.17:30:13 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735813533 ""} |
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815764 ""} |
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815843 ""} |
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815918 ""} |
{ "Info" "" "" "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:15 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735815973 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816040 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816108 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816205 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816278 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816352 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816421 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816501 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816574 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816654 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816731 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816801 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816868 ""} |
{ "Info" "" "" "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:16 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735816942 ""} |
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817025 ""} |
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817110 ""} |
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817182 ""} |
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817249 ""} |
{ "Info" "" "" "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:30:17 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735817317 ""} |
{ "Info" "" "" "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" { } { } 0 0 "2018.01.23.17:30:20 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735820323 ""} |
{ "Info" "" "" "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 0 "2018.01.23.17:30:20 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735820407 ""} |
{ "Info" "" "" "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" { } { } 0 0 "2018.01.23.17:30:20 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735820733 ""} |
{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" { } { } 0 0 "2018.01.23.17:30:20 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735820852 ""} |
{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" { } { } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735820878 ""} |
{ "Info" "" "" "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" { } { } 0 0 "2018.01.23.17:30:20 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735820907 ""} |
{ "Info" "" "" "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" { } { } 0 0 "2018.01.23.17:30:20 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735820943 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" { } { } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735821010 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" { } { } 0 0 "2018.01.23.17:30:21 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735821047 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" { } { } 0 0 "2018.01.23.17:30:21 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735821058 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735821132 ""} |
{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821135 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735821258 ""} |
{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821262 ""} |
{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821263 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735821319 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735821334 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735821340 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" { } { } 0 0 "2018.01.23.17:30:21 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735821360 ""} |
{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821362 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" { } { } 0 0 "2018.01.23.17:30:21 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735821401 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" { } { } 0 0 "2018.01.23.17:30:21 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735821470 ""} |
{ "Info" "verbosity_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""} |
{ "Info" "avalon_utilities_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821471 ""} |
{ "Info" "avalon_mm_pkg.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821472 ""} |
{ "Info" "altera_avalon_mm_slave_bfm.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821474 ""} |
{ "Info" "altera_avalon_interrupt_sink.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""} |
{ "Info" "altera_avalon_clock_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821475 ""} |
{ "Info" "altera_avalon_reset_source.sv" "" "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" { } { } 0 0 "2018.01.23.17:30:21 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation/submodules" 0 0 "Shell" 0 -1 1516735821476 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" { } { } 0 0 "2018.01.23.17:30:21 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735821510 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" { } { } 0 0 "2018.01.23.17:30:21 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 58 files" 0 0 "Shell" 0 -1 1516735821511 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:30:21 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735821581 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: Finished: Create simulation model" { } { } 0 0 "2018.01.23.17:30:21 Info: Finished: Create simulation model" 0 0 "Shell" 0 -1 1516735821581 ""} |
{ "Info" "" "" "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." { } { } 0 0 "2018.01.23.17:30:21 Info: Starting: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735821582 ""} |
{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:21 Info: sim-script-gen --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821583 ""} |
{ "Info" " --use-relative-paths=true" "" "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:21 Info: Doing: ip-make-simscript --spd=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/ulight_fifo.spd --output-directory=/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735821590 ""} |
{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for MODELSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822982 ""} |
{ "Info" "msim_setup.tcl" "" "2018.01.23.17:30:22 Info: mentor" { } { } 0 0 "2018.01.23.17:30:22 Info: mentor" 0 0 "Shell" 0 -1 1516735822983 ""} |
{ "Info" " directory:" "" "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:22 Info: Generating the following file(s) for VCS simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735822995 ""} |
{ "Info" "vcs_setup.sh" "" "2018.01.23.17:30:22 Info: synopsys/vcs" { } { } 0 0 "2018.01.23.17:30:22 Info: synopsys/vcs" 0 0 "Shell" 0 -1 1516735822996 ""} |
{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for VCSMX simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823007 ""} |
{ "Info" "synopsys_sim.setup" "" "2018.01.23.17:30:23 Info: synopsys/vcsmx" { } { } 0 0 "2018.01.23.17:30:23 Info: synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823054 ""} |
{ "Info" "vcsmx_setup.sh" "" "2018.01.23.17:30:23 Info: synopsys/vcsmx" { } { } 0 0 "2018.01.23.17:30:23 Info: synopsys/vcsmx" 0 0 "Shell" 0 -1 1516735823361 ""} |
{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for NCSIM simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823387 ""} |
{ "Info" "cds.lib" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823388 ""} |
{ "Info" "hdl.var" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823404 ""} |
{ "Info" "ncsim_setup.sh" "" "2018.01.23.17:30:23 Info: cadence" { } { } 0 0 "2018.01.23.17:30:23 Info: cadence" 0 0 "Shell" 0 -1 1516735823411 ""} |
{ "Info" " directory" "" "2018.01.23.17:30:23 Info: 32 .cds.lib files in cadence/cds_libs" { } { } 0 0 "2018.01.23.17:30:23 Info: 32 .cds.lib files in cadence/cds_libs" 0 0 "Shell" 0 -1 1516735823411 ""} |
{ "Info" " directory:" "" "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: Generating the following file(s) for RIVIERA simulator in /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823422 ""} |
{ "Info" "rivierapro_setup.tcl" "" "2018.01.23.17:30:23 Info: aldec" { } { } 0 0 "2018.01.23.17:30:23 Info: aldec" 0 0 "Shell" 0 -1 1516735823423 ""} |
{ "Info" "." "" "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" { } { } 0 0 "2018.01.23.17:30:23 Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/simulation" 0 0 "Shell" 0 -1 1516735823423 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." { } { } 0 0 "2018.01.23.17:30:23 Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project." 0 0 "Shell" 0 -1 1516735823424 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." { } { } 0 0 "2018.01.23.17:30:23 Info: Finished: Create Modelsim Project." 0 0 "Shell" 0 -1 1516735823424 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" { } { } 0 0 "2018.01.23.17:30:23 Info: Starting: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735823425 ""} |
{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:30:23 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735823430 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Reading input file" { } { } 0 0 "2018.01.23.17:30:23 Info: Reading input file" 0 0 "Shell" 0 -1 1516735823456 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823461 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735823461 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735823462 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735823463 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823464 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735823464 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823465 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735823466 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823466 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735823467 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823468 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735823472 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823473 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735823474 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823475 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735823475 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823476 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735823477 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823484 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735823484 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823486 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735823487 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823488 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fifo_full_tx_status" 0 0 "Shell" 0 -1 1516735823488 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding fsm_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823489 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module fsm_info" 0 0 "Shell" 0 -1 1516735823490 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735823491 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735823496 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823514 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735823515 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823516 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735823517 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823518 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735823518 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735823519 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735823521 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823524 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735823524 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823531 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735823531 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823532 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735823533 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:23 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823539 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module timecode_tx_ready" 0 0 "Shell" 0 -1 1516735823542 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823543 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735823543 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:23 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735823544 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735823546 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Building connections" { } { } 0 0 "2018.01.23.17:30:23 Info: Building connections" 0 0 "Shell" 0 -1 1516735823547 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Parameterizing connections" { } { } 0 0 "2018.01.23.17:30:23 Info: Parameterizing connections" 0 0 "Shell" 0 -1 1516735823550 ""} |
{ "Info" "" "" "2018.01.23.17:30:23 Info: Validating" { } { } 0 0 "2018.01.23.17:30:23 Info: Validating" 0 0 "Shell" 0 -1 1516735823560 ""} |
{ "Info" "" "" "2018.01.23.17:30:31 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:30:31 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735831710 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833912 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833913 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833914 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735833914 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735833914 ""} |
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735833914 ""} |
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735833914 ""} |
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735833915 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735833918 ""} |
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735833918 ""} |
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735833918 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735833918 ""} |
{ "Warning" "" "" "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:30:33 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735833918 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""} |
{ "Info" "" "" "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:33 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735833919 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:30:34 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735834875 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" { } { } 0 0 "2018.01.23.17:30:34 Info: Finished: Create block symbol file (.bsf)" 0 0 "Shell" 0 -1 1516735834876 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info:" { } { } 0 0 "2018.01.23.17:30:34 Info:" 0 0 "Shell" 0 -1 1516735834876 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" { } { } 0 0 "2018.01.23.17:30:34 Info: Starting: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735834876 ""} |
{ "Info" "ulight_fifo.qsys" "" "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" { } { } 0 0 "2018.01.23.17:30:34 Info: Loading spw_fifo_ulight" 0 0 "Shell" 0 -1 1516735834883 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Reading input file" { } { } 0 0 "2018.01.23.17:30:34 Info: Reading input file" 0 0 "Shell" 0 -1 1516735834905 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding auto_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834909 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module auto_start" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module auto_start" 0 0 "Shell" 0 -1 1516735834909 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding clk_0 \[clock_source 17.1\]" 0 0 "Shell" 0 -1 1516735834912 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clk_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clk_0" 0 0 "Shell" 0 -1 1516735834913 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding clock_sel \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834913 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module clock_sel" 0 0 "Shell" 0 -1 1516735834914 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding counter_rx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834915 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_rx_fifo" 0 0 "Shell" 0 -1 1516735834915 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding counter_tx_fifo \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834916 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module counter_tx_fifo" 0 0 "Shell" 0 -1 1516735834917 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_flag_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834918 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_flag_rx" 0 0 "Shell" 0 -1 1516735834918 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_info \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834919 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_info" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_info" 0 0 "Shell" 0 -1 1516735834919 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding data_read_en_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834920 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module data_read_en_rx" 0 0 "Shell" 0 -1 1516735834921 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834921 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_rx_status" 0 0 "Shell" 0 -1 1516735834922 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_empty_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834923 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_empty_tx_status" 0 0 "Shell" 0 -1 1516735834925 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_rx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834926 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_rx_status" 0 0 "Shell" 0 -1 1516735834926 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding fifo_full_tx_status \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834927 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module fifo_full_tx_status\n2018.01.23.17:30:34 Info: Adding fsm_info \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module fsm_info\n2018.01.23.17:30:34 Info: Adding hps_0 \[altera_hps 17.1\]" 0 0 "Shell" 0 -1 1516735834929 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module hps_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module hps_0" 0 0 "Shell" 0 -1 1516735834934 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding led_pio_test \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834943 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module led_pio_test" 0 0 "Shell" 0 -1 1516735834944 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding link_disable \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834946 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_disable" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_disable" 0 0 "Shell" 0 -1 1516735834946 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding link_start \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834948 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module link_start" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module link_start" 0 0 "Shell" 0 -1 1516735834948 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding pll_0 \[altera_pll 17.1\]" 0 0 "Shell" 0 -1 1516735834949 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module pll_0" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module pll_0" 0 0 "Shell" 0 -1 1516735834950 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_ready_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_ready_rx" 0 0 "Shell" 0 -1 1516735834953 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_rx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834953 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_rx" 0 0 "Shell" 0 -1 1516735834953 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_data \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834954 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_data" 0 0 "Shell" 0 -1 1516735834955 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding timecode_tx_enable \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_enable\n2018.01.23.17:30:34 Info: Adding timecode_tx_ready \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module timecode_tx_ready\n2018.01.23.17:30:34 Info: Adding write_data_fifo_tx \[altera_avalon_pio 17.1\]\n2018.01.23.17:30:34 Info: Parameterizing module write_data_fifo_tx" 0 0 "Shell" 0 -1 1516735834958 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" { } { } 0 0 "2018.01.23.17:30:34 Info: Adding write_en_tx \[altera_avalon_pio 17.1\]" 0 0 "Shell" 0 -1 1516735834959 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing module write_en_tx" 0 0 "Shell" 0 -1 1516735834959 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Building connections" { } { } 0 0 "2018.01.23.17:30:34 Info: Building connections" 0 0 "Shell" 0 -1 1516735834960 ""} |
{ "Info" "" "" "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" { } { } 0 0 "2018.01.23.17:30:34 Info: Parameterizing connections\n2018.01.23.17:30:34 Info: Validating" 0 0 "Shell" 0 -1 1516735834965 ""} |
{ "Info" "" "" "2018.01.23.17:30:41 Info: Done reading input file" { } { } 0 0 "2018.01.23.17:30:41 Info: Done reading input file" 0 0 "Shell" 0 -1 1516735841270 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_rx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843344 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.counter_tx_fifo: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_flag_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.data_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843345 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735843346 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735843346 ""} |
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735843346 ""} |
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735843346 ""} |
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735843346 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz" 0 0 "Shell" 0 -1 1516735843348 ""} |
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure" 0 0 "Shell" 0 -1 1516735843349 ""} |
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work" 0 0 "Shell" 0 -1 1516735843349 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.pll_0: Able to implement PLL with user settings" 0 0 "Shell" 0 -1 1516735843349 ""} |
{ "Warning" "" "" "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" { } { } 0 0 "2018.01.23.17:30:43 Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1" 0 0 "Shell" 0 -1 1516735843349 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""} |
{ "Info" "" "" "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." { } { } 0 0 "2018.01.23.17:30:43 Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation." 0 0 "Shell" 0 -1 1516735843349 ""} |
{ "Info" "" "" "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" { } { } 0 0 "2018.01.23.17:30:46 Info: ulight_fifo: Generating ulight_fifo \"ulight_fifo\" for QUARTUS_SYNTH" 0 0 "Shell" 0 -1 1516735846790 ""} |
{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" { } { } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for clk_0:clk:clk_out (clk)\"" 0 0 "Shell" 0 -1 1516735856250 ""} |
{ "Warning" "" "" "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" { } { } 0 0 "2018.01.23.17:30:56 Warning: ulight_fifo: \"No matching role found for pll_0:refclk1:refclk1 (refclk1)\"" 0 0 "Shell" 0 -1 1516735856250 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858344 ""} |
{ "Info" "ulight_fifo_auto_start_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0030_auto_start_gen/" 0 0 "Shell" 0 -1 1516735858345 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'" 0 0 "Shell" 0 -1 1516735858460 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" { } { } 0 0 "2018.01.23.17:30:58 Info: auto_start: \"ulight_fifo\" instantiated altera_avalon_pio \"auto_start\"" 0 0 "Shell" 0 -1 1516735858461 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858554 ""} |
{ "Info" "ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0031_clock_sel_gen/" 0 0 "Shell" 0 -1 1516735858555 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'" 0 0 "Shell" 0 -1 1516735858668 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" { } { } 0 0 "2018.01.23.17:30:58 Info: clock_sel: \"ulight_fifo\" instantiated altera_avalon_pio \"clock_sel\"" 0 0 "Shell" 0 -1 1516735858670 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858778 ""} |
{ "Info" "ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0032_counter_rx_fifo_gen/" 0 0 "Shell" 0 -1 1516735858778 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'" 0 0 "Shell" 0 -1 1516735858895 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" { } { } 0 0 "2018.01.23.17:30:58 Info: counter_rx_fifo: \"ulight_fifo\" instantiated altera_avalon_pio \"counter_rx_fifo\"" 0 0 "Shell" 0 -1 1516735858898 ""} |
{ "Info" "" "" "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735858988 ""} |
{ "Info" "ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:58 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" { } { } 0 0 "2018.01.23.17:30:58 Info: data_flag_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0033_data_flag_rx_gen/" 0 0 "Shell" 0 -1 1516735858988 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'" 0 0 "Shell" 0 -1 1516735859104 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" { } { } 0 0 "2018.01.23.17:30:59 Info: data_flag_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"data_flag_rx\"" 0 0 "Shell" 0 -1 1516735859105 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859198 ""} |
{ "Info" "ulight_fifo_data_info_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:59 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0034_data_info_gen/" 0 0 "Shell" 0 -1 1516735859199 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'" 0 0 "Shell" 0 -1 1516735859311 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" { } { } 0 0 "2018.01.23.17:30:59 Info: data_info: \"ulight_fifo\" instantiated altera_avalon_pio \"data_info\"" 0 0 "Shell" 0 -1 1516735859312 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859420 ""} |
{ "Info" "ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0035_fifo_empty_rx_status_gen/" 0 0 "Shell" 0 -1 1516735859420 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'" 0 0 "Shell" 0 -1 1516735859548 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" { } { } 0 0 "2018.01.23.17:30:59 Info: fifo_empty_rx_status: \"ulight_fifo\" instantiated altera_avalon_pio \"fifo_empty_rx_status\"" 0 0 "Shell" 0 -1 1516735859548 ""} |
{ "Info" "" "" "2018.01.23.17:30:59 Info: hps_0: \"Running for module: hps_0\"" { } { } 0 0 "2018.01.23.17:30:59 Info: hps_0: \"Running for module: hps_0\"" 0 0 "Shell" 0 -1 1516735859549 ""} |
{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" { } { } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36" 0 0 "Shell" 0 -1 1516735860279 ""} |
{ "Info" "" "" "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" { } { } 0 0 "2018.01.23.17:31:00 Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19" 0 0 "Shell" 0 -1 1516735860805 ""} |
{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies." 0 0 "Shell" 0 -1 1516735860809 ""} |
{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity" 0 0 "Shell" 0 -1 1516735860825 ""} |
{ "Warning" "" "" "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" { } { } 0 0 "2018.01.23.17:31:00 Warning: hps_0: set_interface_assignment: Interface \"hps_io\" does not exist" 0 0 "Shell" 0 -1 1516735860912 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" { } { } 0 0 "2018.01.23.17:31:01 Info: hps_0: \"ulight_fifo\" instantiated altera_hps \"hps_0\"" 0 0 "Shell" 0 -1 1516735861270 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861415 ""} |
{ "Info" "ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0036_led_pio_test_gen/" 0 0 "Shell" 0 -1 1516735861415 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'" 0 0 "Shell" 0 -1 1516735861536 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" { } { } 0 0 "2018.01.23.17:31:01 Info: led_pio_test: \"ulight_fifo\" instantiated altera_avalon_pio \"led_pio_test\"" 0 0 "Shell" 0 -1 1516735861537 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" { } { } 0 0 "2018.01.23.17:31:01 Info: pll_0: \"ulight_fifo\" instantiated altera_pll \"pll_0\"" 0 0 "Shell" 0 -1 1516735861569 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861676 ""} |
{ "Info" "ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0038_timecode_rx_gen/" 0 0 "Shell" 0 -1 1516735861676 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'" 0 0 "Shell" 0 -1 1516735861788 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_rx: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_rx\"" 0 0 "Shell" 0 -1 1516735861789 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861875 ""} |
{ "Info" "ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0039_timecode_tx_data_gen/" 0 0 "Shell" 0 -1 1516735861876 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'" 0 0 "Shell" 0 -1 1516735861988 ""} |
{ "Info" "" "" "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" { } { } 0 0 "2018.01.23.17:31:01 Info: timecode_tx_data: \"ulight_fifo\" instantiated altera_avalon_pio \"timecode_tx_data\"" 0 0 "Shell" 0 -1 1516735861989 ""} |
{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862097 ""} |
{ "Info" "ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=0 ]" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Generation command is \[exec /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.1/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.1/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.1/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.1/quartus --verilog --config=/tmp/alt7554_7831099621877055177.dir/0040_write_data_fifo_tx_gen/" 0 0 "Shell" 0 -1 1516735862097 ""} |
{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'" 0 0 "Shell" 0 -1 1516735862210 ""} |
{ "Info" "" "" "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" { } { } 0 0 "2018.01.23.17:31:02 Info: write_data_fifo_tx: \"ulight_fifo\" instantiated altera_avalon_pio \"write_data_fifo_tx\"" 0 0 "Shell" 0 -1 1516735862211 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863534 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863572 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863611 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863671 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863741 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863801 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_006: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863855 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_007: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863921 ""} |
{ "Info" "" "" "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:03 Info: avalon_st_adapter_008: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735863979 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_009: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864040 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_010: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864101 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_011: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864161 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_012: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864253 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_013: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864297 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_014: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864334 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_015: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864391 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_016: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864443 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_017: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864499 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_018: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864548 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_019: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864595 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_020: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864650 ""} |
{ "Info" "" "" "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" { } { } 0 0 "2018.01.23.17:31:04 Info: avalon_st_adapter_021: Inserting error_adapter: error_adapter_0" 0 0 "Shell" 0 -1 1516735864729 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" { } { } 0 0 "2018.01.23.17:31:06 Info: mm_interconnect_0: \"ulight_fifo\" instantiated altera_mm_interconnect \"mm_interconnect_0\"" 0 0 "Shell" 0 -1 1516735866289 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rst_controller: \"ulight_fifo\" instantiated altera_reset_controller \"rst_controller\"" 0 0 "Shell" 0 -1 1516735866293 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" { } { } 0 0 "2018.01.23.17:31:06 Info: fpga_interfaces: \"hps_0\" instantiated altera_interface_generator \"fpga_interfaces\"" 0 0 "Shell" 0 -1 1516735866347 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_io: \"hps_0\" instantiated altera_hps_io \"hps_io\"" 0 0 "Shell" 0 -1 1516735866457 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_translator: \"mm_interconnect_0\" instantiated altera_merlin_slave_translator \"led_pio_test_s1_translator\"" 0 0 "Shell" 0 -1 1516735866458 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_agent: \"mm_interconnect_0\" instantiated altera_merlin_axi_master_ni \"hps_0_h2f_axi_master_agent\"" 0 0 "Shell" 0 -1 1516735866460 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent: \"mm_interconnect_0\" instantiated altera_merlin_slave_agent \"led_pio_test_s1_agent\"" 0 0 "Shell" 0 -1 1516735866461 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_agent_rsp_fifo: \"mm_interconnect_0\" instantiated altera_avalon_sc_fifo \"led_pio_test_s1_agent_rsp_fifo\"" 0 0 "Shell" 0 -1 1516735866463 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" { } { } 0 0 "2018.01.23.17:31:06 Info: router: \"mm_interconnect_0\" instantiated altera_merlin_router \"router\"" 0 0 "Shell" 0 -1 1516735866471 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" { } { } 0 0 "2018.01.23.17:31:06 Info: router_002: \"mm_interconnect_0\" instantiated altera_merlin_router \"router_002\"" 0 0 "Shell" 0 -1 1516735866481 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: hps_0_h2f_axi_master_wr_limiter: \"mm_interconnect_0\" instantiated altera_merlin_traffic_limiter \"hps_0_h2f_axi_master_wr_limiter\"" 0 0 "Shell" 0 -1 1516735866484 ""} |
{ "Info" "altera_avalon_sc_fifo.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866484 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: led_pio_test_s1_burst_adapter: \"mm_interconnect_0\" instantiated altera_merlin_burst_adapter \"led_pio_test_s1_burst_adapter\"" 0 0 "Shell" 0 -1 1516735866489 ""} |
{ "Info" "altera_merlin_address_alignment.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866490 ""} |
{ "Info" "altera_avalon_st_pipeline_base.v" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866491 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: cmd_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"cmd_demux\"" 0 0 "Shell" 0 -1 1516735866497 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: cmd_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"cmd_mux\"" 0 0 "Shell" 0 -1 1516735866516 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rsp_demux: \"mm_interconnect_0\" instantiated altera_merlin_demultiplexer \"rsp_demux\"" 0 0 "Shell" 0 -1 1516735866526 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" { } { } 0 0 "2018.01.23.17:31:06 Info: rsp_mux: \"mm_interconnect_0\" instantiated altera_merlin_multiplexer \"rsp_mux\"" 0 0 "Shell" 0 -1 1516735866542 ""} |
{ "Info" "altera_merlin_arbitrator.sv" "" "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" { } { } 0 0 "2018.01.23.17:31:06 Info: Reusing file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules" 0 0 "Shell" 0 -1 1516735866544 ""} |
{ "Info" "" "" "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" { } { } 0 0 "2018.01.23.17:31:06 Info: avalon_st_adapter: \"mm_interconnect_0\" instantiated altera_avalon_st_adapter \"avalon_st_adapter\"" 0 0 "Shell" 0 -1 1516735866567 ""} |
{ "Info" "" "" "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" { } { } 0 0 "2018.01.23.17:31:48 Info: border: \"hps_io\" instantiated altera_interface_generator \"border\"" 0 0 "Shell" 0 -1 1516735908549 ""} |
{ "Info" "" "" "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" { } { } 0 0 "2018.01.23.17:31:48 Info: error_adapter_0: \"avalon_st_adapter\" instantiated error_adapter \"error_adapter_0\"" 0 0 "Shell" 0 -1 1516735908640 ""} |
{ "Info" "" "" "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" { } { } 0 0 "2018.01.23.17:31:48 Info: ulight_fifo: Done \"ulight_fifo\" with 32 modules, 89 files" 0 0 "Shell" 0 -1 1516735908640 ""} |
{ "Info" "" "" "2018.01.23.17:31:49 Info: qsys-generate succeeded." { } { } 0 0 "2018.01.23.17:31:49 Info: qsys-generate succeeded." 0 0 "Shell" 0 -1 1516735909794 ""} |
{ "Info" "" "" "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" { } { } 0 0 "2018.01.23.17:31:49 Info: Finished: Create HDL design files for synthesis" 0 0 "Shell" 0 -1 1516735909794 ""} |
{ "Info" "IIPMAN_IPRGEN_SUCCESSFUL" "Qsys ulight_fifo.qsys " "Completed upgrading IP component Qsys with file \"ulight_fifo.qsys\"" { } { } 0 11131 "Completed upgrading IP component %1!s! with file \"%2!s!\"" 0 0 "Shell" 0 -1 1516735919862 ""} |
{ "Info" "IQEXE_TCL_SCRIPT_STATUS" "/home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl " "Evaluation of Tcl script /home/felipe/intelFPGA_lite/17.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful" { } { } 0 23030 "Evaluation of Tcl script %1!s! was successful" 0 0 "Shell" 0 -1 1516735929556 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "Shell 0 s 30 s Quartus Prime " "Quartus Prime Shell was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1063 " "Peak virtual memory: 1063 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 23 17:32:09 2018 " "Processing ended: Tue Jan 23 17:32:09 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:09 " "Elapsed time: 00:05:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:27 " "Total CPU time (on all processors): 00:08:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1516735929557 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Shell" 0 -1 1516735929557 ""} |
/spw_fifo_ulight.(0).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(0).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(1).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(1).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(10).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(10).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(100).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(100).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(101).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(101).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(102).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(102).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(11).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(11).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(12).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(12).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(13).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(13).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(14).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(14).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(15).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(15).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(16).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(16).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(17).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(17).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(18).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(18).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(19).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(19).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(2).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(2).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(20).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(20).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(21).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(21).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(22).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(22).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(23).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(23).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(24).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(24).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(25).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(25).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(26).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(26).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(27).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(27).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(28).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(28).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(29).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(29).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(3).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(3).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(30).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(30).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(31).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(31).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(32).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(32).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(33).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(33).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(34).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(34).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(35).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(35).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(36).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(36).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(37).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(37).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(38).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(38).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(39).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(39).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(4).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(4).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(40).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(40).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(41).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(41).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(42).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(42).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(43).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(43).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(44).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(44).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(45).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(45).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(46).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(46).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(47).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(47).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(48).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(48).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(49).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(49).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(5).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(5).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(50).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(50).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(51).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(51).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(52).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(52).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(53).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(53).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(54).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(54).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(55).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(55).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(56).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(56).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(57).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(57).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(58).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(58).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(59).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(59).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(6).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(6).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(60).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(60).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(61).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(61).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(62).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(62).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(63).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(63).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(64).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(64).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(65).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(65).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(66).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(66).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(67).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(67).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(68).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(68).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(69).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(69).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(7).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(7).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(70).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(70).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(71).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(71).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(72).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(72).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(73).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(73).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(74).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(74).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(75).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(75).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(76).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(76).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(77).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(77).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(78).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(78).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(79).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(79).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(8).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(8).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(80).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(80).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(81).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(81).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(82).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(82).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(83).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(83).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(84).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(84).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(85).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(85).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(86).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(86).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(87).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(87).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(88).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(88).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(89).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(89).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(9).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(9).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(90).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(90).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(91).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(91).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(92).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(92).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(93).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(93).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(94).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(94).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(95).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(95).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(96).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(96).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(97).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(97).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(98).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(98).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(99).cnf.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.(99).cnf.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.asm.qmsg
1,7 → 1,7
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1505474277344 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1505474277352 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 08:17:57 2017 " "Processing started: Fri Sep 15 08:17:57 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1505474277352 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1505474277352 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1505474277353 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1505474282393 ""} |
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1505474292873 ""} |
{ "Info" "IPGMIO_NO_ISW_UPDATE" "" "Hard Processor Subsystem configuration has not changed and a Preloader software update is not required" { } { } 0 11878 "Hard Processor Subsystem configuration has not changed and a Preloader software update is not required" 0 0 "Assembler" 0 -1 1505474295410 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1040 " "Peak virtual memory: 1040 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505474295579 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:18:15 2017 " "Processing ended: Fri Sep 15 08:18:15 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505474295579 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Elapsed time: 00:00:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505474295579 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505474295579 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1505474295579 ""} |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517799446073 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517799446104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:57:25 2018 " "Processing started: Mon Feb 5 00:57:25 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517799446104 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1517799446104 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1517799446104 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1517799450579 ""} |
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1517799462002 ""} |
{ "Info" "IPGMIO_NO_ISW_UPDATE" "" "Hard Processor Subsystem configuration has not changed and a Preloader software update is not required" { } { } 0 11878 "Hard Processor Subsystem configuration has not changed and a Preloader software update is not required" 0 0 "Assembler" 0 -1 1517799464261 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1044 " "Peak virtual memory: 1044 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799464433 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:57:44 2018 " "Processing ended: Mon Feb 5 00:57:44 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799464433 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799464433 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799464433 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1517799464433 ""} |
/spw_fifo_ulight.asm.rdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.borde_432f1.map.reg_db.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cmp.bpm
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cmp.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cmp.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cmp.idb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cmp.logdb
1,5 → 1,5
v1 |
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, |
IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,PASS,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,0 such failures found.,,I/O,, |
IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, |
IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, |
IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, |
29,19 → 29,19
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,PASS,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,0 such failures found.,,I/O,, |
IO_RULES,DEV_IO_RULE_LVDS_DISCLAIMER,,,,,,,,,, |
IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034, |
IO_RULES_MATRIX,Total Pass,0;19;19;0;0;19;19;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;19;19;16, |
IO_RULES_MATRIX,Total Pass,5;19;19;0;0;19;19;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;19;19;16, |
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, |
IO_RULES_MATRIX,Total Inapplicable,19;0;0;19;19;0;0;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;0;0;3, |
IO_RULES_MATRIX,Total Inapplicable,14;0;0;19;19;0;0;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;19;0;0;3, |
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, |
IO_RULES_MATRIX,LED[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,dout_a,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,sout_a,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[5],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[7],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[1],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[2],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[3],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[4],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[0],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[1],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[2],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[3],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,LED[4],Pass;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,KEY[0],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, |
IO_RULES_MATRIX,LED[6],Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,FPGA_CLK1_50,Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable, |
53,7 → 53,7
IO_RULES_MATRIX,din_a(n),Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_MATRIX,sin_a(n),Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Pass, |
IO_RULES_SUMMARY,Total I/O Rules,28, |
IO_RULES_SUMMARY,Number of I/O Rules Passed,7, |
IO_RULES_SUMMARY,Number of I/O Rules Passed,8, |
IO_RULES_SUMMARY,Number of I/O Rules Failed,0, |
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, |
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21, |
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,20, |
/spw_fifo_ulight.cmp.rdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cmp_merge.kpt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cyclonev_io_sim_cache.ff_0c_fast.hsd
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cyclonev_io_sim_cache.ff_85c_fast.hsd
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cyclonev_io_sim_cache.tt_0c_slow.hsd
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.cyclonev_io_sim_cache.tt_85c_slow.hsd
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.db_info
1,3 → 1,3
Quartus_Version = Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Version_Index = 436360704 |
Creation_Time = Fri Sep 15 09:03:37 2017 |
Quartus_Version = Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
Version_Index = 453136640 |
Creation_Time = Mon Feb 12 16:20:57 2018 |
/spw_fifo_ulight.eda.qmsg
1,7 → 1,11
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1505474352323 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1505474352334 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 08:19:12 2017 " "Processing started: Fri Sep 15 08:19:12 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1505474352334 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1505474352334 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1505474352334 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1505474357626 ""} |
{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." { } { } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1505474357769 ""} |
{ "Info" "IWSC_DONE_HDL_GENERATION" "spw_fifo_ulight.vo /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/simulation/modelsim/ simulation " "Generated file spw_fifo_ulight.vo in folder \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1505474360442 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1314 " "Peak virtual memory: 1314 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505474360713 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:19:20 2017 " "Processing ended: Fri Sep 15 08:19:20 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505474360713 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505474360713 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505474360713 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1505474360713 ""} |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517799546352 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517799546385 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:59:06 2018 " "Processing started: Mon Feb 5 00:59:06 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517799546385 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1517799546385 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1517799546385 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1517799550918 ""} |
{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551540 ""} |
{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551541 ""} |
{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551541 ""} |
{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551542 ""} |
{ "Info" "IQNETO_DONE_BOARD_STA_STAMP_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data " "Generated files \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod\" and \"/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data\"" { } { } 0 199047 "Generated files \"%1!s!\" and \"%2!s!\"" 0 0 "EDA Netlist Writer" 0 -1 1517799551543 ""} |
{ "Info" "IQNETO_GENERATED_HSPICE_FILES" "36 " "Generated 36 HSPICE Output files for board level analysis" { { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552966 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552966 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} { "Info" "IQNETO_DONE_HSPICE_GENERATION" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc " "Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc for board level analysis" { } { } 0 199051 "Generated HSPICE Output File %1!s! for board level analysis" 0 0 "Design Software" 0 -1 1517799552967 ""} } { } 0 199053 "Generated %1!d! HSPICE Output files for board level analysis" 0 0 "EDA Netlist Writer" 0 -1 1517799552966 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1244 " "Peak virtual memory: 1244 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799553201 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:59:13 2018 " "Processing ended: Mon Feb 5 00:59:13 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799553201 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799553201 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799553201 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1517799553201 ""} |
/spw_fifo_ulight.fit.qmsg
1,53 → 1,71
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1505473997024 ""} |
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1505473997024 ""} |
{ "Info" "IMPP_MPP_USER_DEVICE" "spw_fifo_ulight 5CSEMA4U23C6 " "Selected device 5CSEMA4U23C6 for design \"spw_fifo_ulight\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1505473997081 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1505473997158 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1505473997158 ""} |
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1505473997958 ""} |
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1505473998068 ""} |
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1505474002927 ""} |
{ "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED_GROUP" "4 " "4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." { { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "dout_a dout_a(n) " "differential I/O pin \"dout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"dout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { dout_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "dout_a" } { 0 "dout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 801 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 805 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { dout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sout_a sout_a(n) " "differential I/O pin \"sout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sout_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sout_a" } { 0 "sout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 10 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 802 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 807 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "din_a din_a(n) " "differential I/O pin \"din_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"din_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { din_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "din_a" } { 0 "din_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 5 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 799 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 804 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { din_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sin_a sin_a(n) " "differential I/O pin \"sin_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sin_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sin_a } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sin_a" } { 0 "sin_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 6 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 800 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 806 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.0/quartus/linux64/pin_planner.ppl" { sin_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1505474011939 ""} } { } 0 184025 "%1!d! differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." 0 0 "Fitter" 0 -1 1505474011939 ""} |
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1505474012167 ""} |
{ "Info" "ICCLK_CLOCKS_TOP" "2 s (2 global) " "Promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 3 global CLKCTRL_G10 " "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G10" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 24 global CLKCTRL_G11 " "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G11" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} } { } 0 11178 "Promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1505474012512 ""} |
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "2 s (2 global) " "Automatically promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "FPGA_CLK1_50~inputCLKENA0 3124 global CLKCTRL_G5 " "FPGA_CLK1_50~inputCLKENA0 with 3124 fanout uses global clock CLKCTRL_G5" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out~CLKENA0 3025 global CLKCTRL_G3 " "ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\|altera_reset_synchronizer_int_chain_out~CLKENA0 with 3025 fanout uses global clock CLKCTRL_G3" { { "Info" "ICCLK_UNLOCKED_FOR_VPR" "" "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" { } { } 0 12525 "This signal is driven by core routing -- it may be moved during placement to reduce routing delays" 0 0 "Design Software" 0 -1 1505474012512 ""} } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1505474012512 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1505474012512 ""} |
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474012514 ""} |
{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1505474015751 ""} |
{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1505474015838 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataa to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataa to: combout " "Cell: m_x\|always3~0 from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474015904 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1505474015904 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "Fitter" 0 -1 1505474015990 ""} |
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1505474015998 ""} |
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 4.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 3.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 3.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 3.000 din_a " " 3.000 din_a" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 FPGA_CLK1_50 " " 10.000 FPGA_CLK1_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 3.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 3.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1505474015998 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1505474015998 ""} |
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1505474016303 ""} |
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1505474016328 ""} |
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1505474016383 ""} |
{ "Info" "IFSAC_FSAC_OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING_OFF" "" "Fitter will not automatically pack the registers into I/Os." { } { } 0 176222 "Fitter will not automatically pack the registers into I/Os." 0 0 "Fitter" 0 -1 1505474016383 ""} |
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1505474016428 ""} |
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1505474016429 ""} |
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1505474016452 ""} |
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1505474017532 ""} |
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1505474017561 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1505474017561 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474017705 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474018213 ""} |
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:16 " "Fitter preparation operations ending: elapsed time is 00:00:16" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474018538 ""} |
{ "Warning" "WFITAPI_FITAPI_VPR_PLACEMENT_EFFORT_MULTIPLIER_USED_WITH_RETRY_LOOP" "90.0 " "Design uses Placement Effort Multiplier = 90.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." { } { } 0 170136 "Design uses Placement Effort Multiplier = %1!s!. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." 0 0 "Fitter" 0 -1 1505474025663 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1505474025664 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474026402 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474026913 ""} |
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1505474028148 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:28 " "Fitter placement preparation operations ending: elapsed time is 00:00:28" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474053768 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474053966 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474054534 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1505474083911 ""} |
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1505474198604 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:01:55 " "Fitter placement operations ending: elapsed time is 00:01:55" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474198605 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1505474201404 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474205572 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1505474206099 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "3 " "Router estimated average interconnect usage is 3% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "15 X11_Y24 X22_Y36 " "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36" { } { { "loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 1 { 0 "Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36"} { { 12 { 0 ""} 11 24 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1505474225170 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1505474225170 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1505474245410 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1505474245410 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:40 " "Fitter routing operations ending: elapsed time is 00:00:40" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474245414 ""} |
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 16.50 " "Total time spent on timing analysis during the Fitter is 16.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1505474262288 ""} |
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:05 " "Fitter post-fit operations ending: elapsed time is 00:00:05" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1505474267685 ""} |
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1505474268262 ""} |
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1505474269280 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2064 " "Peak virtual memory: 2064 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505474271108 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:17:51 2017 " "Processing ended: Fri Sep 15 08:17:51 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505474271108 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:04:44 " "Elapsed time: 00:04:44" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505474271108 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:19 " "Total CPU time (on all processors): 00:08:19" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505474271108 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1505474271108 ""} |
{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "High Performance Effort timing performance increased compilation time " "High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time" { { "Info" "IQCU_OPT_MODE_OVERRIDE" "Fitter Effort Standard Fit " "Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517799137877 ""} { "Info" "IQCU_OPT_MODE_OVERRIDE" "Physical Synthesis Effort Level Normal " "Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517799137877 ""} } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Fitter" 0 -1 1517799137877 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1517799137898 ""} |
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1517799137898 ""} |
{ "Info" "IMPP_MPP_USER_DEVICE" "spw_fifo_ulight 5CSEMA4U23C6 " "Selected device 5CSEMA4U23C6 for design \"spw_fifo_ulight\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1517799137969 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1517799138047 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1517799138047 ""} |
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1517799138850 ""} |
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1517799138937 ""} |
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1517799143937 ""} |
{ "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED_GROUP" "4 " "4 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." { { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "dout_a dout_a(n) " "differential I/O pin \"dout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"dout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { dout_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "dout_a" } { 0 "dout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 9 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 818 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 822 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { dout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sout_a sout_a(n) " "differential I/O pin \"sout_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sout_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sout_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sout_a" } { 0 "sout_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 10 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 819 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 824 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sout_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "din_a din_a(n) " "differential I/O pin \"din_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"din_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { din_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "din_a" } { 0 "din_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 5 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 816 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 821 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { din_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} { "Info" "IFSV_FSV_COMPLEMENT_PIN_CREATED" "sin_a sin_a(n) " "differential I/O pin \"sin_a\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"sin_a(n)\"." { } { { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sin_a } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" "" { Assignment "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/Assignment Editor.qase" 1 { { 0 "sin_a" } { 0 "sin_a(n)" } } } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 6 0 0 } } { "temporary_test_loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 0 { 0 ""} 0 817 14177 15141 0 0 "" 0 "" "" } { 0 { 0 ""} 0 823 14177 15141 0 0 "" 0 "" "" } } } } { "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" "" { PinPlanner "/home/felipe/intelFPGA_lite/17.1/quartus/linux64/pin_planner.ppl" { sin_a(n) } } } } 0 184026 "differential I/O pin \"%1!s!\" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin \"%2!s!\"." 0 0 "Design Software" 0 -1 1517799153225 ""} } { } 0 184025 "%1!d! differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins." 0 0 "Fitter" 0 -1 1517799153225 ""} |
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1517799153477 ""} |
{ "Warning" "WCCLK_MISSING_PLL_COMPENSATED_CLOCK" "FRACTIONALPLL_X68_Y1_N0 " "PLL(s) placed in location FRACTIONALPLL_X68_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks" { { "Info" "ICCLK_PLL_NAME" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\|fpll " "PLL ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\|fpll" { } { } 0 177008 "PLL %1!s!" 0 0 "Design Software" 0 -1 1517799153655 ""} } { } 0 177007 "PLL(s) placed in location %1!s! do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks" 0 0 "Fitter" 0 -1 1517799153655 ""} |
{ "Info" "ICCLK_CLOCKS_TOP" "2 s (2 global) " "Promoted 2 clocks (2 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 3 global CLKCTRL_G11 " "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|h2f_rst_n\[0\]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G11" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1517799153786 ""} { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 24 global CLKCTRL_G8 " "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|divclk\[0\]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G8" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1517799153786 ""} } { } 0 11178 "Promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1517799153786 ""} |
{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "FPGA_CLK1_50~inputCLKENA0 3068 global CLKCTRL_G4 " "FPGA_CLK1_50~inputCLKENA0 with 3068 fanout uses global clock CLKCTRL_G4" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1517799153786 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1517799153786 ""} |
{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799153787 ""} |
{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1517799156769 ""} |
{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1517799156861 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataa to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: datab to: combout " "Cell: m_x\|comb from: datab to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799156990 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1517799156990 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "Fitter" 0 -1 1517799157110 ""} |
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1517799157116 ""} |
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 7 clocks " "Found 7 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.000 din_a " " 4.000 din_a" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 20.000 FPGA_CLK1_50 " " 20.000 FPGA_CLK1_50" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 4.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 4.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 2.500 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\]" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1517799157116 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1517799157116 ""} |
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1517799157465 ""} |
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1517799157488 ""} |
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1517799157542 ""} |
{ "Info" "IFSAC_FSAC_OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING_EXTRA_EFFORT" "" "The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os." { } { } 0 176221 "The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os." 0 0 "Fitter" 0 -1 1517799157542 ""} |
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1517799157589 ""} |
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1517799157589 ""} |
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1517799157614 ""} |
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1517799158752 ""} |
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "5 I/O output buffer " "Packed 5 registers into blocks of type I/O output buffer" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Design Software" 0 -1 1517799158778 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "5 " "Created 5 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Design Software" 0 -1 1517799158778 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1517799158778 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799159580 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799160101 ""} |
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" { } { } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Fitter" 0 -1 1517799160284 ""} |
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Fitter" 0 -1 1517799161364 ""} |
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 662 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 662 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Fitter" 0 -1 1517799164219 ""} |
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" { } { } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Fitter" 0 -1 1517799164228 ""} |
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" { } { } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Fitter" 0 -1 1517799167114 ""} |
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:09 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:09" { } { } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Fitter" 0 -1 1517799168860 ""} |
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1517799169216 ""} |
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1517799169362 ""} |
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1517799169362 ""} |
{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1517799169394 ""} |
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1517799173172 ""} |
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1517799173208 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1517799173208 ""} |
{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:30 " "Fitter preparation operations ending: elapsed time is 00:00:30" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799173546 ""} |
{ "Warning" "WFITAPI_FITAPI_VPR_PLACEMENT_EFFORT_MULTIPLIER_USED_WITH_RETRY_LOOP" "4.0 " "Design uses Placement Effort Multiplier = 4.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." { } { } 0 170136 "Design uses Placement Effort Multiplier = %1!s!. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt." 0 0 "Fitter" 0 -1 1517799180874 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1517799180875 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799181783 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799182302 ""} |
{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1517799183901 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:35 " "Fitter placement preparation operations ending: elapsed time is 00:00:35" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799216311 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799216566 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799217081 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1517799245270 ""} |
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1517799302561 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:58 " "Fitter placement operations ending: elapsed time is 00:00:58" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799302561 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1517799307763 ""} |
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" { } { } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799311838 ""} |
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" { } { } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "Fitter" 0 -1 1517799312357 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "20 X46_Y0 X56_Y11 " "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11" { } { { "loc" "" { Generic "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/" { { 1 { 0 "Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11"} { { 12 { 0 ""} 46 0 11 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1517799337080 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1517799337080 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization." { } { } 0 170202 "The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization." 0 0 "Fitter" 0 -1 1517799387310 ""} |
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:01:16 " "Fitter routing operations ending: elapsed time is 00:01:16" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799387315 ""} |
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 27.50 " "Total time spent on timing analysis during the Fitter is 27.50 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1517799398841 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1517799399079 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1517799405514 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1517799405523 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1517799411502 ""} |
{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:38 " "Fitter post-fit operations ending: elapsed time is 00:00:38" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1517799436539 ""} |
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." { } { } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1517799437203 ""} |
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1517799437984 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2473 " "Peak virtual memory: 2473 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799440640 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:57:20 2018 " "Processing ended: Mon Feb 5 00:57:20 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799440640 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:09 " "Elapsed time: 00:05:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799440640 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:08:50 " "Total CPU time (on all processors): 00:08:50" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799440640 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1517799440640 ""} |
/spw_fifo_ulight.hier_info
166865,6 → 166865,18
pclk => after128us[9].CLK |
pclk => after128us[10].CLK |
pclk => after128us[11].CLK |
pclk => get_rx_credit_error_b.CLK |
pclk => get_rx_credit_error_a.CLK |
pclk => get_rx_got_time_code_b.CLK |
pclk => get_rx_got_time_code_a.CLK |
pclk => get_rx_got_nchar_b.CLK |
pclk => get_rx_got_nchar_a.CLK |
pclk => get_rx_got_null_b.CLK |
pclk => get_rx_got_null_a.CLK |
pclk => get_rx_error_b.CLK |
pclk => get_rx_error_a.CLK |
pclk => get_rx_got_fct_b.CLK |
pclk => get_rx_got_fct_a.CLK |
pclk => send_fct_tx~reg0.CLK |
pclk => send_null_tx~reg0.CLK |
pclk => enable_tx~reg0.CLK |
166871,10 → 166883,23
pclk => rx_resetn~reg0.CLK |
pclk => state_fsm~1.DATAIN |
resetn => got_bit_internal.OUTPUTSELECT |
resetn => get_rx_credit_error_b.ACLR |
resetn => get_rx_credit_error_a.ACLR |
resetn => get_rx_got_time_code_b.ACLR |
resetn => get_rx_got_time_code_a.ACLR |
resetn => get_rx_got_nchar_b.ACLR |
resetn => get_rx_got_nchar_a.ACLR |
resetn => get_rx_got_null_b.ACLR |
resetn => get_rx_got_null_a.ACLR |
resetn => get_rx_error_b.ACLR |
resetn => get_rx_error_a.ACLR |
resetn => get_rx_got_fct_b.ACLR |
resetn => get_rx_got_fct_a.ACLR |
resetn => send_fct_tx~reg0.ACLR |
resetn => send_null_tx~reg0.ACLR |
resetn => enable_tx~reg0.ACLR |
resetn => rx_resetn~reg0.ACLR |
resetn => always5.IN1 |
resetn => always2.IN0 |
resetn => after64us.OUTPUTSELECT |
resetn => after64us.OUTPUTSELECT |
166888,33 → 166913,22
resetn => after64us.OUTPUTSELECT |
resetn => after64us.OUTPUTSELECT |
resetn => after64us.OUTPUTSELECT |
resetn => always5.IN1 |
resetn => state_fsm~3.DATAIN |
auto_start => always0.IN0 |
auto_start => always0.IN1 |
auto_start => always3.IN0 |
link_start => always0.IN1 |
link_start => always3.IN1 |
link_disable => always0.IN1 |
link_disable => always0.IN1 |
rx_error => always0.IN0 |
rx_error => always0.IN0 |
rx_error => always0.IN0 |
rx_credit_error => always0.IN1 |
rx_got_bit => always0.IN0 |
rx_error => get_rx_error_b.DATAIN |
rx_credit_error => get_rx_credit_error_b.DATAIN |
rx_got_bit => always0.IN1 |
rx_got_bit => got_bit_internal.DATAB |
rx_got_null => always0.IN1 |
rx_got_null => always0.IN1 |
rx_got_nchar => always0.IN1 |
rx_got_nchar => always0.IN1 |
rx_got_null => get_rx_got_null_b.DATAIN |
rx_got_nchar => get_rx_got_nchar_b.DATAIN |
rx_got_time_code => always0.IN1 |
rx_got_time_code => always0.IN1 |
rx_got_fct => always0.IN1 |
rx_got_fct => next_state_fsm.OUTPUTSELECT |
rx_got_fct => next_state_fsm.OUTPUTSELECT |
rx_got_fct => next_state_fsm.OUTPUTSELECT |
rx_got_fct => next_state_fsm.OUTPUTSELECT |
rx_got_fct => next_state_fsm.OUTPUTSELECT |
rx_got_fct => next_state_fsm.OUTPUTSELECT |
rx_got_time_code => get_rx_got_time_code_b.DATAIN |
rx_got_fct => get_rx_got_fct_b.DATAIN |
rx_resetn <= rx_resetn~reg0.DB_MAX_OUTPUT_PORT_TYPE |
enable_tx <= enable_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE |
send_null_tx <= send_null_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE |
166928,31 → 166942,328
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX |
rx_din => always0.IN0 |
rx_din => always3.IN0 |
rx_din => rx_din.IN3 |
rx_sin => comb.IN0 |
rx_sin => always1.IN0 |
rx_resetn => rx_resetn.IN8 |
rx_error <= rx_control_data_rdy:control_data_rdy.rx_error |
rx_got_bit <= always1.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_null <= rx_buffer_fsm:buffer_fsm.rx_got_null |
rx_got_nchar <= rx_buffer_fsm:buffer_fsm.rx_got_nchar |
rx_got_time_code <= rx_buffer_fsm:buffer_fsm.rx_got_time_code |
rx_got_fct <= rx_data_receive:rx_dtarcv.rx_got_fct |
rx_got_fct_fsm <= rx_control_data_rdy:control_data_rdy.rx_got_fct_fsm |
rx_data_flag[0] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[1] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[2] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[3] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[4] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[5] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[6] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[7] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_data_flag[8] <= rx_data_receive:rx_dtarcv.rx_data_flag |
rx_buffer_write <= rx_data_buffer_data_w:buffer_data_flag.rx_buffer_write |
rx_time_out[0] <= rx_time_out[0].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[1] <= rx_time_out[1].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[2] <= rx_time_out[2].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[3] <= rx_time_out[3].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[4] <= rx_time_out[4].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[5] <= rx_time_out[5].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[6] <= rx_time_out[6].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[7] <= rx_time_out[7].DB_MAX_OUTPUT_PORT_TYPE |
rx_tick_out <= rx_data_buffer_data_w:buffer_data_flag.rx_tick_out |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm |
posedge_clk => rx_got_time_code~reg0.CLK |
posedge_clk => rx_got_nchar~reg0.CLK |
posedge_clk => rx_got_null~reg0.CLK |
rx_resetn => rx_got_time_code~reg0.ACLR |
rx_resetn => rx_got_nchar~reg0.ACLR |
rx_resetn => rx_got_null~reg0.ACLR |
last_is_data => rx_got_null.OUTPUTSELECT |
last_is_data => rx_got_time_code.OUTPUTSELECT |
last_is_data => rx_got_nchar~reg0.DATAIN |
last_is_timec => rx_got_null.OUTPUTSELECT |
last_is_timec => rx_got_time_code.DATAA |
last_is_control => rx_got_null.DATAA |
rx_got_null <= rx_got_null~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_nchar <= rx_got_nchar~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_time_code <= rx_got_time_code~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag |
negedge_clk => rx_tick_out~reg0.CLK |
negedge_clk => rx_buffer_write~reg0.CLK |
rx_resetn => rx_tick_out~reg0.ACLR |
rx_resetn => rx_buffer_write~reg0.ACLR |
state_data_process[0] => Equal0.IN0 |
state_data_process[1] => Equal0.IN1 |
control[0] => Equal1.IN2 |
control[0] => Equal2.IN1 |
control[1] => Equal1.IN1 |
control[1] => Equal2.IN2 |
control[2] => Equal1.IN0 |
control[2] => Equal2.IN0 |
last_is_timec => rx_buffer_write.OUTPUTSELECT |
last_is_timec => rx_tick_out.DATAB |
last_is_data => rx_buffer_write.OUTPUTSELECT |
last_is_control => rx_buffer_write.OUTPUTSELECT |
rx_buffer_write <= rx_buffer_write~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_tick_out <= rx_tick_out~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy |
posedge_clk => rx_error~reg0.CLK |
posedge_clk => ready_data_p_r~reg0.CLK |
posedge_clk => ready_control_p_r~reg0.CLK |
posedge_clk => rx_got_fct_fsm~reg0.CLK |
rx_resetn => rx_error~reg0.ACLR |
rx_resetn => ready_data_p_r~reg0.ACLR |
rx_resetn => ready_control_p_r~reg0.ACLR |
rx_resetn => rx_got_fct_fsm~reg0.ACLR |
rx_error_c => rx_error.IN0 |
rx_error_d => rx_error.IN1 |
control[0] => Equal3.IN2 |
control[1] => Equal3.IN1 |
control[2] => Equal3.IN0 |
control_l_r[0] => Equal2.IN2 |
control_l_r[1] => Equal2.IN1 |
control_l_r[2] => Equal2.IN0 |
is_control => always0.IN1 |
counter_neg[0] => Equal0.IN5 |
counter_neg[0] => Equal1.IN5 |
counter_neg[1] => Equal0.IN4 |
counter_neg[1] => Equal1.IN4 |
counter_neg[2] => Equal0.IN0 |
counter_neg[2] => Equal1.IN3 |
counter_neg[3] => Equal0.IN3 |
counter_neg[3] => Equal1.IN2 |
counter_neg[4] => Equal0.IN2 |
counter_neg[4] => Equal1.IN1 |
counter_neg[5] => Equal0.IN1 |
counter_neg[5] => Equal1.IN0 |
last_is_control => always0.IN1 |
rx_error <= rx_error~reg0.DB_MAX_OUTPUT_PORT_TYPE |
ready_control_p_r <= ready_control_p_r~reg0.DB_MAX_OUTPUT_PORT_TYPE |
ready_data_p_r <= ready_data_p_r~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_fct_fsm <= rx_got_fct_fsm~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control |
posedge_clk => parity_rec_c_gen~reg0.CLK |
posedge_clk => parity_rec_c~reg0.CLK |
posedge_clk => control_l_r[0]~reg0.CLK |
posedge_clk => control_l_r[1]~reg0.CLK |
posedge_clk => control_l_r[2]~reg0.CLK |
posedge_clk => control_p_r[0]~reg0.CLK |
posedge_clk => control_p_r[1]~reg0.CLK |
posedge_clk => control_p_r[2]~reg0.CLK |
posedge_clk => dta_timec_p[0]~reg0.CLK |
posedge_clk => dta_timec_p[1]~reg0.CLK |
posedge_clk => dta_timec_p[2]~reg0.CLK |
posedge_clk => dta_timec_p[3]~reg0.CLK |
posedge_clk => dta_timec_p[4]~reg0.CLK |
posedge_clk => dta_timec_p[5]~reg0.CLK |
posedge_clk => dta_timec_p[6]~reg0.CLK |
posedge_clk => dta_timec_p[7]~reg0.CLK |
posedge_clk => dta_timec_p[8]~reg0.CLK |
posedge_clk => parity_rec_d_gen~reg0.CLK |
posedge_clk => parity_rec_d~reg0.CLK |
rx_resetn => dta_timec_p[0]~reg0.ACLR |
rx_resetn => dta_timec_p[1]~reg0.ACLR |
rx_resetn => dta_timec_p[2]~reg0.ACLR |
rx_resetn => dta_timec_p[3]~reg0.ACLR |
rx_resetn => dta_timec_p[4]~reg0.ACLR |
rx_resetn => dta_timec_p[5]~reg0.ACLR |
rx_resetn => dta_timec_p[6]~reg0.ACLR |
rx_resetn => dta_timec_p[7]~reg0.ACLR |
rx_resetn => dta_timec_p[8]~reg0.ACLR |
rx_resetn => parity_rec_d_gen~reg0.ACLR |
rx_resetn => parity_rec_d~reg0.ACLR |
rx_resetn => parity_rec_c_gen~reg0.ACLR |
rx_resetn => parity_rec_c~reg0.ACLR |
rx_resetn => control_l_r[0]~reg0.ACLR |
rx_resetn => control_l_r[1]~reg0.ACLR |
rx_resetn => control_l_r[2]~reg0.ACLR |
rx_resetn => control_p_r[0]~reg0.ACLR |
rx_resetn => control_p_r[1]~reg0.ACLR |
rx_resetn => control_p_r[2]~reg0.ACLR |
bit_c_3 => parity_rec_c~reg0.DATAIN |
bit_c_2 => parity_rec_c_gen.IN1 |
bit_c_2 => parity_rec_c_gen.IN1 |
bit_c_2 => control_p_r[2]~reg0.DATAIN |
bit_c_1 => control_p_r[1]~reg0.DATAIN |
bit_c_0 => control_p_r[0]~reg0.DATAIN |
bit_d_9 => parity_rec_d~reg0.DATAIN |
bit_d_8 => parity_rec_d_gen.IN1 |
bit_d_8 => parity_rec_d_gen.IN1 |
bit_d_8 => dta_timec_p[8]~reg0.DATAIN |
bit_d_0 => dta_timec_p[7]~reg0.DATAIN |
bit_d_1 => dta_timec_p[6]~reg0.DATAIN |
bit_d_2 => dta_timec_p[5]~reg0.DATAIN |
bit_d_3 => dta_timec_p[4]~reg0.DATAIN |
bit_d_4 => dta_timec_p[3]~reg0.DATAIN |
bit_d_5 => dta_timec_p[2]~reg0.DATAIN |
bit_d_6 => dta_timec_p[1]~reg0.DATAIN |
bit_d_7 => dta_timec_p[0]~reg0.DATAIN |
last_is_control => parity_rec_d_gen.OUTPUTSELECT |
last_is_control => parity_rec_c_gen.OUTPUTSELECT |
last_is_data => parity_rec_d_gen.OUTPUTSELECT |
last_is_data => parity_rec_c_gen.OUTPUTSELECT |
is_control => always0.IN1 |
is_control => always1.IN1 |
counter_neg[0] => Equal0.IN5 |
counter_neg[0] => Equal1.IN5 |
counter_neg[1] => Equal0.IN4 |
counter_neg[1] => Equal1.IN4 |
counter_neg[2] => Equal0.IN3 |
counter_neg[2] => Equal1.IN0 |
counter_neg[3] => Equal0.IN2 |
counter_neg[3] => Equal1.IN3 |
counter_neg[4] => Equal0.IN1 |
counter_neg[4] => Equal1.IN2 |
counter_neg[5] => Equal0.IN0 |
counter_neg[5] => Equal1.IN1 |
dta_timec_p[0] <= dta_timec_p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[1] <= dta_timec_p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[2] <= dta_timec_p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[3] <= dta_timec_p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[4] <= dta_timec_p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[5] <= dta_timec_p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[6] <= dta_timec_p[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[7] <= dta_timec_p[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
dta_timec_p[8] <= dta_timec_p[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
parity_rec_d <= parity_rec_d~reg0.DB_MAX_OUTPUT_PORT_TYPE |
parity_rec_d_gen <= parity_rec_d_gen~reg0.DB_MAX_OUTPUT_PORT_TYPE |
control_p_r[0] <= control_p_r[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
control_p_r[1] <= control_p_r[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
control_p_r[2] <= control_p_r[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
control_l_r[0] <= control_l_r[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
control_l_r[1] <= control_l_r[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
control_l_r[2] <= control_l_r[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
parity_rec_c <= parity_rec_c~reg0.DB_MAX_OUTPUT_PORT_TYPE |
parity_rec_c_gen <= parity_rec_c_gen~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d |
negedge_clk => bit_d_8~reg0.CLK |
negedge_clk => bit_d_6~reg0.CLK |
negedge_clk => bit_d_4~reg0.CLK |
negedge_clk => bit_d_2~reg0.CLK |
negedge_clk => bit_d_0~reg0.CLK |
posedge_clk => bit_d_9~reg0.CLK |
posedge_clk => bit_d_7~reg0.CLK |
posedge_clk => bit_d_5~reg0.CLK |
posedge_clk => bit_d_3~reg0.CLK |
posedge_clk => bit_d_1~reg0.CLK |
rx_resetn => bit_d_8~reg0.ACLR |
rx_resetn => bit_d_6~reg0.ACLR |
rx_resetn => bit_d_4~reg0.ACLR |
rx_resetn => bit_d_2~reg0.ACLR |
rx_resetn => bit_d_0~reg0.ACLR |
rx_resetn => bit_d_9~reg0.ACLR |
rx_resetn => bit_d_7~reg0.ACLR |
rx_resetn => bit_d_5~reg0.ACLR |
rx_resetn => bit_d_3~reg0.ACLR |
rx_resetn => bit_d_1~reg0.ACLR |
rx_din => bit_d_0~reg0.DATAIN |
rx_din => bit_d_1~reg0.DATAIN |
bit_d_0 <= bit_d_0~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_1 <= bit_d_1~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_2 <= bit_d_2~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_3 <= bit_d_3~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_4 <= bit_d_4~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_5 <= bit_d_5~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_6 <= bit_d_6~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_7 <= bit_d_7~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_8 <= bit_d_8~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_9 <= bit_d_9~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c |
negedge_clk => bit_c_2~reg0.CLK |
negedge_clk => bit_c_0~reg0.CLK |
posedge_clk => bit_c_3~reg0.CLK |
posedge_clk => bit_c_1~reg0.CLK |
rx_resetn => bit_c_2~reg0.ACLR |
rx_resetn => bit_c_0~reg0.ACLR |
rx_resetn => bit_c_3~reg0.ACLR |
rx_resetn => bit_c_1~reg0.ACLR |
rx_din => bit_c_0~reg0.DATAIN |
rx_din => bit_c_1~reg0.DATAIN |
bit_c_0 <= bit_c_0~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_c_1 <= bit_c_1~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_c_2 <= bit_c_2~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_c_3 <= bit_c_3~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg |
negedge_clk => counter_neg[0]~reg0.CLK |
negedge_clk => counter_neg[1]~reg0.CLK |
negedge_clk => counter_neg[2]~reg0.CLK |
negedge_clk => counter_neg[3]~reg0.CLK |
negedge_clk => counter_neg[4]~reg0.CLK |
negedge_clk => counter_neg[5]~reg0.CLK |
negedge_clk => control_bit_found.CLK |
negedge_clk => is_control~reg0.CLK |
rx_resetn => counter_neg[0]~reg0.PRESET |
rx_resetn => counter_neg[1]~reg0.ACLR |
rx_resetn => counter_neg[2]~reg0.ACLR |
rx_resetn => counter_neg[3]~reg0.ACLR |
rx_resetn => counter_neg[4]~reg0.ACLR |
rx_resetn => counter_neg[5]~reg0.ACLR |
rx_resetn => control_bit_found.ACLR |
rx_resetn => is_control~reg0.ACLR |
rx_din => control_bit_found.DATAIN |
rx_din => bit_c_0.DATAIN |
rx_din => bit_c_1.DATAIN |
rx_din => bit_d_0.DATAIN |
rx_din => bit_d_1.DATAIN |
rx_sin => always0.IN1 |
rx_sin => always3.IN1 |
rx_resetn => last_was_timec.ACLR |
rx_resetn => last_was_data.ACLR |
rx_resetn => last_was_control.ACLR |
rx_resetn => last_is_timec.ACLR |
rx_resetn => last_is_data.ACLR |
rx_resetn => last_is_control.ACLR |
rx_resetn => rx_tick_out~reg0.ACLR |
rx_resetn => timecode[0].ACLR |
rx_resetn => timecode[1].ACLR |
rx_resetn => timecode[2].ACLR |
rx_resetn => timecode[3].ACLR |
rx_resetn => timecode[4].ACLR |
rx_resetn => timecode[5].ACLR |
rx_resetn => timecode[6].ACLR |
rx_resetn => timecode[7].ACLR |
rx_resetn => rx_data_take.ACLR |
is_control <= is_control~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[0] <= counter_neg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[1] <= counter_neg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[2] <= counter_neg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[3] <= counter_neg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[4] <= counter_neg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[5] <= counter_neg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv |
posedge_clk => rx_got_fct~reg0.CLK |
posedge_clk => rx_error_d~reg0.CLK |
posedge_clk => rx_error_c~reg0.CLK |
posedge_clk => state_data_process[0]~reg0.CLK |
posedge_clk => state_data_process[1]~reg0.CLK |
posedge_clk => timecode[0]~reg0.CLK |
posedge_clk => timecode[1]~reg0.CLK |
posedge_clk => timecode[2]~reg0.CLK |
posedge_clk => timecode[3]~reg0.CLK |
posedge_clk => timecode[4]~reg0.CLK |
posedge_clk => timecode[5]~reg0.CLK |
posedge_clk => timecode[6]~reg0.CLK |
posedge_clk => timecode[7]~reg0.CLK |
posedge_clk => rx_data_flag[0]~reg0.CLK |
posedge_clk => rx_data_flag[1]~reg0.CLK |
posedge_clk => rx_data_flag[2]~reg0.CLK |
posedge_clk => rx_data_flag[3]~reg0.CLK |
posedge_clk => rx_data_flag[4]~reg0.CLK |
posedge_clk => rx_data_flag[5]~reg0.CLK |
posedge_clk => rx_data_flag[6]~reg0.CLK |
posedge_clk => rx_data_flag[7]~reg0.CLK |
posedge_clk => rx_data_flag[8]~reg0.CLK |
posedge_clk => last_is_timec~reg0.CLK |
posedge_clk => last_is_data~reg0.CLK |
posedge_clk => last_is_control~reg0.CLK |
rx_resetn => rx_got_fct~reg0.ACLR |
rx_resetn => rx_error_d~reg0.ACLR |
rx_resetn => rx_error_c~reg0.ACLR |
rx_resetn => state_data_process[0]~reg0.ACLR |
rx_resetn => state_data_process[1]~reg0.ACLR |
rx_resetn => timecode[0]~reg0.ACLR |
rx_resetn => timecode[1]~reg0.ACLR |
rx_resetn => timecode[2]~reg0.ACLR |
rx_resetn => timecode[3]~reg0.ACLR |
rx_resetn => timecode[4]~reg0.ACLR |
rx_resetn => timecode[5]~reg0.ACLR |
rx_resetn => timecode[6]~reg0.ACLR |
rx_resetn => timecode[7]~reg0.ACLR |
rx_resetn => rx_data_flag[0]~reg0.ACLR |
rx_resetn => rx_data_flag[1]~reg0.ACLR |
rx_resetn => rx_data_flag[2]~reg0.ACLR |
166962,97 → 167273,102
rx_resetn => rx_data_flag[6]~reg0.ACLR |
rx_resetn => rx_data_flag[7]~reg0.ACLR |
rx_resetn => rx_data_flag[8]~reg0.ACLR |
rx_resetn => data_l_r[1].ACLR |
rx_resetn => data_l_r[2].ACLR |
rx_resetn => data_l_r[3].ACLR |
rx_resetn => data_l_r[4].ACLR |
rx_resetn => data_l_r[5].ACLR |
rx_resetn => data_l_r[6].ACLR |
rx_resetn => data_l_r[7].ACLR |
rx_resetn => data[0].ACLR |
rx_resetn => data[1].ACLR |
rx_resetn => data[2].ACLR |
rx_resetn => data[3].ACLR |
rx_resetn => data[4].ACLR |
rx_resetn => data[5].ACLR |
rx_resetn => data[6].ACLR |
rx_resetn => data[7].ACLR |
rx_resetn => data[8].ACLR |
rx_resetn => data[9].ACLR |
rx_resetn => control[0].ACLR |
rx_resetn => control[1].ACLR |
rx_resetn => control[2].ACLR |
rx_resetn => control[3].ACLR |
rx_resetn => control_l_r[0].ACLR |
rx_resetn => control_l_r[1].ACLR |
rx_resetn => control_l_r[2].ACLR |
rx_resetn => rx_got_time_code~reg0.ACLR |
rx_resetn => rx_got_nchar~reg0.ACLR |
rx_resetn => rx_got_null~reg0.ACLR |
rx_resetn => rx_error~reg0.ACLR |
rx_resetn => rx_got_fct~reg0.ACLR |
rx_resetn => ready_data_p_r.ACLR |
rx_resetn => ready_control_p_r.ACLR |
rx_resetn => rx_data_take_0.ACLR |
rx_resetn => rx_buffer_write~reg0.ACLR |
rx_resetn => rx_got_fct_fsm~reg0.ACLR |
rx_resetn => bit_d_9.ACLR |
rx_resetn => bit_d_7.ACLR |
rx_resetn => bit_d_5.ACLR |
rx_resetn => bit_d_3.ACLR |
rx_resetn => bit_d_1.ACLR |
rx_resetn => bit_d_8.ACLR |
rx_resetn => bit_d_6.ACLR |
rx_resetn => bit_d_4.ACLR |
rx_resetn => bit_d_2.ACLR |
rx_resetn => bit_d_0.ACLR |
rx_resetn => bit_c_3.ACLR |
rx_resetn => bit_c_1.ACLR |
rx_resetn => bit_c_2.ACLR |
rx_resetn => bit_c_0.ACLR |
rx_resetn => control_r[0].ACLR |
rx_resetn => control_r[1].ACLR |
rx_resetn => control_r[2].ACLR |
rx_resetn => control_r[3].ACLR |
rx_resetn => control_p_r[0].ACLR |
rx_resetn => control_p_r[1].ACLR |
rx_resetn => control_p_r[2].ACLR |
rx_resetn => control_p_r[3].ACLR |
rx_resetn => dta_timec[0].ACLR |
rx_resetn => dta_timec[1].ACLR |
rx_resetn => dta_timec[2].ACLR |
rx_resetn => dta_timec[3].ACLR |
rx_resetn => dta_timec[4].ACLR |
rx_resetn => dta_timec[5].ACLR |
rx_resetn => dta_timec[6].ACLR |
rx_resetn => dta_timec[7].ACLR |
rx_resetn => dta_timec[8].ACLR |
rx_resetn => dta_timec[9].ACLR |
rx_resetn => dta_timec_p[0].ACLR |
rx_resetn => dta_timec_p[1].ACLR |
rx_resetn => dta_timec_p[2].ACLR |
rx_resetn => dta_timec_p[3].ACLR |
rx_resetn => dta_timec_p[4].ACLR |
rx_resetn => dta_timec_p[5].ACLR |
rx_resetn => dta_timec_p[6].ACLR |
rx_resetn => dta_timec_p[7].ACLR |
rx_resetn => dta_timec_p[8].ACLR |
rx_resetn => dta_timec_p[9].ACLR |
rx_resetn => counter_neg[0].PRESET |
rx_resetn => counter_neg[1].ACLR |
rx_resetn => counter_neg[2].ACLR |
rx_resetn => counter_neg[3].ACLR |
rx_resetn => counter_neg[4].ACLR |
rx_resetn => counter_neg[5].ACLR |
rx_resetn => control_bit_found.ACLR |
rx_resetn => is_control.ACLR |
rx_error <= rx_error~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_bit <= always0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_null <= rx_got_null~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_nchar <= rx_got_nchar~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_time_code <= rx_got_time_code~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_resetn => last_is_timec~reg0.ACLR |
rx_resetn => last_is_data~reg0.ACLR |
rx_resetn => last_is_control~reg0.ACLR |
ready_control_p_r => always0.IN0 |
ready_control_p_r => rx_got_fct.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => rx_data_flag.OUTPUTSELECT |
ready_control_p_r => last_is_control.OUTPUTSELECT |
ready_control_p_r => last_is_data.OUTPUTSELECT |
ready_control_p_r => last_is_timec.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => timecode.OUTPUTSELECT |
ready_control_p_r => rx_error_c.OUTPUTSELECT |
ready_control_p_r => rx_got_fct.OUTPUTSELECT |
ready_control_p_r => rx_error_d.OUTPUTSELECT |
ready_data_p_r => always0.IN1 |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => rx_data_flag.OUTPUTSELECT |
ready_data_p_r => last_is_control.OUTPUTSELECT |
ready_data_p_r => last_is_data.OUTPUTSELECT |
ready_data_p_r => last_is_timec.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => timecode.OUTPUTSELECT |
ready_data_p_r => rx_error_d.OUTPUTSELECT |
ready_control => always0.IN0 |
ready_data => always0.IN1 |
parity_rec_c => always1.IN0 |
parity_rec_d => always1.IN0 |
parity_rec_c_gen => always1.IN1 |
parity_rec_d_gen => always1.IN1 |
control_p_r[0] => Equal3.IN2 |
control_p_r[0] => Equal4.IN2 |
control_p_r[0] => Equal5.IN1 |
control_p_r[0] => Equal6.IN2 |
control_p_r[1] => Equal3.IN1 |
control_p_r[1] => Equal4.IN1 |
control_p_r[1] => Equal5.IN2 |
control_p_r[1] => Equal6.IN1 |
control_p_r[2] => Equal3.IN0 |
control_p_r[2] => Equal4.IN0 |
control_p_r[2] => Equal5.IN0 |
control_p_r[2] => Equal6.IN0 |
control_l_r[0] => Equal2.IN2 |
control_l_r[1] => Equal2.IN1 |
control_l_r[2] => Equal2.IN0 |
dta_timec_p[0] => timecode.DATAB |
dta_timec_p[0] => rx_data_flag.DATAB |
dta_timec_p[1] => timecode.DATAB |
dta_timec_p[1] => rx_data_flag.DATAB |
dta_timec_p[2] => timecode.DATAB |
dta_timec_p[2] => rx_data_flag.DATAB |
dta_timec_p[3] => timecode.DATAB |
dta_timec_p[3] => rx_data_flag.DATAB |
dta_timec_p[4] => timecode.DATAB |
dta_timec_p[4] => rx_data_flag.DATAB |
dta_timec_p[5] => timecode.DATAB |
dta_timec_p[5] => rx_data_flag.DATAB |
dta_timec_p[6] => timecode.DATAB |
dta_timec_p[6] => rx_data_flag.DATAB |
dta_timec_p[7] => timecode.DATAB |
dta_timec_p[7] => rx_data_flag.DATAB |
dta_timec_p[8] => rx_data_flag.DATAB |
state_data_process[0] <= state_data_process[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
state_data_process[1] <= state_data_process[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
last_is_control <= last_is_control~reg0.DB_MAX_OUTPUT_PORT_TYPE |
last_is_data <= last_is_data~reg0.DB_MAX_OUTPUT_PORT_TYPE |
last_is_timec <= last_is_timec~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_error_c <= rx_error_c~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_error_d <= rx_error_d~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_fct <= rx_got_fct~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_got_fct_fsm <= rx_got_fct_fsm~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_data_flag[0] <= rx_data_flag[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_data_flag[1] <= rx_data_flag[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_data_flag[2] <= rx_data_flag[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
167062,23 → 167378,224
rx_data_flag[6] <= rx_data_flag[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_data_flag[7] <= rx_data_flag[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_data_flag[8] <= rx_data_flag[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_buffer_write <= rx_buffer_write~reg0.DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[0] <= timecode[0].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[1] <= timecode[1].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[2] <= timecode[2].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[3] <= timecode[3].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[4] <= timecode[4].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[5] <= timecode[5].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[6] <= timecode[6].DB_MAX_OUTPUT_PORT_TYPE |
rx_time_out[7] <= timecode[7].DB_MAX_OUTPUT_PORT_TYPE |
rx_tick_out <= rx_tick_out~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[0] <= timecode[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[1] <= timecode[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[2] <= timecode[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[3] <= timecode[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[4] <= timecode[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[5] <= timecode[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[6] <= timecode[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
timecode[7] <= timecode[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX |
pclk_tx => last_tx_sout.CLK |
pclk_tx => last_tx_dout.CLK |
pclk_tx => block_sum_fct_send.CLK |
pclk_tx => block_sum.CLK |
pclk_tx => pclk_tx.IN2 |
data_tx_i[0] => data_tx_i[0].IN1 |
data_tx_i[1] => data_tx_i[1].IN1 |
data_tx_i[2] => data_tx_i[2].IN1 |
data_tx_i[3] => data_tx_i[3].IN1 |
data_tx_i[4] => data_tx_i[4].IN1 |
data_tx_i[5] => data_tx_i[5].IN1 |
data_tx_i[6] => data_tx_i[6].IN1 |
data_tx_i[7] => data_tx_i[7].IN1 |
data_tx_i[8] => data_tx_i[8].IN1 |
txwrite_tx => txwrite_tx.IN1 |
timecode_tx_i[0] => timecode_tx_i[0].IN1 |
timecode_tx_i[1] => timecode_tx_i[1].IN1 |
timecode_tx_i[2] => timecode_tx_i[2].IN1 |
timecode_tx_i[3] => timecode_tx_i[3].IN1 |
timecode_tx_i[4] => timecode_tx_i[4].IN1 |
timecode_tx_i[5] => timecode_tx_i[5].IN1 |
timecode_tx_i[6] => timecode_tx_i[6].IN1 |
timecode_tx_i[7] => timecode_tx_i[7].IN1 |
tickin_tx => tickin_tx.IN1 |
enable_tx => enable_tx.IN2 |
send_null_tx => send_null_tx.IN1 |
send_fct_tx => send_fct_tx.IN1 |
gotfct_tx => gotfct_tx.IN1 |
send_fct_now => send_fct_now.IN1 |
ready_tx_data <= tx_fsm_m:tx_fsm.ready_tx_data |
ready_tx_timecode <= tx_fsm_m:tx_fsm.ready_tx_timecode |
tx_dout_e <= tx_fsm_m:tx_fsm.tx_dout_e |
tx_sout_e <= tx_fsm_m:tx_fsm.tx_sout_e |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm |
pclk_tx => pclk_tx.IN2 |
enable_tx => enable_tx.IN2 |
send_null_tx => always0.IN0 |
send_null_tx => last_tx_dout.OUTPUTSELECT |
send_null_tx => last_tx_sout.OUTPUTSELECT |
send_null_tx => tx_dout_e.OUTPUTSELECT |
send_null_tx => tx_sout_e.OUTPUTSELECT |
send_null_tx => global_counter_transfer.OUTPUTSELECT |
send_null_tx => global_counter_transfer.OUTPUTSELECT |
send_null_tx => global_counter_transfer.OUTPUTSELECT |
send_null_tx => global_counter_transfer.OUTPUTSELECT |
send_null_tx => Selector1.IN5 |
send_null_tx => Selector0.IN1 |
send_fct_tx => always0.IN1 |
send_fct_tx => always0.IN1 |
tx_data_in[0] => ShiftRight1.IN10 |
tx_data_in[0] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[0] => Equal0.IN1 |
tx_data_in[0] => Equal1.IN1 |
tx_data_in[1] => ShiftRight1.IN9 |
tx_data_in[1] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[1] => Equal0.IN0 |
tx_data_in[1] => Equal1.IN0 |
tx_data_in[2] => ShiftRight1.IN8 |
tx_data_in[2] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[3] => ShiftRight1.IN7 |
tx_data_in[3] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[4] => ShiftRight1.IN6 |
tx_data_in[4] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[5] => ShiftRight1.IN5 |
tx_data_in[5] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[6] => ShiftRight1.IN4 |
tx_data_in[6] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[7] => ShiftRight1.IN3 |
tx_data_in[7] => txdata_flagctrl_tx_last.DATAB |
tx_data_in[8] => result_shift.IN1 |
tx_data_in[8] => result_shift.IN1 |
tx_data_in[8] => counter_aux.IN0 |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in[8] => ready_tx_data.OUTPUTSELECT |
tx_data_in[8] => char_sent.OUTPUTSELECT |
tx_data_in[8] => counter_aux.IN0 |
tx_data_in[8] => result_shift.IN0 |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => next_state_tx.OUTPUTSELECT |
tx_data_in[8] => always1.IN0 |
tx_data_in_0[0] => ShiftRight2.IN10 |
tx_data_in_0[0] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[0] => Equal2.IN1 |
tx_data_in_0[0] => Equal3.IN1 |
tx_data_in_0[1] => ShiftRight2.IN9 |
tx_data_in_0[1] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[1] => Equal2.IN0 |
tx_data_in_0[1] => Equal3.IN0 |
tx_data_in_0[2] => ShiftRight2.IN8 |
tx_data_in_0[2] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[3] => ShiftRight2.IN7 |
tx_data_in_0[3] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[4] => ShiftRight2.IN6 |
tx_data_in_0[4] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[5] => ShiftRight2.IN5 |
tx_data_in_0[5] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[6] => ShiftRight2.IN4 |
tx_data_in_0[6] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[7] => ShiftRight2.IN3 |
tx_data_in_0[7] => txdata_flagctrl_tx_last.DATAB |
tx_data_in_0[8] => result_shift.IN1 |
tx_data_in_0[8] => result_shift.IN1 |
tx_data_in_0[8] => counter_aux.IN1 |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
tx_data_in_0[8] => ready_tx_data.OUTPUTSELECT |
tx_data_in_0[8] => char_sent.OUTPUTSELECT |
tx_data_in_0[8] => counter_aux.IN1 |
tx_data_in_0[8] => result_shift.IN0 |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => next_state_tx.OUTPUTSELECT |
tx_data_in_0[8] => always1.IN1 |
process_data => next_state_tx.DATAA |
process_data => next_state_tx.DATAA |
process_data => next_state_tx.DATAA |
process_data => next_state_tx.DATAA |
process_data_0 => next_state_tx.DATAA |
process_data_0 => next_state_tx.DATAA |
gotfct_tx => gotfct_tx.IN1 |
send_fct_now => send_fct_now.IN1 |
tx_tcode_in[0] => ShiftRight0.IN14 |
tx_tcode_in[0] => last_timein_control_flag_tx.DATAB |
tx_tcode_in[1] => ShiftRight0.IN13 |
tx_tcode_in[1] => last_timein_control_flag_tx.DATAB |
tx_tcode_in[2] => ShiftRight0.IN12 |
tx_tcode_in[2] => last_timein_control_flag_tx.DATAB |
tx_tcode_in[3] => ShiftRight0.IN11 |
tx_tcode_in[3] => last_timein_control_flag_tx.DATAB |
tx_tcode_in[4] => ShiftRight0.IN10 |
tx_tcode_in[4] => last_timein_control_flag_tx.DATAB |
tx_tcode_in[5] => ShiftRight0.IN9 |
tx_tcode_in[5] => last_timein_control_flag_tx.DATAB |
tx_tcode_in[6] => ShiftRight0.IN8 |
tx_tcode_in[6] => last_timein_control_flag_tx.DATAB |
tx_tcode_in[7] => ShiftRight0.IN7 |
tx_tcode_in[7] => last_timein_control_flag_tx.DATAB |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.OUTPUTSELECT |
tcode_rdy_trnsp => next_state_tx.DATAB |
tcode_rdy_trnsp => next_state_tx.DATAB |
tcode_rdy_trnsp => next_state_tx.DATAB |
tcode_rdy_trnsp => next_state_tx.DATAB |
tcode_rdy_trnsp => next_state_tx.DATAB |
ready_tx_data <= ready_tx_data~reg0.DB_MAX_OUTPUT_PORT_TYPE |
ready_tx_timecode <= ready_tx_timecode~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_great_than_zero <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE |
get_data <= get_data.DB_MAX_OUTPUT_PORT_TYPE |
get_data_0 <= get_data_0.DB_MAX_OUTPUT_PORT_TYPE |
tx_dout_e <= tx_dout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_sout_e <= tx_sout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt |
pclk_tx => clear_reg.CLK |
pclk_tx => fct_counter_p[0]~reg0.CLK |
pclk_tx => fct_counter_p[1]~reg0.CLK |
pclk_tx => fct_counter_p[2]~reg0.CLK |
pclk_tx => fct_counter_p[3]~reg0.CLK |
pclk_tx => fct_counter_p[4]~reg0.CLK |
pclk_tx => fct_counter_p[5]~reg0.CLK |
pclk_tx => rec_b.CLK |
pclk_tx => rec_a.CLK |
pclk_tx => fct_counter_receive[0].CLK |
pclk_tx => fct_counter_receive[1].CLK |
pclk_tx => fct_counter_receive[2].CLK |
167085,248 → 167602,271
pclk_tx => fct_counter_receive[3].CLK |
pclk_tx => fct_counter_receive[4].CLK |
pclk_tx => fct_counter_receive[5].CLK |
pclk_tx => last_timein_control_flag_tx[0].CLK |
pclk_tx => last_timein_control_flag_tx[1].CLK |
pclk_tx => last_timein_control_flag_tx[2].CLK |
pclk_tx => last_timein_control_flag_tx[3].CLK |
pclk_tx => last_timein_control_flag_tx[4].CLK |
pclk_tx => last_timein_control_flag_tx[5].CLK |
pclk_tx => last_timein_control_flag_tx[6].CLK |
pclk_tx => last_timein_control_flag_tx[7].CLK |
pclk_tx => txdata_flagctrl_tx_last[0].CLK |
pclk_tx => txdata_flagctrl_tx_last[1].CLK |
pclk_tx => txdata_flagctrl_tx_last[2].CLK |
pclk_tx => txdata_flagctrl_tx_last[3].CLK |
pclk_tx => txdata_flagctrl_tx_last[4].CLK |
pclk_tx => txdata_flagctrl_tx_last[5].CLK |
pclk_tx => txdata_flagctrl_tx_last[6].CLK |
pclk_tx => txdata_flagctrl_tx_last[7].CLK |
pclk_tx => global_counter_transfer[0].CLK |
pclk_tx => global_counter_transfer[1].CLK |
pclk_tx => global_counter_transfer[2].CLK |
pclk_tx => global_counter_transfer[3].CLK |
pclk_tx => hold_time_code.CLK |
pclk_tx => hold_data.CLK |
pclk_tx => hold_fct.CLK |
pclk_tx => hold_null.CLK |
pclk_tx => ready_tx_timecode~reg0.CLK |
pclk_tx => ready_tx_data~reg0.CLK |
pclk_tx => first_time.CLK |
pclk_tx => state_fct_p~1.DATAIN |
pclk_tx => state_fct_receive~1.DATAIN |
enable_tx => fct_counter_p.OUTPUTSELECT |
enable_tx => fct_counter_p.OUTPUTSELECT |
enable_tx => fct_counter_p.OUTPUTSELECT |
enable_tx => fct_counter_p.OUTPUTSELECT |
enable_tx => fct_counter_p.OUTPUTSELECT |
enable_tx => fct_counter_p.OUTPUTSELECT |
enable_tx => state_fct_p.OUTPUTSELECT |
enable_tx => state_fct_p.OUTPUTSELECT |
enable_tx => state_fct_p.OUTPUTSELECT |
enable_tx => state_fct_p.OUTPUTSELECT |
enable_tx => state_fct_p.OUTPUTSELECT |
enable_tx => clear_reg.OUTPUTSELECT |
enable_tx => fct_counter_receive.OUTPUTSELECT |
enable_tx => fct_counter_receive.OUTPUTSELECT |
enable_tx => fct_counter_receive.OUTPUTSELECT |
enable_tx => fct_counter_receive.OUTPUTSELECT |
enable_tx => fct_counter_receive.OUTPUTSELECT |
enable_tx => fct_counter_receive.OUTPUTSELECT |
enable_tx => state_fct_receive.OUTPUTSELECT |
enable_tx => state_fct_receive.OUTPUTSELECT |
enable_tx => state_fct_receive.OUTPUTSELECT |
enable_tx => state_fct_receive.OUTPUTSELECT |
enable_tx => state_fct_receive.OUTPUTSELECT |
enable_tx => rec_a.OUTPUTSELECT |
enable_tx => rec_b.OUTPUTSELECT |
gotfct_tx => rec_a.DATAA |
char_sent => Selector8.IN1 |
char_sent => fct_counter_p.OUTPUTSELECT |
char_sent => fct_counter_p.OUTPUTSELECT |
char_sent => fct_counter_p.OUTPUTSELECT |
char_sent => fct_counter_p.OUTPUTSELECT |
char_sent => fct_counter_p.OUTPUTSELECT |
char_sent => fct_counter_p.OUTPUTSELECT |
char_sent => Selector7.IN4 |
char_sent => Selector9.IN3 |
fct_counter_p[0] <= fct_counter_p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_counter_p[1] <= fct_counter_p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_counter_p[2] <= fct_counter_p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_counter_p[3] <= fct_counter_p[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_counter_p[4] <= fct_counter_p[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_counter_p[5] <= fct_counter_p[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd |
pclk_tx => clear_reg_fct_flag.CLK |
pclk_tx => fct_flag_p[0]~reg0.CLK |
pclk_tx => fct_flag_p[1]~reg0.CLK |
pclk_tx => fct_flag_p[2]~reg0.CLK |
pclk_tx => fct_flag[0].CLK |
pclk_tx => fct_flag[1].CLK |
pclk_tx => fct_flag[2].CLK |
pclk_tx => timecode_s[0].CLK |
pclk_tx => timecode_s[1].CLK |
pclk_tx => timecode_s[2].CLK |
pclk_tx => timecode_s[3].CLK |
pclk_tx => timecode_s[4].CLK |
pclk_tx => timecode_s[5].CLK |
pclk_tx => timecode_s[6].CLK |
pclk_tx => timecode_s[7].CLK |
pclk_tx => timecode_s[8].CLK |
pclk_tx => timecode_s[9].CLK |
pclk_tx => timecode_s[10].CLK |
pclk_tx => timecode_s[11].CLK |
pclk_tx => timecode_s[12].CLK |
pclk_tx => tx_sout_e~reg0.CLK |
pclk_tx => tx_dout_e~reg0.CLK |
pclk_tx => state_tx~1.DATAIN |
pclk_tx => last_type~1.DATAIN |
data_tx_i[0] => tx_dout_data.DATAB |
data_tx_i[0] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[0] => Equal11.IN0 |
data_tx_i[0] => Equal14.IN1 |
data_tx_i[1] => tx_dout_data.DATAB |
data_tx_i[1] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[1] => Equal11.IN1 |
data_tx_i[1] => Equal14.IN0 |
data_tx_i[2] => tx_dout_data.DATAB |
data_tx_i[2] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[3] => tx_dout_data.DATAB |
data_tx_i[3] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[4] => tx_dout_data.DATAB |
data_tx_i[4] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[5] => tx_dout_data.DATAB |
data_tx_i[5] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[6] => tx_dout_data.DATAB |
data_tx_i[6] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[7] => tx_dout_data.DATAB |
data_tx_i[7] => txdata_flagctrl_tx_last.DATAB |
data_tx_i[8] => tx_dout_data.IN1 |
data_tx_i[8] => tx_dout_data.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => tx_dout_data.DATAB |
data_tx_i[8] => tx_dout_data.DATAB |
data_tx_i[8] => tx_dout_data.DATAB |
data_tx_i[8] => hold_data.OUTPUTSELECT |
data_tx_i[8] => ready_tx_data.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => block_sum.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => hold_data.OUTPUTSELECT |
data_tx_i[8] => ready_tx_data.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => global_counter_transfer.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => txdata_flagctrl_tx_last.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => fct_counter_receive.OUTPUTSELECT |
data_tx_i[8] => block_sum.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => last_type.OUTPUTSELECT |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN1 |
data_tx_i[8] => always3.IN0 |
data_tx_i[8] => always3.IN0 |
data_tx_i[8] => always3.IN0 |
data_tx_i[8] => always3.IN0 |
data_tx_i[8] => tx_dout_data.DATAB |
data_tx_i[8] => always3.IN0 |
data_tx_i[8] => tx_dout_data.DATAB |
data_tx_i[8] => always3.IN0 |
txwrite_tx => always7.IN1 |
timecode_tx_i[0] => timecode_s.DATAB |
timecode_tx_i[0] => last_timein_control_flag_tx.DATAA |
timecode_tx_i[1] => timecode_s.DATAB |
timecode_tx_i[1] => last_timein_control_flag_tx.DATAA |
timecode_tx_i[2] => timecode_s.DATAB |
timecode_tx_i[2] => last_timein_control_flag_tx.DATAA |
timecode_tx_i[3] => timecode_s.DATAB |
timecode_tx_i[3] => last_timein_control_flag_tx.DATAA |
timecode_tx_i[4] => timecode_s.DATAB |
timecode_tx_i[4] => last_timein_control_flag_tx.DATAA |
timecode_tx_i[5] => timecode_s.DATAB |
timecode_tx_i[5] => last_timein_control_flag_tx.DATAA |
timecode_tx_i[6] => timecode_s.DATAB |
timecode_tx_i[6] => last_timein_control_flag_tx.DATAA |
timecode_tx_i[7] => timecode_s.DATAB |
timecode_tx_i[7] => last_timein_control_flag_tx.DATAA |
tickin_tx => always7.IN1 |
enable_tx => always7.IN0 |
enable_tx => always7.IN1 |
enable_tx => last_tx_sout.ACLR |
enable_tx => last_tx_dout.ACLR |
enable_tx => block_sum_fct_send.ACLR |
enable_tx => block_sum.ACLR |
enable_tx => fct_counter_receive[0].ACLR |
enable_tx => fct_counter_receive[1].ACLR |
enable_tx => fct_counter_receive[2].ACLR |
enable_tx => fct_counter_receive[3].ACLR |
enable_tx => fct_counter_receive[4].ACLR |
enable_tx => fct_counter_receive[5].ACLR |
enable_tx => last_timein_control_flag_tx[0].ACLR |
enable_tx => last_timein_control_flag_tx[1].ACLR |
enable_tx => last_timein_control_flag_tx[2].ACLR |
enable_tx => last_timein_control_flag_tx[3].ACLR |
enable_tx => last_timein_control_flag_tx[4].ACLR |
enable_tx => last_timein_control_flag_tx[5].ACLR |
enable_tx => last_timein_control_flag_tx[6].ACLR |
enable_tx => last_timein_control_flag_tx[7].ACLR |
enable_tx => txdata_flagctrl_tx_last[0].ACLR |
enable_tx => txdata_flagctrl_tx_last[1].ACLR |
enable_tx => txdata_flagctrl_tx_last[2].ACLR |
enable_tx => txdata_flagctrl_tx_last[3].ACLR |
enable_tx => txdata_flagctrl_tx_last[4].ACLR |
enable_tx => txdata_flagctrl_tx_last[5].ACLR |
enable_tx => txdata_flagctrl_tx_last[6].ACLR |
enable_tx => txdata_flagctrl_tx_last[7].ACLR |
enable_tx => global_counter_transfer[0].ACLR |
enable_tx => global_counter_transfer[1].ACLR |
enable_tx => global_counter_transfer[2].ACLR |
enable_tx => global_counter_transfer[3].ACLR |
enable_tx => hold_time_code.ACLR |
enable_tx => hold_data.ACLR |
enable_tx => hold_fct.ACLR |
enable_tx => hold_null.ACLR |
enable_tx => ready_tx_timecode~reg0.ACLR |
enable_tx => ready_tx_data~reg0.ACLR |
enable_tx => first_time.PRESET |
enable_tx => fct_flag[0].PRESET |
enable_tx => fct_flag[1].PRESET |
enable_tx => fct_flag[2].PRESET |
enable_tx => timecode_s[0].ACLR |
enable_tx => timecode_s[1].ACLR |
enable_tx => timecode_s[2].ACLR |
enable_tx => timecode_s[3].ACLR |
enable_tx => timecode_s[4].ACLR |
enable_tx => timecode_s[5].ACLR |
enable_tx => timecode_s[6].ACLR |
enable_tx => timecode_s[7].ACLR |
enable_tx => timecode_s[8].ACLR |
enable_tx => timecode_s[9].ACLR |
enable_tx => timecode_s[10].PRESET |
enable_tx => timecode_s[11].PRESET |
enable_tx => timecode_s[12].PRESET |
enable_tx => tx_sout_e~reg0.ACLR |
enable_tx => tx_dout_e~reg0.ACLR |
enable_tx => tx_sout.OUTPUTSELECT |
enable_tx => state_tx~3.DATAIN |
enable_tx => last_type~3.DATAIN |
send_null_tx => always7.IN1 |
send_null_tx => always7.IN0 |
send_fct_tx => always7.IN1 |
send_fct_tx => always7.IN1 |
send_fct_tx => always7.IN1 |
gotfct_tx => fct_counter[5].OUTPUTSELECT |
gotfct_tx => fct_counter[4].OUTPUTSELECT |
gotfct_tx => fct_counter[3].OUTPUTSELECT |
gotfct_tx => fct_counter[2].OUTPUTSELECT |
gotfct_tx => fct_counter[1].OUTPUTSELECT |
gotfct_tx => fct_counter[0].OUTPUTSELECT |
gotfct_tx => always10.IN1 |
gotfct_tx => block_sum.OUTPUTSELECT |
send_fct_now => fct_send[2].OUTPUTSELECT |
send_fct_now => fct_send[1].OUTPUTSELECT |
send_fct_now => fct_send[0].OUTPUTSELECT |
send_fct_now => always10.IN1 |
send_fct_now => block_sum_fct_send.OUTPUTSELECT |
tx_dout_e <= tx_dout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_sout_e <= tx_sout_e~reg0.DB_MAX_OUTPUT_PORT_TYPE |
ready_tx_data <= ready_tx_data~reg0.DB_MAX_OUTPUT_PORT_TYPE |
ready_tx_timecode <= ready_tx_timecode~reg0.DB_MAX_OUTPUT_PORT_TYPE |
pclk_tx => state_fct_send_p~1.DATAIN |
pclk_tx => state_fct_send~1.DATAIN |
enable_tx => clear_reg_fct_flag.ACLR |
enable_tx => fct_flag_p[0]~reg0.PRESET |
enable_tx => fct_flag_p[1]~reg0.PRESET |
enable_tx => fct_flag_p[2]~reg0.PRESET |
enable_tx => fct_flag.OUTPUTSELECT |
enable_tx => fct_flag.OUTPUTSELECT |
enable_tx => fct_flag.OUTPUTSELECT |
enable_tx => state_fct_send.OUTPUTSELECT |
enable_tx => state_fct_send.OUTPUTSELECT |
enable_tx => state_fct_send_p~3.DATAIN |
send_fct_now => fct_flag.OUTPUTSELECT |
send_fct_now => fct_flag.OUTPUTSELECT |
send_fct_now => fct_flag.OUTPUTSELECT |
send_fct_now => next_state_fct_send_p.OUTPUTSELECT |
send_fct_now => next_state_fct_send_p.OUTPUTSELECT |
send_fct_now => fct_flag_p.OUTPUTSELECT |
send_fct_now => fct_flag_p.OUTPUTSELECT |
send_fct_now => fct_flag_p.OUTPUTSELECT |
send_fct_now => clear_reg_fct_flag.OUTPUTSELECT |
send_fct_now => state_fct_send.DATAA |
send_fct_now => state_fct_send.DATAA |
fct_sent => fct_flag_p.OUTPUTSELECT |
fct_sent => fct_flag_p.OUTPUTSELECT |
fct_sent => fct_flag_p.OUTPUTSELECT |
fct_sent => Selector2.IN2 |
fct_sent => always2.IN1 |
fct_sent => always2.IN1 |
fct_sent => Selector1.IN2 |
fct_flag_p[0] <= fct_flag_p[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_flag_p[1] <= fct_flag_p[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
fct_flag_p[2] <= fct_flag_p[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd |
pclk_tx => tx_tcode_in[0]~reg0.CLK |
pclk_tx => tx_tcode_in[1]~reg0.CLK |
pclk_tx => tx_tcode_in[2]~reg0.CLK |
pclk_tx => tx_tcode_in[3]~reg0.CLK |
pclk_tx => tx_tcode_in[4]~reg0.CLK |
pclk_tx => tx_tcode_in[5]~reg0.CLK |
pclk_tx => tx_tcode_in[6]~reg0.CLK |
pclk_tx => tx_tcode_in[7]~reg0.CLK |
pclk_tx => tx_data_in_0[0]~reg0.CLK |
pclk_tx => tx_data_in_0[1]~reg0.CLK |
pclk_tx => tx_data_in_0[2]~reg0.CLK |
pclk_tx => tx_data_in_0[3]~reg0.CLK |
pclk_tx => tx_data_in_0[4]~reg0.CLK |
pclk_tx => tx_data_in_0[5]~reg0.CLK |
pclk_tx => tx_data_in_0[6]~reg0.CLK |
pclk_tx => tx_data_in_0[7]~reg0.CLK |
pclk_tx => tx_data_in_0[8]~reg0.CLK |
pclk_tx => tx_data_in[0]~reg0.CLK |
pclk_tx => tx_data_in[1]~reg0.CLK |
pclk_tx => tx_data_in[2]~reg0.CLK |
pclk_tx => tx_data_in[3]~reg0.CLK |
pclk_tx => tx_data_in[4]~reg0.CLK |
pclk_tx => tx_data_in[5]~reg0.CLK |
pclk_tx => tx_data_in[6]~reg0.CLK |
pclk_tx => tx_data_in[7]~reg0.CLK |
pclk_tx => tx_data_in[8]~reg0.CLK |
pclk_tx => tcode_rdy_trnsp~reg0.CLK |
pclk_tx => process_data_0~reg0.CLK |
pclk_tx => process_data~reg0.CLK |
enable_tx => process_data.OUTPUTSELECT |
enable_tx => process_data_0.OUTPUTSELECT |
enable_tx => tcode_rdy_trnsp.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_data_in_0.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
enable_tx => tx_tcode_in.OUTPUTSELECT |
get_data => always0.IN1 |
get_data_0 => always0.IN1 |
timecode_tx_i[0] => tx_tcode_in.DATAB |
timecode_tx_i[1] => tx_tcode_in.DATAB |
timecode_tx_i[2] => tx_tcode_in.DATAB |
timecode_tx_i[3] => tx_tcode_in.DATAB |
timecode_tx_i[4] => tx_tcode_in.DATAB |
timecode_tx_i[5] => tx_tcode_in.DATAB |
timecode_tx_i[6] => tx_tcode_in.DATAB |
timecode_tx_i[7] => tx_tcode_in.DATAB |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tx_tcode_in.OUTPUTSELECT |
tickin_tx => tcode_rdy_trnsp.DATAA |
data_tx_i[0] => tx_data_in.DATAB |
data_tx_i[0] => tx_data_in_0.DATAB |
data_tx_i[1] => tx_data_in.DATAB |
data_tx_i[1] => tx_data_in_0.DATAB |
data_tx_i[2] => tx_data_in.DATAB |
data_tx_i[2] => tx_data_in_0.DATAB |
data_tx_i[3] => tx_data_in.DATAB |
data_tx_i[3] => tx_data_in_0.DATAB |
data_tx_i[4] => tx_data_in.DATAB |
data_tx_i[4] => tx_data_in_0.DATAB |
data_tx_i[5] => tx_data_in.DATAB |
data_tx_i[5] => tx_data_in_0.DATAB |
data_tx_i[6] => tx_data_in.DATAB |
data_tx_i[6] => tx_data_in_0.DATAB |
data_tx_i[7] => tx_data_in.DATAB |
data_tx_i[7] => tx_data_in_0.DATAB |
data_tx_i[8] => tx_data_in.DATAB |
data_tx_i[8] => tx_data_in_0.DATAB |
txwrite_tx => process_data_en.IN0 |
fct_counter_p => process_data_en.IN1 |
tx_data_in[0] <= tx_data_in[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[1] <= tx_data_in[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[2] <= tx_data_in[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[3] <= tx_data_in[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[4] <= tx_data_in[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[5] <= tx_data_in[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[6] <= tx_data_in[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[7] <= tx_data_in[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in[8] <= tx_data_in[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[0] <= tx_data_in_0[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[1] <= tx_data_in_0[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[2] <= tx_data_in_0[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[3] <= tx_data_in_0[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[4] <= tx_data_in_0[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[5] <= tx_data_in_0[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[6] <= tx_data_in_0[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[7] <= tx_data_in_0[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_data_in_0[8] <= tx_data_in_0[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
process_data <= process_data~reg0.DB_MAX_OUTPUT_PORT_TYPE |
process_data_0 <= process_data_0~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[0] <= tx_tcode_in[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[1] <= tx_tcode_in[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[2] <= tx_tcode_in[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[3] <= tx_tcode_in[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[4] <= tx_tcode_in[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[5] <= tx_tcode_in[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[6] <= tx_tcode_in[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tx_tcode_in[7] <= tx_tcode_in[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
tcode_rdy_trnsp <= tcode_rdy_trnsp~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data |
clock => block_read.CLK |
clock => open_slot_fct~reg0.CLK |
clock => clock.IN1 |
reset => reset.IN1 |
wr_en => always1.IN1 |
wr_en => Selector4.IN2 |
wr_en => next_state_data_write.10.DATAB |
rd_en => always2.IN1 |
rd_en => always5.IN1 |
rd_en => always5.IN0 |
rd_en => rd_ptr.OUTPUTSELECT |
rd_en => rd_ptr.OUTPUTSELECT |
rd_en => rd_ptr.OUTPUTSELECT |
rd_en => rd_ptr.OUTPUTSELECT |
rd_en => rd_ptr.OUTPUTSELECT |
rd_en => rd_ptr.OUTPUTSELECT |
rd_en => Selector6.IN2 |
rd_en => next_state_data_read.10.DATAB |
data_in[0] => data_in[0].IN1 |
data_in[1] => data_in[1].IN1 |
data_in[2] => data_in[2].IN1 |
data_in[3] => data_in[3].IN1 |
data_in[4] => data_in[4].IN1 |
data_in[5] => data_in[5].IN1 |
data_in[6] => data_in[6].IN1 |
data_in[7] => data_in[7].IN1 |
data_in[8] => data_in[8].IN1 |
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE |
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE |
open_slot_fct <= open_slot_fct~reg0.DB_MAX_OUTPUT_PORT_TYPE |
overflow_credit_error <= overflow_credit_error~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[0] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[1] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[2] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[3] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[4] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[5] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[6] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[7] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[8] <= mem_data:mem_dta_fifo_tx.data_out |
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx |
clock => data_out[0]~reg0.CLK |
clock => data_out[1]~reg0.CLK |
clock => data_out[2]~reg0.CLK |
167336,28 → 167876,6
clock => data_out[6]~reg0.CLK |
clock => data_out[7]~reg0.CLK |
clock => data_out[8]~reg0.CLK |
clock => rd_ptr[0].CLK |
clock => rd_ptr[1].CLK |
clock => rd_ptr[2].CLK |
clock => rd_ptr[3].CLK |
clock => rd_ptr[4].CLK |
clock => rd_ptr[5].CLK |
clock => credit_counter[0].CLK |
clock => credit_counter[1].CLK |
clock => credit_counter[2].CLK |
clock => credit_counter[3].CLK |
clock => credit_counter[4].CLK |
clock => credit_counter[5].CLK |
clock => counter[0]~reg0.CLK |
clock => counter[1]~reg0.CLK |
clock => counter[2]~reg0.CLK |
clock => counter[3]~reg0.CLK |
clock => counter[4]~reg0.CLK |
clock => counter[5]~reg0.CLK |
clock => f_empty~reg0.CLK |
clock => f_full~reg0.CLK |
clock => overflow_credit_error~reg0.CLK |
clock => block_write.CLK |
clock => mem[63][0].CLK |
clock => mem[63][1].CLK |
clock => mem[63][2].CLK |
167934,14 → 168452,6
clock => mem[0][6].CLK |
clock => mem[0][7].CLK |
clock => mem[0][8].CLK |
clock => wr_ptr[0].CLK |
clock => wr_ptr[1].CLK |
clock => wr_ptr[2].CLK |
clock => wr_ptr[3].CLK |
clock => wr_ptr[4].CLK |
clock => wr_ptr[5].CLK |
reset => overflow_credit_error~reg0.ACLR |
reset => block_write.ACLR |
reset => mem[63][0].ACLR |
reset => mem[63][1].ACLR |
reset => mem[63][2].ACLR |
168518,14 → 169028,6
reset => mem[0][6].ACLR |
reset => mem[0][7].ACLR |
reset => mem[0][8].ACLR |
reset => wr_ptr[0].ACLR |
reset => wr_ptr[1].ACLR |
reset => wr_ptr[2].ACLR |
reset => wr_ptr[3].ACLR |
reset => wr_ptr[4].ACLR |
reset => wr_ptr[5].ACLR |
reset => block_read.ACLR |
reset => open_slot_fct~reg0.ACLR |
reset => data_out[0]~reg0.ACLR |
reset => data_out[1]~reg0.ACLR |
reset => data_out[2]~reg0.ACLR |
168535,617 → 169037,642
reset => data_out[6]~reg0.ACLR |
reset => data_out[7]~reg0.ACLR |
reset => data_out[8]~reg0.ACLR |
reset => rd_ptr[0].ACLR |
reset => rd_ptr[1].ACLR |
reset => rd_ptr[2].ACLR |
reset => rd_ptr[3].ACLR |
reset => rd_ptr[4].ACLR |
reset => rd_ptr[5].ACLR |
reset => credit_counter[0].PRESET |
reset => credit_counter[1].PRESET |
reset => credit_counter[2].PRESET |
reset => credit_counter[3].ACLR |
reset => credit_counter[4].PRESET |
reset => credit_counter[5].PRESET |
reset => counter[0]~reg0.ACLR |
reset => counter[1]~reg0.ACLR |
reset => counter[2]~reg0.ACLR |
reset => counter[3]~reg0.ACLR |
reset => counter[4]~reg0.ACLR |
reset => counter[5]~reg0.ACLR |
reset => f_empty~reg0.PRESET |
reset => f_full~reg0.ACLR |
wr_en => always0.IN1 |
wr_en => always1.IN1 |
wr_en => block_write.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
rd_en => always1.IN1 |
rd_en => block_read.OUTPUTSELECT |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE |
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE |
open_slot_fct <= open_slot_fct~reg0.DB_MAX_OUTPUT_PORT_TYPE |
overflow_credit_error <= overflow_credit_error~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_in[0] => mem[0][0].DATAIN |
data_in[0] => mem[1][0].DATAIN |
data_in[0] => mem[2][0].DATAIN |
data_in[0] => mem[3][0].DATAIN |
data_in[0] => mem[4][0].DATAIN |
data_in[0] => mem[5][0].DATAIN |
data_in[0] => mem[6][0].DATAIN |
data_in[0] => mem[7][0].DATAIN |
data_in[0] => mem[8][0].DATAIN |
data_in[0] => mem[9][0].DATAIN |
data_in[0] => mem[10][0].DATAIN |
data_in[0] => mem[11][0].DATAIN |
data_in[0] => mem[12][0].DATAIN |
data_in[0] => mem[13][0].DATAIN |
data_in[0] => mem[14][0].DATAIN |
data_in[0] => mem[15][0].DATAIN |
data_in[0] => mem[16][0].DATAIN |
data_in[0] => mem[17][0].DATAIN |
data_in[0] => mem[18][0].DATAIN |
data_in[0] => mem[19][0].DATAIN |
data_in[0] => mem[20][0].DATAIN |
data_in[0] => mem[21][0].DATAIN |
data_in[0] => mem[22][0].DATAIN |
data_in[0] => mem[23][0].DATAIN |
data_in[0] => mem[24][0].DATAIN |
data_in[0] => mem[25][0].DATAIN |
data_in[0] => mem[26][0].DATAIN |
data_in[0] => mem[27][0].DATAIN |
data_in[0] => mem[28][0].DATAIN |
data_in[0] => mem[29][0].DATAIN |
data_in[0] => mem[30][0].DATAIN |
data_in[0] => mem[31][0].DATAIN |
data_in[0] => mem[32][0].DATAIN |
data_in[0] => mem[33][0].DATAIN |
data_in[0] => mem[34][0].DATAIN |
data_in[0] => mem[35][0].DATAIN |
data_in[0] => mem[36][0].DATAIN |
data_in[0] => mem[37][0].DATAIN |
data_in[0] => mem[38][0].DATAIN |
data_in[0] => mem[39][0].DATAIN |
data_in[0] => mem[40][0].DATAIN |
data_in[0] => mem[41][0].DATAIN |
data_in[0] => mem[42][0].DATAIN |
data_in[0] => mem[43][0].DATAIN |
data_in[0] => mem[44][0].DATAIN |
data_in[0] => mem[45][0].DATAIN |
data_in[0] => mem[46][0].DATAIN |
data_in[0] => mem[47][0].DATAIN |
data_in[0] => mem[48][0].DATAIN |
data_in[0] => mem[49][0].DATAIN |
data_in[0] => mem[50][0].DATAIN |
data_in[0] => mem[51][0].DATAIN |
data_in[0] => mem[52][0].DATAIN |
data_in[0] => mem[53][0].DATAIN |
data_in[0] => mem[54][0].DATAIN |
data_in[0] => mem[55][0].DATAIN |
data_in[0] => mem[56][0].DATAIN |
data_in[0] => mem[57][0].DATAIN |
data_in[0] => mem[58][0].DATAIN |
data_in[0] => mem[59][0].DATAIN |
data_in[0] => mem[60][0].DATAIN |
data_in[0] => mem[61][0].DATAIN |
data_in[0] => mem[62][0].DATAIN |
data_in[0] => mem[63][0].DATAIN |
data_in[1] => mem[0][1].DATAIN |
data_in[1] => mem[1][1].DATAIN |
data_in[1] => mem[2][1].DATAIN |
data_in[1] => mem[3][1].DATAIN |
data_in[1] => mem[4][1].DATAIN |
data_in[1] => mem[5][1].DATAIN |
data_in[1] => mem[6][1].DATAIN |
data_in[1] => mem[7][1].DATAIN |
data_in[1] => mem[8][1].DATAIN |
data_in[1] => mem[9][1].DATAIN |
data_in[1] => mem[10][1].DATAIN |
data_in[1] => mem[11][1].DATAIN |
data_in[1] => mem[12][1].DATAIN |
data_in[1] => mem[13][1].DATAIN |
data_in[1] => mem[14][1].DATAIN |
data_in[1] => mem[15][1].DATAIN |
data_in[1] => mem[16][1].DATAIN |
data_in[1] => mem[17][1].DATAIN |
data_in[1] => mem[18][1].DATAIN |
data_in[1] => mem[19][1].DATAIN |
data_in[1] => mem[20][1].DATAIN |
data_in[1] => mem[21][1].DATAIN |
data_in[1] => mem[22][1].DATAIN |
data_in[1] => mem[23][1].DATAIN |
data_in[1] => mem[24][1].DATAIN |
data_in[1] => mem[25][1].DATAIN |
data_in[1] => mem[26][1].DATAIN |
data_in[1] => mem[27][1].DATAIN |
data_in[1] => mem[28][1].DATAIN |
data_in[1] => mem[29][1].DATAIN |
data_in[1] => mem[30][1].DATAIN |
data_in[1] => mem[31][1].DATAIN |
data_in[1] => mem[32][1].DATAIN |
data_in[1] => mem[33][1].DATAIN |
data_in[1] => mem[34][1].DATAIN |
data_in[1] => mem[35][1].DATAIN |
data_in[1] => mem[36][1].DATAIN |
data_in[1] => mem[37][1].DATAIN |
data_in[1] => mem[38][1].DATAIN |
data_in[1] => mem[39][1].DATAIN |
data_in[1] => mem[40][1].DATAIN |
data_in[1] => mem[41][1].DATAIN |
data_in[1] => mem[42][1].DATAIN |
data_in[1] => mem[43][1].DATAIN |
data_in[1] => mem[44][1].DATAIN |
data_in[1] => mem[45][1].DATAIN |
data_in[1] => mem[46][1].DATAIN |
data_in[1] => mem[47][1].DATAIN |
data_in[1] => mem[48][1].DATAIN |
data_in[1] => mem[49][1].DATAIN |
data_in[1] => mem[50][1].DATAIN |
data_in[1] => mem[51][1].DATAIN |
data_in[1] => mem[52][1].DATAIN |
data_in[1] => mem[53][1].DATAIN |
data_in[1] => mem[54][1].DATAIN |
data_in[1] => mem[55][1].DATAIN |
data_in[1] => mem[56][1].DATAIN |
data_in[1] => mem[57][1].DATAIN |
data_in[1] => mem[58][1].DATAIN |
data_in[1] => mem[59][1].DATAIN |
data_in[1] => mem[60][1].DATAIN |
data_in[1] => mem[61][1].DATAIN |
data_in[1] => mem[62][1].DATAIN |
data_in[1] => mem[63][1].DATAIN |
data_in[2] => mem[0][2].DATAIN |
data_in[2] => mem[1][2].DATAIN |
data_in[2] => mem[2][2].DATAIN |
data_in[2] => mem[3][2].DATAIN |
data_in[2] => mem[4][2].DATAIN |
data_in[2] => mem[5][2].DATAIN |
data_in[2] => mem[6][2].DATAIN |
data_in[2] => mem[7][2].DATAIN |
data_in[2] => mem[8][2].DATAIN |
data_in[2] => mem[9][2].DATAIN |
data_in[2] => mem[10][2].DATAIN |
data_in[2] => mem[11][2].DATAIN |
data_in[2] => mem[12][2].DATAIN |
data_in[2] => mem[13][2].DATAIN |
data_in[2] => mem[14][2].DATAIN |
data_in[2] => mem[15][2].DATAIN |
data_in[2] => mem[16][2].DATAIN |
data_in[2] => mem[17][2].DATAIN |
data_in[2] => mem[18][2].DATAIN |
data_in[2] => mem[19][2].DATAIN |
data_in[2] => mem[20][2].DATAIN |
data_in[2] => mem[21][2].DATAIN |
data_in[2] => mem[22][2].DATAIN |
data_in[2] => mem[23][2].DATAIN |
data_in[2] => mem[24][2].DATAIN |
data_in[2] => mem[25][2].DATAIN |
data_in[2] => mem[26][2].DATAIN |
data_in[2] => mem[27][2].DATAIN |
data_in[2] => mem[28][2].DATAIN |
data_in[2] => mem[29][2].DATAIN |
data_in[2] => mem[30][2].DATAIN |
data_in[2] => mem[31][2].DATAIN |
data_in[2] => mem[32][2].DATAIN |
data_in[2] => mem[33][2].DATAIN |
data_in[2] => mem[34][2].DATAIN |
data_in[2] => mem[35][2].DATAIN |
data_in[2] => mem[36][2].DATAIN |
data_in[2] => mem[37][2].DATAIN |
data_in[2] => mem[38][2].DATAIN |
data_in[2] => mem[39][2].DATAIN |
data_in[2] => mem[40][2].DATAIN |
data_in[2] => mem[41][2].DATAIN |
data_in[2] => mem[42][2].DATAIN |
data_in[2] => mem[43][2].DATAIN |
data_in[2] => mem[44][2].DATAIN |
data_in[2] => mem[45][2].DATAIN |
data_in[2] => mem[46][2].DATAIN |
data_in[2] => mem[47][2].DATAIN |
data_in[2] => mem[48][2].DATAIN |
data_in[2] => mem[49][2].DATAIN |
data_in[2] => mem[50][2].DATAIN |
data_in[2] => mem[51][2].DATAIN |
data_in[2] => mem[52][2].DATAIN |
data_in[2] => mem[53][2].DATAIN |
data_in[2] => mem[54][2].DATAIN |
data_in[2] => mem[55][2].DATAIN |
data_in[2] => mem[56][2].DATAIN |
data_in[2] => mem[57][2].DATAIN |
data_in[2] => mem[58][2].DATAIN |
data_in[2] => mem[59][2].DATAIN |
data_in[2] => mem[60][2].DATAIN |
data_in[2] => mem[61][2].DATAIN |
data_in[2] => mem[62][2].DATAIN |
data_in[2] => mem[63][2].DATAIN |
data_in[3] => mem[0][3].DATAIN |
data_in[3] => mem[1][3].DATAIN |
data_in[3] => mem[2][3].DATAIN |
data_in[3] => mem[3][3].DATAIN |
data_in[3] => mem[4][3].DATAIN |
data_in[3] => mem[5][3].DATAIN |
data_in[3] => mem[6][3].DATAIN |
data_in[3] => mem[7][3].DATAIN |
data_in[3] => mem[8][3].DATAIN |
data_in[3] => mem[9][3].DATAIN |
data_in[3] => mem[10][3].DATAIN |
data_in[3] => mem[11][3].DATAIN |
data_in[3] => mem[12][3].DATAIN |
data_in[3] => mem[13][3].DATAIN |
data_in[3] => mem[14][3].DATAIN |
data_in[3] => mem[15][3].DATAIN |
data_in[3] => mem[16][3].DATAIN |
data_in[3] => mem[17][3].DATAIN |
data_in[3] => mem[18][3].DATAIN |
data_in[3] => mem[19][3].DATAIN |
data_in[3] => mem[20][3].DATAIN |
data_in[3] => mem[21][3].DATAIN |
data_in[3] => mem[22][3].DATAIN |
data_in[3] => mem[23][3].DATAIN |
data_in[3] => mem[24][3].DATAIN |
data_in[3] => mem[25][3].DATAIN |
data_in[3] => mem[26][3].DATAIN |
data_in[3] => mem[27][3].DATAIN |
data_in[3] => mem[28][3].DATAIN |
data_in[3] => mem[29][3].DATAIN |
data_in[3] => mem[30][3].DATAIN |
data_in[3] => mem[31][3].DATAIN |
data_in[3] => mem[32][3].DATAIN |
data_in[3] => mem[33][3].DATAIN |
data_in[3] => mem[34][3].DATAIN |
data_in[3] => mem[35][3].DATAIN |
data_in[3] => mem[36][3].DATAIN |
data_in[3] => mem[37][3].DATAIN |
data_in[3] => mem[38][3].DATAIN |
data_in[3] => mem[39][3].DATAIN |
data_in[3] => mem[40][3].DATAIN |
data_in[3] => mem[41][3].DATAIN |
data_in[3] => mem[42][3].DATAIN |
data_in[3] => mem[43][3].DATAIN |
data_in[3] => mem[44][3].DATAIN |
data_in[3] => mem[45][3].DATAIN |
data_in[3] => mem[46][3].DATAIN |
data_in[3] => mem[47][3].DATAIN |
data_in[3] => mem[48][3].DATAIN |
data_in[3] => mem[49][3].DATAIN |
data_in[3] => mem[50][3].DATAIN |
data_in[3] => mem[51][3].DATAIN |
data_in[3] => mem[52][3].DATAIN |
data_in[3] => mem[53][3].DATAIN |
data_in[3] => mem[54][3].DATAIN |
data_in[3] => mem[55][3].DATAIN |
data_in[3] => mem[56][3].DATAIN |
data_in[3] => mem[57][3].DATAIN |
data_in[3] => mem[58][3].DATAIN |
data_in[3] => mem[59][3].DATAIN |
data_in[3] => mem[60][3].DATAIN |
data_in[3] => mem[61][3].DATAIN |
data_in[3] => mem[62][3].DATAIN |
data_in[3] => mem[63][3].DATAIN |
data_in[4] => mem[0][4].DATAIN |
data_in[4] => mem[1][4].DATAIN |
data_in[4] => mem[2][4].DATAIN |
data_in[4] => mem[3][4].DATAIN |
data_in[4] => mem[4][4].DATAIN |
data_in[4] => mem[5][4].DATAIN |
data_in[4] => mem[6][4].DATAIN |
data_in[4] => mem[7][4].DATAIN |
data_in[4] => mem[8][4].DATAIN |
data_in[4] => mem[9][4].DATAIN |
data_in[4] => mem[10][4].DATAIN |
data_in[4] => mem[11][4].DATAIN |
data_in[4] => mem[12][4].DATAIN |
data_in[4] => mem[13][4].DATAIN |
data_in[4] => mem[14][4].DATAIN |
data_in[4] => mem[15][4].DATAIN |
data_in[4] => mem[16][4].DATAIN |
data_in[4] => mem[17][4].DATAIN |
data_in[4] => mem[18][4].DATAIN |
data_in[4] => mem[19][4].DATAIN |
data_in[4] => mem[20][4].DATAIN |
data_in[4] => mem[21][4].DATAIN |
data_in[4] => mem[22][4].DATAIN |
data_in[4] => mem[23][4].DATAIN |
data_in[4] => mem[24][4].DATAIN |
data_in[4] => mem[25][4].DATAIN |
data_in[4] => mem[26][4].DATAIN |
data_in[4] => mem[27][4].DATAIN |
data_in[4] => mem[28][4].DATAIN |
data_in[4] => mem[29][4].DATAIN |
data_in[4] => mem[30][4].DATAIN |
data_in[4] => mem[31][4].DATAIN |
data_in[4] => mem[32][4].DATAIN |
data_in[4] => mem[33][4].DATAIN |
data_in[4] => mem[34][4].DATAIN |
data_in[4] => mem[35][4].DATAIN |
data_in[4] => mem[36][4].DATAIN |
data_in[4] => mem[37][4].DATAIN |
data_in[4] => mem[38][4].DATAIN |
data_in[4] => mem[39][4].DATAIN |
data_in[4] => mem[40][4].DATAIN |
data_in[4] => mem[41][4].DATAIN |
data_in[4] => mem[42][4].DATAIN |
data_in[4] => mem[43][4].DATAIN |
data_in[4] => mem[44][4].DATAIN |
data_in[4] => mem[45][4].DATAIN |
data_in[4] => mem[46][4].DATAIN |
data_in[4] => mem[47][4].DATAIN |
data_in[4] => mem[48][4].DATAIN |
data_in[4] => mem[49][4].DATAIN |
data_in[4] => mem[50][4].DATAIN |
data_in[4] => mem[51][4].DATAIN |
data_in[4] => mem[52][4].DATAIN |
data_in[4] => mem[53][4].DATAIN |
data_in[4] => mem[54][4].DATAIN |
data_in[4] => mem[55][4].DATAIN |
data_in[4] => mem[56][4].DATAIN |
data_in[4] => mem[57][4].DATAIN |
data_in[4] => mem[58][4].DATAIN |
data_in[4] => mem[59][4].DATAIN |
data_in[4] => mem[60][4].DATAIN |
data_in[4] => mem[61][4].DATAIN |
data_in[4] => mem[62][4].DATAIN |
data_in[4] => mem[63][4].DATAIN |
data_in[5] => mem[0][5].DATAIN |
data_in[5] => mem[1][5].DATAIN |
data_in[5] => mem[2][5].DATAIN |
data_in[5] => mem[3][5].DATAIN |
data_in[5] => mem[4][5].DATAIN |
data_in[5] => mem[5][5].DATAIN |
data_in[5] => mem[6][5].DATAIN |
data_in[5] => mem[7][5].DATAIN |
data_in[5] => mem[8][5].DATAIN |
data_in[5] => mem[9][5].DATAIN |
data_in[5] => mem[10][5].DATAIN |
data_in[5] => mem[11][5].DATAIN |
data_in[5] => mem[12][5].DATAIN |
data_in[5] => mem[13][5].DATAIN |
data_in[5] => mem[14][5].DATAIN |
data_in[5] => mem[15][5].DATAIN |
data_in[5] => mem[16][5].DATAIN |
data_in[5] => mem[17][5].DATAIN |
data_in[5] => mem[18][5].DATAIN |
data_in[5] => mem[19][5].DATAIN |
data_in[5] => mem[20][5].DATAIN |
data_in[5] => mem[21][5].DATAIN |
data_in[5] => mem[22][5].DATAIN |
data_in[5] => mem[23][5].DATAIN |
data_in[5] => mem[24][5].DATAIN |
data_in[5] => mem[25][5].DATAIN |
data_in[5] => mem[26][5].DATAIN |
data_in[5] => mem[27][5].DATAIN |
data_in[5] => mem[28][5].DATAIN |
data_in[5] => mem[29][5].DATAIN |
data_in[5] => mem[30][5].DATAIN |
data_in[5] => mem[31][5].DATAIN |
data_in[5] => mem[32][5].DATAIN |
data_in[5] => mem[33][5].DATAIN |
data_in[5] => mem[34][5].DATAIN |
data_in[5] => mem[35][5].DATAIN |
data_in[5] => mem[36][5].DATAIN |
data_in[5] => mem[37][5].DATAIN |
data_in[5] => mem[38][5].DATAIN |
data_in[5] => mem[39][5].DATAIN |
data_in[5] => mem[40][5].DATAIN |
data_in[5] => mem[41][5].DATAIN |
data_in[5] => mem[42][5].DATAIN |
data_in[5] => mem[43][5].DATAIN |
data_in[5] => mem[44][5].DATAIN |
data_in[5] => mem[45][5].DATAIN |
data_in[5] => mem[46][5].DATAIN |
data_in[5] => mem[47][5].DATAIN |
data_in[5] => mem[48][5].DATAIN |
data_in[5] => mem[49][5].DATAIN |
data_in[5] => mem[50][5].DATAIN |
data_in[5] => mem[51][5].DATAIN |
data_in[5] => mem[52][5].DATAIN |
data_in[5] => mem[53][5].DATAIN |
data_in[5] => mem[54][5].DATAIN |
data_in[5] => mem[55][5].DATAIN |
data_in[5] => mem[56][5].DATAIN |
data_in[5] => mem[57][5].DATAIN |
data_in[5] => mem[58][5].DATAIN |
data_in[5] => mem[59][5].DATAIN |
data_in[5] => mem[60][5].DATAIN |
data_in[5] => mem[61][5].DATAIN |
data_in[5] => mem[62][5].DATAIN |
data_in[5] => mem[63][5].DATAIN |
data_in[6] => mem[0][6].DATAIN |
data_in[6] => mem[1][6].DATAIN |
data_in[6] => mem[2][6].DATAIN |
data_in[6] => mem[3][6].DATAIN |
data_in[6] => mem[4][6].DATAIN |
data_in[6] => mem[5][6].DATAIN |
data_in[6] => mem[6][6].DATAIN |
data_in[6] => mem[7][6].DATAIN |
data_in[6] => mem[8][6].DATAIN |
data_in[6] => mem[9][6].DATAIN |
data_in[6] => mem[10][6].DATAIN |
data_in[6] => mem[11][6].DATAIN |
data_in[6] => mem[12][6].DATAIN |
data_in[6] => mem[13][6].DATAIN |
data_in[6] => mem[14][6].DATAIN |
data_in[6] => mem[15][6].DATAIN |
data_in[6] => mem[16][6].DATAIN |
data_in[6] => mem[17][6].DATAIN |
data_in[6] => mem[18][6].DATAIN |
data_in[6] => mem[19][6].DATAIN |
data_in[6] => mem[20][6].DATAIN |
data_in[6] => mem[21][6].DATAIN |
data_in[6] => mem[22][6].DATAIN |
data_in[6] => mem[23][6].DATAIN |
data_in[6] => mem[24][6].DATAIN |
data_in[6] => mem[25][6].DATAIN |
data_in[6] => mem[26][6].DATAIN |
data_in[6] => mem[27][6].DATAIN |
data_in[6] => mem[28][6].DATAIN |
data_in[6] => mem[29][6].DATAIN |
data_in[6] => mem[30][6].DATAIN |
data_in[6] => mem[31][6].DATAIN |
data_in[6] => mem[32][6].DATAIN |
data_in[6] => mem[33][6].DATAIN |
data_in[6] => mem[34][6].DATAIN |
data_in[6] => mem[35][6].DATAIN |
data_in[6] => mem[36][6].DATAIN |
data_in[6] => mem[37][6].DATAIN |
data_in[6] => mem[38][6].DATAIN |
data_in[6] => mem[39][6].DATAIN |
data_in[6] => mem[40][6].DATAIN |
data_in[6] => mem[41][6].DATAIN |
data_in[6] => mem[42][6].DATAIN |
data_in[6] => mem[43][6].DATAIN |
data_in[6] => mem[44][6].DATAIN |
data_in[6] => mem[45][6].DATAIN |
data_in[6] => mem[46][6].DATAIN |
data_in[6] => mem[47][6].DATAIN |
data_in[6] => mem[48][6].DATAIN |
data_in[6] => mem[49][6].DATAIN |
data_in[6] => mem[50][6].DATAIN |
data_in[6] => mem[51][6].DATAIN |
data_in[6] => mem[52][6].DATAIN |
data_in[6] => mem[53][6].DATAIN |
data_in[6] => mem[54][6].DATAIN |
data_in[6] => mem[55][6].DATAIN |
data_in[6] => mem[56][6].DATAIN |
data_in[6] => mem[57][6].DATAIN |
data_in[6] => mem[58][6].DATAIN |
data_in[6] => mem[59][6].DATAIN |
data_in[6] => mem[60][6].DATAIN |
data_in[6] => mem[61][6].DATAIN |
data_in[6] => mem[62][6].DATAIN |
data_in[6] => mem[63][6].DATAIN |
data_in[7] => mem[0][7].DATAIN |
data_in[7] => mem[1][7].DATAIN |
data_in[7] => mem[2][7].DATAIN |
data_in[7] => mem[3][7].DATAIN |
data_in[7] => mem[4][7].DATAIN |
data_in[7] => mem[5][7].DATAIN |
data_in[7] => mem[6][7].DATAIN |
data_in[7] => mem[7][7].DATAIN |
data_in[7] => mem[8][7].DATAIN |
data_in[7] => mem[9][7].DATAIN |
data_in[7] => mem[10][7].DATAIN |
data_in[7] => mem[11][7].DATAIN |
data_in[7] => mem[12][7].DATAIN |
data_in[7] => mem[13][7].DATAIN |
data_in[7] => mem[14][7].DATAIN |
data_in[7] => mem[15][7].DATAIN |
data_in[7] => mem[16][7].DATAIN |
data_in[7] => mem[17][7].DATAIN |
data_in[7] => mem[18][7].DATAIN |
data_in[7] => mem[19][7].DATAIN |
data_in[7] => mem[20][7].DATAIN |
data_in[7] => mem[21][7].DATAIN |
data_in[7] => mem[22][7].DATAIN |
data_in[7] => mem[23][7].DATAIN |
data_in[7] => mem[24][7].DATAIN |
data_in[7] => mem[25][7].DATAIN |
data_in[7] => mem[26][7].DATAIN |
data_in[7] => mem[27][7].DATAIN |
data_in[7] => mem[28][7].DATAIN |
data_in[7] => mem[29][7].DATAIN |
data_in[7] => mem[30][7].DATAIN |
data_in[7] => mem[31][7].DATAIN |
data_in[7] => mem[32][7].DATAIN |
data_in[7] => mem[33][7].DATAIN |
data_in[7] => mem[34][7].DATAIN |
data_in[7] => mem[35][7].DATAIN |
data_in[7] => mem[36][7].DATAIN |
data_in[7] => mem[37][7].DATAIN |
data_in[7] => mem[38][7].DATAIN |
data_in[7] => mem[39][7].DATAIN |
data_in[7] => mem[40][7].DATAIN |
data_in[7] => mem[41][7].DATAIN |
data_in[7] => mem[42][7].DATAIN |
data_in[7] => mem[43][7].DATAIN |
data_in[7] => mem[44][7].DATAIN |
data_in[7] => mem[45][7].DATAIN |
data_in[7] => mem[46][7].DATAIN |
data_in[7] => mem[47][7].DATAIN |
data_in[7] => mem[48][7].DATAIN |
data_in[7] => mem[49][7].DATAIN |
data_in[7] => mem[50][7].DATAIN |
data_in[7] => mem[51][7].DATAIN |
data_in[7] => mem[52][7].DATAIN |
data_in[7] => mem[53][7].DATAIN |
data_in[7] => mem[54][7].DATAIN |
data_in[7] => mem[55][7].DATAIN |
data_in[7] => mem[56][7].DATAIN |
data_in[7] => mem[57][7].DATAIN |
data_in[7] => mem[58][7].DATAIN |
data_in[7] => mem[59][7].DATAIN |
data_in[7] => mem[60][7].DATAIN |
data_in[7] => mem[61][7].DATAIN |
data_in[7] => mem[62][7].DATAIN |
data_in[7] => mem[63][7].DATAIN |
data_in[8] => mem[0][8].DATAIN |
data_in[8] => mem[1][8].DATAIN |
data_in[8] => mem[2][8].DATAIN |
data_in[8] => mem[3][8].DATAIN |
data_in[8] => mem[4][8].DATAIN |
data_in[8] => mem[5][8].DATAIN |
data_in[8] => mem[6][8].DATAIN |
data_in[8] => mem[7][8].DATAIN |
data_in[8] => mem[8][8].DATAIN |
data_in[8] => mem[9][8].DATAIN |
data_in[8] => mem[10][8].DATAIN |
data_in[8] => mem[11][8].DATAIN |
data_in[8] => mem[12][8].DATAIN |
data_in[8] => mem[13][8].DATAIN |
data_in[8] => mem[14][8].DATAIN |
data_in[8] => mem[15][8].DATAIN |
data_in[8] => mem[16][8].DATAIN |
data_in[8] => mem[17][8].DATAIN |
data_in[8] => mem[18][8].DATAIN |
data_in[8] => mem[19][8].DATAIN |
data_in[8] => mem[20][8].DATAIN |
data_in[8] => mem[21][8].DATAIN |
data_in[8] => mem[22][8].DATAIN |
data_in[8] => mem[23][8].DATAIN |
data_in[8] => mem[24][8].DATAIN |
data_in[8] => mem[25][8].DATAIN |
data_in[8] => mem[26][8].DATAIN |
data_in[8] => mem[27][8].DATAIN |
data_in[8] => mem[28][8].DATAIN |
data_in[8] => mem[29][8].DATAIN |
data_in[8] => mem[30][8].DATAIN |
data_in[8] => mem[31][8].DATAIN |
data_in[8] => mem[32][8].DATAIN |
data_in[8] => mem[33][8].DATAIN |
data_in[8] => mem[34][8].DATAIN |
data_in[8] => mem[35][8].DATAIN |
data_in[8] => mem[36][8].DATAIN |
data_in[8] => mem[37][8].DATAIN |
data_in[8] => mem[38][8].DATAIN |
data_in[8] => mem[39][8].DATAIN |
data_in[8] => mem[40][8].DATAIN |
data_in[8] => mem[41][8].DATAIN |
data_in[8] => mem[42][8].DATAIN |
data_in[8] => mem[43][8].DATAIN |
data_in[8] => mem[44][8].DATAIN |
data_in[8] => mem[45][8].DATAIN |
data_in[8] => mem[46][8].DATAIN |
data_in[8] => mem[47][8].DATAIN |
data_in[8] => mem[48][8].DATAIN |
data_in[8] => mem[49][8].DATAIN |
data_in[8] => mem[50][8].DATAIN |
data_in[8] => mem[51][8].DATAIN |
data_in[8] => mem[52][8].DATAIN |
data_in[8] => mem[53][8].DATAIN |
data_in[8] => mem[54][8].DATAIN |
data_in[8] => mem[55][8].DATAIN |
data_in[8] => mem[56][8].DATAIN |
data_in[8] => mem[57][8].DATAIN |
data_in[8] => mem[58][8].DATAIN |
data_in[8] => mem[59][8].DATAIN |
data_in[8] => mem[60][8].DATAIN |
data_in[8] => mem[61][8].DATAIN |
data_in[8] => mem[62][8].DATAIN |
data_in[8] => mem[63][8].DATAIN |
wr_ptr[0] => Decoder0.IN5 |
wr_ptr[1] => Decoder0.IN4 |
wr_ptr[2] => Decoder0.IN3 |
wr_ptr[3] => Decoder0.IN2 |
wr_ptr[4] => Decoder0.IN1 |
wr_ptr[5] => Decoder0.IN0 |
rd_ptr[0] => Mux0.IN5 |
rd_ptr[0] => Mux1.IN5 |
rd_ptr[0] => Mux2.IN5 |
rd_ptr[0] => Mux3.IN5 |
rd_ptr[0] => Mux4.IN5 |
rd_ptr[0] => Mux5.IN5 |
rd_ptr[0] => Mux6.IN5 |
rd_ptr[0] => Mux7.IN5 |
rd_ptr[0] => Mux8.IN5 |
rd_ptr[1] => Mux0.IN4 |
rd_ptr[1] => Mux1.IN4 |
rd_ptr[1] => Mux2.IN4 |
rd_ptr[1] => Mux3.IN4 |
rd_ptr[1] => Mux4.IN4 |
rd_ptr[1] => Mux5.IN4 |
rd_ptr[1] => Mux6.IN4 |
rd_ptr[1] => Mux7.IN4 |
rd_ptr[1] => Mux8.IN4 |
rd_ptr[2] => Mux0.IN3 |
rd_ptr[2] => Mux1.IN3 |
rd_ptr[2] => Mux2.IN3 |
rd_ptr[2] => Mux3.IN3 |
rd_ptr[2] => Mux4.IN3 |
rd_ptr[2] => Mux5.IN3 |
rd_ptr[2] => Mux6.IN3 |
rd_ptr[2] => Mux7.IN3 |
rd_ptr[2] => Mux8.IN3 |
rd_ptr[3] => Mux0.IN2 |
rd_ptr[3] => Mux1.IN2 |
rd_ptr[3] => Mux2.IN2 |
rd_ptr[3] => Mux3.IN2 |
rd_ptr[3] => Mux4.IN2 |
rd_ptr[3] => Mux5.IN2 |
rd_ptr[3] => Mux6.IN2 |
rd_ptr[3] => Mux7.IN2 |
rd_ptr[3] => Mux8.IN2 |
rd_ptr[4] => Mux0.IN1 |
rd_ptr[4] => Mux1.IN1 |
rd_ptr[4] => Mux2.IN1 |
rd_ptr[4] => Mux3.IN1 |
rd_ptr[4] => Mux4.IN1 |
rd_ptr[4] => Mux5.IN1 |
rd_ptr[4] => Mux6.IN1 |
rd_ptr[4] => Mux7.IN1 |
rd_ptr[4] => Mux8.IN1 |
rd_ptr[5] => Mux0.IN0 |
rd_ptr[5] => Mux1.IN0 |
rd_ptr[5] => Mux2.IN0 |
rd_ptr[5] => Mux3.IN0 |
rd_ptr[5] => Mux4.IN0 |
rd_ptr[5] => Mux5.IN0 |
rd_ptr[5] => Mux6.IN0 |
rd_ptr[5] => Mux7.IN0 |
rd_ptr[5] => Mux8.IN0 |
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
169155,6 → 169682,39
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data |
clock => clock.IN1 |
reset => reset.IN1 |
wr_en => always0.IN1 |
wr_en => Selector1.IN2 |
wr_en => next_state_data_write.10.DATAB |
rd_en => always4.IN1 |
rd_en => Selector4.IN3 |
rd_en => always3.IN0 |
rd_en => next_state_data_read.11.DATAB |
data_in[0] => data_in[0].IN1 |
data_in[1] => data_in[1].IN1 |
data_in[2] => data_in[2].IN1 |
data_in[3] => data_in[3].IN1 |
data_in[4] => data_in[4].IN1 |
data_in[5] => data_in[5].IN1 |
data_in[6] => data_in[6].IN1 |
data_in[7] => data_in[7].IN1 |
data_in[8] => data_in[8].IN1 |
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE |
write_tx <= write_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE |
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[0] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[1] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[2] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[3] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[4] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[5] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[6] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[7] <= mem_data:mem_dta_fifo_tx.data_out |
data_out[8] <= mem_data:mem_dta_fifo_tx.data_out |
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
169163,9 → 169723,7
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data |
clock => block_read.CLK |
clock => write_tx~reg0.CLK |
|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx |
clock => data_out[0]~reg0.CLK |
clock => data_out[1]~reg0.CLK |
clock => data_out[2]~reg0.CLK |
169175,27 → 169733,6
clock => data_out[6]~reg0.CLK |
clock => data_out[7]~reg0.CLK |
clock => data_out[8]~reg0.CLK |
clock => rd_ptr[0].CLK |
clock => rd_ptr[1].CLK |
clock => rd_ptr[2].CLK |
clock => rd_ptr[3].CLK |
clock => rd_ptr[4].CLK |
clock => rd_ptr[5].CLK |
clock => counter[0]~reg0.CLK |
clock => counter[1]~reg0.CLK |
clock => counter[2]~reg0.CLK |
clock => counter[3]~reg0.CLK |
clock => counter[4]~reg0.CLK |
clock => counter[5]~reg0.CLK |
clock => f_empty~reg0.CLK |
clock => f_full~reg0.CLK |
clock => block_write.CLK |
clock => wr_ptr[0].CLK |
clock => wr_ptr[1].CLK |
clock => wr_ptr[2].CLK |
clock => wr_ptr[3].CLK |
clock => wr_ptr[4].CLK |
clock => wr_ptr[5].CLK |
clock => mem[63][0].CLK |
clock => mem[63][1].CLK |
clock => mem[63][2].CLK |
169772,13 → 170309,6
clock => mem[0][6].CLK |
clock => mem[0][7].CLK |
clock => mem[0][8].CLK |
reset => block_write.ACLR |
reset => wr_ptr[0].ACLR |
reset => wr_ptr[1].ACLR |
reset => wr_ptr[2].ACLR |
reset => wr_ptr[3].ACLR |
reset => wr_ptr[4].ACLR |
reset => wr_ptr[5].ACLR |
reset => mem[63][0].ACLR |
reset => mem[63][1].ACLR |
reset => mem[63][2].ACLR |
170355,8 → 170885,6
reset => mem[0][6].ACLR |
reset => mem[0][7].ACLR |
reset => mem[0][8].ACLR |
reset => block_read.ACLR |
reset => write_tx~reg0.ACLR |
reset => data_out[0]~reg0.ACLR |
reset => data_out[1]~reg0.ACLR |
reset => data_out[2]~reg0.ACLR |
170366,610 → 170894,642
reset => data_out[6]~reg0.ACLR |
reset => data_out[7]~reg0.ACLR |
reset => data_out[8]~reg0.ACLR |
reset => rd_ptr[0].ACLR |
reset => rd_ptr[1].ACLR |
reset => rd_ptr[2].ACLR |
reset => rd_ptr[3].ACLR |
reset => rd_ptr[4].ACLR |
reset => rd_ptr[5].ACLR |
reset => counter[0]~reg0.ACLR |
reset => counter[1]~reg0.ACLR |
reset => counter[2]~reg0.ACLR |
reset => counter[3]~reg0.ACLR |
reset => counter[4]~reg0.ACLR |
reset => counter[5]~reg0.ACLR |
reset => f_empty~reg0.PRESET |
reset => f_full~reg0.ACLR |
wr_en => always1.IN1 |
wr_en => block_write.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
wr_en => wr_ptr.OUTPUTSELECT |
rd_en => always1.IN1 |
rd_en => write_tx.OUTPUTSELECT |
rd_en => block_read.OUTPUTSELECT |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[0] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[1] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[2] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[3] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[4] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[5] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[6] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[7] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
data_in[8] => mem.DATAB |
f_full <= f_full~reg0.DB_MAX_OUTPUT_PORT_TYPE |
write_tx <= write_tx~reg0.DB_MAX_OUTPUT_PORT_TYPE |
f_empty <= f_empty~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_in[0] => mem[0][0].DATAIN |
data_in[0] => mem[1][0].DATAIN |
data_in[0] => mem[2][0].DATAIN |
data_in[0] => mem[3][0].DATAIN |
data_in[0] => mem[4][0].DATAIN |
data_in[0] => mem[5][0].DATAIN |
data_in[0] => mem[6][0].DATAIN |
data_in[0] => mem[7][0].DATAIN |
data_in[0] => mem[8][0].DATAIN |
data_in[0] => mem[9][0].DATAIN |
data_in[0] => mem[10][0].DATAIN |
data_in[0] => mem[11][0].DATAIN |
data_in[0] => mem[12][0].DATAIN |
data_in[0] => mem[13][0].DATAIN |
data_in[0] => mem[14][0].DATAIN |
data_in[0] => mem[15][0].DATAIN |
data_in[0] => mem[16][0].DATAIN |
data_in[0] => mem[17][0].DATAIN |
data_in[0] => mem[18][0].DATAIN |
data_in[0] => mem[19][0].DATAIN |
data_in[0] => mem[20][0].DATAIN |
data_in[0] => mem[21][0].DATAIN |
data_in[0] => mem[22][0].DATAIN |
data_in[0] => mem[23][0].DATAIN |
data_in[0] => mem[24][0].DATAIN |
data_in[0] => mem[25][0].DATAIN |
data_in[0] => mem[26][0].DATAIN |
data_in[0] => mem[27][0].DATAIN |
data_in[0] => mem[28][0].DATAIN |
data_in[0] => mem[29][0].DATAIN |
data_in[0] => mem[30][0].DATAIN |
data_in[0] => mem[31][0].DATAIN |
data_in[0] => mem[32][0].DATAIN |
data_in[0] => mem[33][0].DATAIN |
data_in[0] => mem[34][0].DATAIN |
data_in[0] => mem[35][0].DATAIN |
data_in[0] => mem[36][0].DATAIN |
data_in[0] => mem[37][0].DATAIN |
data_in[0] => mem[38][0].DATAIN |
data_in[0] => mem[39][0].DATAIN |
data_in[0] => mem[40][0].DATAIN |
data_in[0] => mem[41][0].DATAIN |
data_in[0] => mem[42][0].DATAIN |
data_in[0] => mem[43][0].DATAIN |
data_in[0] => mem[44][0].DATAIN |
data_in[0] => mem[45][0].DATAIN |
data_in[0] => mem[46][0].DATAIN |
data_in[0] => mem[47][0].DATAIN |
data_in[0] => mem[48][0].DATAIN |
data_in[0] => mem[49][0].DATAIN |
data_in[0] => mem[50][0].DATAIN |
data_in[0] => mem[51][0].DATAIN |
data_in[0] => mem[52][0].DATAIN |
data_in[0] => mem[53][0].DATAIN |
data_in[0] => mem[54][0].DATAIN |
data_in[0] => mem[55][0].DATAIN |
data_in[0] => mem[56][0].DATAIN |
data_in[0] => mem[57][0].DATAIN |
data_in[0] => mem[58][0].DATAIN |
data_in[0] => mem[59][0].DATAIN |
data_in[0] => mem[60][0].DATAIN |
data_in[0] => mem[61][0].DATAIN |
data_in[0] => mem[62][0].DATAIN |
data_in[0] => mem[63][0].DATAIN |
data_in[1] => mem[0][1].DATAIN |
data_in[1] => mem[1][1].DATAIN |
data_in[1] => mem[2][1].DATAIN |
data_in[1] => mem[3][1].DATAIN |
data_in[1] => mem[4][1].DATAIN |
data_in[1] => mem[5][1].DATAIN |
data_in[1] => mem[6][1].DATAIN |
data_in[1] => mem[7][1].DATAIN |
data_in[1] => mem[8][1].DATAIN |
data_in[1] => mem[9][1].DATAIN |
data_in[1] => mem[10][1].DATAIN |
data_in[1] => mem[11][1].DATAIN |
data_in[1] => mem[12][1].DATAIN |
data_in[1] => mem[13][1].DATAIN |
data_in[1] => mem[14][1].DATAIN |
data_in[1] => mem[15][1].DATAIN |
data_in[1] => mem[16][1].DATAIN |
data_in[1] => mem[17][1].DATAIN |
data_in[1] => mem[18][1].DATAIN |
data_in[1] => mem[19][1].DATAIN |
data_in[1] => mem[20][1].DATAIN |
data_in[1] => mem[21][1].DATAIN |
data_in[1] => mem[22][1].DATAIN |
data_in[1] => mem[23][1].DATAIN |
data_in[1] => mem[24][1].DATAIN |
data_in[1] => mem[25][1].DATAIN |
data_in[1] => mem[26][1].DATAIN |
data_in[1] => mem[27][1].DATAIN |
data_in[1] => mem[28][1].DATAIN |
data_in[1] => mem[29][1].DATAIN |
data_in[1] => mem[30][1].DATAIN |
data_in[1] => mem[31][1].DATAIN |
data_in[1] => mem[32][1].DATAIN |
data_in[1] => mem[33][1].DATAIN |
data_in[1] => mem[34][1].DATAIN |
data_in[1] => mem[35][1].DATAIN |
data_in[1] => mem[36][1].DATAIN |
data_in[1] => mem[37][1].DATAIN |
data_in[1] => mem[38][1].DATAIN |
data_in[1] => mem[39][1].DATAIN |
data_in[1] => mem[40][1].DATAIN |
data_in[1] => mem[41][1].DATAIN |
data_in[1] => mem[42][1].DATAIN |
data_in[1] => mem[43][1].DATAIN |
data_in[1] => mem[44][1].DATAIN |
data_in[1] => mem[45][1].DATAIN |
data_in[1] => mem[46][1].DATAIN |
data_in[1] => mem[47][1].DATAIN |
data_in[1] => mem[48][1].DATAIN |
data_in[1] => mem[49][1].DATAIN |
data_in[1] => mem[50][1].DATAIN |
data_in[1] => mem[51][1].DATAIN |
data_in[1] => mem[52][1].DATAIN |
data_in[1] => mem[53][1].DATAIN |
data_in[1] => mem[54][1].DATAIN |
data_in[1] => mem[55][1].DATAIN |
data_in[1] => mem[56][1].DATAIN |
data_in[1] => mem[57][1].DATAIN |
data_in[1] => mem[58][1].DATAIN |
data_in[1] => mem[59][1].DATAIN |
data_in[1] => mem[60][1].DATAIN |
data_in[1] => mem[61][1].DATAIN |
data_in[1] => mem[62][1].DATAIN |
data_in[1] => mem[63][1].DATAIN |
data_in[2] => mem[0][2].DATAIN |
data_in[2] => mem[1][2].DATAIN |
data_in[2] => mem[2][2].DATAIN |
data_in[2] => mem[3][2].DATAIN |
data_in[2] => mem[4][2].DATAIN |
data_in[2] => mem[5][2].DATAIN |
data_in[2] => mem[6][2].DATAIN |
data_in[2] => mem[7][2].DATAIN |
data_in[2] => mem[8][2].DATAIN |
data_in[2] => mem[9][2].DATAIN |
data_in[2] => mem[10][2].DATAIN |
data_in[2] => mem[11][2].DATAIN |
data_in[2] => mem[12][2].DATAIN |
data_in[2] => mem[13][2].DATAIN |
data_in[2] => mem[14][2].DATAIN |
data_in[2] => mem[15][2].DATAIN |
data_in[2] => mem[16][2].DATAIN |
data_in[2] => mem[17][2].DATAIN |
data_in[2] => mem[18][2].DATAIN |
data_in[2] => mem[19][2].DATAIN |
data_in[2] => mem[20][2].DATAIN |
data_in[2] => mem[21][2].DATAIN |
data_in[2] => mem[22][2].DATAIN |
data_in[2] => mem[23][2].DATAIN |
data_in[2] => mem[24][2].DATAIN |
data_in[2] => mem[25][2].DATAIN |
data_in[2] => mem[26][2].DATAIN |
data_in[2] => mem[27][2].DATAIN |
data_in[2] => mem[28][2].DATAIN |
data_in[2] => mem[29][2].DATAIN |
data_in[2] => mem[30][2].DATAIN |
data_in[2] => mem[31][2].DATAIN |
data_in[2] => mem[32][2].DATAIN |
data_in[2] => mem[33][2].DATAIN |
data_in[2] => mem[34][2].DATAIN |
data_in[2] => mem[35][2].DATAIN |
data_in[2] => mem[36][2].DATAIN |
data_in[2] => mem[37][2].DATAIN |
data_in[2] => mem[38][2].DATAIN |
data_in[2] => mem[39][2].DATAIN |
data_in[2] => mem[40][2].DATAIN |
data_in[2] => mem[41][2].DATAIN |
data_in[2] => mem[42][2].DATAIN |
data_in[2] => mem[43][2].DATAIN |
data_in[2] => mem[44][2].DATAIN |
data_in[2] => mem[45][2].DATAIN |
data_in[2] => mem[46][2].DATAIN |
data_in[2] => mem[47][2].DATAIN |
data_in[2] => mem[48][2].DATAIN |
data_in[2] => mem[49][2].DATAIN |
data_in[2] => mem[50][2].DATAIN |
data_in[2] => mem[51][2].DATAIN |
data_in[2] => mem[52][2].DATAIN |
data_in[2] => mem[53][2].DATAIN |
data_in[2] => mem[54][2].DATAIN |
data_in[2] => mem[55][2].DATAIN |
data_in[2] => mem[56][2].DATAIN |
data_in[2] => mem[57][2].DATAIN |
data_in[2] => mem[58][2].DATAIN |
data_in[2] => mem[59][2].DATAIN |
data_in[2] => mem[60][2].DATAIN |
data_in[2] => mem[61][2].DATAIN |
data_in[2] => mem[62][2].DATAIN |
data_in[2] => mem[63][2].DATAIN |
data_in[3] => mem[0][3].DATAIN |
data_in[3] => mem[1][3].DATAIN |
data_in[3] => mem[2][3].DATAIN |
data_in[3] => mem[3][3].DATAIN |
data_in[3] => mem[4][3].DATAIN |
data_in[3] => mem[5][3].DATAIN |
data_in[3] => mem[6][3].DATAIN |
data_in[3] => mem[7][3].DATAIN |
data_in[3] => mem[8][3].DATAIN |
data_in[3] => mem[9][3].DATAIN |
data_in[3] => mem[10][3].DATAIN |
data_in[3] => mem[11][3].DATAIN |
data_in[3] => mem[12][3].DATAIN |
data_in[3] => mem[13][3].DATAIN |
data_in[3] => mem[14][3].DATAIN |
data_in[3] => mem[15][3].DATAIN |
data_in[3] => mem[16][3].DATAIN |
data_in[3] => mem[17][3].DATAIN |
data_in[3] => mem[18][3].DATAIN |
data_in[3] => mem[19][3].DATAIN |
data_in[3] => mem[20][3].DATAIN |
data_in[3] => mem[21][3].DATAIN |
data_in[3] => mem[22][3].DATAIN |
data_in[3] => mem[23][3].DATAIN |
data_in[3] => mem[24][3].DATAIN |
data_in[3] => mem[25][3].DATAIN |
data_in[3] => mem[26][3].DATAIN |
data_in[3] => mem[27][3].DATAIN |
data_in[3] => mem[28][3].DATAIN |
data_in[3] => mem[29][3].DATAIN |
data_in[3] => mem[30][3].DATAIN |
data_in[3] => mem[31][3].DATAIN |
data_in[3] => mem[32][3].DATAIN |
data_in[3] => mem[33][3].DATAIN |
data_in[3] => mem[34][3].DATAIN |
data_in[3] => mem[35][3].DATAIN |
data_in[3] => mem[36][3].DATAIN |
data_in[3] => mem[37][3].DATAIN |
data_in[3] => mem[38][3].DATAIN |
data_in[3] => mem[39][3].DATAIN |
data_in[3] => mem[40][3].DATAIN |
data_in[3] => mem[41][3].DATAIN |
data_in[3] => mem[42][3].DATAIN |
data_in[3] => mem[43][3].DATAIN |
data_in[3] => mem[44][3].DATAIN |
data_in[3] => mem[45][3].DATAIN |
data_in[3] => mem[46][3].DATAIN |
data_in[3] => mem[47][3].DATAIN |
data_in[3] => mem[48][3].DATAIN |
data_in[3] => mem[49][3].DATAIN |
data_in[3] => mem[50][3].DATAIN |
data_in[3] => mem[51][3].DATAIN |
data_in[3] => mem[52][3].DATAIN |
data_in[3] => mem[53][3].DATAIN |
data_in[3] => mem[54][3].DATAIN |
data_in[3] => mem[55][3].DATAIN |
data_in[3] => mem[56][3].DATAIN |
data_in[3] => mem[57][3].DATAIN |
data_in[3] => mem[58][3].DATAIN |
data_in[3] => mem[59][3].DATAIN |
data_in[3] => mem[60][3].DATAIN |
data_in[3] => mem[61][3].DATAIN |
data_in[3] => mem[62][3].DATAIN |
data_in[3] => mem[63][3].DATAIN |
data_in[4] => mem[0][4].DATAIN |
data_in[4] => mem[1][4].DATAIN |
data_in[4] => mem[2][4].DATAIN |
data_in[4] => mem[3][4].DATAIN |
data_in[4] => mem[4][4].DATAIN |
data_in[4] => mem[5][4].DATAIN |
data_in[4] => mem[6][4].DATAIN |
data_in[4] => mem[7][4].DATAIN |
data_in[4] => mem[8][4].DATAIN |
data_in[4] => mem[9][4].DATAIN |
data_in[4] => mem[10][4].DATAIN |
data_in[4] => mem[11][4].DATAIN |
data_in[4] => mem[12][4].DATAIN |
data_in[4] => mem[13][4].DATAIN |
data_in[4] => mem[14][4].DATAIN |
data_in[4] => mem[15][4].DATAIN |
data_in[4] => mem[16][4].DATAIN |
data_in[4] => mem[17][4].DATAIN |
data_in[4] => mem[18][4].DATAIN |
data_in[4] => mem[19][4].DATAIN |
data_in[4] => mem[20][4].DATAIN |
data_in[4] => mem[21][4].DATAIN |
data_in[4] => mem[22][4].DATAIN |
data_in[4] => mem[23][4].DATAIN |
data_in[4] => mem[24][4].DATAIN |
data_in[4] => mem[25][4].DATAIN |
data_in[4] => mem[26][4].DATAIN |
data_in[4] => mem[27][4].DATAIN |
data_in[4] => mem[28][4].DATAIN |
data_in[4] => mem[29][4].DATAIN |
data_in[4] => mem[30][4].DATAIN |
data_in[4] => mem[31][4].DATAIN |
data_in[4] => mem[32][4].DATAIN |
data_in[4] => mem[33][4].DATAIN |
data_in[4] => mem[34][4].DATAIN |
data_in[4] => mem[35][4].DATAIN |
data_in[4] => mem[36][4].DATAIN |
data_in[4] => mem[37][4].DATAIN |
data_in[4] => mem[38][4].DATAIN |
data_in[4] => mem[39][4].DATAIN |
data_in[4] => mem[40][4].DATAIN |
data_in[4] => mem[41][4].DATAIN |
data_in[4] => mem[42][4].DATAIN |
data_in[4] => mem[43][4].DATAIN |
data_in[4] => mem[44][4].DATAIN |
data_in[4] => mem[45][4].DATAIN |
data_in[4] => mem[46][4].DATAIN |
data_in[4] => mem[47][4].DATAIN |
data_in[4] => mem[48][4].DATAIN |
data_in[4] => mem[49][4].DATAIN |
data_in[4] => mem[50][4].DATAIN |
data_in[4] => mem[51][4].DATAIN |
data_in[4] => mem[52][4].DATAIN |
data_in[4] => mem[53][4].DATAIN |
data_in[4] => mem[54][4].DATAIN |
data_in[4] => mem[55][4].DATAIN |
data_in[4] => mem[56][4].DATAIN |
data_in[4] => mem[57][4].DATAIN |
data_in[4] => mem[58][4].DATAIN |
data_in[4] => mem[59][4].DATAIN |
data_in[4] => mem[60][4].DATAIN |
data_in[4] => mem[61][4].DATAIN |
data_in[4] => mem[62][4].DATAIN |
data_in[4] => mem[63][4].DATAIN |
data_in[5] => mem[0][5].DATAIN |
data_in[5] => mem[1][5].DATAIN |
data_in[5] => mem[2][5].DATAIN |
data_in[5] => mem[3][5].DATAIN |
data_in[5] => mem[4][5].DATAIN |
data_in[5] => mem[5][5].DATAIN |
data_in[5] => mem[6][5].DATAIN |
data_in[5] => mem[7][5].DATAIN |
data_in[5] => mem[8][5].DATAIN |
data_in[5] => mem[9][5].DATAIN |
data_in[5] => mem[10][5].DATAIN |
data_in[5] => mem[11][5].DATAIN |
data_in[5] => mem[12][5].DATAIN |
data_in[5] => mem[13][5].DATAIN |
data_in[5] => mem[14][5].DATAIN |
data_in[5] => mem[15][5].DATAIN |
data_in[5] => mem[16][5].DATAIN |
data_in[5] => mem[17][5].DATAIN |
data_in[5] => mem[18][5].DATAIN |
data_in[5] => mem[19][5].DATAIN |
data_in[5] => mem[20][5].DATAIN |
data_in[5] => mem[21][5].DATAIN |
data_in[5] => mem[22][5].DATAIN |
data_in[5] => mem[23][5].DATAIN |
data_in[5] => mem[24][5].DATAIN |
data_in[5] => mem[25][5].DATAIN |
data_in[5] => mem[26][5].DATAIN |
data_in[5] => mem[27][5].DATAIN |
data_in[5] => mem[28][5].DATAIN |
data_in[5] => mem[29][5].DATAIN |
data_in[5] => mem[30][5].DATAIN |
data_in[5] => mem[31][5].DATAIN |
data_in[5] => mem[32][5].DATAIN |
data_in[5] => mem[33][5].DATAIN |
data_in[5] => mem[34][5].DATAIN |
data_in[5] => mem[35][5].DATAIN |
data_in[5] => mem[36][5].DATAIN |
data_in[5] => mem[37][5].DATAIN |
data_in[5] => mem[38][5].DATAIN |
data_in[5] => mem[39][5].DATAIN |
data_in[5] => mem[40][5].DATAIN |
data_in[5] => mem[41][5].DATAIN |
data_in[5] => mem[42][5].DATAIN |
data_in[5] => mem[43][5].DATAIN |
data_in[5] => mem[44][5].DATAIN |
data_in[5] => mem[45][5].DATAIN |
data_in[5] => mem[46][5].DATAIN |
data_in[5] => mem[47][5].DATAIN |
data_in[5] => mem[48][5].DATAIN |
data_in[5] => mem[49][5].DATAIN |
data_in[5] => mem[50][5].DATAIN |
data_in[5] => mem[51][5].DATAIN |
data_in[5] => mem[52][5].DATAIN |
data_in[5] => mem[53][5].DATAIN |
data_in[5] => mem[54][5].DATAIN |
data_in[5] => mem[55][5].DATAIN |
data_in[5] => mem[56][5].DATAIN |
data_in[5] => mem[57][5].DATAIN |
data_in[5] => mem[58][5].DATAIN |
data_in[5] => mem[59][5].DATAIN |
data_in[5] => mem[60][5].DATAIN |
data_in[5] => mem[61][5].DATAIN |
data_in[5] => mem[62][5].DATAIN |
data_in[5] => mem[63][5].DATAIN |
data_in[6] => mem[0][6].DATAIN |
data_in[6] => mem[1][6].DATAIN |
data_in[6] => mem[2][6].DATAIN |
data_in[6] => mem[3][6].DATAIN |
data_in[6] => mem[4][6].DATAIN |
data_in[6] => mem[5][6].DATAIN |
data_in[6] => mem[6][6].DATAIN |
data_in[6] => mem[7][6].DATAIN |
data_in[6] => mem[8][6].DATAIN |
data_in[6] => mem[9][6].DATAIN |
data_in[6] => mem[10][6].DATAIN |
data_in[6] => mem[11][6].DATAIN |
data_in[6] => mem[12][6].DATAIN |
data_in[6] => mem[13][6].DATAIN |
data_in[6] => mem[14][6].DATAIN |
data_in[6] => mem[15][6].DATAIN |
data_in[6] => mem[16][6].DATAIN |
data_in[6] => mem[17][6].DATAIN |
data_in[6] => mem[18][6].DATAIN |
data_in[6] => mem[19][6].DATAIN |
data_in[6] => mem[20][6].DATAIN |
data_in[6] => mem[21][6].DATAIN |
data_in[6] => mem[22][6].DATAIN |
data_in[6] => mem[23][6].DATAIN |
data_in[6] => mem[24][6].DATAIN |
data_in[6] => mem[25][6].DATAIN |
data_in[6] => mem[26][6].DATAIN |
data_in[6] => mem[27][6].DATAIN |
data_in[6] => mem[28][6].DATAIN |
data_in[6] => mem[29][6].DATAIN |
data_in[6] => mem[30][6].DATAIN |
data_in[6] => mem[31][6].DATAIN |
data_in[6] => mem[32][6].DATAIN |
data_in[6] => mem[33][6].DATAIN |
data_in[6] => mem[34][6].DATAIN |
data_in[6] => mem[35][6].DATAIN |
data_in[6] => mem[36][6].DATAIN |
data_in[6] => mem[37][6].DATAIN |
data_in[6] => mem[38][6].DATAIN |
data_in[6] => mem[39][6].DATAIN |
data_in[6] => mem[40][6].DATAIN |
data_in[6] => mem[41][6].DATAIN |
data_in[6] => mem[42][6].DATAIN |
data_in[6] => mem[43][6].DATAIN |
data_in[6] => mem[44][6].DATAIN |
data_in[6] => mem[45][6].DATAIN |
data_in[6] => mem[46][6].DATAIN |
data_in[6] => mem[47][6].DATAIN |
data_in[6] => mem[48][6].DATAIN |
data_in[6] => mem[49][6].DATAIN |
data_in[6] => mem[50][6].DATAIN |
data_in[6] => mem[51][6].DATAIN |
data_in[6] => mem[52][6].DATAIN |
data_in[6] => mem[53][6].DATAIN |
data_in[6] => mem[54][6].DATAIN |
data_in[6] => mem[55][6].DATAIN |
data_in[6] => mem[56][6].DATAIN |
data_in[6] => mem[57][6].DATAIN |
data_in[6] => mem[58][6].DATAIN |
data_in[6] => mem[59][6].DATAIN |
data_in[6] => mem[60][6].DATAIN |
data_in[6] => mem[61][6].DATAIN |
data_in[6] => mem[62][6].DATAIN |
data_in[6] => mem[63][6].DATAIN |
data_in[7] => mem[0][7].DATAIN |
data_in[7] => mem[1][7].DATAIN |
data_in[7] => mem[2][7].DATAIN |
data_in[7] => mem[3][7].DATAIN |
data_in[7] => mem[4][7].DATAIN |
data_in[7] => mem[5][7].DATAIN |
data_in[7] => mem[6][7].DATAIN |
data_in[7] => mem[7][7].DATAIN |
data_in[7] => mem[8][7].DATAIN |
data_in[7] => mem[9][7].DATAIN |
data_in[7] => mem[10][7].DATAIN |
data_in[7] => mem[11][7].DATAIN |
data_in[7] => mem[12][7].DATAIN |
data_in[7] => mem[13][7].DATAIN |
data_in[7] => mem[14][7].DATAIN |
data_in[7] => mem[15][7].DATAIN |
data_in[7] => mem[16][7].DATAIN |
data_in[7] => mem[17][7].DATAIN |
data_in[7] => mem[18][7].DATAIN |
data_in[7] => mem[19][7].DATAIN |
data_in[7] => mem[20][7].DATAIN |
data_in[7] => mem[21][7].DATAIN |
data_in[7] => mem[22][7].DATAIN |
data_in[7] => mem[23][7].DATAIN |
data_in[7] => mem[24][7].DATAIN |
data_in[7] => mem[25][7].DATAIN |
data_in[7] => mem[26][7].DATAIN |
data_in[7] => mem[27][7].DATAIN |
data_in[7] => mem[28][7].DATAIN |
data_in[7] => mem[29][7].DATAIN |
data_in[7] => mem[30][7].DATAIN |
data_in[7] => mem[31][7].DATAIN |
data_in[7] => mem[32][7].DATAIN |
data_in[7] => mem[33][7].DATAIN |
data_in[7] => mem[34][7].DATAIN |
data_in[7] => mem[35][7].DATAIN |
data_in[7] => mem[36][7].DATAIN |
data_in[7] => mem[37][7].DATAIN |
data_in[7] => mem[38][7].DATAIN |
data_in[7] => mem[39][7].DATAIN |
data_in[7] => mem[40][7].DATAIN |
data_in[7] => mem[41][7].DATAIN |
data_in[7] => mem[42][7].DATAIN |
data_in[7] => mem[43][7].DATAIN |
data_in[7] => mem[44][7].DATAIN |
data_in[7] => mem[45][7].DATAIN |
data_in[7] => mem[46][7].DATAIN |
data_in[7] => mem[47][7].DATAIN |
data_in[7] => mem[48][7].DATAIN |
data_in[7] => mem[49][7].DATAIN |
data_in[7] => mem[50][7].DATAIN |
data_in[7] => mem[51][7].DATAIN |
data_in[7] => mem[52][7].DATAIN |
data_in[7] => mem[53][7].DATAIN |
data_in[7] => mem[54][7].DATAIN |
data_in[7] => mem[55][7].DATAIN |
data_in[7] => mem[56][7].DATAIN |
data_in[7] => mem[57][7].DATAIN |
data_in[7] => mem[58][7].DATAIN |
data_in[7] => mem[59][7].DATAIN |
data_in[7] => mem[60][7].DATAIN |
data_in[7] => mem[61][7].DATAIN |
data_in[7] => mem[62][7].DATAIN |
data_in[7] => mem[63][7].DATAIN |
data_in[8] => mem[0][8].DATAIN |
data_in[8] => mem[1][8].DATAIN |
data_in[8] => mem[2][8].DATAIN |
data_in[8] => mem[3][8].DATAIN |
data_in[8] => mem[4][8].DATAIN |
data_in[8] => mem[5][8].DATAIN |
data_in[8] => mem[6][8].DATAIN |
data_in[8] => mem[7][8].DATAIN |
data_in[8] => mem[8][8].DATAIN |
data_in[8] => mem[9][8].DATAIN |
data_in[8] => mem[10][8].DATAIN |
data_in[8] => mem[11][8].DATAIN |
data_in[8] => mem[12][8].DATAIN |
data_in[8] => mem[13][8].DATAIN |
data_in[8] => mem[14][8].DATAIN |
data_in[8] => mem[15][8].DATAIN |
data_in[8] => mem[16][8].DATAIN |
data_in[8] => mem[17][8].DATAIN |
data_in[8] => mem[18][8].DATAIN |
data_in[8] => mem[19][8].DATAIN |
data_in[8] => mem[20][8].DATAIN |
data_in[8] => mem[21][8].DATAIN |
data_in[8] => mem[22][8].DATAIN |
data_in[8] => mem[23][8].DATAIN |
data_in[8] => mem[24][8].DATAIN |
data_in[8] => mem[25][8].DATAIN |
data_in[8] => mem[26][8].DATAIN |
data_in[8] => mem[27][8].DATAIN |
data_in[8] => mem[28][8].DATAIN |
data_in[8] => mem[29][8].DATAIN |
data_in[8] => mem[30][8].DATAIN |
data_in[8] => mem[31][8].DATAIN |
data_in[8] => mem[32][8].DATAIN |
data_in[8] => mem[33][8].DATAIN |
data_in[8] => mem[34][8].DATAIN |
data_in[8] => mem[35][8].DATAIN |
data_in[8] => mem[36][8].DATAIN |
data_in[8] => mem[37][8].DATAIN |
data_in[8] => mem[38][8].DATAIN |
data_in[8] => mem[39][8].DATAIN |
data_in[8] => mem[40][8].DATAIN |
data_in[8] => mem[41][8].DATAIN |
data_in[8] => mem[42][8].DATAIN |
data_in[8] => mem[43][8].DATAIN |
data_in[8] => mem[44][8].DATAIN |
data_in[8] => mem[45][8].DATAIN |
data_in[8] => mem[46][8].DATAIN |
data_in[8] => mem[47][8].DATAIN |
data_in[8] => mem[48][8].DATAIN |
data_in[8] => mem[49][8].DATAIN |
data_in[8] => mem[50][8].DATAIN |
data_in[8] => mem[51][8].DATAIN |
data_in[8] => mem[52][8].DATAIN |
data_in[8] => mem[53][8].DATAIN |
data_in[8] => mem[54][8].DATAIN |
data_in[8] => mem[55][8].DATAIN |
data_in[8] => mem[56][8].DATAIN |
data_in[8] => mem[57][8].DATAIN |
data_in[8] => mem[58][8].DATAIN |
data_in[8] => mem[59][8].DATAIN |
data_in[8] => mem[60][8].DATAIN |
data_in[8] => mem[61][8].DATAIN |
data_in[8] => mem[62][8].DATAIN |
data_in[8] => mem[63][8].DATAIN |
wr_ptr[0] => Decoder0.IN5 |
wr_ptr[1] => Decoder0.IN4 |
wr_ptr[2] => Decoder0.IN3 |
wr_ptr[3] => Decoder0.IN2 |
wr_ptr[4] => Decoder0.IN1 |
wr_ptr[5] => Decoder0.IN0 |
rd_ptr[0] => Mux0.IN5 |
rd_ptr[0] => Mux1.IN5 |
rd_ptr[0] => Mux2.IN5 |
rd_ptr[0] => Mux3.IN5 |
rd_ptr[0] => Mux4.IN5 |
rd_ptr[0] => Mux5.IN5 |
rd_ptr[0] => Mux6.IN5 |
rd_ptr[0] => Mux7.IN5 |
rd_ptr[0] => Mux8.IN5 |
rd_ptr[1] => Mux0.IN4 |
rd_ptr[1] => Mux1.IN4 |
rd_ptr[1] => Mux2.IN4 |
rd_ptr[1] => Mux3.IN4 |
rd_ptr[1] => Mux4.IN4 |
rd_ptr[1] => Mux5.IN4 |
rd_ptr[1] => Mux6.IN4 |
rd_ptr[1] => Mux7.IN4 |
rd_ptr[1] => Mux8.IN4 |
rd_ptr[2] => Mux0.IN3 |
rd_ptr[2] => Mux1.IN3 |
rd_ptr[2] => Mux2.IN3 |
rd_ptr[2] => Mux3.IN3 |
rd_ptr[2] => Mux4.IN3 |
rd_ptr[2] => Mux5.IN3 |
rd_ptr[2] => Mux6.IN3 |
rd_ptr[2] => Mux7.IN3 |
rd_ptr[2] => Mux8.IN3 |
rd_ptr[3] => Mux0.IN2 |
rd_ptr[3] => Mux1.IN2 |
rd_ptr[3] => Mux2.IN2 |
rd_ptr[3] => Mux3.IN2 |
rd_ptr[3] => Mux4.IN2 |
rd_ptr[3] => Mux5.IN2 |
rd_ptr[3] => Mux6.IN2 |
rd_ptr[3] => Mux7.IN2 |
rd_ptr[3] => Mux8.IN2 |
rd_ptr[4] => Mux0.IN1 |
rd_ptr[4] => Mux1.IN1 |
rd_ptr[4] => Mux2.IN1 |
rd_ptr[4] => Mux3.IN1 |
rd_ptr[4] => Mux4.IN1 |
rd_ptr[4] => Mux5.IN1 |
rd_ptr[4] => Mux6.IN1 |
rd_ptr[4] => Mux7.IN1 |
rd_ptr[4] => Mux8.IN1 |
rd_ptr[5] => Mux0.IN0 |
rd_ptr[5] => Mux1.IN0 |
rd_ptr[5] => Mux2.IN0 |
rd_ptr[5] => Mux3.IN0 |
rd_ptr[5] => Mux4.IN0 |
rd_ptr[5] => Mux5.IN0 |
rd_ptr[5] => Mux6.IN0 |
rd_ptr[5] => Mux7.IN0 |
rd_ptr[5] => Mux8.IN0 |
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
170979,12 → 171539,6
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
data_out[8] <= data_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[0] <= counter[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[1] <= counter[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[2] <= counter[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[3] <= counter[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[4] <= counter[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter[5] <= counter[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b |
171120,122 → 171674,10
|
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x |
rx_din => always0.IN0 |
rx_din => always3.IN0 |
rx_din => control_bit_found.DATAIN |
rx_din => bit_c_0.DATAIN |
rx_din => bit_d_0.DATAIN |
rx_din => bit_c_1.DATAIN |
rx_din => bit_d_1.DATAIN |
rx_sin => always0.IN1 |
rx_sin => always3.IN1 |
rx_resetn => info[0]~reg0.ACLR |
rx_resetn => info[1]~reg0.ACLR |
rx_resetn => info[2]~reg0.ACLR |
rx_resetn => info[3]~reg0.ACLR |
rx_resetn => info[4]~reg0.ACLR |
rx_resetn => info[5]~reg0.ACLR |
rx_resetn => info[6]~reg0.ACLR |
rx_resetn => info[7]~reg0.ACLR |
rx_resetn => info[8]~reg0.ACLR |
rx_resetn => info[9]~reg0.ACLR |
rx_resetn => info[10]~reg0.ACLR |
rx_resetn => info[11]~reg0.ACLR |
rx_resetn => info[12]~reg0.ACLR |
rx_resetn => info[13]~reg0.ACLR |
rx_resetn => last_was_timec.ACLR |
rx_resetn => last_was_data.ACLR |
rx_resetn => last_was_control.ACLR |
rx_resetn => last_is_timec.ACLR |
rx_resetn => last_is_data.ACLR |
rx_resetn => last_is_control.ACLR |
rx_resetn => timecode[0].ACLR |
rx_resetn => timecode[1].ACLR |
rx_resetn => timecode[2].ACLR |
rx_resetn => timecode[3].ACLR |
rx_resetn => timecode[4].ACLR |
rx_resetn => timecode[5].ACLR |
rx_resetn => timecode[6].ACLR |
rx_resetn => timecode[7].ACLR |
rx_resetn => data_l_r[1].ACLR |
rx_resetn => data_l_r[2].ACLR |
rx_resetn => data_l_r[3].ACLR |
rx_resetn => data_l_r[4].ACLR |
rx_resetn => data_l_r[5].ACLR |
rx_resetn => data_l_r[6].ACLR |
rx_resetn => data_l_r[7].ACLR |
rx_resetn => data[0].ACLR |
rx_resetn => data[1].ACLR |
rx_resetn => data[2].ACLR |
rx_resetn => data[3].ACLR |
rx_resetn => data[4].ACLR |
rx_resetn => data[5].ACLR |
rx_resetn => data[6].ACLR |
rx_resetn => data[7].ACLR |
rx_resetn => data[8].ACLR |
rx_resetn => data[9].ACLR |
rx_resetn => control_l_r[0].ACLR |
rx_resetn => control_l_r[1].ACLR |
rx_resetn => control_l_r[2].ACLR |
rx_resetn => control_l_r[3].ACLR |
rx_resetn => control[0].ACLR |
rx_resetn => control[1].ACLR |
rx_resetn => control[2].ACLR |
rx_resetn => control[3].ACLR |
rx_resetn => bit_d_7.ACLR |
rx_resetn => bit_d_5.ACLR |
rx_resetn => bit_d_3.ACLR |
rx_resetn => bit_d_1.ACLR |
rx_resetn => bit_c_3.ACLR |
rx_resetn => bit_c_1.ACLR |
rx_resetn => bit_d_8.ACLR |
rx_resetn => bit_d_6.ACLR |
rx_resetn => bit_d_4.ACLR |
rx_resetn => bit_d_2.ACLR |
rx_resetn => bit_d_0.ACLR |
rx_resetn => bit_c_2.ACLR |
rx_resetn => bit_c_0.ACLR |
rx_resetn => counter_neg[0].PRESET |
rx_resetn => counter_neg[1].ACLR |
rx_resetn => counter_neg[2].ACLR |
rx_resetn => counter_neg[3].ACLR |
rx_resetn => counter_neg[4].ACLR |
rx_resetn => counter_neg[5].ACLR |
rx_resetn => control_bit_found.ACLR |
rx_resetn => is_control.ACLR |
rx_resetn => rx_error.ACLR |
rx_resetn => rx_got_fct.ACLR |
rx_resetn => rx_got_time_code.ACLR |
rx_resetn => rx_got_nchar.ACLR |
rx_resetn => rx_got_null.ACLR |
rx_resetn => ready_data_p_r.ACLR |
rx_resetn => ready_control_p_r.ACLR |
rx_resetn => control_r[0].ACLR |
rx_resetn => control_r[1].ACLR |
rx_resetn => control_r[2].ACLR |
rx_resetn => control_r[3].ACLR |
rx_resetn => control_p_r[0].ACLR |
rx_resetn => control_p_r[1].ACLR |
rx_resetn => control_p_r[2].ACLR |
rx_resetn => control_p_r[3].ACLR |
rx_resetn => dta_timec[0].ACLR |
rx_resetn => dta_timec[1].ACLR |
rx_resetn => dta_timec[2].ACLR |
rx_resetn => dta_timec[3].ACLR |
rx_resetn => dta_timec[4].ACLR |
rx_resetn => dta_timec[5].ACLR |
rx_resetn => dta_timec[6].ACLR |
rx_resetn => dta_timec[7].ACLR |
rx_resetn => dta_timec[8].ACLR |
rx_resetn => dta_timec_p[0].ACLR |
rx_resetn => dta_timec_p[1].ACLR |
rx_resetn => dta_timec_p[2].ACLR |
rx_resetn => dta_timec_p[3].ACLR |
rx_resetn => dta_timec_p[4].ACLR |
rx_resetn => dta_timec_p[5].ACLR |
rx_resetn => dta_timec_p[6].ACLR |
rx_resetn => dta_timec_p[7].ACLR |
rx_resetn => dta_timec_p[8].ACLR |
rx_din => rx_din.IN3 |
rx_sin => comb.IN0 |
rx_sin => always1.IN0 |
rx_resetn => rx_resetn.IN3 |
info[0] <= info[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
info[1] <= info[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
info[2] <= info[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
171252,3 → 171694,82
info[13] <= info[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d |
negedge_clk => bit_d_8~reg0.CLK |
negedge_clk => bit_d_6~reg0.CLK |
negedge_clk => bit_d_4~reg0.CLK |
negedge_clk => bit_d_2~reg0.CLK |
negedge_clk => bit_d_0~reg0.CLK |
posedge_clk => bit_d_9~reg0.CLK |
posedge_clk => bit_d_7~reg0.CLK |
posedge_clk => bit_d_5~reg0.CLK |
posedge_clk => bit_d_3~reg0.CLK |
posedge_clk => bit_d_1~reg0.CLK |
rx_resetn => bit_d_8~reg0.ACLR |
rx_resetn => bit_d_6~reg0.ACLR |
rx_resetn => bit_d_4~reg0.ACLR |
rx_resetn => bit_d_2~reg0.ACLR |
rx_resetn => bit_d_0~reg0.ACLR |
rx_resetn => bit_d_9~reg0.ACLR |
rx_resetn => bit_d_7~reg0.ACLR |
rx_resetn => bit_d_5~reg0.ACLR |
rx_resetn => bit_d_3~reg0.ACLR |
rx_resetn => bit_d_1~reg0.ACLR |
rx_din => bit_d_0~reg0.DATAIN |
rx_din => bit_d_1~reg0.DATAIN |
bit_d_0 <= bit_d_0~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_1 <= bit_d_1~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_2 <= bit_d_2~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_3 <= bit_d_3~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_4 <= bit_d_4~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_5 <= bit_d_5~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_6 <= bit_d_6~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_7 <= bit_d_7~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_8 <= bit_d_8~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_d_9 <= bit_d_9~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c |
negedge_clk => bit_c_2~reg0.CLK |
negedge_clk => bit_c_0~reg0.CLK |
posedge_clk => bit_c_3~reg0.CLK |
posedge_clk => bit_c_1~reg0.CLK |
rx_resetn => bit_c_2~reg0.ACLR |
rx_resetn => bit_c_0~reg0.ACLR |
rx_resetn => bit_c_3~reg0.ACLR |
rx_resetn => bit_c_1~reg0.ACLR |
rx_din => bit_c_0~reg0.DATAIN |
rx_din => bit_c_1~reg0.DATAIN |
bit_c_0 <= bit_c_0~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_c_1 <= bit_c_1~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_c_2 <= bit_c_2~reg0.DB_MAX_OUTPUT_PORT_TYPE |
bit_c_3 <= bit_c_3~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
|SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg |
negedge_clk => counter_neg[0]~reg0.CLK |
negedge_clk => counter_neg[1]~reg0.CLK |
negedge_clk => counter_neg[2]~reg0.CLK |
negedge_clk => counter_neg[3]~reg0.CLK |
negedge_clk => counter_neg[4]~reg0.CLK |
negedge_clk => counter_neg[5]~reg0.CLK |
negedge_clk => control_bit_found.CLK |
negedge_clk => is_control~reg0.CLK |
rx_resetn => counter_neg[0]~reg0.PRESET |
rx_resetn => counter_neg[1]~reg0.ACLR |
rx_resetn => counter_neg[2]~reg0.ACLR |
rx_resetn => counter_neg[3]~reg0.ACLR |
rx_resetn => counter_neg[4]~reg0.ACLR |
rx_resetn => counter_neg[5]~reg0.ACLR |
rx_resetn => control_bit_found.ACLR |
rx_resetn => is_control~reg0.ACLR |
rx_din => control_bit_found.DATAIN |
is_control <= is_control~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[0] <= counter_neg[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[1] <= counter_neg[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[2] <= counter_neg[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[3] <= counter_neg[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[4] <= counter_neg[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
counter_neg[5] <= counter_neg[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE |
|
|
/spw_fifo_ulight.hif
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.lpc.html
16,6 → 16,54
<TH>Output only Bidir</TH> |
</TR> |
<TR > |
<TD >m_x|cnt_neg</TD> |
<TD >3</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >7</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >m_x|capture_c</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >m_x|capture_d</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >10</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >m_x</TD> |
<TD >3</TD> |
<TD >0</TD> |
64,6 → 112,22
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|tx_data|mem_dta_fifo_tx</TD> |
<TD >23</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >9</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|tx_data</TD> |
<TD >13</TD> |
<TD >0</TD> |
80,6 → 144,22
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|rx_data|mem_dta_fifo_tx</TD> |
<TD >23</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >9</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|rx_data</TD> |
<TD >13</TD> |
<TD >0</TD> |
96,6 → 176,70
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|TX|tx_data_snd</TD> |
<TD >24</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >29</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|TX|tx_fsm|tx_fct_snd</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >3</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|TX|tx_fsm|tx_fct_cnt</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >6</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|TX|tx_fsm</TD> |
<TD >35</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >7</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|TX</TD> |
<TD >25</TD> |
<TD >0</TD> |
112,6 → 256,134
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|rx_dtarcv</TD> |
<TD >25</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >25</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|cnt_neg</TD> |
<TD >3</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >7</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|capture_c</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|capture_d</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >10</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|data_control</TD> |
<TD >25</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >19</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|control_data_rdy</TD> |
<TD >18</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >4</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|buffer_data_flag</TD> |
<TD >10</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >2</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX|buffer_fsm</TD> |
<TD >5</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >3</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
<TD >0</TD> |
</TR> |
<TR > |
<TD >A_SPW_TOP|SPW|RX</TD> |
<TD >3</TD> |
<TD >0</TD> |
/spw_fifo_ulight.lpc.rdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.lpc.txt
3,12 → 3,29
+-----------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ |
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; |
+-----------------------------------------------------------------------------------------------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ |
; m_x|cnt_neg ; 3 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; m_x|capture_c ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; m_x|capture_d ; 4 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; m_x ; 3 ; 0 ; 0 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; R_400_to_2_5_10_100_200_300MHZ ; 5 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; db_system_spwulight_b ; 2 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|tx_data|mem_dta_fifo_tx ; 23 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|tx_data ; 13 ; 0 ; 0 ; 0 ; 18 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|rx_data|mem_dta_fifo_tx ; 23 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|rx_data ; 13 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|TX|tx_data_snd ; 24 ; 0 ; 0 ; 0 ; 29 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|TX|tx_fsm|tx_fct_snd ; 4 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|TX|tx_fsm|tx_fct_cnt ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|TX|tx_fsm ; 35 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|TX ; 25 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|rx_dtarcv ; 25 ; 0 ; 0 ; 0 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|cnt_neg ; 3 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|capture_c ; 4 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|capture_d ; 4 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|data_control ; 25 ; 0 ; 0 ; 0 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|control_data_rdy ; 18 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|buffer_data_flag ; 10 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX|buffer_fsm ; 5 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|RX ; 3 ; 0 ; 0 ; 0 ; 26 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW|FSM ; 12 ; 1 ; 0 ; 1 ; 10 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; A_SPW_TOP|SPW ; 29 ; 0 ; 0 ; 0 ; 29 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
/spw_fifo_ulight.map.ammdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.map.bpm
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.map.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.map.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.map.kpt
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.map.qmsg
1,235 → 1,305
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1505473661257 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1505473661268 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 08:07:41 2017 " "Processing started: Fri Sep 15 08:07:41 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1505473661268 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473661268 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473661269 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1505473670037 ""} |
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1505473670038 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685425 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685425 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" { } { { "../../rtl/DEBUG_VERILOG/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685428 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685428 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" { } { { "../../rtl/DEBUG_VERILOG/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685442 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685442 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685464 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685466 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685466 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" { } { { "../../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685482 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685482 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" { } { { "../../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685490 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685490 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685497 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685497 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685511 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685511 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" { } { { "../../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685525 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685525 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685562 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685562 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685581 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685581 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685594 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685594 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685651 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685651 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685698 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685698 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685704 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685704 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685718 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685718 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685729 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685729 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685729 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685740 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685740 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685753 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685753 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685758 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685758 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685767 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685767 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685770 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685770 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685788 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685788 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685788 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685788 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685788 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1505473685840 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685841 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685841 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685846 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1505473685852 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685852 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685862 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685862 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685875 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685875 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685876 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685876 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685878 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685878 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685891 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685891 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685897 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685897 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685897 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685903 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685903 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1505473685915 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1505473685915 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685916 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685916 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685916 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1505473685928 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1505473685929 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685930 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685930 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685930 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685946 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685946 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685980 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685980 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685994 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685994 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473685998 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473685998 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686009 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686009 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686015 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686015 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686027 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686027 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686029 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686029 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686040 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686040 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686042 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686042 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686045 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686045 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686052 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686052 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686053 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686053 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 29 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686243 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686243 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686269 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686269 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686283 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686283 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686295 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686295 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686306 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686306 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686307 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686307 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686312 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686312 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686313 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686313 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686314 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686314 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686325 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686325 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686336 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686336 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686338 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686338 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686347 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686347 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686358 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686358 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686373 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686373 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686399 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686399 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686432 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686432 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686445 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686445 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686446 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686446 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686447 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686448 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686448 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686449 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686449 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686461 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686461 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686462 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686462 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686463 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686463 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473686465 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473686465 ""} |
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(96) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(96): created implicit net for \"top_tx_ready_tick\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 96 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473686465 ""} |
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473686465 ""} |
{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1505473687157 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473687164 "|SPW_ULIGHT_FIFO"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" { } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687166 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687251 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687259 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687265 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687275 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687282 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687290 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687308 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687322 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687509 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687518 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687524 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687573 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1505473687574 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473687574 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687618 ""} |
{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } } } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473687620 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "umemphy" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 573 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687669 ""} |
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "reset_n_seq_clk hps_sdram_p0_acv_hard_memphy.v(420) " "Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1505473687673 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 hps_sdram_p0_acv_hard_memphy.v(557) " "Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 557 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1505473687674 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "reset_n_seq_clk 0 hps_sdram_p0_acv_hard_memphy.v(420) " "Net \"reset_n_seq_clk\" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0'" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1505473687680 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ctl_reset_export_n hps_sdram_p0_acv_hard_memphy.v(222) " "Output port \"ctl_reset_export_n\" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 222 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473687681 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_ldc ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc " "Elaborating entity \"hps_sdram_p0_acv_ldc\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "memphy_ldc" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 554 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687826 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dq hps_sdram_p0_acv_ldc.v(45) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object \"phy_clk_dq\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 45 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1505473687827 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dqs_2x hps_sdram_p0_acv_ldc.v(47) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object \"phy_clk_dqs_2x\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1505473687827 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_io_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_io_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "uio_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 780 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687869 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ddio_phy_dqdin\[179..32\] hps_sdram_p0_acv_hard_io_pads.v(191) " "Output port \"ddio_phy_dqdin\[179..32\]\" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 191 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473687877 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_addr_cmd_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_addr_cmd_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "uaddr_cmd_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687888 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "uaddress_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473687973 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ubank_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 166 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688030 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ucmd_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688043 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ureset_n_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 198 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688062 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altddio_out\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688483 ""} |
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688495 ""} |
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Parameter \"extend_oe_disable\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invert_output OFF " "Parameter \"invert_output\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Parameter \"lpm_type\" = \"altddio_out\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Parameter \"oe_reg\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_high OFF " "Parameter \"power_up_high\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Parameter \"width\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473688495 ""} } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1505473688495 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_uqe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_uqe " "Found entity 1: ddio_out_uqe" { } { { "db/ddio_out_uqe.tdf" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1505473688565 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473688565 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_uqe ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated " "Elaborating entity \"ddio_out_uqe\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated\"" { } { { "altddio_out.tdf" "auto_generated" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altddio_out.tdf" 101 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688566 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_clock_pair_generator ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator " "Elaborating entity \"hps_sdram_p0_clock_pair_generator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].uclk_generator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 337 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688572 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_altdqdqs ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs " "Elaborating entity \"hps_sdram_p0_altdqdqs\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "dq_ddio\[0\].ubidir_dq_dqs" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688580 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdq_dqs2_acv_connect_to_hard_phy_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst " "Elaborating entity \"altdq_dqs2_acv_connect_to_hard_phy_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "altdq_dqs2_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 146 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688591 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hhp_qseq_synth_top ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq " "Elaborating entity \"altera_mem_if_hhp_qseq_synth_top\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688991 ""} |
{ "Warning" "WSGN_EMPTY_SHELL" "altera_mem_if_hhp_qseq_synth_top " "Entity \"altera_mem_if_hhp_qseq_synth_top\" contains only dangling pins" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } } } 0 12158 "Entity \"%1!s!\" contains only dangling pins" 0 0 "Analysis & Synthesis" 0 -1 1505473688993 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hard_memory_controller_top_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0 " "Elaborating entity \"altera_mem_if_hard_memory_controller_top_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "c0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473688999 ""} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1505473689052 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1505473689052 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1505473689052 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1505473689053 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1505473689053 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1505473689053 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_oct_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct " "Elaborating entity \"altera_mem_if_oct_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "oct" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689574 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_dll_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll " "Elaborating entity \"altera_mem_if_dll_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "dll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 814 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689583 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_led_pio_test ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test " "Elaborating entity \"ulight_fifo_led_pio_test\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "led_pio_test" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 339 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689590 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_pll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0 " "Elaborating entity \"ulight_fifo_pll_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "pll_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689598 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborating entity \"altera_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "altera_pll_i" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689625 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvds_clk altera_pll.v(320) " "Output port \"lvds_clk\" at altera_pll.v(320) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 320 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473689662 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_pll.v(321) " "Output port \"loaden\" at altera_pll.v(321) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 321 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473689662 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk_out altera_pll.v(322) " "Output port \"extclk_out\" at altera_pll.v(322) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 322 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473689662 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "wire_to_nowhere_64 " "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "Analysis & Synthesis" 0 -1 1505473689662 ""} |
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689662 ""} |
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "fractional_vco_multiplier false " "Parameter \"fractional_vco_multiplier\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "reference_clock_frequency 100.0 MHz " "Parameter \"reference_clock_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_cout 32 " "Parameter \"pll_fractional_cout\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_dsm_out_sel 1st_order " "Parameter \"pll_dsm_out_sel\" = \"1st_order\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode direct " "Parameter \"operation_mode\" = \"direct\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_clocks 1 " "Parameter \"number_of_clocks\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency0 400.000000 MHz " "Parameter \"output_clock_frequency0\" = \"400.000000 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift0 0 ps " "Parameter \"phase_shift0\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle0 50 " "Parameter \"duty_cycle0\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency1 0 MHz " "Parameter \"output_clock_frequency1\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift1 0 ps " "Parameter \"phase_shift1\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle1 50 " "Parameter \"duty_cycle1\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency2 0 MHz " "Parameter \"output_clock_frequency2\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift2 0 ps " "Parameter \"phase_shift2\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle2 50 " "Parameter \"duty_cycle2\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency3 0 MHz " "Parameter \"output_clock_frequency3\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift3 0 ps " "Parameter \"phase_shift3\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle3 50 " "Parameter \"duty_cycle3\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency4 0 MHz " "Parameter \"output_clock_frequency4\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift4 0 ps " "Parameter \"phase_shift4\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle4 50 " "Parameter \"duty_cycle4\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency5 0 MHz " "Parameter \"output_clock_frequency5\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift5 0 ps " "Parameter \"phase_shift5\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle5 50 " "Parameter \"duty_cycle5\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency6 0 MHz " "Parameter \"output_clock_frequency6\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift6 0 ps " "Parameter \"phase_shift6\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle6 50 " "Parameter \"duty_cycle6\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency7 0 MHz " "Parameter \"output_clock_frequency7\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift7 0 ps " "Parameter \"phase_shift7\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle7 50 " "Parameter \"duty_cycle7\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency8 0 MHz " "Parameter \"output_clock_frequency8\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift8 0 ps " "Parameter \"phase_shift8\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle8 50 " "Parameter \"duty_cycle8\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency9 0 MHz " "Parameter \"output_clock_frequency9\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift9 0 ps " "Parameter \"phase_shift9\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle9 50 " "Parameter \"duty_cycle9\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency10 0 MHz " "Parameter \"output_clock_frequency10\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift10 0 ps " "Parameter \"phase_shift10\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle10 50 " "Parameter \"duty_cycle10\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency11 0 MHz " "Parameter \"output_clock_frequency11\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift11 0 ps " "Parameter \"phase_shift11\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle11 50 " "Parameter \"duty_cycle11\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency12 0 MHz " "Parameter \"output_clock_frequency12\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift12 0 ps " "Parameter \"phase_shift12\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle12 50 " "Parameter \"duty_cycle12\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency13 0 MHz " "Parameter \"output_clock_frequency13\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift13 0 ps " "Parameter \"phase_shift13\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle13 50 " "Parameter \"duty_cycle13\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency14 0 MHz " "Parameter \"output_clock_frequency14\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift14 0 ps " "Parameter \"phase_shift14\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle14 50 " "Parameter \"duty_cycle14\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency15 0 MHz " "Parameter \"output_clock_frequency15\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift15 0 ps " "Parameter \"phase_shift15\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle15 50 " "Parameter \"duty_cycle15\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency16 0 MHz " "Parameter \"output_clock_frequency16\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift16 0 ps " "Parameter \"phase_shift16\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle16 50 " "Parameter \"duty_cycle16\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency17 0 MHz " "Parameter \"output_clock_frequency17\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift17 0 ps " "Parameter \"phase_shift17\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle17 50 " "Parameter \"duty_cycle17\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type Cyclone V " "Parameter \"pll_type\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_subtype General " "Parameter \"pll_subtype\" = \"General\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_hi_div 2 " "Parameter \"m_cnt_hi_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_lo_div 2 " "Parameter \"m_cnt_lo_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_hi_div 256 " "Parameter \"n_cnt_hi_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_lo_div 256 " "Parameter \"n_cnt_lo_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_bypass_en false " "Parameter \"m_cnt_bypass_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_bypass_en true " "Parameter \"n_cnt_bypass_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_odd_div_duty_en false " "Parameter \"m_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_odd_div_duty_en false " "Parameter \"n_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div0 256 " "Parameter \"c_cnt_hi_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div0 256 " "Parameter \"c_cnt_lo_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst0 1 " "Parameter \"c_cnt_prst0\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst0 0 " "Parameter \"c_cnt_ph_mux_prst0\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src0 ph_mux_clk " "Parameter \"c_cnt_in_src0\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en0 true " "Parameter \"c_cnt_bypass_en0\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en0 false " "Parameter \"c_cnt_odd_div_duty_en0\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div1 1 " "Parameter \"c_cnt_hi_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div1 1 " "Parameter \"c_cnt_lo_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst1 1 " "Parameter \"c_cnt_prst1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst1 0 " "Parameter \"c_cnt_ph_mux_prst1\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src1 ph_mux_clk " "Parameter \"c_cnt_in_src1\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en1 true " "Parameter \"c_cnt_bypass_en1\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en1 false " "Parameter \"c_cnt_odd_div_duty_en1\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div2 1 " "Parameter \"c_cnt_hi_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div2 1 " "Parameter \"c_cnt_lo_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst2 1 " "Parameter \"c_cnt_prst2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst2 0 " "Parameter \"c_cnt_ph_mux_prst2\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src2 ph_mux_clk " "Parameter \"c_cnt_in_src2\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en2 true " "Parameter \"c_cnt_bypass_en2\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en2 false " "Parameter \"c_cnt_odd_div_duty_en2\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div3 1 " "Parameter \"c_cnt_hi_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div3 1 " "Parameter \"c_cnt_lo_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst3 1 " "Parameter \"c_cnt_prst3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst3 0 " "Parameter \"c_cnt_ph_mux_prst3\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src3 ph_mux_clk " "Parameter \"c_cnt_in_src3\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en3 true " "Parameter \"c_cnt_bypass_en3\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en3 false " "Parameter \"c_cnt_odd_div_duty_en3\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div4 1 " "Parameter \"c_cnt_hi_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div4 1 " "Parameter \"c_cnt_lo_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst4 1 " "Parameter \"c_cnt_prst4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst4 0 " "Parameter \"c_cnt_ph_mux_prst4\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src4 ph_mux_clk " "Parameter \"c_cnt_in_src4\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en4 true " "Parameter \"c_cnt_bypass_en4\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en4 false " "Parameter \"c_cnt_odd_div_duty_en4\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div5 1 " "Parameter \"c_cnt_hi_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div5 1 " "Parameter \"c_cnt_lo_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst5 1 " "Parameter \"c_cnt_prst5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst5 0 " "Parameter \"c_cnt_ph_mux_prst5\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src5 ph_mux_clk " "Parameter \"c_cnt_in_src5\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en5 true " "Parameter \"c_cnt_bypass_en5\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en5 false " "Parameter \"c_cnt_odd_div_duty_en5\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div6 1 " "Parameter \"c_cnt_hi_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div6 1 " "Parameter \"c_cnt_lo_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst6 1 " "Parameter \"c_cnt_prst6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst6 0 " "Parameter \"c_cnt_ph_mux_prst6\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src6 ph_mux_clk " "Parameter \"c_cnt_in_src6\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en6 true " "Parameter \"c_cnt_bypass_en6\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en6 false " "Parameter \"c_cnt_odd_div_duty_en6\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div7 1 " "Parameter \"c_cnt_hi_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div7 1 " "Parameter \"c_cnt_lo_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst7 1 " "Parameter \"c_cnt_prst7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst7 0 " "Parameter \"c_cnt_ph_mux_prst7\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src7 ph_mux_clk " "Parameter \"c_cnt_in_src7\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en7 true " "Parameter \"c_cnt_bypass_en7\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en7 false " "Parameter \"c_cnt_odd_div_duty_en7\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div8 1 " "Parameter \"c_cnt_hi_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div8 1 " "Parameter \"c_cnt_lo_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst8 1 " "Parameter \"c_cnt_prst8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst8 0 " "Parameter \"c_cnt_ph_mux_prst8\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src8 ph_mux_clk " "Parameter \"c_cnt_in_src8\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en8 true " "Parameter \"c_cnt_bypass_en8\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en8 false " "Parameter \"c_cnt_odd_div_duty_en8\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div9 1 " "Parameter \"c_cnt_hi_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div9 1 " "Parameter \"c_cnt_lo_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst9 1 " "Parameter \"c_cnt_prst9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst9 0 " "Parameter \"c_cnt_ph_mux_prst9\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src9 ph_mux_clk " "Parameter \"c_cnt_in_src9\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en9 true " "Parameter \"c_cnt_bypass_en9\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en9 false " "Parameter \"c_cnt_odd_div_duty_en9\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div10 1 " "Parameter \"c_cnt_hi_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div10 1 " "Parameter \"c_cnt_lo_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst10 1 " "Parameter \"c_cnt_prst10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst10 0 " "Parameter \"c_cnt_ph_mux_prst10\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src10 ph_mux_clk " "Parameter \"c_cnt_in_src10\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en10 true " "Parameter \"c_cnt_bypass_en10\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en10 false " "Parameter \"c_cnt_odd_div_duty_en10\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div11 1 " "Parameter \"c_cnt_hi_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div11 1 " "Parameter \"c_cnt_lo_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst11 1 " "Parameter \"c_cnt_prst11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst11 0 " "Parameter \"c_cnt_ph_mux_prst11\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src11 ph_mux_clk " "Parameter \"c_cnt_in_src11\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en11 true " "Parameter \"c_cnt_bypass_en11\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en11 false " "Parameter \"c_cnt_odd_div_duty_en11\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div12 1 " "Parameter \"c_cnt_hi_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div12 1 " "Parameter \"c_cnt_lo_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst12 1 " "Parameter \"c_cnt_prst12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst12 0 " "Parameter \"c_cnt_ph_mux_prst12\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src12 ph_mux_clk " "Parameter \"c_cnt_in_src12\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en12 true " "Parameter \"c_cnt_bypass_en12\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en12 false " "Parameter \"c_cnt_odd_div_duty_en12\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div13 1 " "Parameter \"c_cnt_hi_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div13 1 " "Parameter \"c_cnt_lo_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst13 1 " "Parameter \"c_cnt_prst13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst13 0 " "Parameter \"c_cnt_ph_mux_prst13\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src13 ph_mux_clk " "Parameter \"c_cnt_in_src13\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en13 true " "Parameter \"c_cnt_bypass_en13\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en13 false " "Parameter \"c_cnt_odd_div_duty_en13\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div14 1 " "Parameter \"c_cnt_hi_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div14 1 " "Parameter \"c_cnt_lo_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst14 1 " "Parameter \"c_cnt_prst14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst14 0 " "Parameter \"c_cnt_ph_mux_prst14\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src14 ph_mux_clk " "Parameter \"c_cnt_in_src14\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en14 true " "Parameter \"c_cnt_bypass_en14\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en14 false " "Parameter \"c_cnt_odd_div_duty_en14\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div15 1 " "Parameter \"c_cnt_hi_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div15 1 " "Parameter \"c_cnt_lo_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst15 1 " "Parameter \"c_cnt_prst15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst15 0 " "Parameter \"c_cnt_ph_mux_prst15\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src15 ph_mux_clk " "Parameter \"c_cnt_in_src15\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en15 true " "Parameter \"c_cnt_bypass_en15\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en15 false " "Parameter \"c_cnt_odd_div_duty_en15\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div16 1 " "Parameter \"c_cnt_hi_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div16 1 " "Parameter \"c_cnt_lo_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst16 1 " "Parameter \"c_cnt_prst16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst16 0 " "Parameter \"c_cnt_ph_mux_prst16\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src16 ph_mux_clk " "Parameter \"c_cnt_in_src16\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en16 true " "Parameter \"c_cnt_bypass_en16\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en16 false " "Parameter \"c_cnt_odd_div_duty_en16\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div17 1 " "Parameter \"c_cnt_hi_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div17 1 " "Parameter \"c_cnt_lo_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst17 1 " "Parameter \"c_cnt_prst17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst17 0 " "Parameter \"c_cnt_ph_mux_prst17\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src17 ph_mux_clk " "Parameter \"c_cnt_in_src17\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en17 true " "Parameter \"c_cnt_bypass_en17\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en17 false " "Parameter \"c_cnt_odd_div_duty_en17\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_vco_div 2 " "Parameter \"pll_vco_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_cp_current 30 " "Parameter \"pll_cp_current\" = \"30\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_bwctrl 2000 " "Parameter \"pll_bwctrl\" = \"2000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_output_clk_frequency 400.0 MHz " "Parameter \"pll_output_clk_frequency\" = \"400.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_division 1 " "Parameter \"pll_fractional_division\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "mimic_fbclk_type none " "Parameter \"mimic_fbclk_type\" = \"none\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_1 glb " "Parameter \"pll_fbclk_mux_1\" = \"glb\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_2 m_cnt " "Parameter \"pll_fbclk_mux_2\" = \"m_cnt\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_m_cnt_in_src ph_mux_clk " "Parameter \"pll_m_cnt_in_src\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_slf_rst false " "Parameter \"pll_slf_rst\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "refclk1_frequency 100.0 MHz " "Parameter \"refclk1_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_loss_sw_en true " "Parameter \"pll_clk_loss_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_manu_clk_sw_en false " "Parameter \"pll_manu_clk_sw_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_auto_clk_sw_en true " "Parameter \"pll_auto_clk_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clkin_1_src clk_1 " "Parameter \"pll_clkin_1_src\" = \"clk_1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_sw_dly 0 " "Parameter \"pll_clk_sw_dly\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1505473689663 ""} } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1505473689663 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dps_extra_kick ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst " "Elaborating entity \"dps_extra_kick\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\"" { } { { "altera_pll.v" "dps_extra_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689669 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 769 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689696 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dprio_init ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst " "Elaborating entity \"dprio_init\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\"" { } { { "altera_pll.v" "dprio_init_inst" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689698 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 784 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689699 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\"" { } { { "altera_pll.v" "lcell_cntsel_int_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689705 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1961 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689706 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\"" { } { { "altera_pll.v" "lcell_cntsel_int_1" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689708 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1972 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689708 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\"" { } { { "altera_pll.v" "lcell_cntsel_int_2" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689710 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1983 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689725 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\"" { } { { "altera_pll.v" "lcell_cntsel_int_3" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689727 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 1994 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689729 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\"" { } { { "altera_pll.v" "lcell_cntsel_int_4" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689731 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2005 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689732 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll " "Elaborating entity \"altera_cyclonev_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\"" { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689750 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk altera_cyclonev_pll.v(632) " "Output port \"extclk\" at altera_cyclonev_pll.v(632) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 632 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473689754 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "clkout\[0\] altera_cyclonev_pll.v(637) " "Output port \"clkout\[0\]\" at altera_cyclonev_pll.v(637) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 637 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473689754 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_cyclonev_pll.v(641) " "Output port \"loaden\" at altera_cyclonev_pll.v(641) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 641 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473689754 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvdsclk altera_cyclonev_pll.v(642) " "Output port \"lvdsclk\" at altera_cyclonev_pll.v(642) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 642 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1505473689754 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689754 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll_base ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 " "Elaborating entity \"altera_cyclonev_pll_base\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\"" { } { { "altera_cyclonev_pll.v" "fpll_0" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689757 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1153 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689761 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_rx ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx " "Elaborating entity \"ulight_fifo_timecode_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 385 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689767 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_tx_data ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data " "Elaborating entity \"ulight_fifo_timecode_tx_data\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 396 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689775 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_write_data_fifo_tx ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx " "Elaborating entity \"ulight_fifo_write_data_fifo_tx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "write_data_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689783 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "mm_interconnect_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473689790 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_translator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 1962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691167 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_axi_master_ni ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent " "Elaborating entity \"altera_merlin_axi_master_ni\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3434 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691217 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691252 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3518 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691303 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691329 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rsp_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3559 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691353 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rdata_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3600 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691400 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691579 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691633 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router_002" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691643 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691655 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_wr_limiter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7520 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691730 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7620 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691758 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_13_1 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter_13_1\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_13_1.burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691771 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 778 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691836 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_burstwrap_increment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment " "Elaborating entity \"altera_merlin_burst_adapter_burstwrap_increment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_burstwrap_increment" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691847 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_min ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min " "Elaborating entity \"altera_merlin_burst_adapter_min\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_min" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 1004 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691852 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_subtractor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub " "Elaborating entity \"altera_merlin_burst_adapter_subtractor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "ab_sub" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691861 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract " "Elaborating entity \"altera_merlin_burst_adapter_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "subtract" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 88 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473691865 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8813 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692536 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692595 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 287 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692614 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692619 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692723 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10111 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692763 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 630 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692947 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692954 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "avalon_st_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10283 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692970 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473692975 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller ulight_fifo:u0\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "rst_controller" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 616 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693042 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693051 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693055 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spw_ulight_con_top_x spw_ulight_con_top_x:A_SPW_TOP " "Elaborating entity \"spw_ulight_con_top_x\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\"" { } { { "top_rtl/spw_fifo_ulight.v" "A_SPW_TOP" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 143 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693064 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top_spw_ultra_light spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW " "Elaborating entity \"top_spw_ultra_light\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "SPW" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 133 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693070 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM " "Elaborating entity \"FSM_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "FSM" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 113 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693092 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX " "Elaborating entity \"RX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "RX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 135 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693094 ""} |
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "rx_spw.v(508) " "Verilog HDL Case Statement information at rx_spw.v(508): all case item expressions in this case statement are onehot" { } { { "../../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 508 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1505473693097 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX " "Elaborating entity \"TX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "TX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693115 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_rx spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data " "Elaborating entity \"fifo_rx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "rx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 148 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693168 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_tx spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Elaborating entity \"fifo_tx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 162 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693271 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce_db debounce_db:db_system_spwulight_b " "Elaborating entity \"debounce_db\" for hierarchy \"debounce_db:db_system_spwulight_b\"" { } { { "top_rtl/spw_fifo_ulight.v" "db_system_spwulight_b" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 150 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693367 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_reduce clock_reduce:R_400_to_2_5_10_100_200_300MHZ " "Elaborating entity \"clock_reduce\" for hierarchy \"clock_reduce:R_400_to_2_5_10_100_200_300MHZ\"" { } { { "top_rtl/spw_fifo_ulight.v" "R_400_to_2_5_10_100_200_300MHZ" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 158 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693395 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detector_tokens detector_tokens:m_x " "Elaborating entity \"detector_tokens\" for hierarchy \"detector_tokens:m_x\"" { } { { "top_rtl/spw_fifo_ulight.v" "m_x" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473693405 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "bit_c_ex detector_tokens.v(62) " "Verilog HDL or VHDL warning at detector_tokens.v(62): object \"bit_c_ex\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 62 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1505473693413 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "rx_data_take_0 detector_tokens.v(103) " "Verilog HDL or VHDL warning at detector_tokens.v(103): object \"rx_data_take_0\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 103 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1505473693413 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "detector_tokens.v(271) " "Verilog HDL Case Statement information at detector_tokens.v(271): all case item expressions in this case statement are onehot" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 271 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1505473693413 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "extclk cyclonev_pll 1 2 " "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 2224 0 0 } } } 0 12030 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be left dangling without any fan-out logic." 0 0 "Analysis & Synthesis" 0 -1 1505473700339 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1505473702824 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[4]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1505473702824 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[3]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1505473702824 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[2]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1505473702824 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[1]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 425 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1505473702824 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[0]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v" 427 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 102 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1505473702824 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|gnd"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1505473702824 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1505473702824 ""} |
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "32 " "32 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1505473717874 ""} |
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1505473728677 "|SPW_ULIGHT_FIFO|LED[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1505473728677 ""} |
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473729242 ""} |
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1372 " "1372 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1505473736349 ""} |
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "ulight_fifo_hps_0_hps_io_border:border " "Timing-Driven Synthesis is running on partition \"ulight_fifo_hps_0_hps_io_border:border\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473736895 ""} |
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473737909 ""} |
{ "Warning" "WAMERGE_PARTITION_MISSING_TOP" "1 " "Found 1 partition definition(s) having no effect on incremental compilation" { { "Warning" "WAMERGE_PARTITION_MISSING" "ulight_fifo_hps_0_hps_io_border:border " "Partition \"ulight_fifo_hps_0_hps_io_border:border\" has no effect on incremental compilation" { } { } 0 35015 "Partition \"%1!s!\" has no effect on incremental compilation" 0 0 "Design Software" 0 -1 1505473983648 ""} } { } 0 35014 "Found %1!d! partition definition(s) having no effect on incremental compilation" 0 0 "Analysis & Synthesis" 0 -1 1505473983648 ""} |
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "15 0 0 0 0 " "Adding 15 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1505473983880 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1505473983880 ""} |
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1505473985606 "|SPW_ULIGHT_FIFO|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1505473985606 ""} |
{ "Info" "ICUT_CUT_TM_SUMMARY" "8580 " "Implemented 8580 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1505473985651 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1505473985651 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8554 " "Implemented 8554 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1505473985651 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1505473985651 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 45 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 45 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1351 " "Peak virtual memory: 1351 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505473985789 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:13:05 2017 " "Processing ended: Fri Sep 15 08:13:05 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505473985789 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:24 " "Elapsed time: 00:05:24" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505473985789 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:06:00 " "Total CPU time (on all processors): 00:06:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505473985789 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1505473985789 ""} |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517798813318 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517798813386 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:46:52 2018 " "Processing started: Mon Feb 5 00:46:52 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517798813386 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798813386 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798813387 ""} |
{ "Info" "IQCU_OPT_MODE_DESCRIPTION" "High Performance Effort timing performance increased compilation time " "High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time" { { "Info" "IQCU_OPT_MODE_OVERRIDE" "Fitter Effort Standard Fit " "Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517798823446 ""} { "Info" "IQCU_OPT_MODE_OVERRIDE" "Physical Synthesis Effort Level Normal " "Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal)" { } { } 0 16304 "Mode behavior is affected by advanced setting %1!s! (default for this mode is %2!s!)" 0 0 "Design Software" 0 -1 1517798823446 ""} } { } 0 16303 "%1!s! optimization mode selected -- %2!s! will be prioritized at the potential cost of %3!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798823446 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1517798823763 ""} |
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1517798823763 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fsm_m " "Found entity 1: tx_fsm_m" { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841413 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841413 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fct_send " "Found entity 1: tx_fct_send" { } { { "../../rtl/RTL_VB/tx_fct_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841447 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_fct_counter " "Found entity 1: tx_fct_counter" { } { { "../../rtl/RTL_VB/tx_fct_counter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841449 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841449 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v" { { "Info" "ISGN_ENTITY_NAME" "1 tx_data_send " "Found entity 1: tx_data_send" { } { { "../../rtl/RTL_VB/tx_data_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841459 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841459 ""} |
{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "dont_replicate rx_data_receive.v(64) " "Verilog HDL Attribute warning at rx_data_receive.v(64): overriding existing value for attribute \"dont_replicate\"" { } { { "../../rtl/RTL_VB/rx_data_receive.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" 64 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841470 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_receive " "Found entity 1: rx_data_receive" { } { { "../../rtl/RTL_VB/rx_data_receive.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841470 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841470 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_control_p " "Found entity 1: rx_data_control_p" { } { { "../../rtl/RTL_VB/rx_data_control_p.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841474 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_data_buffer_data_w " "Found entity 1: rx_data_buffer_data_w" { } { { "../../rtl/RTL_VB/rx_data_buffer_data_w.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841476 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841476 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_control_data_rdy " "Found entity 1: rx_control_data_rdy" { } { { "../../rtl/RTL_VB/rx_control_data_rdy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841477 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841477 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v" { { "Info" "ISGN_ENTITY_NAME" "1 rx_buffer_fsm " "Found entity 1: rx_buffer_fsm" { } { { "../../rtl/RTL_VB/rx_buffer_fsm.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841480 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841480 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 mem_data " "Found entity 1: mem_data" { } { { "../../rtl/RTL_VB/mem_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841491 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841491 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter_neg " "Found entity 1: counter_neg" { } { { "../../rtl/RTL_VB/counter_neg.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841493 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841493 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v" { { "Info" "ISGN_ENTITY_NAME" "1 bit_capture_control " "Found entity 1: bit_capture_control" { } { { "../../rtl/RTL_VB/bitc_capture_control.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841496 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841496 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 bit_capture_data " "Found entity 1: bit_capture_data" { } { { "../../rtl/RTL_VB/bit_capture_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841498 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841498 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 TX_SPW " "Found entity 1: TX_SPW" { } { { "../../rtl/RTL_VB/tx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841513 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841513 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" { { "Info" "ISGN_ENTITY_NAME" "1 top_spw_ultra_light " "Found entity 1: top_spw_ultra_light" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841515 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841515 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" { { "Info" "ISGN_ENTITY_NAME" "1 spw_ulight_con_top_x " "Found entity 1: spw_ulight_con_top_x" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841526 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841526 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 RX_SPW " "Found entity 1: RX_SPW" { } { { "../../rtl/RTL_VB/rx_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841537 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841537 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" { { "Info" "ISGN_ENTITY_NAME" "1 FSM_SPW " "Found entity 1: FSM_SPW" { } { { "../../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" 36 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841540 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841540 ""} |
{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "syn_noprune fifo_tx.v(43) " "Verilog HDL Attribute warning at fifo_tx.v(43): overriding existing value for attribute \"syn_noprune\"" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 43 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841556 ""} |
{ "Warning" "WVRFX_L2_VERI_DUPLICATE_ATTRIBUTE" "syn_noprune fifo_tx.v(44) " "Verilog HDL Attribute warning at fifo_tx.v(44): overriding existing value for attribute \"syn_noprune\"" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 44 0 0 } } } 0 10890 "Verilog HDL Attribute warning at %2!s!: overriding existing value for attribute \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798841556 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_tx " "Found entity 1: fifo_tx" { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841557 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841557 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_rx " "Found entity 1: fifo_rx" { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841565 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841565 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" { { "Info" "ISGN_ENTITY_NAME" "1 debounce_db " "Found entity 1: debounce_db" { } { { "../../rtl/DEBUG_VERILOG/debounce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841587 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841587 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" { { "Info" "ISGN_ENTITY_NAME" "1 detector_tokens " "Found entity 1: detector_tokens" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841619 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841619 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v 1 1 " "Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_reduce " "Found entity 1: clock_reduce" { } { { "../../rtl/DEBUG_VERILOG/clock_reduce.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841635 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841635 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/ulight_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo " "Found entity 1: ulight_fifo" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 6 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841654 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841654 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841669 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" { } { { "ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841685 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0 " "Found entity 1: ulight_fifo_mm_interconnect_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841728 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841728 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841730 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841730 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841757 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841757 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841760 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841760 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841761 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841761 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841761 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_rsp_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_rsp_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841806 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841806 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_mux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_mux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841849 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841849 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_cmd_demux " "Found entity 1: ulight_fifo_mm_interconnect_0_cmd_demux" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841860 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841860 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841909 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841909 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841922 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841922 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841929 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841929 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798841949 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841950 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841950 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841952 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841952 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798841954 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841955 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841955 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" { } { { "ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841956 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841956 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841959 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841959 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841960 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841960 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798841997 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798841997 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_traffic_limiter " "Found entity 1: altera_merlin_traffic_limiter" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_traffic_limiter.sv" 49 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842043 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842043 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_reorder_memory " "Found entity 1: altera_merlin_reorder_memory" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842045 ""} { "Info" "ISGN_ENTITY_NAME" "2 memory_pointer_controller " "Found entity 2: memory_pointer_controller" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_reorder_memory.sv" 185 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842045 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842045 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" { } { { "ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842087 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842087 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842139 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842139 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_002_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_002_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842140 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router_002 " "Found entity 2: ulight_fifo_mm_interconnect_0_router_002" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842140 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842140 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ulight_fifo_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 48 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842182 ""} |
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ulight_fifo_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ulight_fifo_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 49 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1517798842182 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_mm_interconnect_0_router_default_decode " "Found entity 1: ulight_fifo_mm_interconnect_0_router_default_decode" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 45 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842184 ""} { "Info" "ISGN_ENTITY_NAME" "2 ulight_fifo_mm_interconnect_0_router " "Found entity 2: ulight_fifo_mm_interconnect_0_router" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 84 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842184 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842184 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842230 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842230 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842266 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842266 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_axi_master_ni " "Found entity 1: altera_merlin_axi_master_ni" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842284 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842284 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842287 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842287 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_write_data_fifo_tx " "Found entity 1: ulight_fifo_write_data_fifo_tx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_write_data_fifo_tx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842330 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842330 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_tx_data " "Found entity 1: ulight_fifo_timecode_tx_data" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_tx_data.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842341 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842341 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_timecode_rx " "Found entity 1: ulight_fifo_timecode_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_timecode_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842342 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842342 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_pll_0 " "Found entity 1: ulight_fifo_pll_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842343 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842343 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_led_pio_test " "Found entity 1: ulight_fifo_led_pio_test" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_led_pio_test.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842388 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842388 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0 " "Found entity 1: ulight_fifo_hps_0" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842446 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842446 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io " "Found entity 1: ulight_fifo_hps_0_hps_io" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842447 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842447 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram " "Found entity 1: hps_sdram" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842457 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842457 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_pll " "Found entity 1: hps_sdram_pll" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 25 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842467 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842467 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_clock_pair_generator " "Found entity 1: hps_sdram_p0_clock_pair_generator" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v" 28 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842650 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842650 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_addr_cmd_pads " "Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842667 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842667 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_memphy " "Found entity 1: hps_sdram_p0_acv_hard_memphy" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842676 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842676 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_ldc " "Found entity 1: hps_sdram_p0_acv_ldc" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842685 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842685 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_acv_hard_io_pads " "Found entity 1: hps_sdram_p0_acv_hard_io_pads" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842686 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842686 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_generic_ddio " "Found entity 1: hps_sdram_p0_generic_ddio" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_generic_ddio.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842687 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842687 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset " "Found entity 1: hps_sdram_p0_reset" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset.v" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842699 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842699 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_reset_sync " "Found entity 1: hps_sdram_p0_reset_sync" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_reset_sync.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842714 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842714 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_phy_csr " "Found entity 1: hps_sdram_p0_phy_csr" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_phy_csr.sv" 31 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842715 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842715 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_iss_probe " "Found entity 1: hps_sdram_p0_iss_probe" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_iss_probe.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842717 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842717 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0 " "Found entity 1: hps_sdram_p0" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842719 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842719 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" { { "Info" "ISGN_ENTITY_NAME" "1 hps_sdram_p0_altdqdqs " "Found entity 1: hps_sdram_p0_altdqdqs" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 17 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842721 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842721 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altdq_dqs2_acv_connect_to_hard_phy_cyclonev " "Found entity 1: altdq_dqs2_acv_connect_to_hard_phy_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv" 19 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842740 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842740 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hhp_qseq_synth_top " "Found entity 1: altera_mem_if_hhp_qseq_synth_top" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v" 15 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842752 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842752 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_hard_memory_controller_top_cyclonev " "Found entity 1: altera_mem_if_hard_memory_controller_top_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 18 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842809 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842809 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_oct_cyclonev " "Found entity 1: altera_mem_if_oct_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_oct_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842822 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842822 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_dll_cyclonev " "Found entity 1: altera_mem_if_dll_cyclonev" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_dll_cyclonev.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842828 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842828 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_hps_io_border " "Found entity 1: ulight_fifo_hps_0_hps_io_border" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842830 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842830 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_hps_0_fpga_interfaces " "Found entity 1: ulight_fifo_hps_0_fpga_interfaces" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_fpga_interfaces.sv" 14 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842834 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842834 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_fifo_empty_rx_status " "Found entity 1: ulight_fifo_fifo_empty_rx_status" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_fifo_empty_rx_status.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842842 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842842 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_info " "Found entity 1: ulight_fifo_data_info" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_info.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842843 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842843 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_data_flag_rx " "Found entity 1: ulight_fifo_data_flag_rx" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_data_flag_rx.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842845 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842845 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_counter_rx_fifo " "Found entity 1: ulight_fifo_counter_rx_fifo" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_counter_rx_fifo.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842846 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842846 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_clock_sel " "Found entity 1: ulight_fifo_clock_sel" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842847 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842847 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v 1 1 " "Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" { { "Info" "ISGN_ENTITY_NAME" "1 ulight_fifo_auto_start " "Found entity 1: ulight_fifo_auto_start" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v" 21 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842850 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842850 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top_rtl/spw_fifo_ulight.v 1 1 " "Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v" { { "Info" "ISGN_ENTITY_NAME" "1 SPW_ULIGHT_FIFO " "Found entity 1: SPW_ULIGHT_FIFO" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798842852 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""} |
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "top_tx_ready_tick spw_fifo_ulight.v(99) " "Verilog HDL Implicit Net warning at spw_fifo_ulight.v(99): created implicit net for \"top_tx_ready_tick\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 99 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""} |
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for \"pll_dr_clk\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798842852 ""} |
{ "Info" "ISGN_START_ELABORATION_TOP" "SPW_ULIGHT_FIFO " "Elaborating entity \"SPW_ULIGHT_FIFO\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1517798843221 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LED\[6\] spw_fifo_ulight.v(17) " "Output port \"LED\[6\]\" at spw_fifo_ulight.v(17) has no driver" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843242 "|SPW_ULIGHT_FIFO"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo ulight_fifo:u0 " "Elaborating entity \"ulight_fifo\" for hierarchy \"ulight_fifo:u0\"" { } { { "top_rtl/spw_fifo_ulight.v" "u0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843245 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_auto_start ulight_fifo:u0\|ulight_fifo_auto_start:auto_start " "Elaborating entity \"ulight_fifo_auto_start\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_auto_start:auto_start\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "auto_start" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 174 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843262 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_clock_sel ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel " "Elaborating entity \"ulight_fifo_clock_sel\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_clock_sel:clock_sel\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "clock_sel" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 185 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843287 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_counter_rx_fifo ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo " "Elaborating entity \"ulight_fifo_counter_rx_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_counter_rx_fifo:counter_rx_fifo\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "counter_rx_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 193 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843332 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_flag_rx ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx " "Elaborating entity \"ulight_fifo_data_flag_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_flag_rx:data_flag_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_flag_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 209 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843346 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_data_info ulight_fifo:u0\|ulight_fifo_data_info:data_info " "Elaborating entity \"ulight_fifo_data_info\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_data_info:data_info\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "data_info" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 217 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843368 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_fifo_empty_rx_status ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status " "Elaborating entity \"ulight_fifo_fifo_empty_rx_status\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "fifo_empty_rx_status" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 236 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843383 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0 " "Elaborating entity \"ulight_fifo_hps_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "hps_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 328 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843418 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_fpga_interfaces ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces " "Elaborating entity \"ulight_fifo_hps_0_fpga_interfaces\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "fpga_interfaces" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843456 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io " "Elaborating entity \"ulight_fifo_hps_0_hps_io\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" "hps_io" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0.v" 153 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843552 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_hps_0_hps_io_border ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border " "Elaborating entity \"ulight_fifo_hps_0_hps_io_border\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" "border" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v" 45 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843603 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst " "Elaborating entity \"hps_sdram\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" "hps_sdram_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io_border.sv" 84 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843672 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_pll ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll " "Elaborating entity \"hps_sdram_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_pll:pll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "pll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 105 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843696 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_dr_clk hps_sdram_pll.sv(168) " "Verilog HDL or VHDL warning at hps_sdram_pll.sv(168): object \"pll_dr_clk\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 168 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798843707 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "pll_locked hps_sdram_pll.sv(91) " "Output port \"pll_locked\" at hps_sdram_pll.sv(91) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv" 91 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843707 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0 ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0 " "Elaborating entity \"hps_sdram_p0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "p0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 230 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843710 ""} |
{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models hps_sdram_p0.sv(405) " "Verilog HDL Display System Task info at hps_sdram_p0.sv(405): Using Regular core emif simulation models" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 405 0 0 } } } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798843726 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_memphy ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy " "Elaborating entity \"hps_sdram_p0_acv_hard_memphy\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" "umemphy" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0.sv" 573 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843729 ""} |
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "reset_n_seq_clk hps_sdram_p0_acv_hard_memphy.v(420) " "Verilog HDL warning at hps_sdram_p0_acv_hard_memphy.v(420): object reset_n_seq_clk used but never assigned" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 1 hps_sdram_p0_acv_hard_memphy.v(557) " "Verilog HDL assignment warning at hps_sdram_p0_acv_hard_memphy.v(557): truncated value with size 4 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 557 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "reset_n_seq_clk 0 hps_sdram_p0_acv_hard_memphy.v(420) " "Net \"reset_n_seq_clk\" at hps_sdram_p0_acv_hard_memphy.v(420) has no driver or initial value, using a default initial value '0'" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 420 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ctl_reset_export_n hps_sdram_p0_acv_hard_memphy.v(222) " "Output port \"ctl_reset_export_n\" at hps_sdram_p0_acv_hard_memphy.v(222) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 222 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843769 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_ldc ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc " "Elaborating entity \"hps_sdram_p0_acv_ldc\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_ldc:memphy_ldc\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "memphy_ldc" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 554 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843772 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dq hps_sdram_p0_acv_ldc.v(45) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(45): object \"phy_clk_dq\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 45 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798843781 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "phy_clk_dqs_2x hps_sdram_p0_acv_ldc.v(47) " "Verilog HDL or VHDL warning at hps_sdram_p0_acv_ldc.v(47): object \"phy_clk_dqs_2x\" assigned a value but never read" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_ldc.v" 47 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798843781 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_io_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_io_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" "uio_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v" 780 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843784 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "ddio_phy_dqdin\[179..32\] hps_sdram_p0_acv_hard_io_pads.v(191) " "Output port \"ddio_phy_dqdin\[179..32\]\" at hps_sdram_p0_acv_hard_io_pads.v(191) has no driver" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 191 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798843798 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_acv_hard_addr_cmd_pads ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads " "Elaborating entity \"hps_sdram_p0_acv_hard_addr_cmd_pads\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "uaddr_cmd_pads" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 244 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843801 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:uaddress_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "uaddress_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843890 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ubank_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ubank_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 166 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843937 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ucmd_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ucmd_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 189 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843957 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_generic_ddio ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad " "Elaborating entity \"hps_sdram_p0_generic_ddio\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_generic_ddio:ureset_n_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "ureset_n_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 198 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798843993 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altddio_out ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altddio_out\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844604 ""} |
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844640 ""} |
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "extend_oe_disable UNUSED " "Parameter \"extend_oe_disable\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone V " "Parameter \"intended_device_family\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "invert_output OFF " "Parameter \"invert_output\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint UNUSED " "Parameter \"lpm_hint\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altddio_out " "Parameter \"lpm_type\" = \"altddio_out\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "oe_reg UNUSED " "Parameter \"oe_reg\" = \"UNUSED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_high OFF " "Parameter \"power_up_high\" = \"OFF\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width 1 " "Parameter \"width\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798844641 ""} } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 317 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1517798844641 ""} |
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ddio_out_uqe.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 ddio_out_uqe " "Found entity 1: ddio_out_uqe" { } { { "db/ddio_out_uqe.tdf" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1517798844747 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798844747 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddio_out_uqe ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated " "Elaborating entity \"ddio_out_uqe\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|altddio_out:clock_gen\[0\].umem_ck_pad\|ddio_out_uqe:auto_generated\"" { } { { "altddio_out.tdf" "auto_generated" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altddio_out.tdf" 100 4 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844749 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_clock_pair_generator ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator " "Elaborating entity \"hps_sdram_p0_clock_pair_generator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads\|hps_sdram_p0_clock_pair_generator:clock_gen\[0\].uclk_generator\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" "clock_gen\[0\].uclk_generator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v" 337 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844809 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hps_sdram_p0_altdqdqs ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs " "Elaborating entity \"hps_sdram_p0_altdqdqs\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" "dq_ddio\[0\].ubidir_dq_dqs" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v" 317 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844868 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altdq_dqs2_acv_connect_to_hard_phy_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst " "Elaborating entity \"altdq_dqs2_acv_connect_to_hard_phy_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|hps_sdram_p0:p0\|hps_sdram_p0_acv_hard_memphy:umemphy\|hps_sdram_p0_acv_hard_io_pads:uio_pads\|hps_sdram_p0_altdqdqs:dq_ddio\[0\].ubidir_dq_dqs\|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" "altdq_dqs2_inst" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v" 146 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798844920 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hhp_qseq_synth_top ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq " "Elaborating entity \"altera_mem_if_hhp_qseq_synth_top\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hhp_qseq_synth_top:seq\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "seq" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 238 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845026 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_hard_memory_controller_top_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0 " "Elaborating entity \"altera_mem_if_hard_memory_controller_top_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_hard_memory_controller_top_cyclonev:c0\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "c0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 794 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845070 ""} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1166 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1167 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1168): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1168 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1169): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1169 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1170): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1170 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "320 1 altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171) " "Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1171): truncated value with size 320 to match size of target (1)" { } { { "ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv" 1171 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1517798845097 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_oct_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct " "Elaborating entity \"altera_mem_if_oct_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_oct_cyclonev:oct\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "oct" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 802 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845101 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_dll_cyclonev ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll " "Elaborating entity \"altera_mem_if_dll_cyclonev\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_hps_io:hps_io\|ulight_fifo_hps_0_hps_io_border:border\|hps_sdram:hps_sdram_inst\|altera_mem_if_dll_cyclonev:dll\"" { } { { "ulight_fifo/synthesis/submodules/hps_sdram.v" "dll" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v" 814 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845115 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_led_pio_test ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test " "Elaborating entity \"ulight_fifo_led_pio_test\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_led_pio_test:led_pio_test\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "led_pio_test" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 339 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845124 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_pll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0 " "Elaborating entity \"ulight_fifo_pll_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "pll_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845134 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborating entity \"altera_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "altera_pll_i" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845181 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvds_clk altera_pll.v(319) " "Output port \"lvds_clk\" at altera_pll.v(319) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 319 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845241 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_pll.v(320) " "Output port \"loaden\" at altera_pll.v(320) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 320 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845241 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk_out altera_pll.v(321) " "Output port \"extclk_out\" at altera_pll.v(321) has no driver" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 321 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845241 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i"} |
{ "Info" "IVRFX_MULTI_DIMENSION_OBJECT_INFO" "wire_to_nowhere_64 " "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"wire_to_nowhere_64\" into its bus" { } { } 0 10008 "Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array \"%1!s!\" into its bus" 0 0 "Analysis & Synthesis" 0 -1 1517798845242 ""} |
{ "Info" "ISGN_ELABORATION_HEADER" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845242 ""} |
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Instantiated megafunction \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "fractional_vco_multiplier false " "Parameter \"fractional_vco_multiplier\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "reference_clock_frequency 50.0 MHz " "Parameter \"reference_clock_frequency\" = \"50.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_cout 32 " "Parameter \"pll_fractional_cout\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_dsm_out_sel 1st_order " "Parameter \"pll_dsm_out_sel\" = \"1st_order\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode normal " "Parameter \"operation_mode\" = \"normal\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "number_of_clocks 1 " "Parameter \"number_of_clocks\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency0 400.000000 MHz " "Parameter \"output_clock_frequency0\" = \"400.000000 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift0 0 ps " "Parameter \"phase_shift0\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle0 50 " "Parameter \"duty_cycle0\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency1 0 MHz " "Parameter \"output_clock_frequency1\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift1 0 ps " "Parameter \"phase_shift1\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle1 50 " "Parameter \"duty_cycle1\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency2 0 MHz " "Parameter \"output_clock_frequency2\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift2 0 ps " "Parameter \"phase_shift2\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle2 50 " "Parameter \"duty_cycle2\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency3 0 MHz " "Parameter \"output_clock_frequency3\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift3 0 ps " "Parameter \"phase_shift3\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle3 50 " "Parameter \"duty_cycle3\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency4 0 MHz " "Parameter \"output_clock_frequency4\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift4 0 ps " "Parameter \"phase_shift4\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle4 50 " "Parameter \"duty_cycle4\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency5 0 MHz " "Parameter \"output_clock_frequency5\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift5 0 ps " "Parameter \"phase_shift5\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle5 50 " "Parameter \"duty_cycle5\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency6 0 MHz " "Parameter \"output_clock_frequency6\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift6 0 ps " "Parameter \"phase_shift6\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle6 50 " "Parameter \"duty_cycle6\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency7 0 MHz " "Parameter \"output_clock_frequency7\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift7 0 ps " "Parameter \"phase_shift7\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle7 50 " "Parameter \"duty_cycle7\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency8 0 MHz " "Parameter \"output_clock_frequency8\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift8 0 ps " "Parameter \"phase_shift8\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle8 50 " "Parameter \"duty_cycle8\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency9 0 MHz " "Parameter \"output_clock_frequency9\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift9 0 ps " "Parameter \"phase_shift9\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle9 50 " "Parameter \"duty_cycle9\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency10 0 MHz " "Parameter \"output_clock_frequency10\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift10 0 ps " "Parameter \"phase_shift10\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle10 50 " "Parameter \"duty_cycle10\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency11 0 MHz " "Parameter \"output_clock_frequency11\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift11 0 ps " "Parameter \"phase_shift11\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle11 50 " "Parameter \"duty_cycle11\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency12 0 MHz " "Parameter \"output_clock_frequency12\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift12 0 ps " "Parameter \"phase_shift12\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle12 50 " "Parameter \"duty_cycle12\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency13 0 MHz " "Parameter \"output_clock_frequency13\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift13 0 ps " "Parameter \"phase_shift13\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle13 50 " "Parameter \"duty_cycle13\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency14 0 MHz " "Parameter \"output_clock_frequency14\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift14 0 ps " "Parameter \"phase_shift14\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle14 50 " "Parameter \"duty_cycle14\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency15 0 MHz " "Parameter \"output_clock_frequency15\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift15 0 ps " "Parameter \"phase_shift15\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle15 50 " "Parameter \"duty_cycle15\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency16 0 MHz " "Parameter \"output_clock_frequency16\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift16 0 ps " "Parameter \"phase_shift16\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle16 50 " "Parameter \"duty_cycle16\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock_frequency17 0 MHz " "Parameter \"output_clock_frequency17\" = \"0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "phase_shift17 0 ps " "Parameter \"phase_shift17\" = \"0 ps\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "duty_cycle17 50 " "Parameter \"duty_cycle17\" = \"50\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type Cyclone V " "Parameter \"pll_type\" = \"Cyclone V\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_subtype General " "Parameter \"pll_subtype\" = \"General\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_hi_div 4 " "Parameter \"m_cnt_hi_div\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_lo_div 4 " "Parameter \"m_cnt_lo_div\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_hi_div 256 " "Parameter \"n_cnt_hi_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_lo_div 256 " "Parameter \"n_cnt_lo_div\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_bypass_en false " "Parameter \"m_cnt_bypass_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_bypass_en true " "Parameter \"n_cnt_bypass_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "m_cnt_odd_div_duty_en false " "Parameter \"m_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "n_cnt_odd_div_duty_en false " "Parameter \"n_cnt_odd_div_duty_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div0 256 " "Parameter \"c_cnt_hi_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div0 256 " "Parameter \"c_cnt_lo_div0\" = \"256\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst0 1 " "Parameter \"c_cnt_prst0\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst0 0 " "Parameter \"c_cnt_ph_mux_prst0\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src0 ph_mux_clk " "Parameter \"c_cnt_in_src0\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en0 true " "Parameter \"c_cnt_bypass_en0\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en0 false " "Parameter \"c_cnt_odd_div_duty_en0\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div1 1 " "Parameter \"c_cnt_hi_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div1 1 " "Parameter \"c_cnt_lo_div1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst1 1 " "Parameter \"c_cnt_prst1\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst1 0 " "Parameter \"c_cnt_ph_mux_prst1\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src1 ph_mux_clk " "Parameter \"c_cnt_in_src1\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en1 true " "Parameter \"c_cnt_bypass_en1\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en1 false " "Parameter \"c_cnt_odd_div_duty_en1\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div2 1 " "Parameter \"c_cnt_hi_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div2 1 " "Parameter \"c_cnt_lo_div2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst2 1 " "Parameter \"c_cnt_prst2\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst2 0 " "Parameter \"c_cnt_ph_mux_prst2\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src2 ph_mux_clk " "Parameter \"c_cnt_in_src2\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en2 true " "Parameter \"c_cnt_bypass_en2\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en2 false " "Parameter \"c_cnt_odd_div_duty_en2\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div3 1 " "Parameter \"c_cnt_hi_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div3 1 " "Parameter \"c_cnt_lo_div3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst3 1 " "Parameter \"c_cnt_prst3\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst3 0 " "Parameter \"c_cnt_ph_mux_prst3\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src3 ph_mux_clk " "Parameter \"c_cnt_in_src3\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en3 true " "Parameter \"c_cnt_bypass_en3\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en3 false " "Parameter \"c_cnt_odd_div_duty_en3\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div4 1 " "Parameter \"c_cnt_hi_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div4 1 " "Parameter \"c_cnt_lo_div4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst4 1 " "Parameter \"c_cnt_prst4\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst4 0 " "Parameter \"c_cnt_ph_mux_prst4\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src4 ph_mux_clk " "Parameter \"c_cnt_in_src4\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en4 true " "Parameter \"c_cnt_bypass_en4\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en4 false " "Parameter \"c_cnt_odd_div_duty_en4\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div5 1 " "Parameter \"c_cnt_hi_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div5 1 " "Parameter \"c_cnt_lo_div5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst5 1 " "Parameter \"c_cnt_prst5\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst5 0 " "Parameter \"c_cnt_ph_mux_prst5\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src5 ph_mux_clk " "Parameter \"c_cnt_in_src5\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en5 true " "Parameter \"c_cnt_bypass_en5\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en5 false " "Parameter \"c_cnt_odd_div_duty_en5\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div6 1 " "Parameter \"c_cnt_hi_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div6 1 " "Parameter \"c_cnt_lo_div6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst6 1 " "Parameter \"c_cnt_prst6\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst6 0 " "Parameter \"c_cnt_ph_mux_prst6\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src6 ph_mux_clk " "Parameter \"c_cnt_in_src6\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en6 true " "Parameter \"c_cnt_bypass_en6\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en6 false " "Parameter \"c_cnt_odd_div_duty_en6\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div7 1 " "Parameter \"c_cnt_hi_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div7 1 " "Parameter \"c_cnt_lo_div7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst7 1 " "Parameter \"c_cnt_prst7\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst7 0 " "Parameter \"c_cnt_ph_mux_prst7\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src7 ph_mux_clk " "Parameter \"c_cnt_in_src7\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en7 true " "Parameter \"c_cnt_bypass_en7\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en7 false " "Parameter \"c_cnt_odd_div_duty_en7\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div8 1 " "Parameter \"c_cnt_hi_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div8 1 " "Parameter \"c_cnt_lo_div8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst8 1 " "Parameter \"c_cnt_prst8\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst8 0 " "Parameter \"c_cnt_ph_mux_prst8\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src8 ph_mux_clk " "Parameter \"c_cnt_in_src8\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en8 true " "Parameter \"c_cnt_bypass_en8\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en8 false " "Parameter \"c_cnt_odd_div_duty_en8\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div9 1 " "Parameter \"c_cnt_hi_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div9 1 " "Parameter \"c_cnt_lo_div9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst9 1 " "Parameter \"c_cnt_prst9\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst9 0 " "Parameter \"c_cnt_ph_mux_prst9\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src9 ph_mux_clk " "Parameter \"c_cnt_in_src9\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en9 true " "Parameter \"c_cnt_bypass_en9\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en9 false " "Parameter \"c_cnt_odd_div_duty_en9\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div10 1 " "Parameter \"c_cnt_hi_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div10 1 " "Parameter \"c_cnt_lo_div10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst10 1 " "Parameter \"c_cnt_prst10\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst10 0 " "Parameter \"c_cnt_ph_mux_prst10\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src10 ph_mux_clk " "Parameter \"c_cnt_in_src10\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en10 true " "Parameter \"c_cnt_bypass_en10\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en10 false " "Parameter \"c_cnt_odd_div_duty_en10\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div11 1 " "Parameter \"c_cnt_hi_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div11 1 " "Parameter \"c_cnt_lo_div11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst11 1 " "Parameter \"c_cnt_prst11\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst11 0 " "Parameter \"c_cnt_ph_mux_prst11\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src11 ph_mux_clk " "Parameter \"c_cnt_in_src11\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en11 true " "Parameter \"c_cnt_bypass_en11\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en11 false " "Parameter \"c_cnt_odd_div_duty_en11\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div12 1 " "Parameter \"c_cnt_hi_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div12 1 " "Parameter \"c_cnt_lo_div12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst12 1 " "Parameter \"c_cnt_prst12\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst12 0 " "Parameter \"c_cnt_ph_mux_prst12\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src12 ph_mux_clk " "Parameter \"c_cnt_in_src12\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en12 true " "Parameter \"c_cnt_bypass_en12\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en12 false " "Parameter \"c_cnt_odd_div_duty_en12\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div13 1 " "Parameter \"c_cnt_hi_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div13 1 " "Parameter \"c_cnt_lo_div13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst13 1 " "Parameter \"c_cnt_prst13\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst13 0 " "Parameter \"c_cnt_ph_mux_prst13\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src13 ph_mux_clk " "Parameter \"c_cnt_in_src13\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en13 true " "Parameter \"c_cnt_bypass_en13\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en13 false " "Parameter \"c_cnt_odd_div_duty_en13\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div14 1 " "Parameter \"c_cnt_hi_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div14 1 " "Parameter \"c_cnt_lo_div14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst14 1 " "Parameter \"c_cnt_prst14\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst14 0 " "Parameter \"c_cnt_ph_mux_prst14\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src14 ph_mux_clk " "Parameter \"c_cnt_in_src14\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en14 true " "Parameter \"c_cnt_bypass_en14\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en14 false " "Parameter \"c_cnt_odd_div_duty_en14\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div15 1 " "Parameter \"c_cnt_hi_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div15 1 " "Parameter \"c_cnt_lo_div15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst15 1 " "Parameter \"c_cnt_prst15\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst15 0 " "Parameter \"c_cnt_ph_mux_prst15\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src15 ph_mux_clk " "Parameter \"c_cnt_in_src15\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en15 true " "Parameter \"c_cnt_bypass_en15\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en15 false " "Parameter \"c_cnt_odd_div_duty_en15\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div16 1 " "Parameter \"c_cnt_hi_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div16 1 " "Parameter \"c_cnt_lo_div16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst16 1 " "Parameter \"c_cnt_prst16\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst16 0 " "Parameter \"c_cnt_ph_mux_prst16\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src16 ph_mux_clk " "Parameter \"c_cnt_in_src16\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en16 true " "Parameter \"c_cnt_bypass_en16\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en16 false " "Parameter \"c_cnt_odd_div_duty_en16\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_hi_div17 1 " "Parameter \"c_cnt_hi_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_lo_div17 1 " "Parameter \"c_cnt_lo_div17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_prst17 1 " "Parameter \"c_cnt_prst17\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_ph_mux_prst17 0 " "Parameter \"c_cnt_ph_mux_prst17\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_in_src17 ph_mux_clk " "Parameter \"c_cnt_in_src17\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_bypass_en17 true " "Parameter \"c_cnt_bypass_en17\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "c_cnt_odd_div_duty_en17 false " "Parameter \"c_cnt_odd_div_duty_en17\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_vco_div 2 " "Parameter \"pll_vco_div\" = \"2\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_cp_current 20 " "Parameter \"pll_cp_current\" = \"20\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_bwctrl 4000 " "Parameter \"pll_bwctrl\" = \"4000\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_output_clk_frequency 400.0 MHz " "Parameter \"pll_output_clk_frequency\" = \"400.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fractional_division 1 " "Parameter \"pll_fractional_division\" = \"1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "mimic_fbclk_type gclk " "Parameter \"mimic_fbclk_type\" = \"gclk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_1 glb " "Parameter \"pll_fbclk_mux_1\" = \"glb\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_fbclk_mux_2 fb_1 " "Parameter \"pll_fbclk_mux_2\" = \"fb_1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_m_cnt_in_src ph_mux_clk " "Parameter \"pll_m_cnt_in_src\" = \"ph_mux_clk\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_slf_rst false " "Parameter \"pll_slf_rst\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "refclk1_frequency 100.0 MHz " "Parameter \"refclk1_frequency\" = \"100.0 MHz\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_loss_sw_en true " "Parameter \"pll_clk_loss_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_manu_clk_sw_en false " "Parameter \"pll_manu_clk_sw_en\" = \"false\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_auto_clk_sw_en true " "Parameter \"pll_auto_clk_sw_en\" = \"true\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clkin_1_src clk_1 " "Parameter \"pll_clkin_1_src\" = \"clk_1\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_clk_sw_dly 0 " "Parameter \"pll_clk_sw_dly\" = \"0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1517798845243 ""} } { { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1517798845243 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dps_extra_kick ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst " "Elaborating entity \"dps_extra_kick\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\"" { } { { "altera_pll.v" "dps_extra_inst" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 768 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845249 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 768 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845310 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dprio_init ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst " "Elaborating entity \"dprio_init\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\"" { } { { "altera_pll.v" "dprio_init_inst" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 783 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845313 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dprio_init:dprio_init_inst\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 783 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845316 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\"" { } { { "altera_pll.v" "lcell_cntsel_int_0" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1960 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845325 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1960 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845367 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\"" { } { { "altera_pll.v" "lcell_cntsel_int_1" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1971 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845369 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_1\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1971 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845406 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\"" { } { { "altera_pll.v" "lcell_cntsel_int_2" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1982 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845408 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_2\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1982 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845438 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\"" { } { { "altera_pll.v" "lcell_cntsel_int_3" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1993 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845441 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_3\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 1993 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845453 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_pll_dps_lcell_comb ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 " "Elaborating entity \"altera_pll_dps_lcell_comb\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\"" { } { { "altera_pll.v" "lcell_cntsel_int_4" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2004 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845457 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_pll_dps_lcell_comb:lcell_cntsel_int_4\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2004 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845480 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll " "Elaborating entity \"altera_cyclonev_pll\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\"" { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2223 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845497 ""} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "extclk altera_cyclonev_pll.v(631) " "Output port \"extclk\" at altera_cyclonev_pll.v(631) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 631 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845533 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "clkout\[0\] altera_cyclonev_pll.v(636) " "Output port \"clkout\[0\]\" at altera_cyclonev_pll.v(636) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 636 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "loaden altera_cyclonev_pll.v(640) " "Output port \"loaden\" at altera_cyclonev_pll.v(640) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 640 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "lvdsclk altera_cyclonev_pll.v(641) " "Output port \"lvdsclk\" at altera_cyclonev_pll.v(641) has no driver" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 641 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2223 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845534 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_cyclonev_pll_base ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 " "Elaborating entity \"altera_cyclonev_pll_base\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\"" { } { { "altera_cyclonev_pll.v" "fpll_0" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1152 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845536 ""} |
{ "Info" "ISGN_MEGAFN_DESCENDANT" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0 ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i " "Elaborated megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|altera_cyclonev_pll:cyclonev_pll\|altera_cyclonev_pll_base:fpll_0\", which is child of megafunction instantiation \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\"" { } { { "altera_cyclonev_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v" 1152 0 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845573 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_rx ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx " "Elaborating entity \"ulight_fifo_timecode_rx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_rx:timecode_rx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_rx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 385 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845580 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_timecode_tx_data ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data " "Elaborating entity \"ulight_fifo_timecode_tx_data\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_timecode_tx_data:timecode_tx_data\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "timecode_tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 396 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845584 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_write_data_fifo_tx ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx " "Elaborating entity \"ulight_fifo_write_data_fifo_tx\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "write_data_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 426 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845592 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "mm_interconnect_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 553 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845630 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:led_pio_test_s1_translator\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_translator" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 1962 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845879 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_axi_master_ni ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent " "Elaborating entity \"altera_merlin_axi_master_ni\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3434 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845953 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_axi_master_ni.sv" 485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798845980 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3518 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846007 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:led_pio_test_s1_agent\|altera_merlin_burst_uncompressor:uncompressor\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846033 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rsp_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3559 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846048 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_agent_rdata_fifo" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 3600 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846060 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7102 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846300 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router:router\|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router.sv" 205 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846335 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "router_002" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846352 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_router_002_default_decode ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode " "Elaborating entity \"ulight_fifo_mm_interconnect_0_router_002_default_decode\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_router_002:router_002\|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" "the_default_decode" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_router_002.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846404 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_traffic_limiter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter " "Elaborating entity \"altera_merlin_traffic_limiter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "hps_0_h2f_axi_master_wr_limiter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7520 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846478 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "led_pio_test_s1_burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 7620 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846513 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_13_1 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter_13_1\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_13_1.burst_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter.sv" 181 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846546 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_address_alignment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size " "Elaborating entity \"altera_merlin_address_alignment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_address_alignment:align_address_to_size\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "align_address_to_size" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 778 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846577 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_burstwrap_increment ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment " "Elaborating entity \"altera_merlin_burst_adapter_burstwrap_increment\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_burstwrap_increment" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846581 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_min ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min " "Elaborating entity \"altera_merlin_burst_adapter_min\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "the_min" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 1004 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846584 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_subtractor ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub " "Elaborating entity \"altera_merlin_burst_adapter_subtractor\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "ab_sub" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846611 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract " "Elaborating entity \"altera_merlin_burst_adapter_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|altera_merlin_burst_adapter_min:the_min\|altera_merlin_burst_adapter_subtractor:ab_sub\|altera_merlin_burst_adapter_adder:subtract\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "subtract" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 88 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798846625 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8813 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847450 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_cmd_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_cmd_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "cmd_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 8979 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847487 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_cmd_mux.sv" 287 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847537 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847593 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_demux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_demux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_demux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 9485 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847740 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_rsp_mux ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"ulight_fifo_mm_interconnect_0_rsp_mux\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "rsp_mux" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10111 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847808 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" "arb" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_rsp_mux.sv" 630 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847862 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" { } { { "ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847897 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" "avalon_st_adapter" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0.v" 10283 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847916 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0 ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" { } { { "ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798847920 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller ulight_fifo:u0\|altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\"" { } { { "ulight_fifo/synthesis/ulight_fifo.v" "rst_controller" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 616 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848007 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 208 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848031 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"ulight_fifo:u0\|altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" { } { { "ulight_fifo/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v" 220 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848035 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "spw_ulight_con_top_x spw_ulight_con_top_x:A_SPW_TOP " "Elaborating entity \"spw_ulight_con_top_x\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\"" { } { { "top_rtl/spw_fifo_ulight.v" "A_SPW_TOP" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 148 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848043 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top_spw_ultra_light spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW " "Elaborating entity \"top_spw_ultra_light\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "SPW" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 136 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848096 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FSM_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM " "Elaborating entity \"FSM_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "FSM" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 112 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848109 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX " "Elaborating entity \"RX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "RX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 134 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848125 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_buffer_fsm spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_buffer_fsm:buffer_fsm " "Elaborating entity \"rx_buffer_fsm\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_buffer_fsm:buffer_fsm\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "buffer_fsm" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 176 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848143 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_data_buffer_data_w spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_buffer_data_w:buffer_data_flag " "Elaborating entity \"rx_data_buffer_data_w\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_buffer_data_w:buffer_data_flag\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "buffer_data_flag" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 191 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848173 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_control_data_rdy spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_control_data_rdy:control_data_rdy " "Elaborating entity \"rx_control_data_rdy\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_control_data_rdy:control_data_rdy\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "control_data_rdy" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 213 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848203 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_data_control_p spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_control_p:data_control " "Elaborating entity \"rx_data_control_p\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_control_p:data_control\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "data_control" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 250 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848211 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bit_capture_data spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_data:capture_d " "Elaborating entity \"bit_capture_data\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_data:capture_d\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "capture_d" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 270 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848214 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bit_capture_control spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_control:capture_c " "Elaborating entity \"bit_capture_control\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|bit_capture_control:capture_c\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "capture_c" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 283 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848219 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_neg spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|counter_neg:cnt_neg " "Elaborating entity \"counter_neg\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|counter_neg:cnt_neg\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "cnt_neg" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 291 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848228 ""} |
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "counter_neg.v(58) " "Verilog HDL Case Statement information at counter_neg.v(58): all case item expressions in this case statement are onehot" { } { { "../../rtl/RTL_VB/counter_neg.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v" 58 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1517798848229 "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg"} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rx_data_receive spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_receive:rx_dtarcv " "Elaborating entity \"rx_data_receive\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|RX_SPW:RX\|rx_data_receive:rx_dtarcv\"" { } { { "../../rtl/RTL_VB/rx_spw.v" "rx_dtarcv" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v" 325 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848231 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "TX_SPW spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX " "Elaborating entity \"TX_SPW\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\"" { } { { "../../rtl/RTL_VB/top_spw_ultra_light.v" "TX" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v" 157 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848234 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_fsm_m spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm " "Elaborating entity \"tx_fsm_m\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\"" { } { { "../../rtl/RTL_VB/tx_spw.v" "tx_fsm" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 117 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848250 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_fct_counter spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt " "Elaborating entity \"tx_fct_counter\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\"" { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "tx_fct_cnt" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 789 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848269 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_fct_send spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd " "Elaborating entity \"tx_fct_send\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\"" { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "tx_fct_snd" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 797 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848276 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx_data_send spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_data_send:tx_data_snd " "Elaborating entity \"tx_data_send\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_data_send:tx_data_snd\"" { } { { "../../rtl/RTL_VB/tx_spw.v" "tx_data_snd" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v" 142 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848296 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_rx spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data " "Elaborating entity \"fifo_rx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "rx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 151 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848352 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mem_data spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_data:mem_dta_fifo_tx " "Elaborating entity \"mem_data\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|mem_data:mem_dta_fifo_tx\"" { } { { "../../rtl/RTL_VB/fifo_rx.v" "mem_dta_fifo_tx" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 415 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848378 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_tx spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data " "Elaborating entity \"fifo_tx\" for hierarchy \"spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\"" { } { { "../../rtl/RTL_VB/spw_ulight_con_top_x.v" "tx_data" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v" 165 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848406 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "debounce_db debounce_db:db_system_spwulight_b " "Elaborating entity \"debounce_db\" for hierarchy \"debounce_db:db_system_spwulight_b\"" { } { { "top_rtl/spw_fifo_ulight.v" "db_system_spwulight_b" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 155 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848420 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_reduce clock_reduce:R_400_to_2_5_10_100_200_300MHZ " "Elaborating entity \"clock_reduce\" for hierarchy \"clock_reduce:R_400_to_2_5_10_100_200_300MHZ\"" { } { { "top_rtl/spw_fifo_ulight.v" "R_400_to_2_5_10_100_200_300MHZ" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 163 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848422 ""} |
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "detector_tokens detector_tokens:m_x " "Elaborating entity \"detector_tokens\" for hierarchy \"detector_tokens:m_x\"" { } { { "top_rtl/spw_fifo_ulight.v" "m_x" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 170 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798848437 ""} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "control_r detector_tokens.v(87) " "Verilog HDL or VHDL warning at detector_tokens.v(87): object \"control_r\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 87 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848442 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "control_p_r detector_tokens.v(88) " "Verilog HDL warning at detector_tokens.v(88): object control_p_r used but never assigned" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 88 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "dta_timec detector_tokens.v(92) " "Verilog HDL or VHDL warning at detector_tokens.v(92): object \"dta_timec\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 92 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "dta_timec_p detector_tokens.v(93) " "Verilog HDL warning at detector_tokens.v(93): object dta_timec_p used but never assigned" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 93 0 0 } } } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ready_control detector_tokens.v(104) " "Verilog HDL or VHDL warning at detector_tokens.v(104): object \"ready_control\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 104 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ready_data detector_tokens.v(105) " "Verilog HDL or VHDL warning at detector_tokens.v(105): object \"ready_data\" assigned a value but never read" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 105 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "control_p_r 0 detector_tokens.v(88) " "Net \"control_p_r\" at detector_tokens.v(88) has no driver or initial value, using a default initial value '0'" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 88 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "dta_timec_p\[7..0\] 0 detector_tokens.v(93) " "Net \"dta_timec_p\[7..0\]\" at detector_tokens.v(93) has no driver or initial value, using a default initial value '0'" { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 93 0 0 } } } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1517798848443 "|SPW_ULIGHT_FIFO|detector_tokens:m_x"} |
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "extclk cyclonev_pll 1 2 " "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic." { } { { "altera_pll.v" "cyclonev_pll" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2223 0 0 } } } 0 12030 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!. The extra bits will be left dangling without any fan-out logic." 0 0 "Analysis & Synthesis" 0 -1 1517798855164 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll"} |
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "LCELL buffer " "Synthesized away the following LCELL buffer node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[4\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[4]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[3\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[3]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[2\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[2]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[1\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[1]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\] " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|cntsel_temp\[0\]\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 424 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[0]"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd " "Synthesized away node \"ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|gnd\"" { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 426 -1 0 } } { "ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v" 241 0 0 } } { "ulight_fifo/synthesis/ulight_fifo.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v" 369 0 0 } } { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 105 0 0 } } } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1517798857940 "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|gnd"} } { } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1517798857940 ""} } { } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1517798857940 ""} |
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "2 " "Ignored 2 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_SOFT" "2 " "Ignored 2 SOFT buffer(s)" { } { } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Design Software" 0 -1 1517798860164 ""} } { } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Analysis & Synthesis" 0 -1 1517798860164 ""} |
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "32 " "32 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1517798873413 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873498 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873499 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873501 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873503 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_info_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873505 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873506 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873508 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873510 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873511 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873513 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873515 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873517 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_disable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_disable_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873520 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:auto_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:auto_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873522 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:link_start_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873524 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873525 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873526 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873528 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873529 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873531 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873532 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter\|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter\|state\" will be implemented as a safe state machine." { } { { "ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 398 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873534 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|detector_tokens:m_x\|state_data_process " "State machine \"\|SPW_ULIGHT_FIFO\|detector_tokens:m_x\|state_data_process\" will be implemented as a safe state machine." { } { { "../../rtl/DEBUG_VERILOG/detector_tokens.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v" 51 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873535 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_open_slot " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_open_slot\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 60 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873535 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_write " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_write\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 54 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873536 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_read " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_rx:rx_data\|state_data_read\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_rx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v" 57 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873536 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\|dps_current_state " "State machine \"\|SPW_ULIGHT_FIFO\|ulight_fifo:u0\|ulight_fifo_pll_0:pll_0\|altera_pll:altera_pll_i\|dps_extra_kick:dps_extra_inst\|dps_current_state\" will be implemented as a safe state machine." { } { { "altera_pll.v" "" { Text "/home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v" 2672 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873537 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_read " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_read\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 52 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873537 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|state_tx " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|state_tx\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fsm_m.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v" 92 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873539 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" 45 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873540 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send_p " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_send:tx_fct_snd\|state_fct_send_p\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_send.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v" 48 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873540 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_p " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_p\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_counter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" 47 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873541 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_write " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|fifo_tx:tx_data\|state_data_write\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fifo_tx.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v" 49 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873541 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_receive " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_fct_counter:tx_fct_cnt\|state_fct_receive\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/tx_fct_counter.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v" 44 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873542 ""} |
{ "Info" "ISMP_OPT_REPORT_SAFE_STATE_MACHINE" "\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\|state_fsm " "State machine \"\|SPW_ULIGHT_FIFO\|spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|FSM_SPW:FSM\|state_fsm\" will be implemented as a safe state machine." { } { { "../../rtl/RTL_VB/fsm_spw.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v" 71 -1 0 } } } 0 284007 "State machine \"%1!s!\" will be implemented as a safe state machine." 0 0 "Analysis & Synthesis" 0 -1 1517798873543 ""} |
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LED\[6\] GND " "Pin \"LED\[6\]\" is stuck at GND" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1517798887177 "|SPW_ULIGHT_FIFO|LED[6]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1517798887177 ""} |
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798887909 ""} |
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1382 " "1382 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1517798893747 ""} |
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "ulight_fifo_hps_0_hps_io_border:border " "Timing-Driven Synthesis is running on partition \"ulight_fifo_hps_0_hps_io_border:border\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517798894460 ""} |
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg " "Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1517798895861 ""} |
{ "Warning" "WAMERGE_PARTITION_MISSING_TOP" "1 " "Found 1 partition definition(s) having no effect on incremental compilation" { { "Warning" "WAMERGE_PARTITION_MISSING" "ulight_fifo_hps_0_hps_io_border:border " "Partition \"ulight_fifo_hps_0_hps_io_border:border\" has no effect on incremental compilation" { } { } 0 35015 "Partition \"%1!s!\" has no effect on incremental compilation" 0 0 "Design Software" 0 -1 1517799127876 ""} } { } 0 35014 "Found %1!d! partition definition(s) having no effect on incremental compilation" 0 0 "Analysis & Synthesis" 0 -1 1517799127876 ""} |
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "15 0 0 0 0 " "Adding 15 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1517799128148 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1517799128148 ""} |
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "No output dependent on input pin \"KEY\[0\]\"" { } { { "top_rtl/spw_fifo_ulight.v" "" { Text "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v" 3 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1517799130174 "|SPW_ULIGHT_FIFO|KEY[0]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1517799130174 ""} |
{ "Info" "ICUT_CUT_TM_SUMMARY" "8595 " "Implemented 8595 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Implemented 5 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1517799130206 ""} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Implemented 10 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1517799130206 ""} { "Info" "ICUT_CUT_TM_LCELLS" "8569 " "Implemented 8569 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1517799130206 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1517799130206 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 53 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 53 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1310 " "Peak virtual memory: 1310 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799130374 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:52:10 2018 " "Processing ended: Mon Feb 5 00:52:10 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799130374 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:05:18 " "Elapsed time: 00:05:18" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799130374 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:05:46 " "Total CPU time (on all processors): 00:05:46" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799130374 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1517799130374 ""} |
/spw_fifo_ulight.map.rdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.map_bb.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.map_bb.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.pre_map.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.root_partition.map.reg_db.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.routing.rdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.rtlv.hdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.rtlv_sg.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.rtlv_sg_swap.cdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.sld_design_entry.sci
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.sld_design_entry_dsc.sci
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.smp_dump.txt
153,6 → 153,29
state.ST_UNCOMP_TRANS 1 0 1 0 |
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 |
|
State Machine - |SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process |
Name state_data_process.01 |
state_data_process.00 0 |
state_data_process.01 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot |
Name state_open_slot.00 state_open_slot.10 state_open_slot.01 |
state_open_slot.00 0 0 0 |
state_open_slot.01 1 0 1 |
state_open_slot.10 1 1 0 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write |
Name state_data_write.00 state_data_write.10 state_data_write.01 |
state_data_write.00 0 0 0 |
state_data_write.01 1 0 1 |
state_data_write.10 1 1 0 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read |
Name state_data_read.00 state_data_read.10 state_data_read.01 |
state_data_read.00 0 0 0 |
state_data_read.01 1 0 1 |
state_data_read.10 1 1 0 |
|
State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state |
Name dps_current_state.PHASE_DONE_LOW_0 dps_current_state.PHASE_DONE_LOW_4 dps_current_state.PHASE_DONE_LOW_3 dps_current_state.PHASE_DONE_LOW_2 dps_current_state.PHASE_DONE_LOW_1 dps_current_state.PHASE_DONE_HIGH |
dps_current_state.PHASE_DONE_HIGH 0 0 0 0 0 0 |
162,22 → 185,57
dps_current_state.PHASE_DONE_LOW_4 0 1 0 0 0 1 |
dps_current_state.PHASE_DONE_LOW_0 1 0 0 0 0 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|state_tx |
Name state_tx.tx_spw_start state_tx.tx_spw_full state_tx.tx_spw_null_fct state_tx.tx_spw_null |
state_tx.tx_spw_start 0 0 0 0 |
state_tx.tx_spw_null 1 0 0 1 |
state_tx.tx_spw_null_fct 1 0 1 0 |
state_tx.tx_spw_full 1 1 0 0 |
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read |
Name state_data_read.11 state_data_read.10 state_data_read.01 state_data_read.00 |
state_data_read.00 0 0 0 0 |
state_data_read.01 0 0 1 1 |
state_data_read.10 0 1 0 1 |
state_data_read.11 1 0 0 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_type |
Name last_type.TIMEC last_type.DATA last_type.EEP last_type.EOP last_type.FCT last_type.NULL |
last_type.NULL 0 0 0 0 0 0 |
last_type.FCT 0 0 0 0 1 1 |
last_type.EOP 0 0 0 1 0 1 |
last_type.EEP 0 0 1 0 0 1 |
last_type.DATA 0 1 0 0 0 1 |
last_type.TIMEC 1 0 0 0 0 1 |
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx |
Name state_tx.tx_spw_time_code_c state_tx.tx_spw_data_c_0 state_tx.tx_spw_data_c state_tx.tx_spw_fct_c state_tx.tx_spw_null_c state_tx.tx_spw_fct state_tx.tx_spw_null state_tx.tx_spw_start |
state_tx.tx_spw_start 0 0 0 0 0 0 0 0 |
state_tx.tx_spw_null 0 0 0 0 0 0 1 1 |
state_tx.tx_spw_fct 0 0 0 0 0 1 0 1 |
state_tx.tx_spw_null_c 0 0 0 0 1 0 0 1 |
state_tx.tx_spw_fct_c 0 0 0 1 0 0 0 1 |
state_tx.tx_spw_data_c 0 0 1 0 0 0 0 1 |
state_tx.tx_spw_data_c_0 0 1 0 0 0 0 0 1 |
state_tx.tx_spw_time_code_c 1 0 0 0 0 0 0 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send |
Name state_fct_send.001 |
state_fct_send.000 0 |
state_fct_send.001 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p |
Name state_fct_send_p.000 state_fct_send_p.010 state_fct_send_p.001 |
state_fct_send_p.001 0 0 0 |
state_fct_send_p.000 1 0 1 |
state_fct_send_p.010 0 1 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p |
Name state_fct_p.011 state_fct_p.010 state_fct_p.001 state_fct_p.000 state_fct_p.100 |
state_fct_p.000 0 0 0 0 0 |
state_fct_p.001 0 0 1 1 0 |
state_fct_p.010 0 1 0 1 0 |
state_fct_p.011 1 0 0 1 0 |
state_fct_p.100 0 0 0 1 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write |
Name state_data_write.00 state_data_write.10 state_data_write.01 |
state_data_write.00 0 0 0 |
state_data_write.01 1 0 1 |
state_data_write.10 1 1 0 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive |
Name state_fct_receive.011 state_fct_receive.010 state_fct_receive.001 state_fct_receive.000 state_fct_receive.100 |
state_fct_receive.000 0 0 0 0 0 |
state_fct_receive.001 0 0 1 1 0 |
state_fct_receive.010 0 1 0 1 0 |
state_fct_receive.011 1 0 0 1 0 |
state_fct_receive.100 0 0 0 1 1 |
|
State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm |
Name state_fsm.error_reset state_fsm.run state_fsm.connecting state_fsm.started state_fsm.ready state_fsm.error_wait |
state_fsm.error_reset 0 0 0 0 0 0 |
/spw_fifo_ulight.sta.qmsg
1,58 → 1,58
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1505474300667 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition " "Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1505474300677 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 15 08:18:16 2017 " "Processing started: Fri Sep 15 08:18:16 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1505474300677 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474300677 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474300678 ""} |
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474300762 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302382 ""} |
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302382 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302439 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302439 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474302585 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474310743 ""} |
{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474311778 ""} |
{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474311869 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474311944 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474311944 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474312732 ""} |
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474314242 ""} |
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474314279 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.196 " "Worst-case setup slack is 1.196" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314528 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.196 0.000 FPGA_CLK1_50 " " 1.196 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314528 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314528 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.271 " "Worst-case hold slack is 0.271" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314573 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.271 0.000 FPGA_CLK1_50 " " 0.271 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314573 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314573 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 4.785 " "Worst-case recovery slack is 4.785" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314595 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.785 0.000 FPGA_CLK1_50 " " 4.785 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314595 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314595 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.979 " "Worst-case removal slack is 0.979" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.979 0.000 FPGA_CLK1_50 " " 0.979 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314613 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314613 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.538 " "Worst-case minimum pulse width slack is 0.538" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.538 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.538 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.597 0.000 din_a " " 0.597 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.657 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.657 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.679 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.679 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.084 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.084 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.202 0.000 FPGA_CLK1_50 " " 4.202 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474314618 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314618 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.106 ns " "Worst Case Available Settling Time: 12.106 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474314745 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314745 ""} |
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474314753 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474314901 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474322895 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474323422 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474323422 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474324158 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 1.204 " "Worst-case setup slack is 1.204" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325760 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.204 0.000 FPGA_CLK1_50 " " 1.204 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325760 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325760 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.253 " "Worst-case hold slack is 0.253" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325799 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.253 0.000 FPGA_CLK1_50 " " 0.253 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325799 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325799 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 4.852 " "Worst-case recovery slack is 4.852" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325813 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.852 0.000 FPGA_CLK1_50 " " 4.852 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325813 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325813 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.920 " "Worst-case removal slack is 0.920" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325827 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.920 0.000 FPGA_CLK1_50 " " 0.920 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325827 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325827 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.465 " "Worst-case minimum pulse width slack is 0.465" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.465 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.465 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.633 0.000 din_a " " 0.633 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.663 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.663 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.716 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.716 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.117 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.117 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.284 0.000 FPGA_CLK1_50 " " 4.284 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474325834 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325834 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.241 ns " "Worst Case Available Settling Time: 12.241 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474325905 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474325905 ""} |
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474325912 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474326188 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474334571 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474335087 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474335087 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474335856 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 4.542 " "Worst-case setup slack is 4.542" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337423 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.542 0.000 FPGA_CLK1_50 " " 4.542 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337423 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337423 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.162 " "Worst-case hold slack is 0.162" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337464 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337464 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.162 0.000 FPGA_CLK1_50 " " 0.162 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337464 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337464 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 6.857 " "Worst-case recovery slack is 6.857" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337482 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.857 0.000 FPGA_CLK1_50 " " 6.857 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337482 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337482 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.574 " "Worst-case removal slack is 0.574" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337498 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337498 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.574 0.000 FPGA_CLK1_50 " " 0.574 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337498 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337498 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.799 " "Worst-case minimum pulse width slack is 0.799" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.799 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.799 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.812 0.000 din_a " " 0.812 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.897 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.897 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.920 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.920 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.333 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.333 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.076 0.000 FPGA_CLK1_50 " " 4.076 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474337504 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337504 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.202 ns " "Worst Case Available Settling Time: 15.202 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474337576 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337576 ""} |
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1505474337586 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474337830 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474345644 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|always3~0 from: dataf to: combout " "Cell: m_x\|always3~0 from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1505474346174 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474346174 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474346947 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 5.038 " "Worst-case setup slack is 5.038" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348554 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.038 0.000 FPGA_CLK1_50 " " 5.038 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348554 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348554 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.146 " "Worst-case hold slack is 0.146" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348602 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348602 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.146 0.000 FPGA_CLK1_50 " " 0.146 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348602 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348602 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 7.031 " "Worst-case recovery slack is 7.031" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348616 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.031 0.000 FPGA_CLK1_50 " " 7.031 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348616 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348616 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.524 " "Worst-case removal slack is 0.524" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348631 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.524 0.000 FPGA_CLK1_50 " " 0.524 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348631 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348631 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.793 " "Worst-case minimum pulse width slack is 0.793" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.793 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.793 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.828 0.000 din_a " " 0.828 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.961 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " " 0.961 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.969 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.969 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.399 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.399 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.039 0.000 FPGA_CLK1_50 " " 4.039 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1505474348637 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348637 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 59 synchronizer chains. " "Report Metastability: Found 59 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 59 " "Number of Synchronizer Chains Found: 59" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.621 ns " "Worst Case Available Settling Time: 15.621 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1505474348722 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474348722 ""} |
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474350120 ""} |
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474350121 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 1 Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1351 " "Peak virtual memory: 1351 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1505474350295 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 08:19:10 2017 " "Processing ended: Fri Sep 15 08:19:10 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1505474350295 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:54 " "Elapsed time: 00:00:54" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1505474350295 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:15 " "Total CPU time (on all processors): 00:01:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1505474350295 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1505474350295 ""} |
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1517799469419 ""} |
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition " "Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1517799469450 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 5 00:57:45 2018 " "Processing started: Mon Feb 5 00:57:45 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1517799469450 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799469450 ""} |
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta spw_fifo_ulight -c spw_fifo_ulight " "Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799469451 ""} |
{ "Info" "0" "" "qsta_default_script.tcl version: #3" { } { } 0 0 "qsta_default_script.tcl version: #3" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799471769 ""} |
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473399 ""} |
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473399 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473513 ""} |
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799473513 ""} |
{ "Info" "ISTA_SDC_FOUND" "sdc/spw_fifo_ulight.out.sdc " "Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799474925 ""} |
{ "Info" "ISTA_SDC_FOUND" "ulight_fifo/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799475012 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799475087 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799475087 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799480099 ""} |
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799485632 ""} |
{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799485658 ""} |
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799486065 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486065 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.369 " "Worst-case setup slack is -4.369" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.369 -113.702 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -4.369 -113.702 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.697 -1112.931 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -3.697 -1112.931 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.138 -13.527 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -3.138 -13.527 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.473 -27.460 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -2.473 -27.460 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.037 -45.867 din_a " " -2.037 -45.867 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.110 -2.017 FPGA_CLK1_50 " " -1.110 -2.017 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486066 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486066 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.322 " "Worst-case hold slack is 0.322" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.322 0.000 FPGA_CLK1_50 " " 0.322 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.336 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.336 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.393 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.393 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.470 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.470 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.547 0.000 din_a " " 0.547 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.624 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.624 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486139 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486139 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.289 " "Worst-case recovery slack is -0.289" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.289 -4.795 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -0.289 -4.795 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.248 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 5.248 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.466 0.000 FPGA_CLK1_50 " " 14.466 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486164 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486164 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.563 " "Worst-case removal slack is 0.563" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.563 0.000 FPGA_CLK1_50 " " 0.563 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.308 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.308 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.746 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.746 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486188 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486188 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.533 " "Worst-case minimum pulse width slack is 0.533" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.533 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.533 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.575 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.575 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.994 0.000 din_a " " 0.994 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.301 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.301 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.952 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 3.952 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.195 0.000 FPGA_CLK1_50 " " 9.195 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799486194 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486194 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.091 ns " "Worst Case Available Settling Time: 12.091 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799486396 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486396 ""} |
{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799486609 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799486697 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799497651 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799498179 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799498179 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799503229 ""} |
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799509026 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509026 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.207 " "Worst-case setup slack is -4.207" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.207 -109.829 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -4.207 -109.829 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.461 -1038.103 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -3.461 -1038.103 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.976 -12.650 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -2.976 -12.650 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.359 -27.122 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -2.359 -27.122 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.919 -41.436 din_a " " -1.919 -41.436 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.765 -1.140 FPGA_CLK1_50 " " -0.765 -1.140 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509027 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.211 " "Worst-case hold slack is 0.211" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.211 0.000 FPGA_CLK1_50 " " 0.211 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.325 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.325 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.388 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.388 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.478 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.478 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.530 0.000 din_a " " 0.530 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.599 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.599 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509091 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509091 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.346 " "Worst-case recovery slack is -0.346" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.346 -5.707 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -0.346 -5.707 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 5.377 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 5.377 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 14.772 0.000 FPGA_CLK1_50 " " 14.772 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509113 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509113 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.464 " "Worst-case removal slack is 0.464" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.464 0.000 FPGA_CLK1_50 " " 0.464 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.288 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 1.288 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.777 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.777 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509140 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509140 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.499 " "Worst-case minimum pulse width slack is 0.499" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.499 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.499 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.523 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.523 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.986 0.000 din_a " " 0.986 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.324 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.324 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.980 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 3.980 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.277 0.000 FPGA_CLK1_50 " " 9.277 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799509146 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509146 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 12.233 ns " "Worst Case Available Settling Time: 12.233 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799509251 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509251 ""} |
{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799509304 ""} |
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799509697 ""} |
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799519796 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799520325 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799520325 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799525307 ""} |
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799530934 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799530934 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.086 " "Worst-case setup slack is -2.086" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.086 -3.029 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -2.086 -3.029 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.935 -13.800 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -1.935 -13.800 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.826 -329.386 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -1.826 -329.386 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.068 -12.429 din_a " " -1.068 -12.429 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.558 -5.149 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -0.558 -5.149 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.405 -0.405 FPGA_CLK1_50 " " -0.405 -0.405 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799530935 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799530935 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.122 " "Worst-case hold slack is 0.122" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.122 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.122 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.175 0.000 FPGA_CLK1_50 " " 0.175 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.179 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.217 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.217 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.242 0.000 din_a " " 0.242 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.302 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.302 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531001 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531001 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.648 " "Worst-case recovery slack is 0.648" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.648 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.648 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 6.842 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 6.842 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 16.136 0.000 FPGA_CLK1_50 " " 16.136 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531027 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531027 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.424 " "Worst-case removal slack is 0.424" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.424 0.000 FPGA_CLK1_50 " " 0.424 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.665 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.665 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.750 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.750 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531055 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531055 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.732 " "Worst-case minimum pulse width slack is 0.732" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.732 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.732 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.833 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.833 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.215 0.000 din_a " " 1.215 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.480 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.480 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.240 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 4.240 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.073 0.000 FPGA_CLK1_50 " " 9.073 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799531061 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531061 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 14.729 ns " "Worst Case Available Settling Time: 14.729 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799531167 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531167 ""} |
{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1517799531222 ""} |
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout " "Cell: A_SPW_TOP\|SPW\|RX\|comb from: dataf to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: m_x\|comb from: dataa to: combout " "Cell: m_x\|comb from: dataa to: combout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457 " "From: u0\|hps_0\|fpga_interfaces\|hps2fpga\|clk to: ulight_fifo:u0\|ulight_fifo_hps_0:hps_0\|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces\|hps2fpga~FF_3457" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter from: vco0ph\[0\] to: divclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|REFCLK_SELECT from: clkin\[0\] to: clkout" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk " "Cell: u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll from: refclkin to: fbclk" { } { } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1517799531779 ""} } { } 0 332097 "The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799531779 ""} |
{ "Info" "ISTA_IGNORED_CLOCK_UNCERTAINTY" "" "The following assignments are ignored by the derive_clock_uncertainty command" { } { } 0 332152 "The following assignments are ignored by the derive_clock_uncertainty command" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799536621 ""} |
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1517799542119 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542119 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.794 " "Worst-case setup slack is -1.794" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.794 -2.071 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " -1.794 -2.071 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.717 -6.939 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " -1.717 -6.939 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.507 -230.983 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " -1.507 -230.983 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.704 -5.641 din_a " " -0.704 -5.641 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.395 -3.443 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " -0.395 -3.443 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.113 -0.113 FPGA_CLK1_50 " " -0.113 -0.113 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542120 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542120 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.104 " "Worst-case hold slack is 0.104" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.104 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.104 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.164 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.164 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.166 0.000 FPGA_CLK1_50 " " 0.166 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.199 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.199 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.208 0.000 din_a " " 0.208 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.263 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.263 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542183 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542183 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.654 " "Worst-case recovery slack is 0.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.654 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.654 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 7.148 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 7.148 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 16.628 0.000 FPGA_CLK1_50 " " 16.628 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542205 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542205 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.327 " "Worst-case removal slack is 0.327" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.327 0.000 FPGA_CLK1_50 " " 0.327 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.616 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 0.616 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.684 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 0.684 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542234 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542234 ""} |
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 0.757 " "Worst-case minimum pulse width slack is 0.757" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.757 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " " 0.757 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.823 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " " 0.823 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|counter\[0\].output_counter\|divclk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " " 1.250 0.000 u0\|pll_0\|altera_pll_i\|cyclonev_pll\|fpll_0\|fpll\|vcoph\[0\] " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.293 0.000 din_a " " 1.293 0.000 din_a " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.525 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " " 1.525 0.000 spw_ulight_con_top_x:A_SPW_TOP\|top_spw_ultra_light:SPW\|TX_SPW:TX\|tx_fsm_m:tx_fsm\|tx_dout_e " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 4.335 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " " 4.335 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ\|clk_100_reduced_i " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 9.039 0.000 FPGA_CLK1_50 " " 9.039 0.000 FPGA_CLK1_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1517799542244 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542244 ""} |
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 49 synchronizer chains. " "Report Metastability: Found 49 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 49 " "Number of Synchronizer Chains Found: 49" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 15.223 ns " "Worst Case Available Settling Time: 15.223 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1517799542362 ""} } { } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799542362 ""} |
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799544068 ""} |
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799544068 ""} |
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1444 " "Peak virtual memory: 1444 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1517799544184 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 5 00:59:04 2018 " "Processing ended: Mon Feb 5 00:59:04 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1517799544184 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:19 " "Elapsed time: 00:01:19" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1517799544184 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:24 " "Total CPU time (on all processors): 00:01:24" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1517799544184 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1517799544184 ""} |
/spw_fifo_ulight.sta.rdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.sta_cmp.6_slow_1100mv_85c.tdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.tis_db_list.ddb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.tiscmp.fast_1100mv_0c.ddb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.tiscmp.fast_1100mv_85c.ddb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.tiscmp.slow_1100mv_0c.ddb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.tiscmp.slow_1100mv_85c.ddb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.tmw_info
1,7 → 1,4
start_full_compilation:s:00:11:43 |
start_analysis_synthesis:s:00:05:29-start_full_compilation |
start_analysis_elaboration:s-start_full_compilation |
start_fitter:s:00:04:45-start_full_compilation |
start_assembler:s:00:00:24-start_full_compilation |
start_timing_analyzer:s:00:00:55-start_full_compilation |
start_eda_netlist_writer:s:00:00:10-start_full_compilation |
start_full_compilation:s |
start_assembler:s-start_full_compilation |
start_timing_analyzer:s-start_full_compilation |
start_eda_netlist_writer:s-start_full_compilation |
/spw_fifo_ulight.vpr.ammdb
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight_partition_pins.json
4,15 → 4,15
"name" : "Top", |
"pins" : [ |
{ |
"name" : "dout_a", |
"name" : "LED[5]", |
"strict" : false |
}, |
{ |
"name" : "sout_a", |
"name" : "dout_a", |
"strict" : false |
}, |
{ |
"name" : "LED[5]", |
"name" : "sout_a", |
"strict" : false |
}, |
{ |