URL
https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
Subversion Repositories spacewiresystemc
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewiresystemc/trunk/altera_work/spw_fifo_ulight/output_files
- from Rev 35 to Rev 40
- ↔ Reverse comparison
Rev 35 → Rev 40
/spw_fifo_ulight.asm.rpt
1,6 → 1,6
Assembler report for spw_fifo_ulight |
Fri Sep 15 08:18:15 2017 |
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Mon Feb 5 00:57:44 2018 |
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
|
|
--------------------- |
26,12 → 26,11
associated documentation or information are expressly subject |
to the terms and conditions of the Intel Program License |
Subscription Agreement, the Intel Quartus Prime License Agreement, |
the Intel MegaCore Function License Agreement, or other |
applicable license agreement, including, without limitation, |
that your use is for the sole purpose of programming logic |
devices manufactured by Intel and sold by Intel or its |
authorized distributors. Please refer to the applicable |
agreement for further details. |
the Intel FPGA IP License Agreement, or other applicable license |
agreement, including, without limitation, that your use is for |
the sole purpose of programming logic devices manufactured by |
Intel and sold by Intel or its authorized distributors. Please |
refer to the applicable agreement for further details. |
|
|
|
38,7 → 37,7
+---------------------------------------------------------------+ |
; Assembler Summary ; |
+-----------------------+---------------------------------------+ |
; Assembler Status ; Successful - Fri Sep 15 08:18:15 2017 ; |
; Assembler Status ; Successful - Mon Feb 5 00:57:44 2018 ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
67,8 → 66,8
+----------------+------------------------------+ |
; Option ; Setting ; |
+----------------+------------------------------+ |
; JTAG usercode ; 0x00BA1C35 ; |
; Checksum ; 0x00BA1C35 ; |
; JTAG usercode ; 0x00C20F9D ; |
; Checksum ; 0x00C20F9D ; |
+----------------+------------------------------+ |
|
|
77,16 → 76,16
+--------------------+ |
Info: ******************************************************************* |
Info: Running Quartus Prime Assembler |
Info: Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Info: Processing started: Fri Sep 15 08:17:57 2017 |
Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
Info: Processing started: Mon Feb 5 00:57:25 2018 |
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight |
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. |
Info (115030): Assembler is generating device programming files |
Info (11878): Hard Processor Subsystem configuration has not changed and a Preloader software update is not required |
Info: Quartus Prime Assembler was successful. 0 errors, 1 warning |
Info: Peak virtual memory: 1040 megabytes |
Info: Processing ended: Fri Sep 15 08:18:15 2017 |
Info: Elapsed time: 00:00:18 |
Info: Total CPU time (on all processors): 00:00:12 |
Info: Peak virtual memory: 1044 megabytes |
Info: Processing ended: Mon Feb 5 00:57:44 2018 |
Info: Elapsed time: 00:00:19 |
Info: Total CPU time (on all processors): 00:00:11 |
|
|
/spw_fifo_ulight.done
1,16 → 76,16
Fri Sep 15 08:19:39 2017 |
Mon Feb 5 00:59:13 2018 |
/spw_fifo_ulight.eda.rpt
1,6 → 1,6
EDA Netlist Writer report for spw_fifo_ulight |
Fri Sep 15 08:19:20 2017 |
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Mon Feb 5 00:59:12 2018 |
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
|
|
--------------------- |
8,8 → 8,8
--------------------- |
1. Legal Notice |
2. EDA Netlist Writer Summary |
3. Simulation Settings |
4. Simulation Generated Files |
3. Board-Level Settings |
4. Board-Level Generated Files |
5. EDA Netlist Writer Messages |
|
|
25,55 → 25,90
associated documentation or information are expressly subject |
to the terms and conditions of the Intel Program License |
Subscription Agreement, the Intel Quartus Prime License Agreement, |
the Intel MegaCore Function License Agreement, or other |
applicable license agreement, including, without limitation, |
that your use is for the sole purpose of programming logic |
devices manufactured by Intel and sold by Intel or its |
authorized distributors. Please refer to the applicable |
agreement for further details. |
the Intel FPGA IP License Agreement, or other applicable license |
agreement, including, without limitation, that your use is for |
the sole purpose of programming logic devices manufactured by |
Intel and sold by Intel or its authorized distributors. Please |
refer to the applicable agreement for further details. |
|
|
|
+-------------------------------------------------------------------+ |
; EDA Netlist Writer Summary ; |
+---------------------------+---------------------------------------+ |
; EDA Netlist Writer Status ; Successful - Fri Sep 15 08:19:20 2017 ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Simulation Files Creation ; Successful ; |
+---------------------------+---------------------------------------+ |
+-------------------------------------------------------------------------------+ |
; EDA Netlist Writer Summary ; |
+---------------------------------------+---------------------------------------+ |
; EDA Netlist Writer Status ; Successful - Mon Feb 5 00:59:12 2018 ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Board Signal Integrity Files Creation ; Successful ; |
; Board Timing Analysis Files Creation ; Successful ; |
+---------------------------------------+---------------------------------------+ |
|
|
+-------------------------------------------------------------------------------------------------------------------------------+ |
; Simulation Settings ; |
+---------------------------------------------------------------------------------------------------+---------------------------+ |
; Option ; Setting ; |
+---------------------------------------------------------------------------------------------------+---------------------------+ |
; Tool Name ; ModelSim-Altera (Verilog) ; |
; Generate functional simulation netlist ; Off ; |
; Time scale ; 1 ps ; |
; Truncate long hierarchy paths ; Off ; |
; Map illegal HDL characters ; Off ; |
; Flatten buses into individual nodes ; Off ; |
; Maintain hierarchy ; Off ; |
; Bring out device-wide set/reset signals as ports ; Off ; |
; Enable glitch filtering ; Off ; |
; Do not write top level VHDL entity ; Off ; |
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; |
; Architecture name in VHDL output netlist ; structure ; |
; Generate third-party EDA tool command script for RTL functional simulation ; Off ; |
; Generate third-party EDA tool command script for gate-level simulation ; Off ; |
+---------------------------------------------------------------------------------------------------+---------------------------+ |
+-----------------------------------------+ |
; Board-Level Settings ; |
+-------------------------------+---------+ |
; Option ; Setting ; |
+-------------------------------+---------+ |
; Board Signal Integrity Format ; HSPICE ; |
; Board Timing Analysis Format ; STAMP ; |
+-------------------------------+---------+ |
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------+ |
; Simulation Generated Files ; |
+---------------------------------------------------------------------------------------------------------------------------------------------+ |
; Generated Files ; |
+---------------------------------------------------------------------------------------------------------------------------------------------+ |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/simulation/modelsim/spw_fifo_ulight.vo ; |
+---------------------------------------------------------------------------------------------------------------------------------------------+ |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Board-Level Generated Files ; |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Generated Files ; |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Board Signal Integrity ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc ; |
; Board Timing Analysis ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod ; |
; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data ; |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
+-----------------------------+ |
81,16 → 116,56
+-----------------------------+ |
Info: ******************************************************************* |
Info: Running Quartus Prime EDA Netlist Writer |
Info: Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Info: Processing started: Fri Sep 15 08:19:12 2017 |
Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
Info: Processing started: Mon Feb 5 00:59:06 2018 |
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight |
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. |
Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device. |
Info (204019): Generated file spw_fifo_ulight.vo in folder "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/simulation/modelsim/" for EDA simulation tool |
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings |
Info: Peak virtual memory: 1314 megabytes |
Info: Processing ended: Fri Sep 15 08:19:20 2017 |
Info: Elapsed time: 00:00:08 |
Info: Total CPU time (on all processors): 00:00:08 |
Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_85c_board_slow.data" |
Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_6_1100mv_0c_board_slow.data" |
Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_0c_board_fast.data" |
Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_min_1100mv_85c_board_fast.data" |
Info (199047): Generated files "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.mod" and "/home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/timing/stamp//spw_fifo_ulight_board.data" |
Info (199053): Generated 36 HSPICE Output files for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae26_led_5__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa23_led_7__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ag28_dout_a_out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af20_sout_a_out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_w15_led_0__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_aa24_led_1__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v16_led_2__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_v15_led_3__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_af26_led_4__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah17_key_0__in.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y16_led_6__out.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y13_fpga_clk1_50_in.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ah16_key_1__in.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_y15_din_a_in.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/5csema4_ae20_sin_a_in.sp for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrt_calibrated.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/output_delay_control.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_vod_select.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/lvds_preemphasis_select.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/slew_rate_control.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/drive_select_io.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ss.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_input_load.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_tt.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrt.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_load.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_oct_rd.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_octrs_calibrated.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/io_load.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/lvds_output_load.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/package.lib for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_load.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/cir/io_buffer_octrs.inc for board level analysis |
Info (199051): Generated HSPICE Output File /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/board/hspice/lib/cv_ff.inc for board level analysis |
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning |
Info: Peak virtual memory: 1244 megabytes |
Info: Processing ended: Mon Feb 5 00:59:13 2018 |
Info: Elapsed time: 00:00:07 |
Info: Total CPU time (on all processors): 00:00:06 |
|
|
/spw_fifo_ulight.fit.rpt
1,6 → 1,6
Fitter report for spw_fifo_ulight |
Fri Sep 15 08:17:49 2017 |
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Mon Feb 5 00:57:17 2018 |
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
|
|
--------------------- |
54,39 → 54,38
associated documentation or information are expressly subject |
to the terms and conditions of the Intel Program License |
Subscription Agreement, the Intel Quartus Prime License Agreement, |
the Intel MegaCore Function License Agreement, or other |
applicable license agreement, including, without limitation, |
that your use is for the sole purpose of programming logic |
devices manufactured by Intel and sold by Intel or its |
authorized distributors. Please refer to the applicable |
agreement for further details. |
the Intel FPGA IP License Agreement, or other applicable license |
agreement, including, without limitation, that your use is for |
the sole purpose of programming logic devices manufactured by |
Intel and sold by Intel or its authorized distributors. Please |
refer to the applicable agreement for further details. |
|
|
|
+-------------------------------------------------------------------------------+ |
; Fitter Summary ; |
+---------------------------------+---------------------------------------------+ |
; Fitter Status ; Successful - Fri Sep 15 08:17:49 2017 ; |
; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Device ; 5CSEMA4U23C6 ; |
; Timing Models ; Final ; |
; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ; |
; Total registers ; 4692 ; |
; Total pins ; 19 / 314 ( 6 % ) ; |
; Total virtual pins ; 0 ; |
; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ; |
; Total RAM Blocks ; 0 / 270 ( 0 % ) ; |
; Total DSP Blocks ; 0 / 84 ( 0 % ) ; |
; Total HSSI RX PCSs ; 0 ; |
; Total HSSI PMA RX Deserializers ; 0 ; |
; Total HSSI TX PCSs ; 0 ; |
; Total HSSI PMA TX Serializers ; 0 ; |
; Total PLLs ; 1 / 5 ( 20 % ) ; |
; Total DLLs ; 0 / 4 ( 0 % ) ; |
+---------------------------------+---------------------------------------------+ |
+----------------------------------------------------------------------------------------+ |
; Fitter Summary ; |
+---------------------------------+------------------------------------------------------+ |
; Fitter Status ; Successful - Mon Feb 5 00:57:17 2018 ; |
; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Device ; 5CSEMA4U23C6 ; |
; Timing Models ; Final ; |
; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ; |
; Total registers ; 4633 ; |
; Total pins ; 19 / 314 ( 6 % ) ; |
; Total virtual pins ; 0 ; |
; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ; |
; Total RAM Blocks ; 0 / 270 ( 0 % ) ; |
; Total DSP Blocks ; 0 / 84 ( 0 % ) ; |
; Total HSSI RX PCSs ; 0 ; |
; Total HSSI PMA RX Deserializers ; 0 ; |
; Total HSSI TX PCSs ; 0 ; |
; Total HSSI PMA TX Serializers ; 0 ; |
; Total PLLs ; 1 / 5 ( 20 % ) ; |
; Total DLLs ; 0 / 4 ( 0 % ) ; |
+---------------------------------+------------------------------------------------------+ |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
98,14 → 97,18
; Minimum Core Junction Temperature ; 0 ; ; |
; Maximum Core Junction Temperature ; 85 ; ; |
; Router Timing Optimization Level ; MAXIMUM ; Normal ; |
; Placement Effort Multiplier ; 90.0 ; 1.0 ; |
; PowerPlay Power Optimization During Fitting ; Extra effort ; Normal compilation ; |
; Optimize IOC Register Placement for Timing ; Off ; Normal ; |
; Fitter Initial Placement Seed ; 893763639 ; 1 ; |
; Auto Delay Chains ; Off ; On ; |
; Placement Effort Multiplier ; 4.0 ; 1.0 ; |
; Auto RAM to MLAB Conversion ; Off ; On ; |
; Power Optimization During Fitting ; Extra effort ; Normal compilation ; |
; Optimize IOC Register Placement for Timing ; Pack All IO Registers ; Normal ; |
; Auto Delay Chains for High Fanout Input Pins ; On ; Off ; |
; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ; |
; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ; |
; Perform Asynchronous Signal Pipelining ; On ; Off ; |
; Physical Synthesis Effort Level ; Extra ; Normal ; |
; Logic Cell Insertion - Logic Duplication ; Off ; Auto ; |
; Auto Register Duplication ; Off ; Auto ; |
; Optimize Design for Metastability ; Off ; On ; |
; Use smart compilation ; Off ; Off ; |
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; |
; Enable compact report table ; Off ; Off ; |
113,7 → 116,6
; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ; |
; Optimize Hold Timing ; All Paths ; All Paths ; |
; Optimize Multi-Corner Timing ; On ; On ; |
; Auto RAM to MLAB Conversion ; On ; On ; |
; Equivalent RAM and MLAB Power Up ; Auto ; Auto ; |
; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ; |
; SSN Optimization ; Off ; Off ; |
122,17 → 124,15
; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; |
; Final Placement Optimizations ; Automatically ; Automatically ; |
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; |
; Fitter Initial Placement Seed ; 1 ; 1 ; |
; Periphery to Core Placement and Routing Optimization ; Off ; Off ; |
; Weak Pull-Up Resistor ; Off ; Off ; |
; Enable Bus-Hold Circuitry ; Off ; Off ; |
; Auto Packed Registers ; Auto ; Auto ; |
; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; |
; Auto Delay Chains ; On ; On ; |
; Treat Bidirectional Pin as Output Pin ; Off ; Off ; |
; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; |
; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; |
; Perform Register Duplication for Performance ; Off ; Off ; |
; Perform Register Retiming for Performance ; Off ; Off ; |
; Perform Asynchronous Signal Pipelining ; Off ; Off ; |
; Fitter Effort ; Auto Fit ; Auto Fit ; |
; Auto Global Clock ; On ; On ; |
; Auto Global Register Control Signals ; On ; On ; |
139,7 → 139,6
; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; |
; Synchronizer Identification ; Auto ; Auto ; |
; Enable Beneficial Skew Optimization ; On ; On ; |
; Optimize Design for Metastability ; On ; On ; |
; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ; |
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; |
; Clamping Diode ; Off ; Off ; |
156,25 → 155,207
; Number detected on machine ; 4 ; |
; Maximum allowed ; 2 ; |
; ; ; |
; Average used ; 1.02 ; |
; Average used ; 1.09 ; |
; Maximum used ; 2 ; |
; ; ; |
; Usage by Processor ; % Time Used ; |
; Processor 1 ; 100.0% ; |
; Processor 2 ; 2.2% ; |
; Processor 2 ; 9.1% ; |
+----------------------------+-------------+ |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Fitter Netlist Optimizations ; |
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+ |
; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; |
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+ |
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; |
; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; |
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------+-----------+----------------------------+-----------+----------------+------------------+------------------+-----------------------+ |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Fitter Netlist Optimizations ; |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+ |
; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+ |
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; |
; FPGA_CLK1_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~41 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Add1~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|Equal2~1_RESYN160_BDD161 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|LessThan16~1_RESYN126_BDD127 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~4_RESYN148_BDD149 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~5_RESYN150_BDD151 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i~7_RESYN152_BDD153 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN138_BDD139 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~0_RESYN140_BDD141 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~53 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~56 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~66 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~97_RESYN164_BDD165 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~98_RESYN166_BDD167 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~99 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter~100_RESYN168_BDD169 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; debounce_db:db_system_spwulight_b|Add0~62 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; debounce_db:db_system_spwulight_b|counter~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|always5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|always5~1_RESYN162_BDD163 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|always5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|counter_neg:cnt_neg|Selector3~0_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; detector_tokens:m_x|counter_neg:cnt_neg|Selector5~1_RESYN170_BDD171 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add0~42 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add5~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Add7~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Selector18~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|rd_ptr~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add1~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Add2~26 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6_RESYN58_BDD59 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7_RESYN60_BDD61 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8_RESYN62_BDD63 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9_RESYN64_BDD65 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10_RESYN66_BDD67 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11_RESYN68_BDD69 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12_RESYN70_BDD71 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns~7 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|always2~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13_RESYN72_BDD73 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector3~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~1_RESYN104_BDD105 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|Selector5~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1_RESYN154_BDD155 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1_RESYN156_BDD157 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0_RESYN158_BDD159 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Equal4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|Selector7~1_RESYN128_BDD129 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ShiftRight1~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|char_sent~4_RESYN146_BDD147 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx~1_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~14 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~15 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift[0]~16_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~7 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~8 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|result_shift~9_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~18_RESYN130_BDD131 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~21_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN132_BDD133 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~23_RESYN134_BDD135 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~25_RESYN136_BDD137 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~28 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last~1_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~1_RESYN120_BDD121 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~3_RESYN122_BDD123 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout~4_RESYN124_BDD125 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|Selector15~1_RESYN142_BDD143 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~0_RESYN144_BDD145 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~3_RESYN76_BDD77 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p~5_RESYN78_BDD79 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~10_RESYN80_BDD81 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.000~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~9_RESYN98_BDD99 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~10_RESYN100_BDD101 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN108_BDD109 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~12_RESYN110_BDD111 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~13_RESYN112_BDD113 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~14_RESYN114_BDD115 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~0_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector3~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~0_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|Selector4~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~2_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~3_RESYN84_BDD85 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~4 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag~5_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|Add0~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|d0_int_nxt_addr[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0]~_Duplicate_1 ; Q ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[0]~output ; I ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1]~_Duplicate_1 ; Q ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[1]~output ; I ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2]~_Duplicate_1 ; Q ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[2]~output ; I ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3]~_Duplicate_1 ; Q ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[3]~output ; I ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4]~_Duplicate_1 ; Q ; ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|data_out[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LED[4]~output ; I ; ; |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+----------------------------+-----------+----------------+-------------------------------------------------------------------------------+------------------+-----------------------+ |
|
|
+---------------------------------------------------------------------------------------------+ |
187,19 → 368,19
+--------------+-----------------+--------------+------------+---------------+----------------+ |
|
|
+---------------------------------------------------------------------------------------------------+ |
; Incremental Compilation Preservation Summary ; |
+---------------------+---------------------+----------------------------+--------------------------+ |
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; |
+---------------------+---------------------+----------------------------+--------------------------+ |
; Placement (by node) ; ; ; ; |
; -- Requested ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; |
; -- Achieved ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; 0.00 % ( 0 / 9969 ) ; |
; ; ; ; ; |
; Routing (by net) ; ; ; ; |
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; |
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; |
+---------------------+---------------------+----------------------------+--------------------------+ |
+----------------------------------------------------------------------------------------------------+ |
; Incremental Compilation Preservation Summary ; |
+---------------------+----------------------+----------------------------+--------------------------+ |
; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ; |
+---------------------+----------------------+----------------------------+--------------------------+ |
; Placement (by node) ; ; ; ; |
; -- Requested ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; |
; -- Achieved ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; 0.00 % ( 0 / 10083 ) ; |
; ; ; ; ; |
; Routing (by net) ; ; ; ; |
; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; |
; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; |
+---------------------+----------------------+----------------------------+--------------------------+ |
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
217,7 → 398,7
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ |
; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ; |
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ |
; Top ; 0.00 % ( 0 / 9951 ) ; N/A ; Source File ; N/A ; ; |
; Top ; 0.00 % ( 0 / 10065 ) ; N/A ; Source File ; N/A ; ; |
; hard_block:auto_generated_inst ; 0.00 % ( 0 / 18 ) ; N/A ; Source File ; N/A ; ; |
+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+ |
|
233,40 → 414,40
+-------------------------------------------------------------+-----------------------+-------+ |
; Resource ; Usage ; % ; |
+-------------------------------------------------------------+-----------------------+-------+ |
; Logic utilization (ALMs needed / total ALMs on device) ; 3,209 / 15,880 ; 20 % ; |
; ALMs needed [=A-B+C] ; 3,209 ; ; |
; [A] ALMs used in final placement [=a+b+c+d] ; 3,800 / 15,880 ; 24 % ; |
; [a] ALMs used for LUT logic and registers ; 1,607 ; ; |
; [b] ALMs used for LUT logic ; 1,468 ; ; |
; [c] ALMs used for registers ; 725 ; ; |
; Logic utilization (ALMs needed / total ALMs on device) ; 3,362 / 15,880 ; 21 % ; |
; ALMs needed [=A-B+C] ; 3,362 ; ; |
; [A] ALMs used in final placement [=a+b+c+d] ; 3,835 / 15,880 ; 24 % ; |
; [a] ALMs used for LUT logic and registers ; 1,626 ; ; |
; [b] ALMs used for LUT logic ; 1,539 ; ; |
; [c] ALMs used for registers ; 670 ; ; |
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ; |
; [B] Estimate of ALMs recoverable by dense packing ; 601 / 15,880 ; 4 % ; |
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 10 / 15,880 ; < 1 % ; |
; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15,880 ; 3 % ; |
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15,880 ; < 1 % ; |
; [a] Due to location constrained logic ; 0 ; ; |
; [b] Due to LAB-wide signal conflicts ; 5 ; ; |
; [c] Due to LAB input limits ; 5 ; ; |
; [b] Due to LAB-wide signal conflicts ; 10 ; ; |
; [c] Due to LAB input limits ; 6 ; ; |
; [d] Due to virtual I/Os ; 0 ; ; |
; ; ; ; |
; Difficulty packing design ; Low ; ; |
; ; ; ; |
; Total LABs: partially or completely used ; 455 / 1,588 ; 29 % ; |
; -- Logic LABs ; 455 ; ; |
; Total LABs: partially or completely used ; 464 / 1,588 ; 29 % ; |
; -- Logic LABs ; 464 ; ; |
; -- Memory LABs (up to half of total LABs) ; 0 ; ; |
; ; ; ; |
; Combinational ALUT usage for logic ; 5,301 ; ; |
; -- 7 input functions ; 59 ; ; |
; -- 6 input functions ; 1,198 ; ; |
; -- 5 input functions ; 825 ; ; |
; -- 4 input functions ; 1,419 ; ; |
; -- <=3 input functions ; 1,800 ; ; |
; Combinational ALUT usage for route-throughs ; 473 ; ; |
; Combinational ALUT usage for logic ; 5,522 ; ; |
; -- 7 input functions ; 72 ; ; |
; -- 6 input functions ; 1,329 ; ; |
; -- 5 input functions ; 874 ; ; |
; -- 4 input functions ; 1,532 ; ; |
; -- <=3 input functions ; 1,715 ; ; |
; Combinational ALUT usage for route-throughs ; 415 ; ; |
; ; ; ; |
; Dedicated logic registers ; 4,692 ; ; |
; Dedicated logic registers ; 4,628 ; ; |
; -- By type: ; ; ; |
; -- Primary logic registers ; 4,664 / 31,760 ; 15 % ; |
; -- Secondary logic registers ; 28 / 31,760 ; < 1 % ; |
; -- Primary logic registers ; 4,592 / 31,760 ; 14 % ; |
; -- Secondary logic registers ; 36 / 31,760 ; < 1 % ; |
; -- By function: ; ; ; |
; -- Design implementation registers ; 4,692 ; ; |
; -- Design implementation registers ; 4,628 ; ; |
; -- Routing optimization registers ; 0 ; ; |
; ; ; ; |
; Virtual pins ; 0 ; ; |
273,6 → 454,7
; I/O pins ; 19 / 314 ; 6 % ; |
; -- Clock pins ; 2 / 6 ; 33 % ; |
; -- Dedicated input pins ; 0 / 21 ; 0 % ; |
; I/O registers ; 5 ; ; |
; ; ; ; |
; Hard processor system peripheral utilization ; ; ; |
; -- Boot from FPGA ; 1 / 1 ( 100 % ) ; ; |
310,7 → 492,7
; ; ; ; |
; Fractional PLLs ; 1 / 5 ; 20 % ; |
; Global signals ; 4 ; ; |
; -- Global clocks ; 4 / 16 ; 25 % ; |
; -- Global clocks ; 3 / 16 ; 19 % ; |
; -- Quadrant clocks ; 0 / 72 ; 0 % ; |
; -- Horizontal periphery clocks ; 0 / 12 ; 0 % ; |
; SERDES Transmitters ; 0 / 76 ; 0 % ; |
322,12 → 504,12
; Oscillator blocks ; 0 / 1 ; 0 % ; |
; Impedance control blocks ; 0 / 3 ; 0 % ; |
; Hard Memory Controllers ; 0 / 2 ; 0 % ; |
; Average interconnect usage (total/H/V) ; 4.9% / 5.0% / 4.6% ; ; |
; Peak interconnect usage (total/H/V) ; 19.3% / 19.7% / 19.5% ; ; |
; Maximum fan-out ; 3124 ; ; |
; Highest non-global fan-out ; 1270 ; ; |
; Total fan-out ; 39487 ; ; |
; Average fan-out ; 3.76 ; ; |
; Average interconnect usage (total/H/V) ; 6.0% / 6.2% / 5.2% ; ; |
; Peak interconnect usage (total/H/V) ; 26.6% / 28.9% / 23.3% ; ; |
; Maximum fan-out ; 3073 ; ; |
; Highest non-global fan-out ; 2974 ; ; |
; Total fan-out ; 40291 ; ; |
; Average fan-out ; 3.79 ; ; |
+-------------------------------------------------------------+-----------------------+-------+ |
|
|
336,33 → 518,33
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+ |
; Statistic ; Top ; ulight_fifo_hps_0_hps_io_border:border ; hard_block:auto_generated_inst ; |
+-------------------------------------------------------------+-----------------------+----------------------------------------+--------------------------------+ |
; Logic utilization (ALMs needed / total ALMs on device) ; 3209 / 15880 ( 20 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; ALMs needed [=A-B+C] ; 3209 ; 0 ; 0 ; |
; [A] ALMs used in final placement [=a+b+c+d] ; 3800 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; [a] ALMs used for LUT logic and registers ; 1607 ; 0 ; 0 ; |
; [b] ALMs used for LUT logic ; 1468 ; 0 ; 0 ; |
; [c] ALMs used for registers ; 725 ; 0 ; 0 ; |
; Logic utilization (ALMs needed / total ALMs on device) ; 3362 / 15880 ( 21 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; ALMs needed [=A-B+C] ; 3362 ; 0 ; 0 ; |
; [A] ALMs used in final placement [=a+b+c+d] ; 3835 / 15880 ( 24 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; [a] ALMs used for LUT logic and registers ; 1626 ; 0 ; 0 ; |
; [b] ALMs used for LUT logic ; 1539 ; 0 ; 0 ; |
; [c] ALMs used for registers ; 670 ; 0 ; 0 ; |
; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ; 0 ; |
; [B] Estimate of ALMs recoverable by dense packing ; 601 / 15880 ( 4 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 10 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; [B] Estimate of ALMs recoverable by dense packing ; 489 / 15880 ( 3 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 16 / 15880 ( < 1 % ) ; 0 / 15880 ( 0 % ) ; 0 / 15880 ( 0 % ) ; |
; [a] Due to location constrained logic ; 0 ; 0 ; 0 ; |
; [b] Due to LAB-wide signal conflicts ; 5 ; 0 ; 0 ; |
; [c] Due to LAB input limits ; 5 ; 0 ; 0 ; |
; [b] Due to LAB-wide signal conflicts ; 10 ; 0 ; 0 ; |
; [c] Due to LAB input limits ; 6 ; 0 ; 0 ; |
; [d] Due to virtual I/Os ; 0 ; 0 ; 0 ; |
; ; ; ; ; |
; Difficulty packing design ; Low ; Low ; Low ; |
; ; ; ; ; |
; Total LABs: partially or completely used ; 455 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ; |
; -- Logic LABs ; 455 ; 0 ; 0 ; |
; Total LABs: partially or completely used ; 464 / 1588 ( 29 % ) ; 0 / 1588 ( 0 % ) ; 0 / 1588 ( 0 % ) ; |
; -- Logic LABs ; 464 ; 0 ; 0 ; |
; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ; 0 ; |
; ; ; ; ; |
; Combinational ALUT usage for logic ; 5301 ; 0 ; 0 ; |
; -- 7 input functions ; 59 ; 0 ; 0 ; |
; -- 6 input functions ; 1198 ; 0 ; 0 ; |
; -- 5 input functions ; 825 ; 0 ; 0 ; |
; -- 4 input functions ; 1419 ; 0 ; 0 ; |
; -- <=3 input functions ; 1800 ; 0 ; 0 ; |
; Combinational ALUT usage for route-throughs ; 473 ; 0 ; 0 ; |
; Combinational ALUT usage for logic ; 5522 ; 0 ; 0 ; |
; -- 7 input functions ; 72 ; 0 ; 0 ; |
; -- 6 input functions ; 1329 ; 0 ; 0 ; |
; -- 5 input functions ; 874 ; 0 ; 0 ; |
; -- 4 input functions ; 1532 ; 0 ; 0 ; |
; -- <=3 input functions ; 1715 ; 0 ; 0 ; |
; Combinational ALUT usage for route-throughs ; 415 ; 0 ; 0 ; |
; Memory ALUT usage ; 0 ; 0 ; 0 ; |
; -- 64-address deep ; 0 ; 0 ; 0 ; |
; -- 32-address deep ; 0 ; 0 ; 0 ; |
369,19 → 551,20
; ; ; ; ; |
; Dedicated logic registers ; 0 ; 0 ; 0 ; |
; -- By type: ; ; ; ; |
; -- Primary logic registers ; 4664 / 31760 ( 15 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ; |
; -- Secondary logic registers ; 28 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ; |
; -- Primary logic registers ; 4592 / 31760 ( 14 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ; |
; -- Secondary logic registers ; 36 / 31760 ( < 1 % ) ; 0 / 31760 ( 0 % ) ; 0 / 31760 ( 0 % ) ; |
; -- By function: ; ; ; ; |
; -- Design implementation registers ; 4692 ; 0 ; 0 ; |
; -- Design implementation registers ; 4628 ; 0 ; 0 ; |
; -- Routing optimization registers ; 0 ; 0 ; 0 ; |
; ; ; ; ; |
; ; ; ; ; |
; Virtual pins ; 0 ; 0 ; 0 ; |
; I/O pins ; 17 ; 0 ; 2 ; |
; I/O registers ; 0 ; 0 ; 0 ; |
; I/O registers ; 5 ; 0 ; 0 ; |
; Total block memory bits ; 0 ; 0 ; 0 ; |
; Total block memory implementation bits ; 0 ; 0 ; 0 ; |
; Clock enable block ; 1 / 110 ( < 1 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ; |
; Clock enable block ; 0 / 110 ( 0 % ) ; 0 / 110 ( 0 % ) ; 3 / 110 ( 2 % ) ; |
; Double data rate I/O output circuitry ; 5 / 304 ( 1 % ) ; 0 / 304 ( 0 % ) ; 0 / 304 ( 0 % ) ; |
; HPS DBG APB interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ; |
; Fractional PLL ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ; |
; HPS boot from FPGA interface ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 1 / 1 ( 100 % ) ; |
395,22 → 578,22
; PLL Reference Clock Select Block ; 0 / 5 ( 0 % ) ; 0 / 5 ( 0 % ) ; 1 / 5 ( 20 % ) ; |
; ; ; ; ; |
; Connections ; ; ; ; |
; -- Input Connections ; 4319 ; 0 ; 45 ; |
; -- Registered Input Connections ; 3150 ; 0 ; 0 ; |
; -- Output Connections ; 45 ; 0 ; 4319 ; |
; -- Input Connections ; 4377 ; 0 ; 40 ; |
; -- Registered Input Connections ; 3099 ; 0 ; 0 ; |
; -- Output Connections ; 40 ; 0 ; 4377 ; |
; -- Registered Output Connections ; 1 ; 0 ; 0 ; |
; ; ; ; ; |
; Internal Connections ; ; ; ; |
; -- Total Connections ; 39862 ; 0 ; 4401 ; |
; -- Registered Connections ; 19902 ; 0 ; 0 ; |
; -- Total Connections ; 40728 ; 0 ; 4454 ; |
; -- Registered Connections ; 23593 ; 0 ; 0 ; |
; ; ; ; ; |
; External Connections ; ; ; ; |
; -- Top ; 0 ; 0 ; 4364 ; |
; -- Top ; 0 ; 0 ; 4417 ; |
; -- ulight_fifo_hps_0_hps_io_border:border ; 0 ; 0 ; 0 ; |
; -- hard_block:auto_generated_inst ; 4364 ; 0 ; 0 ; |
; -- hard_block:auto_generated_inst ; 4417 ; 0 ; 0 ; |
; ; ; ; ; |
; Partition Interface ; ; ; ; |
; -- Input Ports ; 5 ; 0 ; 46 ; |
; -- Input Ports ; 5 ; 0 ; 41 ; |
; -- Output Ports ; 10 ; 0 ; 106 ; |
; -- Bidir Ports ; 0 ; 0 ; 0 ; |
; ; ; ; ; |
435,12 → 618,12
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ |
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ; |
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ |
; FPGA_CLK1_50 ; Y13 ; 4A ; 38 ; 0 ; 0 ; 3125 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; |
; FPGA_CLK1_50 ; Y13 ; 4A ; 38 ; 0 ; 0 ; 3074 ; 0 ; yes ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; |
; KEY[0] ; AH17 ; 4A ; 46 ; 0 ; 34 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; |
; KEY[1] ; AH16 ; 4A ; 46 ; 0 ; 51 ; 20 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; |
; din_a ; Y15 ; 4A ; 46 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; |
; KEY[1] ; AH16 ; 4A ; 46 ; 0 ; 51 ; 18 ; 0 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; -- ; User ; no ; |
; din_a ; Y15 ; 4A ; 46 ; 0 ; 0 ; 21 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; |
; din_a(n) ; AA15 ; 4A ; 46 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; |
; sin_a ; AE20 ; 4A ; 51 ; 0 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; |
; sin_a ; AE20 ; 4A ; 51 ; 0 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; |
; sin_a(n) ; AD20 ; 4A ; 51 ; 0 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; Off ; LVDS ; Off ; -- ; User ; no ; |
+--------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+ |
|
450,11 → 633,11
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ |
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ; |
+-----------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+ |
; LED[0] ; W15 ; 5A ; 68 ; 12 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[1] ; AA24 ; 5A ; 68 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[2] ; V16 ; 5A ; 68 ; 13 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[3] ; V15 ; 5A ; 68 ; 13 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[4] ; AF26 ; 5A ; 68 ; 10 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[0] ; W15 ; 5A ; 68 ; 12 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[1] ; AA24 ; 5A ; 68 ; 13 ; 37 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[2] ; V16 ; 5A ; 68 ; 13 ; 3 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[3] ; V15 ; 5A ; 68 ; 13 ; 20 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[4] ; AF26 ; 5A ; 68 ; 10 ; 77 ; yes ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[5] ; AE26 ; 5A ; 68 ; 10 ; 94 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[6] ; Y16 ; 5A ; 68 ; 12 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
; LED[7] ; AA23 ; 5A ; 68 ; 13 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; Off ; -- ; no ; no ; 0 ; Off ; User ; - ; - ; |
1190,18 → 1373,18
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll ; ; |
; -- PLL Type ; Integer PLL ; |
; -- PLL Location ; FRACTIONALPLL_X68_Y1_N0 ; |
; -- PLL Feedback clock type ; none ; |
; -- PLL Feedback clock type ; Global Clock ; |
; -- PLL Bandwidth ; Auto ; |
; -- PLL Bandwidth Range ; 2100000 to 1400000 Hz ; |
; -- Reference Clock Frequency ; 100.0 MHz ; |
; -- PLL Bandwidth Range ; 1200000 to 600000 Hz ; |
; -- Reference Clock Frequency ; 50.0 MHz ; |
; -- Reference Clock Sourced by ; Dedicated Pin ; |
; -- PLL VCO Frequency ; 400.0 MHz ; |
; -- PLL Operation Mode ; Direct ; |
; -- PLL Freq Min Lock ; 75.000000 MHz ; |
; -- PLL Freq Max Lock ; 200.000000 MHz ; |
; -- PLL Operation Mode ; Normal ; |
; -- PLL Freq Min Lock ; 37.500000 MHz ; |
; -- PLL Freq Max Lock ; 100.000000 MHz ; |
; -- PLL Enable ; On ; |
; -- PLL Fractional Division ; N/A ; |
; -- M Counter ; 8 ; |
; -- M Counter ; 16 ; |
; -- N Counter ; 2 ; |
; -- PLL Refclk Select ; ; |
; -- PLL Refclk Select Location ; PLLREFCLKSELECT_X68_Y7_N0 ; |
1235,279 → 1418,296
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+ |
; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; |
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+ |
; |SPW_ULIGHT_FIFO ; 3209.0 (0.5) ; 3800.0 (0.5) ; 601.0 (0.0) ; 10.0 (0.0) ; 0.0 (0.0) ; 5301 (1) ; 4692 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ; |
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 44.5 (44.5) ; 46.3 (46.3) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 76 (76) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ; |
; |debounce_db:db_system_spwulight_b| ; 19.0 (19.0) ; 19.0 (19.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 38 (38) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ; |
; |detector_tokens:m_x| ; 35.7 (35.7) ; 67.8 (67.8) ; 32.2 (32.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 106 (106) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ; |
; |spw_ulight_con_top_x:A_SPW_TOP| ; 764.9 (0.3) ; 1126.5 (0.5) ; 365.1 (0.2) ; 3.5 (0.0) ; 0.0 (0.0) ; 984 (1) ; 1439 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ; |
; |fifo_rx:rx_data| ; 272.4 (272.4) ; 435.3 (435.3) ; 164.4 (164.4) ; 1.5 (1.5) ; 0.0 (0.0) ; 318 (318) ; 615 (615) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ; |
; |fifo_tx:tx_data| ; 256.6 (256.6) ; 417.8 (417.8) ; 163.3 (163.3) ; 2.0 (2.0) ; 0.0 (0.0) ; 297 (297) ; 608 (608) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ; |
; |top_spw_ultra_light:SPW| ; 235.6 (0.0) ; 272.8 (0.0) ; 37.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 368 (0) ; 216 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ; |
; |FSM_SPW:FSM| ; 70.3 (70.3) ; 73.4 (73.4) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 125 (125) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ; |
; |RX_SPW:RX| ; 41.9 (41.9) ; 64.4 (64.4) ; 22.5 (22.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 68 (68) ; 109 (109) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ; |
; |TX_SPW:TX| ; 123.3 (123.3) ; 135.0 (135.0) ; 11.7 (11.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 175 (175) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ; |
; |ulight_fifo:u0| ; 2344.4 (0.0) ; 2539.8 (0.0) ; 201.9 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 4143 (0) ; 3105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ; |
; |SPW_ULIGHT_FIFO ; 3361.5 (0.5) ; 3835.0 (0.5) ; 488.5 (0.0) ; 15.0 (0.0) ; 0.0 (0.0) ; 5522 (1) ; 4628 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 19 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ; |
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 109.5 (109.5) ; 117.7 (117.7) ; 9.2 (9.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 184 (184) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ; |
; |debounce_db:db_system_spwulight_b| ; 18.5 (18.5) ; 19.5 (19.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (37) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ; |
; |detector_tokens:m_x| ; 18.8 (9.2) ; 22.5 (10.3) ; 3.7 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (18) ; 38 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ; |
; |bit_capture_control:capture_c| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c ; bit_capture_control ; work ; |
; |bit_capture_data:capture_d| ; 1.7 (1.7) ; 2.8 (2.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d ; bit_capture_data ; work ; |
; |counter_neg:cnt_neg| ; 7.3 (7.3) ; 8.3 (8.3) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg ; counter_neg ; work ; |
; |spw_ulight_con_top_x:A_SPW_TOP| ; 839.8 (0.2) ; 1146.0 (0.5) ; 315.8 (0.2) ; 9.5 (0.0) ; 0.0 (0.0) ; 1060 (1) ; 1499 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ; |
; |fifo_rx:rx_data| ; 291.7 (50.6) ; 440.5 (58.3) ; 150.3 (7.7) ; 1.5 (0.0) ; 0.0 (0.0) ; 340 (87) ; 633 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ; |
; |mem_data:mem_dta_fifo_tx| ; 241.1 (241.1) ; 382.2 (382.2) ; 142.6 (142.6) ; 1.5 (1.5) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ; |
; |fifo_tx:tx_data| ; 287.5 (31.0) ; 418.8 (32.3) ; 139.3 (1.3) ; 8.0 (0.0) ; 0.0 (0.0) ; 299 (46) ; 627 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ; |
; |mem_data:mem_dta_fifo_tx| ; 256.5 (256.5) ; 386.6 (386.6) ; 138.1 (138.1) ; 8.0 (8.0) ; 0.0 (0.0) ; 253 (253) ; 585 (585) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ; |
; |top_spw_ultra_light:SPW| ; 260.3 (0.0) ; 286.2 (0.0) ; 25.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 420 (0) ; 239 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ; |
; |FSM_SPW:FSM| ; 75.6 (75.6) ; 78.3 (78.3) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 130 (130) ; 59 (59) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ; |
; |RX_SPW:RX| ; 41.0 (0.3) ; 50.5 (1.5) ; 9.5 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 66 (3) ; 75 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ; |
; |bit_capture_control:capture_c| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c ; bit_capture_control ; work ; |
; |bit_capture_data:capture_d| ; 2.6 (2.6) ; 3.2 (3.2) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d ; bit_capture_data ; work ; |
; |counter_neg:cnt_neg| ; 7.5 (7.5) ; 8.1 (8.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg ; counter_neg ; work ; |
; |rx_buffer_fsm:buffer_fsm| ; 1.3 (1.3) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm ; rx_buffer_fsm ; work ; |
; |rx_control_data_rdy:control_data_rdy| ; 3.0 (3.0) ; 3.7 (3.7) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy ; rx_control_data_rdy ; work ; |
; |rx_data_buffer_data_w:buffer_data_flag| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag ; rx_data_buffer_data_w ; work ; |
; |rx_data_control_p:data_control| ; 10.6 (10.6) ; 10.7 (10.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control ; rx_data_control_p ; work ; |
; |rx_data_receive:rx_dtarcv| ; 13.7 (13.7) ; 19.8 (19.8) ; 6.1 (6.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ; rx_data_receive ; work ; |
; |TX_SPW:TX| ; 143.8 (0.0) ; 157.3 (0.0) ; 13.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 224 (0) ; 105 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ; |
; |tx_data_send:tx_data_snd| ; 23.3 (23.3) ; 23.3 (23.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 30 (30) ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd ; tx_data_send ; work ; |
; |tx_fsm_m:tx_fsm| ; 120.1 (81.2) ; 134.0 (91.8) ; 13.9 (10.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 194 (132) ; 76 (43) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm ; tx_fsm_m ; work ; |
; |tx_fct_counter:tx_fct_cnt| ; 25.1 (25.1) ; 26.7 (26.7) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (42) ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ; tx_fct_counter ; work ; |
; |tx_fct_send:tx_fct_snd| ; 13.8 (13.8) ; 15.5 (15.5) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 20 (20) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ; tx_fct_send ; work ; |
; |ulight_fifo:u0| ; 2374.4 (0.0) ; 2528.8 (0.0) ; 158.9 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4210 (0) ; 3049 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ; |
; |altera_reset_controller:rst_controller| ; 0.0 (0.0) ; 1.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ; |
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.0 (0.0) ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ; |
; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.3 (0.0) ; 0.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ; |
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.3 (1.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ; |
; |ulight_fifo_auto_start:auto_start| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:data_read_en_rx| ; 0.9 (0.9) ; 1.1 (1.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:link_disable| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:link_start| ; 0.9 (0.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.0 (1.0) ; 1.1 (1.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:write_en_tx| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.6 (2.6) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ; |
; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 3.0 (3.0) ; 3.1 (3.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 5.2 (5.2) ; 5.2 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ; |
; |ulight_fifo_data_info:data_info| ; 7.1 (7.1) ; 7.1 (7.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ; |
; |altera_reset_controller:rst_controller_001| ; 0.7 (0.0) ; 1.5 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (0) ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ; |
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0.7 (0.7) ; 1.5 (1.5) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ; |
; |ulight_fifo_auto_start:auto_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:data_read_en_rx| ; 0.8 (0.8) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:link_disable| ; 1.2 (1.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:link_start| ; 0.6 (0.6) ; 1.0 (1.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:timecode_tx_enable| ; 1.2 (1.2) ; 1.4 (1.4) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_auto_start:write_en_tx| ; 1.3 (1.3) ; 1.4 (1.4) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo_auto_start ; ulight_fifo ; |
; |ulight_fifo_clock_sel:clock_sel| ; 2.1 (2.1) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo_clock_sel ; ulight_fifo ; |
; |ulight_fifo_counter_rx_fifo:counter_rx_fifo| ; 2.5 (2.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 2.6 (2.6) ; 3.0 (3.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_counter_rx_fifo:fsm_info| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 4.1 (4.1) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ; |
; |ulight_fifo_data_info:data_info| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.4 (0.4) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:timecode_ready_rx| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:timecode_tx_ready| ; 0.5 (0.5) ; 0.7 (0.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_hps_0:hps_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ; |
; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ; |
; |ulight_fifo_led_pio_test:led_pio_test| ; 2.2 (2.2) ; 3.9 (3.9) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2300.2 (0.0) ; 2484.3 (0.0) ; 190.6 (0.0) ; 6.5 (0.0) ; 0.0 (0.0) ; 4046 (0) ; 3014 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ; |
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 18.6 (18.6) ; 21.8 (21.8) ; 3.3 (3.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 4.5 (4.5) ; 4.8 (4.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 18.9 (18.9) ; 20.0 (20.0) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 5.4 (5.4) ; 5.4 (5.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.3 (14.3) ; 21.0 (21.0) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.0 (6.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 17.5 (17.5) ; 17.1 (17.1) ; 0.0 (0.0) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 8.9 (8.9) ; 8.9 (8.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 19.3 (19.3) ; 19.2 (19.2) ; 0.0 (0.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 13.7 (13.7) ; 13.8 (13.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 19 (19) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 14.0 (14.0) ; 21.8 (21.8) ; 7.8 (7.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 3.0 (3.0) ; 3.5 (3.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 20.3 (20.3) ; 1.3 (1.3) ; 0.4 (0.4) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.1 (17.1) ; 17.9 (17.9) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.4 (2.4) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 17.6 (17.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 18.6 (18.6) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.3 (14.3) ; 19.0 (19.0) ; 4.7 (4.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.5 (5.5) ; 5.5 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 17.8 (17.8) ; 17.8 (17.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 5.7 (5.7) ; 5.7 (5.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 16.6 (16.6) ; 23.4 (23.4) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 20.1 (20.1) ; 21.0 (21.0) ; 1.9 (1.9) ; 1.0 (1.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 16.2 (16.2) ; 23.3 (23.3) ; 7.0 (7.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 3.3 (3.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.5 (17.5) ; 17.7 (17.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 6.9 (6.9) ; 6.9 (6.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 17.9 (17.9) ; 18.8 (18.8) ; 0.9 (0.9) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 7.0 (7.0) ; 7.0 (7.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 18.8 (18.8) ; 20.3 (20.3) ; 1.8 (1.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 2.9 (2.9) ; 3.1 (3.1) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 20.1 (20.1) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 17.3 (17.3) ; 18.3 (18.3) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 8.3 (8.3) ; 8.3 (8.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 20.0 (20.0) ; 20.5 (20.5) ; 1.3 (1.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 2.8 (2.8) ; 3.2 (3.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 19.4 (19.4) ; 20.5 (20.5) ; 1.2 (1.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 62.2 (28.7) ; 62.2 (30.7) ; 0.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 114 (55) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 31.5 (31.5) ; 31.5 (31.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 42.4 (0.0) ; 45.2 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.4 (42.2) ; 45.2 (44.9) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |ulight_fifo_led_pio_test:led_pio_test| ; 2.9 (2.9) ; 4.2 (4.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 2337.0 (0.0) ; 2478.1 (0.0) ; 145.6 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 4124 (0) ; 2969 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ; |
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.3 (3.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 20.1 (20.1) ; 21.0 (21.0) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 4.3 (4.3) ; 4.3 (4.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo| ; 20.2 (20.2) ; 20.2 (20.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo| ; 14.7 (14.7) ; 17.7 (17.7) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo| ; 6.1 (6.1) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 10 (10) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 18.2 (18.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.0 (9.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 18.3 (18.3) ; 18.5 (18.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 4.2 (4.2) ; 4.2 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 7 (7) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 15.1 (15.1) ; 20.6 (20.6) ; 5.6 (5.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 20.7 (20.7) ; 22.0 (22.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo| ; 2.7 (2.7) ; 2.8 (2.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo| ; 17.2 (17.2) ; 18.8 (18.8) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo| ; 18.2 (18.2) ; 19.7 (19.7) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo| ; 2.6 (2.6) ; 2.8 (2.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo| ; 18.7 (18.7) ; 19.3 (19.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo| ; 2.3 (2.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo| ; 14.4 (14.4) ; 17.5 (17.5) ; 3.1 (3.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo| ; 5.2 (5.2) ; 6.3 (6.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 17.7 (17.7) ; 19.0 (19.0) ; 1.5 (1.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 6.0 (6.0) ; 6.2 (6.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 21.0 (21.0) ; 21.6 (21.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 19.5 (19.5) ; 20.1 (20.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 20.8 (20.8) ; 22.2 (22.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo| ; 2.4 (2.4) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 17.0 (17.0) ; 17.0 (17.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 7.5 (7.5) ; 8.2 (8.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 17.6 (17.6) ; 17.6 (17.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 8.0 (8.0) ; 8.2 (8.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 13 (13) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.8 (20.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.5 (20.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 2.5 (2.5) ; 3.1 (3.1) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 18.1 (18.1) ; 18.7 (18.7) ; 1.0 (1.0) ; 0.5 (0.5) ; 0.0 (0.0) ; 25 (25) ; 42 (42) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 9.0 (9.0) ; 9.2 (9.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 20.3 (20.3) ; 20.6 (20.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 3.2 (3.2) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 20.5 (20.5) ; 20.6 (20.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 26 (26) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 61.8 (29.2) ; 65.0 (32.7) ; 3.2 (3.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 116 (57) ; 26 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 32.3 (32.3) ; 32.3 (32.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 59 (59) ; 20 (20) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 44.3 (0.0) ; 47.3 (0.0) ; 3.0 (0.0) ; 0.1 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.3 (47.0) ; 3.0 (3.0) ; 0.1 (0.1) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 44.2 (0.0) ; 46.7 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.2 (44.0) ; 46.7 (46.4) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 44.3 (0.0) ; 47.2 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.3 (44.1) ; 47.2 (46.9) ; 2.8 (2.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 38.8 (0.0) ; 41.3 (0.0) ; 2.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.8 (37.8) ; 41.3 (40.8) ; 2.5 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.5 (0.5) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 38.3 (0.0) ; 42.0 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.3 (37.6) ; 42.0 (41.7) ; 3.7 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 35.4 (0.0) ; 38.3 (0.0) ; 2.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 35.4 (34.8) ; 38.3 (37.3) ; 2.9 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 1.0 (1.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 36.0 (0.0) ; 38.8 (0.0) ; 2.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.0 (35.3) ; 38.8 (38.3) ; 2.8 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 42.5 (0.0) ; 45.1 (0.0) ; 2.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.5 (42.2) ; 45.1 (44.6) ; 2.6 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 36.8 (0.0) ; 38.4 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.8 (36.1) ; 38.4 (38.1) ; 1.7 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 36.3 (0.0) ; 38.2 (0.0) ; 2.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.3 (35.9) ; 38.2 (37.9) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 41.2 (0.0) ; 43.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.2 (40.9) ; 43.6 (43.1) ; 2.3 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 41.5 (41.2) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 38.8 (0.0) ; 40.4 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 38.8 (38.5) ; 40.4 (40.1) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 39.0 (0.0) ; 40.5 (0.0) ; 1.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.0 (38.7) ; 40.5 (40.5) ; 1.5 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 44.6 (0.0) ; 48.7 (0.0) ; 4.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.6 (44.3) ; 48.7 (48.4) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 39.6 (0.0) ; 41.5 (0.0) ; 1.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.6 (39.3) ; 41.5 (41.2) ; 1.9 (1.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 43.5 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.5) ; 43.5 (43.2) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 36.7 (0.0) ; 39.8 (0.0) ; 3.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.7 (36.4) ; 39.8 (39.8) ; 3.0 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.0 (0.0) ; 42.6 (0.0) ; 3.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.0 (38.3) ; 42.6 (41.9) ; 3.6 (3.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 57 (55) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 37.9 (0.0) ; 41.7 (0.0) ; 3.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 37.9 (37.6) ; 41.7 (41.2) ; 3.8 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 55 (54) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.5 (0.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 47.4 (0.0) ; 51.8 (0.0) ; 4.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 47.4 (47.2) ; 51.8 (51.6) ; 4.4 (4.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 67 (66) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 39.3 (0.0) ; 41.6 (0.0) ; 2.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (39.0) ; 41.6 (41.2) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 39.8 (0.0) ; 41.5 (0.0) ; 1.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.8 (39.3) ; 41.5 (41.5) ; 1.7 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 40.2 (0.0) ; 44.7 (0.0) ; 4.5 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.2 (39.8) ; 44.7 (44.3) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 61 (60) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 44.7 (0.0) ; 48.1 (0.0) ; 3.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 66 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.7 (44.4) ; 48.1 (47.8) ; 3.4 (3.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 66 (66) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 42.4 (0.0) ; 45.3 (0.0) ; 2.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.4 (42.2) ; 45.3 (45.1) ; 2.9 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 45.7 (0.0) ; 49.6 (0.0) ; 3.9 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.4) ; 49.6 (49.3) ; 3.9 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 42.3 (0.0) ; 45.6 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.3 (42.1) ; 45.6 (45.3) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 43.4 (0.0) ; 45.8 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.4 (43.2) ; 45.8 (45.6) ; 2.4 (2.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 36.7 (0.0) ; 41.1 (0.0) ; 4.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.7 (36.0) ; 41.1 (40.2) ; 4.4 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.7 (0.7) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 36.8 (0.0) ; 39.4 (0.0) ; 2.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.8 (36.4) ; 39.4 (39.4) ; 2.7 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (51) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 45.6 (0.0) ; 49.7 (0.0) ; 4.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.6 (45.3) ; 49.7 (49.4) ; 4.1 (4.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 39.3 (0.0) ; 40.8 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 39.3 (38.9) ; 40.8 (40.6) ; 1.6 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 41.5 (0.0) ; 42.3 (0.0) ; 0.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 41.5 (41.2) ; 42.3 (42.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.3 (0.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 47.2 (0.0) ; 52.6 (0.0) ; 5.3 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 69 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 47.2 (47.0) ; 52.6 (52.3) ; 5.3 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 69 (69) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 43.0 (0.0) ; 45.4 (0.0) ; 2.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 43.0 (42.7) ; 45.4 (45.4) ; 2.4 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 36.3 (0.0) ; 39.9 (0.0) ; 3.7 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 36.3 (35.4) ; 39.9 (39.3) ; 3.7 (3.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 52 (50) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.6 (0.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 44.8 (0.0) ; 47.1 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 44.8 (44.6) ; 47.1 (46.8) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 65 (64) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 46.0 (0.0) ; 47.6 (0.0) ; 1.6 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.0 (45.8) ; 47.6 (47.3) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 70 (69) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 40.5 (0.0) ; 42.3 (0.0) ; 1.8 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (0) ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 40.5 (40.2) ; 42.3 (42.3) ; 1.8 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 60 (59) ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 46.8 (0.0) ; 50.0 (0.0) ; 3.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 70 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 46.8 (46.6) ; 50.0 (49.7) ; 3.2 (3.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 42.2 (0.0) ; 46.2 (0.0) ; 4.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 42.2 (41.9) ; 46.2 (45.9) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 64 (63) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 45.7 (0.0) ; 48.0 (0.0) ; 2.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (0) ; 62 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 45.7 (45.5) ; 48.0 (47.7) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 69 (68) ; 62 (62) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 0.2 (0.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_slave_agent:auto_start_s1_agent| ; 16.2 (5.8) ; 16.7 (6.1) ; 0.5 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.4 (10.4) ; 10.6 (10.6) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 15.7 (5.8) ; 16.3 (6.3) ; 0.7 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.3 (2.2) ; 12.3 (2.7) ; 0.0 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 12.1 (2.2) ; 12.1 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 12.3 (2.3) ; 12.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_info_s1_agent| ; 12.5 (2.6) ; 12.5 (2.8) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.1 (5.7) ; 15.1 (5.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 11.8 (2.3) ; 11.8 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:auto_start_s1_agent| ; 14.8 (5.3) ; 14.8 (5.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 15.3 (5.7) ; 15.5 (5.7) ; 0.2 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 27 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 16 (16) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 12.2 (2.7) ; 12.2 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 12.0 (2.5) ; 13.2 (2.8) ; 1.1 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.6 (9.6) ; 10.3 (10.3) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 12.2 (2.2) ; 12.2 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_info_s1_agent| ; 11.7 (2.2) ; 12.6 (2.4) ; 0.9 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 10.2 (10.2) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 15.3 (5.5) ; 17.5 (6.3) ; 2.2 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 11.2 (11.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 11.8 (2.3) ; 11.8 (2.3) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.5 (9.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.4 (2.2) ; 12.8 (3.3) ; 0.4 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 11.7 (2.5) ; 11.7 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 11.9 (2.4) ; 11.9 (2.5) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 12.2 (2.9) ; 12.2 (2.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 14.9 (5.5) ; 14.9 (5.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.4 (9.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_disable_s1_agent| ; 16.1 (5.6) ; 16.5 (5.6) ; 0.4 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.9 (10.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.6 (5.3) ; 15.6 (5.7) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.9 (9.9) ; 9.9 (9.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 12.6 (2.5) ; 12.6 (2.8) ; 0.0 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 12.8 (2.6) ; 13.2 (3.1) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.2 (10.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 16.5 (6.3) ; 17.6 (6.3) ; 1.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 11.2 (11.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 16.0 (5.7) ; 16.2 (5.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.3 (10.3) ; 10.3 (10.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.7 (2.2) ; 13.2 (2.7) ; 0.6 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.5 (10.5) ; 10.6 (10.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.8 (5.4) ; 15.8 (6.0) ; 0.0 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 15.0 (5.9) ; 15.0 (5.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 29 (12) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.1 (9.1) ; 9.1 (9.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.3 (2.3) ; 3.3 (3.3) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 2.7 (2.7) ; 3.7 (3.7) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 1.5 (1.5) ; 4.1 (4.1) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 2.2 (2.2) ; 4.1 (4.1) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 1.2 (1.2) ; 4.8 (4.8) ; 3.6 (3.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.7 (1.7) ; 6.3 (6.3) ; 4.6 (4.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.4 (2.4) ; 3.1 (3.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 2.1 (2.1) ; 2.2 (2.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 2.1 (2.1) ; 3.2 (3.2) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.6 (1.6) ; 3.0 (3.0) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.8 (1.8) ; 3.7 (3.7) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.8 (3.8) ; 3.7 (3.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.4 (2.4) ; 3.2 (3.2) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.3 (2.3) ; 3.2 (3.2) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.8 (2.8) ; 4.2 (4.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 4.2 (4.2) ; 5.0 (5.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 2.8 (2.8) ; 3.2 (3.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 2.1 (2.1) ; 3.0 (3.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.8 (4.8) ; 5.0 (5.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.4 (2.4) ; 3.1 (3.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 14.5 (14.5) ; 14.5 (14.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 11 (11) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 12.8 (12.8) ; 13.5 (13.5) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 15.7 (15.7) ; 17.7 (17.7) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 23.8 (23.8) ; 25.3 (25.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 13.1 (10.8) ; 13.3 (11.2) ; 0.2 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (33) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.1 (2.1) ; 2.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 6.3 (6.3) ; 7.1 (7.1) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.7 (6.7) ; 7.7 (7.7) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 12.8 (10.2) ; 13.7 (11.1) ; 1.0 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.6 (2.6) ; 2.7 (2.7) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.1 (6.1) ; 6.2 (6.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 11.9 (10.6) ; 12.6 (10.8) ; 0.7 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 13.7 (9.7) ; 14.7 (10.4) ; 1.1 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4.0 (4.0) ; 4.3 (4.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 12.8 (9.5) ; 14.4 (11.1) ; 1.6 (1.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.5 (11.6) ; 16.7 (12.7) ; 2.2 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.9 (2.9) ; 4.0 (4.0) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 11.3 (9.3) ; 12.5 (10.7) ; 1.2 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.3 (6.3) ; 6.8 (6.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 6.4 (6.4) ; 6.9 (6.9) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 13.8 (11.2) ; 14.8 (12.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 41 (36) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.7 (2.7) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 11.7 (9.3) ; 12.3 (10.1) ; 0.7 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.2 (2.2) ; 2.2 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 7.4 (7.4) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (23) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.7 (6.7) ; 6.7 (6.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 13.0 (9.7) ; 13.0 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 36 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 3.3 (3.3) ; 3.3 (3.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.0 (6.0) ; 6.7 (6.7) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 6.7 (6.7) ; 6.7 (6.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router| ; 14.3 (14.3) ; 17.3 (17.3) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 21.0 (21.0) ; 23.5 (23.5) ; 2.5 (2.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 44 (44) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 1.1 (1.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.1 (1.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 0.9 (0.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.1 (1.1) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.6 (1.6) ; 1.6 (1.6) ; 0.1 (0.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.5 (1.5) ; 1.6 (1.6) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.1 (0.1) ; 0.1 (0.1) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.0 (1.0) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.4 (1.4) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 0.8 (0.8) ; 1.2 (1.2) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 36.5 (36.5) ; 40.3 (40.3) ; 5.2 (5.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 128.4 (128.4) ; 156.2 (156.2) ; 29.3 (29.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 300 (300) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 12.7 (2.5) ; 13.8 (2.7) ; 1.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 11.2 (11.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 12.1 (2.2) ; 12.1 (2.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 9.8 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 12.1 (2.1) ; 12.1 (2.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.8 (9.8) ; 10.0 (10.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 11.8 (2.2) ; 12.0 (2.3) ; 0.2 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.5 (9.5) ; 9.7 (9.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 14.9 (4.8) ; 16.6 (5.8) ; 1.7 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.8 (10.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_disable_s1_agent| ; 14.9 (5.4) ; 16.0 (6.8) ; 1.1 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.2 (9.2) ; 9.2 (9.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_start_s1_agent| ; 15.2 (5.6) ; 15.5 (5.8) ; 0.3 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.7 (9.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 11.6 (2.2) ; 11.7 (2.2) ; 0.1 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.5 (9.5) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 11.9 (2.2) ; 12.4 (2.5) ; 0.5 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 23 (6) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.9 (9.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 15.5 (5.3) ; 15.8 (5.6) ; 0.2 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.2 (10.2) ; 10.2 (10.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 15.1 (5.4) ; 15.7 (5.8) ; 0.6 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.7 (9.7) ; 9.8 (9.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 12.1 (2.5) ; 12.1 (2.8) ; 0.0 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 24 (7) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.4 (9.4) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 15.5 (5.4) ; 15.5 (5.5) ; 0.0 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 10.0 (10.0) ; 10.0 (10.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 14.5 (5.2) ; 14.5 (5.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (11) ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 9.3 (9.3) ; 9.3 (9.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 17 (17) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 2.1 (2.1) ; 3.3 (3.3) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 3.1 (3.1) ; 3.8 (3.8) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 2.6 (2.6) ; 3.4 (3.4) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 3.0 (3.0) ; 4.4 (4.4) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_info_s1_translator| ; 1.8 (1.8) ; 3.2 (3.2) ; 1.3 (1.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 2.2 (2.2) ; 2.8 (2.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 1.2 (1.2) ; 2.1 (2.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 1.1 (1.1) ; 1.9 (1.9) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 1.4 (1.4) ; 2.1 (2.1) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 1.9 (1.9) ; 2.5 (2.5) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 3.6 (3.6) ; 3.8 (3.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 2.5 (2.5) ; 2.8 (2.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:link_start_s1_translator| ; 2.3 (2.3) ; 3.0 (3.0) ; 0.8 (0.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 1.7 (1.7) ; 2.0 (2.0) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2.4 (2.4) ; 5.0 (5.0) ; 2.6 (2.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 3.5 (3.5) ; 4.5 (4.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 12 (12) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 2.2 (2.2) ; 2.9 (2.9) ; 0.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 1.0 (1.0) ; 1.6 (1.6) ; 0.6 (0.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 4.2 (4.2) ; 5.1 (5.1) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 2.3 (2.3) ; 2.8 (2.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 6 (6) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 15.3 (15.3) ; 15.3 (15.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 12 (12) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 14.4 (14.4) ; 14.4 (14.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 14 (14) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 18.4 (18.4) ; 20.1 (20.1) ; 1.7 (1.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (35) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 31.6 (31.6) ; 31.6 (31.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 11.7 (9.8) ; 12.5 (10.5) ; 0.8 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 37 (32) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 2.0 (2.0) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 7.0 (7.0) ; 8.1 (8.1) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 7.0 (7.0) ; 8.2 (8.2) ; 1.2 (1.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 6.7 (6.7) ; 7.8 (7.8) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 11.1 (9.6) ; 12.2 (10.7) ; 1.1 (1.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 6.8 (6.8) ; 7.2 (7.2) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 7.1 (7.1) ; 8.0 (8.0) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 12.3 (10.3) ; 12.7 (10.8) ; 0.3 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 12.0 (9.8) ; 11.9 (9.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.9 (1.9) ; 2.2 (2.2) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 11.5 (9.7) ; 12.4 (10.6) ; 0.9 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 14.5 (12.5) ; 14.5 (12.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 42 (37) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 11.6 (9.6) ; 12.8 (10.5) ; 1.3 (0.9) ; 0.0 (0.0) ; 0.0 (0.0) ; 34 (29) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.3 (2.3) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 6.6 (6.6) ; 6.6 (6.6) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 6.4 (6.4) ; 6.4 (6.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 12.6 (10.8) ; 14.0 (12.2) ; 1.4 (1.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (35) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 10.6 (8.6) ; 12.1 (10.1) ; 1.5 (1.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 33 (28) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 2.0 (2.0) ; 2.0 (2.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 5 (5) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 6.8 (6.8) ; 6.8 (6.8) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 6.3 (6.3) ; 6.3 (6.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 11.4 (9.9) ; 13.2 (10.7) ; 1.7 (0.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 35 (31) ; 5 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 1.5 (1.5) ; 2.5 (2.5) ; 1.0 (1.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 6.5 (6.5) ; 6.5 (6.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 6.7 (6.7) ; 7.1 (7.1) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 6.4 (6.4) ; 6.7 (6.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 22 (22) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router| ; 10.2 (10.2) ; 13.2 (13.2) ; 3.0 (3.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 28 (28) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 16.0 (16.0) ; 18.3 (18.3) ; 2.3 (2.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 40 (40) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 1.2 (1.2) ; 1.3 (1.3) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 1.1 (1.1) ; 1.2 (1.2) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010| ; 1.3 (1.3) ; 1.8 (1.8) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011| ; 1.8 (1.8) ; 1.8 (1.8) ; 0.1 (0.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014| ; 1.4 (1.4) ; 1.8 (1.8) ; 0.4 (0.4) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 1.5 (1.5) ; 1.7 (1.7) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 0.8 (0.8) ; 0.9 (0.9) ; 0.2 (0.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 37.3 (37.3) ; 36.9 (36.9) ; 0.3 (0.3) ; 0.7 (0.7) ; 0.0 (0.0) ; 88 (88) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 127.2 (127.2) ; 135.9 (135.9) ; 10.3 (10.3) ; 1.5 (1.5) ; 0.0 (0.0) ; 294 (294) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ; |
; |ulight_fifo_pll_0:pll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ; |
; |altera_pll:altera_pll_i| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ; |
; |altera_cyclonev_pll:cyclonev_pll| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll ; altera_cyclonev_pll ; work ; |
; |altera_cyclonev_pll_base:fpll_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0 ; altera_cyclonev_pll_base ; work ; |
; |ulight_fifo_timecode_rx:timecode_rx| ; 4.2 (4.2) ; 4.2 (4.2) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ; |
; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 2.3 (2.3) ; 6.3 (6.3) ; 4.0 (4.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ; |
; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.6 (2.6) ; 7.1 (7.1) ; 4.5 (4.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ; |
; |ulight_fifo_timecode_rx:timecode_rx| ; 2.8 (2.8) ; 3.3 (3.3) ; 0.5 (0.5) ; 0.0 (0.0) ; 0.0 (0.0) ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo_timecode_rx ; ulight_fifo ; |
; |ulight_fifo_timecode_tx_data:timecode_tx_data| ; 3.3 (3.3) ; 6.0 (6.0) ; 2.7 (2.7) ; 0.0 (0.0) ; 0.0 (0.0) ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo_timecode_tx_data ; ulight_fifo ; |
; |ulight_fifo_write_data_fifo_tx:write_data_fifo_tx| ; 2.5 (2.5) ; 7.6 (7.6) ; 5.1 (5.1) ; 0.0 (0.0) ; 0.0 (0.0) ; 10 (10) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo_write_data_fifo_tx ; ulight_fifo ; |
+-----------------------------------------------------------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+ |
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. |
|
1517,17 → 1717,17
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ |
; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ; |
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ |
; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; |
; LED[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; |
; dout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; |
; sout_a ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; |
; LED[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; |
; LED[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; |
; LED[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; |
; LED[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; |
; LED[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; |
; KEY[0] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; |
; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (0) ; -- ; -- ; -- ; |
; LED[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ; |
; FPGA_CLK1_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; |
; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; |
; din_a ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; |
1539,65 → 1739,111
+--------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+ |
|
|
+----------------------------------------------------------------------------------------------------------------------------+ |
; Pad To Core Delay Chain Fanout ; |
+----------------------------------------------------------------------------------------------+-------------------+---------+ |
; Source Pin / Fanout ; Pad To Core Index ; Setting ; |
+----------------------------------------------------------------------------------------------+-------------------+---------+ |
; KEY[0] ; ; ; |
; FPGA_CLK1_50 ; ; ; |
; KEY[1] ; ; ; |
; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter[13]~1 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~7 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~8 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~9 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~10 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~11 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~16 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|PB_down~1 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ; |
; din_a ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 0 ; 0 ; |
; sin_a ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ; |
; din_a(n) ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_d_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|control_bit_found ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_c_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~3 ; 0 ; 0 ; |
; sin_a(n) ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4~2 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2~4 ; 1 ; 0 ; |
+----------------------------------------------------------------------------------------------+-------------------+---------+ |
+---------------------------------------------------------------------------------------------------------------------------------------------+ |
; Pad To Core Delay Chain Fanout ; |
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+ |
; Source Pin / Fanout ; Pad To Core Index ; Setting ; |
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+ |
; KEY[0] ; ; ; |
; FPGA_CLK1_50 ; ; ; |
; KEY[1] ; ; ; |
; - debounce_db:db_system_spwulight_b|PB_down~0 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|aux_pb~0 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~0 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~1 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~2 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~3 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~4 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~5 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~6 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~7 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~8 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~9 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~10 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~11 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~12 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~13 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~14 ; 0 ; 0 ; |
; - debounce_db:db_system_spwulight_b|counter~15 ; 0 ; 0 ; |
; din_a ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ; |
; sin_a ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ; |
; din_a(n) ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c|bit_c_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|control_bit_found ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 0 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 0 ; 0 ; |
; sin_a(n) ; ; ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~20 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|got_bit_internal~0 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~1 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~2 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~3 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~4 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~5 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~6 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~7 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~8 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~9 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~10 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~11 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us~12 ; 1 ; 0 ; |
; - spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~13 ; 1 ; 0 ; |
+---------------------------------------------------------------------------------------------------------------+-------------------+---------+ |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
1605,448 → 1851,410
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ |
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ |
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Clock ; yes ; Global Clock ; GCLK5 ; -- ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X27_Y11_N29 ; 1270 ; Clock ; no ; -- ; -- ; -- ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X13_Y17_N26 ; 60 ; Clock ; no ; -- ; -- ; -- ; |
; debounce_db:db_system_spwulight_b|PB_down~0 ; MLABCELL_X47_Y1_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; debounce_db:db_system_spwulight_b|aux_pb ; FF_X47_Y1_N14 ; 127 ; Async. clear ; no ; -- ; -- ; -- ; |
; debounce_db:db_system_spwulight_b|counter[13]~1 ; MLABCELL_X47_Y1_N21 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|WideOr7~0 ; LABCELL_X18_Y14_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|always1~0 ; LABCELL_X23_Y14_N12 ; 6 ; Clock ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|always2~0 ; LABCELL_X23_Y14_N48 ; 6 ; Clock ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|always3~0 ; MLABCELL_X19_Y14_N21 ; 84 ; Clock ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|data[8]~2 ; MLABCELL_X19_Y15_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|data_l_r[7]~0 ; MLABCELL_X19_Y15_N9 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|data_l_r[7]~1 ; MLABCELL_X19_Y15_N21 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|is_control ; FF_X23_Y14_N56 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|ready_control_p_r ; FF_X19_Y15_N20 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|ready_data_p ; LABCELL_X23_Y14_N39 ; 19 ; Clock ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|rx_got_time_code~1 ; LABCELL_X18_Y15_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|timecode[7]~0 ; LABCELL_X22_Y15_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~10 ; LABCELL_X35_Y8_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~12 ; LABCELL_X27_Y11_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~14 ; LABCELL_X33_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~15 ; LABCELL_X28_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~16 ; LABCELL_X31_Y8_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~18 ; LABCELL_X35_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~19 ; LABCELL_X35_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~2 ; LABCELL_X33_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~20 ; LABCELL_X35_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~21 ; LABCELL_X33_Y8_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~22 ; LABCELL_X33_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~23 ; LABCELL_X33_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~25 ; LABCELL_X28_Y13_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~27 ; MLABCELL_X32_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~28 ; LABCELL_X33_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~29 ; LABCELL_X28_Y13_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~3 ; LABCELL_X31_Y8_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~30 ; MLABCELL_X32_Y12_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~31 ; MLABCELL_X32_Y12_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~32 ; MLABCELL_X32_Y12_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~33 ; MLABCELL_X32_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~34 ; LABCELL_X33_Y11_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~35 ; MLABCELL_X32_Y12_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~37 ; LABCELL_X33_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~38 ; LABCELL_X33_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~39 ; LABCELL_X33_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~40 ; MLABCELL_X32_Y12_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~41 ; LABCELL_X33_Y11_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~42 ; LABCELL_X33_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~44 ; MLABCELL_X32_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~45 ; LABCELL_X27_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~46 ; LABCELL_X28_Y13_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~47 ; LABCELL_X28_Y13_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~48 ; LABCELL_X27_Y11_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~49 ; LABCELL_X27_Y11_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~5 ; MLABCELL_X32_Y12_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~50 ; LABCELL_X27_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~51 ; LABCELL_X27_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~53 ; LABCELL_X27_Y7_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~54 ; MLABCELL_X32_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~55 ; MLABCELL_X32_Y10_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~56 ; LABCELL_X27_Y7_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~57 ; MLABCELL_X32_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~58 ; MLABCELL_X32_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~59 ; MLABCELL_X32_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~6 ; LABCELL_X33_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~60 ; MLABCELL_X32_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~62 ; LABCELL_X33_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~63 ; LABCELL_X27_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~64 ; LABCELL_X28_Y7_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~66 ; LABCELL_X33_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~67 ; LABCELL_X31_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~68 ; LABCELL_X33_Y8_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~69 ; LABCELL_X31_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~70 ; LABCELL_X33_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~71 ; MLABCELL_X32_Y10_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~72 ; LABCELL_X27_Y11_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~74 ; LABCELL_X35_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~76 ; LABCELL_X35_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~77 ; LABCELL_X33_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~78 ; LABCELL_X33_Y8_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~79 ; LABCELL_X35_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~8 ; MLABCELL_X32_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|Decoder0~80 ; LABCELL_X33_Y8_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always0~0 ; LABCELL_X31_Y13_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always1~0 ; LABCELL_X27_Y16_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always1~2 ; LABCELL_X31_Y13_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|block_write ; FF_X28_Y11_N26 ; 67 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[5]~0 ; LABCELL_X27_Y16_N51 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5]~1 ; LABCELL_X31_Y13_N54 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~11 ; LABCELL_X15_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~13 ; LABCELL_X18_Y10_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~14 ; LABCELL_X15_Y12_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~16 ; MLABCELL_X19_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~17 ; MLABCELL_X19_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~19 ; LABCELL_X22_Y10_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~2 ; LABCELL_X15_Y12_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~20 ; LABCELL_X22_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~22 ; LABCELL_X21_Y14_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~23 ; LABCELL_X21_Y14_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~25 ; LABCELL_X22_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~26 ; MLABCELL_X19_Y13_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~28 ; LABCELL_X15_Y12_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~29 ; LABCELL_X17_Y12_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~30 ; LABCELL_X17_Y10_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~31 ; LABCELL_X17_Y12_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~32 ; LABCELL_X17_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~33 ; LABCELL_X17_Y12_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~34 ; LABCELL_X17_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~36 ; MLABCELL_X19_Y10_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~38 ; LABCELL_X17_Y10_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~39 ; LABCELL_X18_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~4 ; LABCELL_X15_Y12_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~41 ; LABCELL_X22_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~43 ; LABCELL_X22_Y11_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~44 ; LABCELL_X17_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~45 ; LABCELL_X17_Y12_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~46 ; LABCELL_X17_Y10_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~47 ; LABCELL_X22_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~49 ; LABCELL_X15_Y12_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~51 ; LABCELL_X15_Y12_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~52 ; LABCELL_X15_Y12_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~53 ; LABCELL_X15_Y12_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~54 ; MLABCELL_X19_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~55 ; LABCELL_X15_Y12_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~56 ; LABCELL_X18_Y10_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~57 ; LABCELL_X15_Y12_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~58 ; MLABCELL_X19_Y13_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~59 ; MLABCELL_X19_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~6 ; LABCELL_X15_Y12_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~60 ; LABCELL_X22_Y10_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~61 ; LABCELL_X22_Y10_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~62 ; MLABCELL_X19_Y13_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~63 ; MLABCELL_X19_Y13_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~64 ; MLABCELL_X19_Y13_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~65 ; LABCELL_X22_Y11_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~66 ; LABCELL_X15_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~67 ; LABCELL_X17_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~68 ; LABCELL_X17_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~69 ; LABCELL_X17_Y12_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~7 ; LABCELL_X15_Y12_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~70 ; LABCELL_X15_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~71 ; LABCELL_X15_Y12_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~72 ; LABCELL_X17_Y10_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~73 ; LABCELL_X17_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~74 ; LABCELL_X17_Y10_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~75 ; LABCELL_X18_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~76 ; MLABCELL_X19_Y10_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~77 ; LABCELL_X22_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~78 ; LABCELL_X17_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~79 ; LABCELL_X17_Y12_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~80 ; MLABCELL_X19_Y10_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~81 ; LABCELL_X22_Y11_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|Decoder0~9 ; MLABCELL_X19_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|always1~0 ; LABCELL_X21_Y14_N36 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|block_write ; FF_X21_Y14_N53 ; 45 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[5]~0 ; LABCELL_X21_Y14_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X28_Y16_N44 ; 65 ; Async. clear ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X28_Y14_N17 ; 109 ; Async. clear ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|WideOr7~0 ; LABCELL_X35_Y15_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always11~0 ; MLABCELL_X32_Y15_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always1~0 ; LABCELL_X31_Y15_N33 ; 6 ; Clock ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always2~0 ; LABCELL_X31_Y15_N24 ; 6 ; Clock ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|always3~0 ; LABCELL_X31_Y15_N39 ; 85 ; Clock ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|data[9]~0 ; MLABCELL_X32_Y15_N48 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data ; FF_X32_Y15_N56 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data~1 ; MLABCELL_X32_Y15_N57 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_control_p_r ; FF_X31_Y15_N14 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data ; LABCELL_X30_Y15_N12 ; 11 ; Clock ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|ready_data_p ; LABCELL_X30_Y15_N27 ; 11 ; Clock ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_flag[8]~2 ; LABCELL_X31_Y15_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|timecode[7]~0 ; LABCELL_X31_Y15_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|Selector4~2 ; LABCELL_X17_Y15_N45 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[0]~6 ; MLABCELL_X14_Y14_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[5]~1 ; MLABCELL_X14_Y14_N27 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[1]~2 ; MLABCELL_X14_Y16_N36 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[0]~4 ; LABCELL_X17_Y16_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[0]~8 ; LABCELL_X17_Y16_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_timein_control_flag_tx~1 ; LABCELL_X17_Y16_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|txdata_flagctrl_tx_last[7]~0 ; LABCELL_X17_Y15_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X28_Y16_N15 ; 1232 ; Async. clear ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X21_Y27_N47 ; 74 ; Async. clear ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Async. clear ; yes ; Global Clock ; GCLK6 ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; LABCELL_X18_Y30_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; MLABCELL_X25_Y30_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X23_Y26_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; LABCELL_X28_Y33_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; MLABCELL_X14_Y24_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; LABCELL_X21_Y23_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; LABCELL_X13_Y20_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK10 ; -- ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X11_Y28_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y30_N42 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y32_N24 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y19_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y19_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X25_Y17_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y25_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y19_N21 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y21_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y20_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X13_Y33_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y16_N21 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y38_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y32_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y32_N21 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y36_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y37_N9 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y34_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X21_Y34_N21 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y34_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y34_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X10_Y33_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X7_Y33_N3 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y17_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y17_N48 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X17_Y18_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X11_Y28_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y25_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y25_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y34_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X27_Y34_N6 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X14_Y31_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y35_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y18_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X7_Y32_N21 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X21_Y19_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X17_Y19_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y24_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y22_N9 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y38_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X22_Y38_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X22_Y20_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X22_Y20_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y24_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X19_Y24_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y29_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y31_N18 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y24_N3 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X14_Y20_N57 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y24_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y24_N45 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y21_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y21_N0 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X13_Y33_N27 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X13_Y33_N21 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y36_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y36_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y30_N39 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X28_Y32_N33 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X17_Y37_N6 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y37_N15 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y34_N0 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y34_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X10_Y34_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X10_Y34_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X8_Y34_N48 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X7_Y34_N48 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X28_Y23_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X28_Y20_N21 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y27_N6 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X15_Y27_N45 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y28_N39 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y26_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y32_N51 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y32_N21 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y35_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X15_Y35_N48 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X9_Y35_N18 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X9_Y35_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X25_Y24_N18 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y19_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y24_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y22_N15 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y38_N15 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y38_N30 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y23_N45 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X25_Y22_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y27_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X19_Y23_N48 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y30_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X13_Y19_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y25_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y21_N15 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y33_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X25_Y38_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y32_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y37_N57 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X21_Y33_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y34_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X7_Y33_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y17_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X10_Y28_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y25_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y34_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X10_Y35_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X6_Y32_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y19_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X14_Y22_N30 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X22_Y38_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X22_Y20_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y24_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; MLABCELL_X19_Y31_N45 ; 29 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|pending_response_count[1]~0 ; LABCELL_X22_Y31_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X30_Y27_N36 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; LABCELL_X28_Y27_N3 ; 27 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|pending_response_count[1]~0 ; LABCELL_X28_Y27_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; MLABCELL_X19_Y31_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; MLABCELL_X19_Y35_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; LABCELL_X10_Y31_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X28_Y30_N12 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; LABCELL_X27_Y30_N33 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; LABCELL_X10_Y34_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; MLABCELL_X19_Y35_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X27_Y32_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; LABCELL_X27_Y32_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y29_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X23_Y29_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y28_N42 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; LABCELL_X23_Y28_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y23_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X23_Y23_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X22_Y27_N57 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X22_Y27_N33 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; LABCELL_X10_Y34_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; MLABCELL_X19_Y33_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|top_priority_reg~1 ; MLABCELL_X25_Y24_N48 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; MLABCELL_X25_Y24_N15 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X22_Y24_N30 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; LABCELL_X22_Y24_N48 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; MLABCELL_X19_Y38_N6 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; LABCELL_X23_Y36_N27 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|top_priority_reg~1 ; LABCELL_X23_Y24_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X23_Y24_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X27_Y25_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X23_Y21_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X27_Y24_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg~0 ; LABCELL_X21_Y27_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; LABCELL_X21_Y27_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK11 ; -- ; |
; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X18_Y20_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X22_Y22_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Clock ; yes ; Global Clock ; GCLK4 ; -- ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FF_X48_Y7_N35 ; 1319 ; Clock ; no ; -- ; -- ; -- ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FF_X61_Y4_N41 ; 105 ; Clock ; no ; -- ; -- ; -- ; |
; debounce_db:db_system_spwulight_b|aux_pb ; FF_X56_Y3_N59 ; 72 ; Async. clear ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|always5~1 ; LABCELL_X53_Y3_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|comb ; LABCELL_X53_Y3_N27 ; 21 ; Clock ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X51_Y3_N30 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|negedge_clk ; LABCELL_X53_Y3_N39 ; 18 ; Clock ; no ; -- ; -- ; -- ; |
; detector_tokens:m_x|state_data_process.01 ; FF_X53_Y3_N11 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|always5~0 ; LABCELL_X48_Y10_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; LABCELL_X51_Y9_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; LABCELL_X58_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; LABCELL_X53_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X53_Y11_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; LABCELL_X58_Y9_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; LABCELL_X53_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; LABCELL_X53_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; LABCELL_X53_Y11_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X58_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X56_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X50_Y8_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X54_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; LABCELL_X51_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; LABCELL_X58_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; MLABCELL_X50_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; MLABCELL_X50_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X54_Y9_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X53_Y10_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; LABCELL_X51_Y11_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; MLABCELL_X50_Y8_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X50_Y10_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X51_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X51_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X58_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; LABCELL_X51_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X51_Y9_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; LABCELL_X51_Y11_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X58_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X50_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; LABCELL_X51_Y11_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; LABCELL_X58_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; LABCELL_X58_Y9_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X50_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X56_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X56_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X58_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; LABCELL_X58_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; LABCELL_X56_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X58_Y9_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; LABCELL_X58_Y8_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; LABCELL_X58_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X50_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; LABCELL_X56_Y9_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X53_Y10_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X53_Y10_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X58_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X58_Y8_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X53_Y10_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; LABCELL_X54_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; LABCELL_X53_Y11_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X56_Y9_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X56_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; LABCELL_X51_Y11_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X53_Y10_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; MLABCELL_X50_Y10_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; MLABCELL_X50_Y10_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; MLABCELL_X50_Y8_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; LABCELL_X54_Y9_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; LABCELL_X54_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X58_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X53_Y11_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X58_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; LABCELL_X58_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; LABCELL_X51_Y11_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~0 ; MLABCELL_X42_Y5_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~1 ; MLABCELL_X42_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~10 ; MLABCELL_X42_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~11 ; LABCELL_X40_Y8_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~12 ; MLABCELL_X42_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~13 ; MLABCELL_X42_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~14 ; MLABCELL_X42_Y9_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~15 ; MLABCELL_X42_Y9_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~16 ; LABCELL_X41_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~17 ; LABCELL_X41_Y6_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~18 ; MLABCELL_X42_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~19 ; LABCELL_X41_Y6_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~2 ; MLABCELL_X42_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~20 ; MLABCELL_X42_Y5_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~21 ; LABCELL_X40_Y5_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~22 ; LABCELL_X41_Y5_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~23 ; LABCELL_X40_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~24 ; LABCELL_X40_Y5_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~25 ; MLABCELL_X42_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~26 ; LABCELL_X40_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~27 ; MLABCELL_X42_Y8_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~28 ; LABCELL_X41_Y7_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~29 ; LABCELL_X41_Y7_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~3 ; LABCELL_X40_Y8_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~30 ; MLABCELL_X42_Y5_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~31 ; LABCELL_X41_Y7_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~32 ; MLABCELL_X42_Y6_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~33 ; LABCELL_X40_Y8_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~34 ; MLABCELL_X42_Y5_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~35 ; MLABCELL_X42_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~36 ; MLABCELL_X42_Y6_N3 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~37 ; MLABCELL_X42_Y9_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~38 ; MLABCELL_X42_Y6_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~39 ; LABCELL_X41_Y9_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~4 ; LABCELL_X41_Y5_N54 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~40 ; LABCELL_X40_Y8_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~41 ; MLABCELL_X42_Y8_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~42 ; MLABCELL_X42_Y5_N39 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~43 ; LABCELL_X41_Y7_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~44 ; MLABCELL_X42_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~45 ; MLABCELL_X42_Y9_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~46 ; MLABCELL_X42_Y5_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~47 ; MLABCELL_X42_Y9_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~48 ; LABCELL_X41_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~49 ; LABCELL_X41_Y6_N51 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~5 ; LABCELL_X41_Y6_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~50 ; LABCELL_X41_Y6_N30 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~51 ; LABCELL_X41_Y6_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~52 ; MLABCELL_X42_Y6_N15 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~53 ; MLABCELL_X42_Y6_N36 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~54 ; LABCELL_X41_Y6_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~55 ; LABCELL_X40_Y5_N33 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~56 ; MLABCELL_X42_Y6_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~57 ; LABCELL_X40_Y8_N42 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~58 ; LABCELL_X41_Y5_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~59 ; LABCELL_X40_Y8_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~6 ; LABCELL_X40_Y9_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~60 ; MLABCELL_X42_Y9_N21 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~61 ; MLABCELL_X42_Y9_N45 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~62 ; LABCELL_X40_Y5_N12 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~63 ; LABCELL_X41_Y7_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~7 ; LABCELL_X40_Y8_N57 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~8 ; MLABCELL_X42_Y8_N18 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|Decoder0~9 ; MLABCELL_X42_Y9_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|next_state_data_read.11~0 ; LABCELL_X49_Y5_N48 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.10 ; FF_X41_Y9_N50 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; FF_X50_Y3_N32 ; 104 ; Async. clear ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|rx_resetn ; FF_X49_Y3_N44 ; 75 ; Async. clear ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|comb ; LABCELL_X54_Y5_N51 ; 60 ; Clock ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|WideOr8~0 ; LABCELL_X53_Y6_N15 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|negedge_clk ; LABCELL_X53_Y6_N0 ; 17 ; Clock ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy|always0~1 ; LABCELL_X56_Y6_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always0~1 ; LABCELL_X54_Y6_N27 ; 11 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|always1~0 ; LABCELL_X54_Y6_N48 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; FF_X53_Y6_N44 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; |
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; LABCELL_X48_Y5_N12 ; 1260 ; Async. clear ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X22_Y29_N56 ; 74 ; Async. clear ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X61_Y6_N44 ; 2974 ; Async. clear ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:auto_start|always0~0 ; LABCELL_X17_Y18_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx|always0~0 ; LABCELL_X17_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:link_disable|always0~0 ; LABCELL_X17_Y19_N45 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:link_start|always0~0 ; MLABCELL_X14_Y15_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable|always0~0 ; MLABCELL_X14_Y22_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx|always0~0 ; LABCELL_X21_Y27_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel|always0~0 ; LABCELL_X21_Y25_N57 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ; |
; ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test|always0~0 ; LABCELL_X33_Y16_N48 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y18_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X14_Y18_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y25_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y25_N36 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X42_Y11_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y12_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y11_N27 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y12_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X42_Y13_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X40_Y10_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y10_N36 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X15_Y14_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X15_Y14_N33 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y12_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y12_N39 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y9_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y9_N0 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y10_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X23_Y10_N33 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|always0~0 ; LABCELL_X18_Y10_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y10_N15 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|always0~0 ; LABCELL_X43_Y15_N9 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|always0~0 ; LABCELL_X40_Y15_N6 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|always0~0 ; LABCELL_X35_Y15_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|always0~0 ; LABCELL_X33_Y16_N51 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|always0~0 ; LABCELL_X23_Y19_N51 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X25_Y19_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|always0~0 ; LABCELL_X11_Y15_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|always0~0 ; LABCELL_X11_Y15_N21 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X31_Y11_N33 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X32_Y11_N51 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X45_Y11_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|always0~0 ; MLABCELL_X37_Y9_N27 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|always0~0 ; LABCELL_X27_Y27_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|always0~0 ; LABCELL_X27_Y27_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y23_N3 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y22_N15 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X25_Y8_N57 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y8_N42 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|always0~0 ; LABCELL_X28_Y19_N9 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X28_Y19_N30 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|always0~0 ; MLABCELL_X19_Y27_N21 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|always0~0 ; LABCELL_X18_Y27_N24 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y20_N0 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y18_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y24_N27 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y25_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y13_N39 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X37_Y13_N36 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X41_Y12_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X41_Y12_N42 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X37_Y14_N45 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y14_N42 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y10_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y16_N15 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y14_N48 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X15_Y13_N36 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X14_Y13_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y11_N57 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X23_Y11_N57 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y9_N12 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y9_N30 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y11_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y11_N6 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X38_Y15_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X38_Y15_N54 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X30_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; MLABCELL_X32_Y16_N18 ; 34 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; MLABCELL_X19_Y18_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X18_Y19_N0 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X21_Y16_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X11_Y16_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X31_Y9_N21 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y9_N9 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X33_Y12_N54 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X35_Y9_N36 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y26_N24 ; 37 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y26_N36 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X18_Y23_N24 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X17_Y23_N6 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X27_Y12_N33 ; 28 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X27_Y12_N9 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X22_Y20_N18 ; 38 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X30_Y20_N30 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|NON_PIPELINED_INPUTS.load_next_cmd ; LABCELL_X23_Y28_N54 ; 30 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|load_next_out_cmd ; LABCELL_X21_Y27_N18 ; 35 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y18_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y25_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X37_Y12_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y12_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X42_Y13_N3 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X40_Y10_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X15_Y14_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y12_N6 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y9_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X23_Y10_N9 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X18_Y10_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X43_Y15_N33 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X35_Y16_N12 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X25_Y19_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X11_Y15_N42 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X32_Y11_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X38_Y9_N27 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y27_N39 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X17_Y22_N21 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X27_Y8_N24 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; LABCELL_X28_Y19_N45 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|always0~0 ; MLABCELL_X19_Y27_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|always1~0 ; LABCELL_X21_Y20_N27 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter|internal_valid~0 ; LABCELL_X23_Y16_N36 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|always1~0 ; MLABCELL_X25_Y24_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|internal_valid~0 ; LABCELL_X22_Y24_N42 ; 22 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|nonposted_cmd_accepted~1 ; MLABCELL_X25_Y24_N33 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|update_grant~0 ; LABCELL_X33_Y12_N24 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|update_grant~0 ; LABCELL_X31_Y9_N9 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|update_grant~0 ; MLABCELL_X37_Y14_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|update_grant~0 ; MLABCELL_X19_Y16_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|update_grant~0 ; LABCELL_X22_Y9_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|update_grant~0 ; LABCELL_X15_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|update_grant~0 ; LABCELL_X21_Y16_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|update_grant~0 ; LABCELL_X15_Y20_N51 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|update_grant~0 ; MLABCELL_X19_Y18_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|update_grant~0 ; LABCELL_X22_Y20_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|update_grant~0 ; LABCELL_X23_Y28_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|update_grant~0 ; MLABCELL_X19_Y11_N39 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|update_grant~0 ; LABCELL_X22_Y11_N36 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|update_grant~0 ; LABCELL_X23_Y26_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|update_grant~0 ; LABCELL_X18_Y23_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|update_grant~0 ; LABCELL_X27_Y12_N48 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|update_grant~0 ; LABCELL_X31_Y11_N18 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|update_grant~0 ; LABCELL_X21_Y24_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|update_grant~0 ; LABCELL_X38_Y13_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|update_grant~0 ; LABCELL_X41_Y12_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|update_grant~0 ; LABCELL_X38_Y13_N54 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|update_grant~0 ; LABCELL_X30_Y16_N54 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Clock ; yes ; Global Clock ; GCLK8 ; -- ; |
; ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data|always0~0 ; LABCELL_X30_Y25_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx|always0~0 ; LABCELL_X30_Y19_N27 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Global & Other Fast Signals ; |
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+ |
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; |
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+ |
; FPGA_CLK1_50 ; PIN_Y13 ; 3124 ; Global Clock ; GCLK5 ; -- ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; FF_X27_Y1_N38 ; 3025 ; Global Clock ; GCLK6 ; -- ; |
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK10 ; -- ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Global Clock ; GCLK11 ; -- ; |
+------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+ |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Global & Other Fast Signals ; |
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+ |
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; |
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+ |
; FPGA_CLK1_50 ; PIN_Y13 ; 3073 ; Global Clock ; GCLK4 ; -- ; |
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0] ; HPSINTERFACECLOCKSRESETS_X32_Y50_N111 ; 3 ; Global Clock ; GCLK11 ; -- ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fboutclk_wire[0] ; FRACTIONALPLL_X68_Y1_N0 ; 1 ; Global Clock ; -- ; -- ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] ; PLLOUTPUTCOUNTER_X68_Y3_N1 ; 24 ; Global Clock ; GCLK8 ; -- ; |
+--------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------+----------------------+------------------+---------------------------+ |
|
|
+-------------------------------------------------------------------------+ |
; Non-Global High Fan-Out Signals ; |
+---------------------------------------------------------------+---------+ |
; Name ; Fan-Out ; |
+---------------------------------------------------------------+---------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1270 ; |
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; 1232 ; |
+---------------------------------------------------------------+---------+ |
+----------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Non-Global High Fan-Out Signals ; |
+------------------------------------------------------------------------------------------------------------------------------------------+---------+ |
; Name ; Fan-Out ; |
+------------------------------------------------------------------------------------------------------------------------------------------+---------+ |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 2974 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1319 ; |
; spw_ulight_con_top_x:A_SPW_TOP|tx_reset_n~0 ; 1260 ; |
+------------------------------------------------------------------------------------------------------------------------------------------+---------+ |
|
|
+-----------------------------------------------------------------------+ |
; Routing Usage Summary ; |
+---------------------------------------------+-------------------------+ |
; Routing Resource Type ; Usage ; |
+---------------------------------------------+-------------------------+ |
; Block interconnects ; 9,946 / 130,276 ( 8 % ) ; |
; C12 interconnects ; 143 / 6,848 ( 2 % ) ; |
; C2 interconnects ; 2,297 / 51,436 ( 4 % ) ; |
; C4 interconnects ; 1,292 / 25,120 ( 5 % ) ; |
; DQS bus muxes ; 0 / 19 ( 0 % ) ; |
; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ; |
; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ; |
; Direct links ; 1,482 / 130,276 ( 1 % ) ; |
; Global clocks ; 4 / 16 ( 25 % ) ; |
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; |
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; |
; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; |
; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; |
; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 1 / 6 ( 17 % ) ; |
; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; |
; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; |
; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; |
; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; |
; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; |
; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; |
; HPS_INTERFACE_HPS2FPGA_INPUTs ; 45 / 165 ( 27 % ) ; |
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; |
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; |
; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 101 / 282 ( 36 % ) ; |
; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; |
; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; |
; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; |
; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; |
; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; |
; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; |
; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; |
; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; |
; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; |
; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; |
; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; |
; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; |
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; |
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; |
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; |
; Local interconnects ; 3,498 / 31,760 ( 11 % ) ; |
; Quadrant clocks ; 0 / 72 ( 0 % ) ; |
; R14 interconnects ; 179 / 6,046 ( 3 % ) ; |
; R14/C12 interconnect drivers ; 267 / 8,584 ( 3 % ) ; |
; R3 interconnects ; 3,386 / 56,712 ( 6 % ) ; |
; R6 interconnects ; 5,364 / 131,000 ( 4 % ) ; |
; Spine clocks ; 9 / 150 ( 6 % ) ; |
; Wire stub REs ; 0 / 6,650 ( 0 % ) ; |
+---------------------------------------------+-------------------------+ |
+------------------------------------------------------------------------+ |
; Routing Usage Summary ; |
+---------------------------------------------+--------------------------+ |
; Routing Resource Type ; Usage ; |
+---------------------------------------------+--------------------------+ |
; Block interconnects ; 10,851 / 130,276 ( 8 % ) ; |
; C12 interconnects ; 122 / 6,848 ( 2 % ) ; |
; C2 interconnects ; 2,619 / 51,436 ( 5 % ) ; |
; C4 interconnects ; 1,582 / 25,120 ( 6 % ) ; |
; DQS bus muxes ; 0 / 19 ( 0 % ) ; |
; DQS-18 I/O buses ; 0 / 19 ( 0 % ) ; |
; DQS-9 I/O buses ; 0 / 19 ( 0 % ) ; |
; Direct links ; 1,438 / 130,276 ( 1 % ) ; |
; Global clocks ; 3 / 16 ( 19 % ) ; |
; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ; |
; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ; |
; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ; |
; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ; |
; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 1 / 6 ( 17 % ) ; |
; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ; |
; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ; |
; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ; |
; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ; |
; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ; |
; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ; |
; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ; |
; HPS_INTERFACE_HPS2FPGA_INPUTs ; 40 / 165 ( 24 % ) ; |
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ; |
; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ; |
; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 101 / 282 ( 36 % ) ; |
; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ; |
; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ; |
; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ; |
; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ; |
; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ; |
; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ; |
; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ; |
; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ; |
; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ; |
; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ; |
; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ; |
; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ; |
; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ; |
; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ; |
; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ; |
; Horizontal periphery clocks ; 0 / 12 ( 0 % ) ; |
; Local interconnects ; 3,340 / 31,760 ( 11 % ) ; |
; Quadrant clocks ; 0 / 72 ( 0 % ) ; |
; R14 interconnects ; 250 / 6,046 ( 4 % ) ; |
; R14/C12 interconnect drivers ; 333 / 8,584 ( 4 % ) ; |
; R3 interconnects ; 4,393 / 56,712 ( 8 % ) ; |
; R6 interconnects ; 6,014 / 131,000 ( 5 % ) ; |
; Spine clocks ; 6 / 150 ( 4 % ) ; |
; Wire stub REs ; 0 / 6,650 ( 0 % ) ; |
+---------------------------------------------+--------------------------+ |
|
|
+------------------------------------------+ |
2055,10 → 2263,10
; I/O Rules Statistic ; Total ; |
+----------------------------------+-------+ |
; Total I/O Rules ; 28 ; |
; Number of I/O Rules Passed ; 7 ; |
; Number of I/O Rules Passed ; 8 ; |
; Number of I/O Rules Failed ; 0 ; |
; Number of I/O Rules Unchecked ; 0 ; |
; Number of I/O Rules Inapplicable ; 21 ; |
; Number of I/O Rules Inapplicable ; 20 ; |
+----------------------------------+-------+ |
|
|
2067,7 → 2275,7
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+ |
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; |
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------------------------+-------------------+ |
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; |
; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ; |
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; |
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; |
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; |
2104,19 → 2312,19
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ |
; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ; |
+--------------------+--------------+-----------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+ |
; Total Pass ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ; |
; Total Pass ; 5 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 ; 19 ; 16 ; |
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; Total Inapplicable ; 19 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ; |
; Total Inapplicable ; 14 ; 0 ; 0 ; 19 ; 19 ; 0 ; 0 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 19 ; 0 ; 0 ; 3 ; |
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; dout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; sout_a ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[5] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[7] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[1] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[2] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[3] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[4] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; LED[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; KEY[0] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; |
; LED[6] ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Pass ; |
; FPGA_CLK1_50 ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; |
2173,123 → 2381,133
+---------------------------+--------+ |
|
|
+------------------------------------------------------------+ |
; Estimated Delay Added for Hold Timing Summary ; |
+-----------------+----------------------+-------------------+ |
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; |
+-----------------+----------------------+-------------------+ |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 417.7 ; |
+-----------------+----------------------+-------------------+ |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Estimated Delay Added for Hold Timing Summary ; |
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+ |
; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; |
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+ |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 603.1 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 152.8 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 85.5 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 83.9 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 65.3 ; |
; din_a ; din_a ; 47.9 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 39.2 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 31.9 ; |
; I/O ; din_a ; 25.0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 23.3 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i,clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 23.3 ; |
+-------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------+ |
Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. |
This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer. |
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Estimated Delay Added for Hold Timing Details ; |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ |
; Source Register ; Destination Register ; Delay Added in ns ; |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ |
; ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_2495 ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[3] ; 0.427 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.370 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.362 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|packet_in_progress ; 0.351 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_byteen_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|packet_in_progress ; 0.345 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.341 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.338 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[4] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[4] ; 0.331 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|new_burst_reg ; 0.325 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.315 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_size_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.315 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.312 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.312 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.312 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.311 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.309 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.308 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[1] ; 0.300 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_valid_reg ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.299 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem_used[1] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1] ; 0.295 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.294 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.294 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.294 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.294 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.293 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.293 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.293 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][78] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|saved_grant[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][74] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.292 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[2] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[0] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_reg[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][77] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[6] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[3] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[4] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[5] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[6] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_ready_hold ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.291 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; 0.290 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][74] ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ; 0.290 ; |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Estimated Delay Added for Hold Timing Details ; |
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+ |
; Source Register ; Destination Register ; Delay Added in ns ; |
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+ |
; din_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d|bit_d_0 ; 4.535 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; detector_tokens:m_x|bit_capture_data:capture_d|bit_d_0 ; 4.290 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[1] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[1] ; 2.916 ; |
; sin_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; 2.828 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[4] ; 2.799 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[7] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[7] ; 2.654 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[3] ; 2.645 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[0] ; 2.639 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[1] ; 2.638 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[2] ; 2.608 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[5] ; 2.608 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[3] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[3] ; 2.546 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[5] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[5] ; 2.540 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_sout_e ; detector_tokens:m_x|info[4] ; 2.341 ; |
; detector_tokens:m_x|info[5] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[5] ; 2.334 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.run ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[4] ; 2.323 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.ready ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[1] ; 2.323 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_wait ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[0] ; 2.310 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[4] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[4] ; 2.289 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[2] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[2] ; 2.289 ; |
; detector_tokens:m_x|info[2] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[2] ; 2.265 ; |
; detector_tokens:m_x|info[4] ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[4] ; 2.253 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[8] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[8] ; 2.240 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[0] ; 2.076 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[0] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[0] ; 2.018 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.started ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[2] ; 2.009 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|open_slot_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.001 ; 2.008 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[6] ; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[6] ; 2.007 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[3] ; 2.001 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[1] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[1] ; 1.991 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[2] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[2] ; 1.983 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[3] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[3] ; 1.970 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[0] ; 1.934 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|send_null_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.862 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[4] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[4] ; 1.857 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter[5] ; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[5] ; 1.839 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.702 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.687 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_timecode ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[0] ; 1.682 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[0] ; 1.670 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.599 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_got_fct_a ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; 1.540 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c_0 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.518 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_time_in_control_flag_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_data_flagctrl_tx_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_timec ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|data_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|eop_eep_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|fct_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|null_last ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[6] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[5] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_time_code_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[1] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_start ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|enable_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[2] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null_c ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.451 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_empty ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[0] ; 1.346 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_full ; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[0] ; 1.343 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[7] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.343 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; 1.318 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|data_out[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[0] ; 1.260 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|overflow_credit_error ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|get_rx_credit_error_b ; 1.259 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|write_tx ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|process_data ; 1.258 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|ready_tx_data ; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read~5 ; 1.255 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[3] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.249 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[8] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.238 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[10] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.230 ; |
; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[5] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.228 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.215 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[4] ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[0] ; 1.169 ; |
; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[3] ; detector_tokens:m_x|counter_neg:cnt_neg|is_control ; 1.153 ; |
+---------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------+-------------------+ |
Note: This table only shows the top 100 path(s) that have the largest delay added for hold. |
|
|
2296,6 → 2514,9
+-----------------+ |
; Fitter Messages ; |
+-----------------+ |
Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time |
Info (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit) |
Info (16304): Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal) |
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. |
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected |
Info (119006): Selected device 5CSEMA4U23C6 for design "spw_fifo_ulight" |
2310,19 → 2531,19
Info (184026): differential I/O pin "din_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "din_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 5 |
Info (184026): differential I/O pin "sin_a" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "sin_a(n)". File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 6 |
Info (184020): Starting Fitter periphery placement operations |
Warning (177007): PLL(s) placed in location FRACTIONALPLL_X68_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks |
Info (177008): PLL ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0|fpll |
Info (11178): Promoted 2 clocks (2 global) |
Info (11162): ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G10 |
Info (11162): ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G11 |
Info (11191): Automatically promoted 2 clocks (2 global) |
Info (11162): FPGA_CLK1_50~inputCLKENA0 with 3124 fanout uses global clock CLKCTRL_G5 |
Info (11162): ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out~CLKENA0 with 3025 fanout uses global clock CLKCTRL_G3 |
Info (12525): This signal is driven by core routing -- it may be moved during placement to reduce routing delays |
Info (11162): ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]~CLKENA0 with 3 fanout uses global clock CLKCTRL_G11 |
Info (11162): ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0]~CLKENA0 with 24 fanout uses global clock CLKCTRL_G8 |
Info (11191): Automatically promoted 1 clock (1 global) |
Info (11162): FPGA_CLK1_50~inputCLKENA0 with 3068 fanout uses global clock CLKCTRL_G4 |
Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00 |
Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc' |
Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc' |
Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. |
Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataa to: combout |
Info (332098): Cell: m_x|always3~0 from: dataa to: combout |
Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataa to: combout |
Info (332098): Cell: m_x|comb from: datab to: combout |
Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457 |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout |
2332,48 → 2553,61
Info (332111): Found 7 clocks |
Info (332111): Period Clock Name |
Info (332111): ======== ============ |
Info (332111): 4.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332111): 3.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332111): 3.000 din_a |
Info (332111): 10.000 FPGA_CLK1_50 |
Info (332111): 3.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e |
Info (332111): 10.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332111): 2.500 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332111): 4.000 din_a |
Info (332111): 20.000 FPGA_CLK1_50 |
Info (332111): 4.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332111): 2.500 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] |
Info (176233): Starting register packing |
Info (176222): Fitter will not automatically pack the registers into I/Os. |
Info (176221): The fitter is attempting to aggressively pack all registers connected to the input, output, or output enable pins into I/Os. |
Info (176235): Finished register packing |
Extra Info (176219): No registers were packed into other blocks |
Extra Info (176218): Packed 5 registers into blocks of type I/O output buffer |
Extra Info (176220): Created 5 register duplicates |
Info (223000): Starting Vectorless Power Activity Estimation |
Info (223001): Completed Vectorless Power Activity Estimation |
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:16 |
Warning (170136): Design uses Placement Effort Multiplier = 90.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt. |
Info (128000): Starting physical synthesis optimizations for speed |
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division |
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 662 ps |
Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division |
Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps |
Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:09 |
Info (176233): Starting register packing |
Info (176235): Finished register packing |
Extra Info (176219): No registers were packed into other blocks |
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:30 |
Warning (170136): Design uses Placement Effort Multiplier = 4.0. Using a Placement Effort Multiplier > 1.0 can increase processing time, especially when used during a second or third fitting attempt. |
Info (170189): Fitter placement preparation operations beginning |
Info (223000): Starting Vectorless Power Activity Estimation |
Info (223001): Completed Vectorless Power Activity Estimation |
Info (14951): The Fitter is using Advanced Physical Optimization. |
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:28 |
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:35 |
Info (223000): Starting Vectorless Power Activity Estimation |
Info (223001): Completed Vectorless Power Activity Estimation |
Info (170191): Fitter placement operations beginning |
Info (170137): Fitter placement was successful |
Info (170192): Fitter placement operations ending: elapsed time is 00:01:55 |
Info (170192): Fitter placement operations ending: elapsed time is 00:00:58 |
Info (170193): Fitter routing operations beginning |
Info (223000): Starting Vectorless Power Activity Estimation |
Info (223001): Completed Vectorless Power Activity Estimation |
Info (170195): Router estimated average interconnect usage is 3% of the available device resources |
Info (170196): Router estimated peak interconnect usage is 15% of the available device resources in the region that extends from location X11_Y24 to location X22_Y36 |
Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. |
Info (170200): Optimizations that may affect the design's timing were skipped |
Info (170194): Fitter routing operations ending: elapsed time is 00:00:40 |
Info (11888): Total time spent on timing analysis during the Fitter is 16.50 seconds. |
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:05 |
Info (170195): Router estimated average interconnect usage is 4% of the available device resources |
Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X46_Y0 to location X56_Y11 |
Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization. |
Info (170194): Fitter routing operations ending: elapsed time is 00:01:16 |
Info (11888): Total time spent on timing analysis during the Fitter is 27.50 seconds. |
Info (334003): Started post-fitting delay annotation |
Info (334004): Delay annotation completed successfully |
Info (334003): Started post-fitting delay annotation |
Info (334004): Delay annotation completed successfully |
Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:38 |
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. |
Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.fit.smsg |
Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings |
Info: Peak virtual memory: 2064 megabytes |
Info: Processing ended: Fri Sep 15 08:17:51 2017 |
Info: Elapsed time: 00:04:44 |
Info: Total CPU time (on all processors): 00:08:19 |
Info: Quartus Prime Fitter was successful. 0 errors, 6 warnings |
Info: Peak virtual memory: 2473 megabytes |
Info: Processing ended: Mon Feb 5 00:57:20 2018 |
Info: Elapsed time: 00:05:09 |
Info: Total CPU time (on all processors): 00:08:50 |
|
|
+----------------------------+ |
/spw_fifo_ulight.fit.smsg
4,3 → 4,7
Extra Info (176239): Inferring scan chains for DSP blocks is complete |
Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density |
Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks |
Extra Info (176238): Start inferring scan chains for DSP blocks |
Extra Info (176239): Inferring scan chains for DSP blocks is complete |
Extra Info (176246): Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density |
Extra Info (176247): Finished moving registers into I/O cells, DSP blocks, and RAM blocks |
/spw_fifo_ulight.fit.summary
1,12 → 1,12
Fitter Status : Successful - Fri Sep 15 08:17:49 2017 |
Quartus Prime Version : 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Fitter Status : Successful - Mon Feb 5 00:57:17 2018 |
Quartus Prime Version : 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
Revision Name : spw_fifo_ulight |
Top-level Entity Name : SPW_ULIGHT_FIFO |
Family : Cyclone V |
Device : 5CSEMA4U23C6 |
Timing Models : Final |
Logic utilization (in ALMs) : 3,209 / 15,880 ( 20 % ) |
Total registers : 4692 |
Logic utilization (in ALMs) : 3,362 / 15,880 ( 21 % ) |
Total registers : 4633 |
Total pins : 19 / 314 ( 6 % ) |
Total virtual pins : 0 |
Total block memory bits : 0 / 2,764,800 ( 0 % ) |
/spw_fifo_ulight.flow.rpt
1,6 → 1,6
Flow report for spw_fifo_ulight |
Fri Sep 15 08:19:20 2017 |
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Mon Feb 5 00:59:12 2018 |
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
|
|
--------------------- |
29,38 → 29,37
associated documentation or information are expressly subject |
to the terms and conditions of the Intel Program License |
Subscription Agreement, the Intel Quartus Prime License Agreement, |
the Intel MegaCore Function License Agreement, or other |
applicable license agreement, including, without limitation, |
that your use is for the sole purpose of programming logic |
devices manufactured by Intel and sold by Intel or its |
authorized distributors. Please refer to the applicable |
agreement for further details. |
the Intel FPGA IP License Agreement, or other applicable license |
agreement, including, without limitation, that your use is for |
the sole purpose of programming logic devices manufactured by |
Intel and sold by Intel or its authorized distributors. Please |
refer to the applicable agreement for further details. |
|
|
|
+-------------------------------------------------------------------------------+ |
; Flow Summary ; |
+---------------------------------+---------------------------------------------+ |
; Flow Status ; Successful - Fri Sep 15 08:19:20 2017 ; |
; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Device ; 5CSEMA4U23C6 ; |
; Timing Models ; Final ; |
; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ; |
; Total registers ; 4692 ; |
; Total pins ; 19 / 314 ( 6 % ) ; |
; Total virtual pins ; 0 ; |
; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ; |
; Total DSP Blocks ; 0 / 84 ( 0 % ) ; |
; Total HSSI RX PCSs ; 0 ; |
; Total HSSI PMA RX Deserializers ; 0 ; |
; Total HSSI TX PCSs ; 0 ; |
; Total HSSI PMA TX Serializers ; 0 ; |
; Total PLLs ; 1 / 5 ( 20 % ) ; |
; Total DLLs ; 0 / 4 ( 0 % ) ; |
+---------------------------------+---------------------------------------------+ |
+----------------------------------------------------------------------------------------+ |
; Flow Summary ; |
+---------------------------------+------------------------------------------------------+ |
; Flow Status ; Successful - Mon Feb 5 00:59:12 2018 ; |
; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Device ; 5CSEMA4U23C6 ; |
; Timing Models ; Final ; |
; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ; |
; Total registers ; 4633 ; |
; Total pins ; 19 / 314 ( 6 % ) ; |
; Total virtual pins ; 0 ; |
; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ; |
; Total DSP Blocks ; 0 / 84 ( 0 % ) ; |
; Total HSSI RX PCSs ; 0 ; |
; Total HSSI PMA RX Deserializers ; 0 ; |
; Total HSSI TX PCSs ; 0 ; |
; Total HSSI PMA TX Serializers ; 0 ; |
; Total PLLs ; 1 / 5 ( 20 % ) ; |
; Total DLLs ; 0 / 4 ( 0 % ) ; |
+---------------------------------+------------------------------------------------------+ |
|
|
+-----------------------------------------+ |
68,84 → 67,109
+-------------------+---------------------+ |
; Option ; Setting ; |
+-------------------+---------------------+ |
; Start date & time ; 09/15/2017 08:07:49 ; |
; Start date & time ; 02/05/2018 00:47:03 ; |
; Main task ; Compilation ; |
; Revision Name ; spw_fifo_ulight ; |
+-------------------+---------------------+ |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Flow Non-Default Global Settings ; |
+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+ |
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; |
+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+ |
; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ; |
; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ; |
; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ; |
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ; |
; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ; |
; AUTO_DELAY_CHAINS ; Off ; On ; -- ; -- ; |
; COMPILER_SIGNATURE_ID ; 31032335263289.150547366508423 ; -- ; -- ; -- ; |
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; |
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ; |
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_PARTITION ; On ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; INFER_RAMS_FROM_RAW_LOGIC ; Off ; On ; -- ; -- ; |
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; |
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/../ulight_fifo.cmp ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/ulight_fifo_hps_0_hps.svd ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/../../ulight_fifo.qsys ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ; |
; OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ; |
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Off ; Normal ; -- ; -- ; |
; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ; |
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ; |
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ; |
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ; |
; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ; |
; PLACEMENT_EFFORT_MULTIPLIER ; 90.0 ; 1.0 ; -- ; -- ; |
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; |
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; |
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; |
; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ; |
; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ; |
; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ; |
; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ; |
; SEED ; 893763639 ; 1 ; -- ; -- ; |
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ; |
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ; |
; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928 ; -- ; ulight_fifo ; -- ; |
; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ; |
; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ; |
; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ; |
; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ; |
+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+ |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Flow Non-Default Global Settings ; |
+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+ |
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; |
+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+ |
; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ; |
; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ; |
; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ; |
; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ; |
; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ; |
; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ; |
; AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ; On ; Off ; -- ; -- ; |
; AUTO_DSP_RECOGNITION ; Off ; On ; -- ; -- ; |
; AUTO_RAM_RECOGNITION ; Off ; On ; -- ; -- ; |
; AUTO_ROM_RECOGNITION ; Off ; On ; -- ; -- ; |
; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; Auto ; -- ; -- ; |
; BLOCK_RAM_TO_MLAB_CELL_CONVERSION ; Off ; On ; -- ; -- ; |
; COMPILER_SIGNATURE_ID ; 31032335263289.151779881804543 ; -- ; -- ; -- ; |
; DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ; |
; EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ; HSPICE (Signal Integrity) ; <None> ; -- ; -- ; |
; EDA_BOARD_DESIGN_TIMING_TOOL ; Stamp (Timing) ; <None> ; -- ; -- ; |
; EDA_INPUT_DATA_FORMAT ; Edif ; -- ; -- ; eda_design_synthesis ; |
; EDA_OUTPUT_DATA_FORMAT ; Stamp ; -- ; -- ; eda_board_design_timing ; |
; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ; |
; EDA_OUTPUT_DATA_FORMAT ; Hspice ; -- ; -- ; eda_board_design_signal_integrity ; |
; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_board_design_symbol ; |
; EDA_RUN_TOOL_AUTOMATICALLY ; Off ; -- ; -- ; eda_simulation ; |
; EDA_RUN_TOOL_AUTOMATICALLY ; Off ; -- ; -- ; eda_design_synthesis ; |
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; |
; ENABLE_SIGNALTAP ; Off ; -- ; -- ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; HPS_PARTITION ; On ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ; |
; INFER_RAMS_FROM_RAW_LOGIC ; Off ; On ; -- ; -- ; |
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; |
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/../ulight_fifo.cmp ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/ulight_fifo_hps_0_hps.svd ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/../../ulight_fifo.qsys ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ; |
; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ; |
; MUX_RESTRUCTURE ; Off ; Auto ; -- ; -- ; |
; OPTIMIZATION_MODE ; High Performance Effort ; Balanced ; -- ; -- ; |
; OPTIMIZE_FOR_METASTABILITY ; Off ; On ; -- ; -- ; |
; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ; |
; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ; |
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ; |
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ; |
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ; |
; PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ; On ; Off ; -- ; -- ; |
; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ; |
; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ; |
; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ; |
; PLACEMENT_EFFORT_MULTIPLIER ; 4.0 ; 1.0 ; -- ; -- ; |
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; |
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; |
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; |
; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ; |
; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ; |
; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ; |
; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ; |
; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; |
; SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL ; Off ; On ; -- ; -- ; |
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ; |
; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ; |
; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1516735843 ; -- ; ulight_fifo ; -- ; |
; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ; |
; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ; |
; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ; |
; SYNTH_GATED_CLOCK_CONVERSION ; On ; Off ; -- ; -- ; |
; SYNTH_PROTECT_SDC_CONSTRAINT ; On ; Off ; -- ; -- ; |
; SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ; Off ; On ; -- ; -- ; |
; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ; |
; USE_SIGNALTAP_FILE ; output_files/stp2.stp ; -- ; -- ; -- ; |
+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+ |
|
|
+-------------------------------------------------------------------------------------------------------------------------------+ |
153,12 → 177,12
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ |
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; |
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ |
; Analysis & Synthesis ; 00:01:16 ; 1.3 ; 1339 MB ; 00:01:53 ; |
; Fitter ; 00:04:42 ; 1.0 ; 2064 MB ; 00:08:17 ; |
; Assembler ; 00:00:18 ; 1.0 ; 1040 MB ; 00:00:12 ; |
; TimeQuest Timing Analyzer ; 00:00:54 ; 1.5 ; 1351 MB ; 00:01:15 ; |
; EDA Netlist Writer ; 00:00:08 ; 1.0 ; 1314 MB ; 00:00:08 ; |
; Total ; 00:07:18 ; -- ; -- ; 00:11:45 ; |
; Analysis & Synthesis ; 00:01:23 ; 1.3 ; 1287 MB ; 00:01:52 ; |
; Fitter ; 00:05:06 ; 1.1 ; 2473 MB ; 00:08:48 ; |
; Assembler ; 00:00:19 ; 1.0 ; 1044 MB ; 00:00:11 ; |
; TimeQuest Timing Analyzer ; 00:01:19 ; 1.2 ; 1444 MB ; 00:01:24 ; |
; EDA Netlist Writer ; 00:00:06 ; 1.0 ; 1244 MB ; 00:00:06 ; |
; Total ; 00:08:13 ; -- ; -- ; 00:12:21 ; |
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+ |
|
|
/spw_fifo_ulight.jdi
1,6 → 1,6
<sld_project_info> |
<project> |
<hash md5_digest_80b="44aae282629f81e64ba6"/> |
<hash md5_digest_80b="75ec33d5280c476d4c87"/> |
</project> |
<file_info> |
<file device="5CSEMA4U23C6" path="spw_fifo_ulight.sof" usercode="0xFFFFFFFF"/> |
8,7 → 8,7
<sld_infos> |
<sld_info hpath="ulight_fifo:u0" name="u0"> |
<assignment_values> |
<assignment_value text="QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928"/> |
<assignment_value text="QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1516735843"/> |
</assignment_values> |
<parameters/> |
</sld_info> |
/spw_fifo_ulight.map.rpt
1,6 → 1,6
Analysis & Synthesis report for spw_fifo_ulight |
Fri Sep 15 08:13:05 2017 |
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Mon Feb 5 00:52:10 2018 |
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
|
|
--------------------- |
36,839 → 36,856
28. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state |
29. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state |
30. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state |
31. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state |
32. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|state_tx |
33. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_type |
34. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm |
35. Registers Protected by Synthesis |
36. Registers Removed During Synthesis |
37. Removed Registers Triggering Further Register Optimizations |
38. General Register Statistics |
39. Inverted Register Statistics |
40. Multiplexer Restructuring Statistics (Restructuring Performed) |
41. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll |
42. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0 |
43. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad |
44. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated |
45. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst |
46. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0 |
47. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct |
48. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll |
49. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i |
50. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 |
51. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 |
52. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 |
53. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 |
54. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 |
55. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux |
56. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 |
57. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux |
58. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_001 |
59. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_002 |
60. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_003 |
61. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 |
62. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_005 |
63. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_006 |
64. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 |
65. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 |
66. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 |
67. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 |
68. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 |
69. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_012 |
70. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_013 |
71. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 |
72. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 |
73. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_016 |
74. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_017 |
75. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 |
76. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_019 |
77. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_020 |
78. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_021 |
79. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 |
80. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
81. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 |
82. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
83. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0 |
84. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll |
85. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0 |
86. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy |
87. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc |
88. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads |
89. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads |
90. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc |
91. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc |
92. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc |
93. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc |
94. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc |
95. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc |
96. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc |
97. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc |
98. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc |
99. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc |
100. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc |
101. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc |
102. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc |
103. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc |
104. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc |
105. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc |
106. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc |
107. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc |
108. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc |
109. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc |
110. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc |
111. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc |
112. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc |
113. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad |
114. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad |
115. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad |
116. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad |
117. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad |
118. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs |
119. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst |
120. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq |
121. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0 |
122. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct |
123. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll |
124. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i |
125. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator |
126. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator |
127. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator |
128. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator |
129. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator |
130. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator |
131. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator |
132. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator |
133. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator |
134. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator |
135. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator |
136. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator |
137. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator |
138. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator |
139. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator |
140. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator |
141. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator |
142. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator |
143. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator |
144. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator |
145. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator |
146. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator |
147. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent |
148. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size |
149. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent |
150. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
151. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo |
152. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo |
153. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent |
154. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
155. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo |
156. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo |
157. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent |
158. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
159. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo |
160. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo |
161. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent |
162. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
163. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo |
164. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo |
165. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent |
166. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
167. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo |
168. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo |
169. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent |
170. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
171. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo |
172. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo |
173. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent |
174. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
175. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo |
176. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo |
177. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent |
178. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
179. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo |
180. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo |
181. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent |
182. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
183. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo |
184. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo |
185. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent |
186. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
187. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo |
188. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo |
189. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent |
190. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
191. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo |
192. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo |
193. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent |
194. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
195. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo |
196. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo |
197. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent |
198. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
199. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo |
200. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo |
201. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent |
202. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
203. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo |
204. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo |
205. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent |
206. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
207. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo |
208. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo |
209. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent |
210. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
211. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo |
212. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo |
213. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent |
214. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
215. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo |
216. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo |
217. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent |
218. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
219. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo |
220. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo |
221. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent |
222. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
223. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo |
224. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo |
225. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent |
226. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
227. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo |
228. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo |
229. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent |
230. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
231. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo |
232. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo |
233. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent |
234. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
235. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo |
236. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo |
237. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode |
238. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode |
239. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
240. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_003|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
241. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_004|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
242. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_005|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
243. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_006|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
244. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_007|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
245. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_008|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
246. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_009|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
247. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_010|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
248. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_011|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
249. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_012|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
250. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_013|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
251. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_014|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
252. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_015|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
253. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_016|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
254. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_017|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
255. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_018|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
256. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_019|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
257. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_020|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
258. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_021|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
259. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_022|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
260. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_023|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
261. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter |
262. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter |
263. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter |
264. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
265. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
266. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
267. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
268. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
269. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
270. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
271. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
272. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
273. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
274. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
275. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
276. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
277. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
278. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
279. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
280. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter |
281. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
282. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
283. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
284. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
285. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
286. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
287. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
288. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
289. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
290. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
291. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
292. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
293. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
294. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
295. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
296. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
297. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter |
298. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
299. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
300. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
301. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
302. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
303. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
304. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
305. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
306. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
307. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
308. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
309. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
310. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
311. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
312. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
313. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
314. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter |
315. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
316. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
317. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
318. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
319. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
320. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
321. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
322. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
323. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
324. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
325. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
326. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
327. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
328. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
329. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
330. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
331. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter |
332. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
333. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
334. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
335. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
336. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
337. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
338. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
339. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
340. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
341. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
342. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
343. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
344. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
345. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
346. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
347. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
348. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter |
349. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
350. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
351. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
352. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
353. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
354. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
355. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
356. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
357. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
358. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
359. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
360. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
361. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
362. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
363. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
364. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
365. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter |
366. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
367. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
368. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
369. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
370. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
371. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
372. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
373. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
374. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
375. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
376. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
377. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
378. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
379. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
380. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
381. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
382. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter |
383. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
384. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
385. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
386. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
387. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
388. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
389. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
390. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
391. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
392. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
393. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
394. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
395. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
396. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
397. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
398. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
399. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter |
400. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
401. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
402. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
403. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
404. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
405. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
406. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
407. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
408. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
409. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
410. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
411. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
412. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
413. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
414. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
415. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
416. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter |
417. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
418. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
419. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
420. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
421. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
422. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
423. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
424. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
425. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
426. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
427. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
428. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
429. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
430. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
431. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
432. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
433. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter |
434. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
435. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
436. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
437. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
438. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
439. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
440. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
441. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
442. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
443. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
444. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
445. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
446. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
447. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
448. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
449. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
450. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter |
451. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
452. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
453. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
454. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
455. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
456. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
457. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
458. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
459. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
460. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
461. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
462. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
463. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
464. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
465. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
466. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
467. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter |
468. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
469. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
470. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
471. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
472. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
473. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
474. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
475. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
476. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
477. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
478. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
479. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
480. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
481. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
482. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
483. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
484. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter |
485. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
486. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
487. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
488. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
489. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
490. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
491. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
492. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
493. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
494. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
495. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
496. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
497. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
498. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
499. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
500. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
501. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter |
502. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
503. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
504. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
505. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
506. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
507. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
508. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
509. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
510. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
511. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
512. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
513. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
514. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
515. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
516. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
517. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
518. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter |
519. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
520. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
521. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
522. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
523. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
524. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
525. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
526. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
527. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
528. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
529. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
530. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
531. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
532. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
533. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
534. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
535. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter |
536. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
537. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
538. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
539. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
540. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
541. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
542. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
543. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
544. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
545. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
546. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
547. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
548. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
549. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
550. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
551. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
552. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter |
553. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
554. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
555. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
556. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
557. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
558. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
559. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
560. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
561. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
562. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
563. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
564. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
565. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
566. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
567. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
568. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
569. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter |
570. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
571. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
572. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
573. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
574. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
575. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
576. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
577. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
578. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
579. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
580. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
581. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
582. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
583. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
584. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
585. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
586. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter |
587. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
588. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
589. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
590. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
591. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
592. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
593. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
594. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
595. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
596. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
597. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
598. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
599. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
600. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
601. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
602. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
603. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter |
604. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
605. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
606. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
607. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
608. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
609. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
610. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
611. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
612. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
613. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
614. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
615. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
616. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
617. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
618. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
619. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
620. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter |
621. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
622. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
623. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
624. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
625. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
626. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
627. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
628. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
629. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
630. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
631. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
632. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
633. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
634. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
635. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
636. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
637. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb |
638. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
639. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb |
640. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
641. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb |
642. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
643. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb |
644. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
645. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb |
646. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
647. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb |
648. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
649. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb |
650. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
651. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb |
652. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
653. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb |
654. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
655. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb |
656. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
657. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb |
658. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
659. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb |
660. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
661. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb |
662. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
663. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb |
664. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
665. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb |
666. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
667. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb |
668. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
669. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb |
670. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
671. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb |
672. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
673. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb |
674. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
675. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb |
676. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
677. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb |
678. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
679. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb |
680. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
681. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb |
682. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
683. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb |
684. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
685. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter |
686. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 |
687. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 |
688. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 |
689. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 |
690. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 |
691. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 |
692. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 |
693. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 |
694. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 |
695. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 |
696. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 |
697. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 |
698. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 |
699. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014 |
700. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015 |
701. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016 |
702. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017 |
703. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018 |
704. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019 |
705. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020 |
706. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021 |
707. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller |
708. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 |
709. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
710. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001 |
711. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 |
712. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
713. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data |
714. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data |
715. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller_001" |
716. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" |
717. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller" |
718. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" |
719. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" |
720. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub" |
721. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub" |
722. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub" |
723. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub" |
724. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub" |
725. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" |
726. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" |
727. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" |
728. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" |
729. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode" |
730. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode" |
731. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo" |
732. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo" |
733. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent" |
734. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo" |
735. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo" |
736. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent" |
737. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo" |
738. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo" |
739. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent" |
740. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo" |
741. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo" |
742. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent" |
743. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo" |
744. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo" |
745. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent" |
746. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo" |
747. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo" |
748. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent" |
749. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo" |
750. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo" |
751. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent" |
752. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo" |
753. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo" |
754. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent" |
755. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo" |
756. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo" |
757. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent" |
758. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo" |
759. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo" |
760. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent" |
761. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo" |
762. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo" |
763. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent" |
764. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo" |
765. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo" |
766. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent" |
767. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo" |
768. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo" |
769. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent" |
770. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo" |
771. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo" |
772. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent" |
773. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo" |
774. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo" |
775. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent" |
776. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo" |
777. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo" |
778. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent" |
779. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo" |
780. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo" |
781. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent" |
782. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo" |
783. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo" |
784. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent" |
785. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo" |
786. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo" |
787. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent" |
788. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo" |
789. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo" |
790. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent" |
791. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo" |
792. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo" |
793. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent" |
794. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo" |
795. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo" |
796. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent" |
797. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" |
798. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent" |
799. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator" |
800. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator" |
801. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator" |
802. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator" |
803. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator" |
804. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator" |
805. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator" |
806. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator" |
807. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator" |
808. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator" |
809. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator" |
810. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator" |
811. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator" |
812. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator" |
813. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator" |
814. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator" |
815. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator" |
816. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator" |
817. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator" |
818. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator" |
819. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator" |
820. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator" |
821. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" |
822. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0" |
823. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0" |
824. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" |
825. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" |
826. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad" |
827. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad" |
828. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad" |
829. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad" |
830. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc" |
831. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc" |
832. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc" |
833. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc" |
834. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc" |
835. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc" |
836. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc" |
837. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc" |
838. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc" |
839. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc" |
840. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc" |
841. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc" |
842. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc" |
843. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc" |
844. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc" |
845. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc" |
846. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc" |
847. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc" |
848. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc" |
849. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc" |
850. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc" |
851. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc" |
852. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc" |
853. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" |
854. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads" |
855. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc" |
856. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0" |
857. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst" |
858. Port Connectivity Checks: "ulight_fifo:u0" |
859. Post-Synthesis Netlist Statistics for Top Partition |
860. Post-Synthesis Netlist Statistics for Partition ulight_fifo_hps_0_hps_io_border:border |
861. Elapsed Time Per Partition |
862. Analysis & Synthesis Messages |
863. Analysis & Synthesis Suppressed Messages |
31. State Machine - |SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process |
32. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot |
33. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write |
34. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read |
35. State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state |
36. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read |
37. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx |
38. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send |
39. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p |
40. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p |
41. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write |
42. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive |
43. State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm |
44. Registers Protected by Synthesis |
45. Registers Removed During Synthesis |
46. Removed Registers Triggering Further Register Optimizations |
47. General Register Statistics |
48. Inverted Register Statistics |
49. Multiplexer Restructuring Statistics (No Restructuring Performed) |
50. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll |
51. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0 |
52. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad |
53. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated |
54. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst |
55. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0 |
56. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct |
57. Source assignments for ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll |
58. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i |
59. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0 |
60. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1 |
61. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2 |
62. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3 |
63. Source assignments for ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4 |
64. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux |
65. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 |
66. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux |
67. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_001 |
68. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_002 |
69. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_003 |
70. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 |
71. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_005 |
72. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_006 |
73. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 |
74. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 |
75. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 |
76. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 |
77. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 |
78. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_012 |
79. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_013 |
80. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 |
81. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 |
82. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_016 |
83. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_017 |
84. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 |
85. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_019 |
86. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_020 |
87. Source assignments for ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_021 |
88. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 |
89. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
90. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 |
91. Source assignments for ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
92. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv |
93. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt |
94. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd |
95. Source assignments for spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data |
96. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0 |
97. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll |
98. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0 |
99. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy |
100. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc |
101. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads |
102. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads |
103. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc |
104. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc |
105. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc |
106. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc |
107. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc |
108. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc |
109. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc |
110. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc |
111. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc |
112. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc |
113. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc |
114. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc |
115. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc |
116. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc |
117. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc |
118. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc |
119. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc |
120. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc |
121. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc |
122. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc |
123. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc |
124. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc |
125. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc |
126. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad |
127. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad |
128. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad |
129. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad |
130. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad |
131. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs |
132. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst |
133. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq |
134. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0 |
135. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_oct_cyclonev:oct |
136. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_dll_cyclonev:dll |
137. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i |
138. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator |
139. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator |
140. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator |
141. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator |
142. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator |
143. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator |
144. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator |
145. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator |
146. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator |
147. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator |
148. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator |
149. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator |
150. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator |
151. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator |
152. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator |
153. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator |
154. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator |
155. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator |
156. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator |
157. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator |
158. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator |
159. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator |
160. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent |
161. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size |
162. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent |
163. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
164. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo |
165. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo |
166. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent |
167. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
168. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo |
169. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo |
170. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent |
171. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
172. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo |
173. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo |
174. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent |
175. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
176. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo |
177. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo |
178. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent |
179. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
180. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo |
181. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo |
182. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent |
183. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
184. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo |
185. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo |
186. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent |
187. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
188. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo |
189. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo |
190. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent |
191. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
192. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo |
193. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo |
194. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent |
195. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
196. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo |
197. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo |
198. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent |
199. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
200. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo |
201. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo |
202. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent |
203. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
204. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo |
205. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo |
206. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent |
207. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
208. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo |
209. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo |
210. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent |
211. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
212. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo |
213. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo |
214. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent |
215. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
216. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo |
217. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo |
218. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent |
219. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
220. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo |
221. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo |
222. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent |
223. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
224. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo |
225. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo |
226. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent |
227. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
228. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo |
229. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo |
230. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent |
231. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
232. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo |
233. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo |
234. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent |
235. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
236. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo |
237. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo |
238. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent |
239. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
240. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo |
241. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo |
242. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent |
243. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
244. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo |
245. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo |
246. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent |
247. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor |
248. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo |
249. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo |
250. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode |
251. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode |
252. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
253. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_003|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
254. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_004|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
255. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_005|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
256. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_006|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
257. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_007|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
258. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_008|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
259. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_009|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
260. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_010|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
261. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_011|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
262. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_012|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
263. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_013|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
264. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_014|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
265. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_015|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
266. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_016|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
267. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_017|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
268. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_018|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
269. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_019|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
270. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_020|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
271. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_021|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
272. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_022|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
273. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_023|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode |
274. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter |
275. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter |
276. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter |
277. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
278. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
279. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
280. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
281. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
282. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
283. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
284. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
285. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
286. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
287. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
288. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
289. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
290. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
291. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
292. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
293. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter |
294. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
295. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
296. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
297. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
298. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
299. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
300. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
301. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
302. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
303. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
304. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
305. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
306. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
307. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
308. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
309. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
310. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter |
311. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
312. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
313. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
314. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
315. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
316. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
317. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
318. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
319. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
320. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
321. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
322. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
323. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
324. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
325. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
326. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
327. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter |
328. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
329. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
330. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
331. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
332. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
333. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
334. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
335. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
336. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
337. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
338. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
339. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
340. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
341. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
342. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
343. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
344. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter |
345. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
346. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
347. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
348. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
349. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
350. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
351. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
352. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
353. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
354. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
355. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
356. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
357. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
358. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
359. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
360. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
361. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter |
362. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
363. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
364. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
365. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
366. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
367. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
368. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
369. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
370. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
371. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
372. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
373. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
374. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
375. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
376. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
377. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
378. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter |
379. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
380. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
381. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
382. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
383. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
384. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
385. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
386. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
387. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
388. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
389. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
390. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
391. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
392. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
393. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
394. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
395. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter |
396. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
397. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
398. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
399. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
400. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
401. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
402. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
403. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
404. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
405. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
406. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
407. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
408. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
409. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
410. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
411. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
412. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter |
413. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
414. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
415. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
416. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
417. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
418. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
419. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
420. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
421. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
422. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
423. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
424. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
425. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
426. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
427. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
428. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
429. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter |
430. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
431. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
432. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
433. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
434. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
435. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
436. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
437. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
438. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
439. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
440. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
441. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
442. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
443. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
444. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
445. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
446. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter |
447. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
448. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
449. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
450. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
451. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
452. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
453. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
454. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
455. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
456. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
457. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
458. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
459. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
460. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
461. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
462. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
463. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter |
464. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
465. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
466. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
467. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
468. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
469. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
470. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
471. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
472. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
473. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
474. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
475. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
476. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
477. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
478. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
479. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
480. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter |
481. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
482. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
483. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
484. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
485. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
486. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
487. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
488. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
489. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
490. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
491. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
492. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
493. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
494. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
495. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
496. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
497. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter |
498. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
499. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
500. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
501. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
502. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
503. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
504. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
505. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
506. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
507. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
508. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
509. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
510. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
511. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
512. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
513. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
514. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter |
515. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
516. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
517. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
518. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
519. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
520. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
521. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
522. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
523. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
524. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
525. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
526. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
527. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
528. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
529. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
530. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
531. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter |
532. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
533. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
534. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
535. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
536. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
537. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
538. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
539. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
540. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
541. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
542. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
543. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
544. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
545. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
546. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
547. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
548. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter |
549. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
550. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
551. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
552. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
553. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
554. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
555. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
556. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
557. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
558. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
559. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
560. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
561. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
562. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
563. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
564. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
565. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter |
566. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
567. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
568. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
569. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
570. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
571. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
572. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
573. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
574. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
575. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
576. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
577. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
578. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
579. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
580. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
581. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
582. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter |
583. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
584. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
585. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
586. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
587. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
588. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
589. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
590. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
591. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
592. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
593. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
594. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
595. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
596. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
597. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
598. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
599. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter |
600. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
601. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
602. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
603. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
604. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
605. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
606. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
607. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
608. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
609. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
610. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
611. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
612. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
613. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
614. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
615. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
616. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter |
617. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
618. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
619. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
620. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
621. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
622. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
623. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
624. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
625. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
626. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
627. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
628. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
629. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
630. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
631. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
632. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
633. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter |
634. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter |
635. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size |
636. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_burstwrap_increment:the_burstwrap_increment |
637. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min |
638. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub |
639. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract |
640. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub |
641. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub|altera_merlin_burst_adapter_adder:subtract |
642. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub |
643. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub|altera_merlin_burst_adapter_adder:subtract |
644. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub |
645. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub|altera_merlin_burst_adapter_adder:subtract |
646. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub |
647. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub|altera_merlin_burst_adapter_adder:subtract |
648. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub |
649. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub|altera_merlin_burst_adapter_adder:subtract |
650. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb |
651. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
652. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb |
653. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
654. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb |
655. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
656. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb |
657. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
658. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb |
659. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
660. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb |
661. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
662. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb |
663. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
664. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb |
665. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
666. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb |
667. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
668. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb |
669. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
670. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb |
671. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
672. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb |
673. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
674. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb |
675. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
676. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb |
677. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
678. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb |
679. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
680. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb |
681. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
682. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb |
683. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
684. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb |
685. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
686. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb |
687. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
688. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb |
689. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
690. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb |
691. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
692. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb |
693. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
694. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb |
695. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
696. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb |
697. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder |
698. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter |
699. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 |
700. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 |
701. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 |
702. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 |
703. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 |
704. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 |
705. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 |
706. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 |
707. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 |
708. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 |
709. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 |
710. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 |
711. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 |
712. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014 |
713. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015 |
714. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016 |
715. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017 |
716. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018 |
717. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019 |
718. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020 |
719. Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021 |
720. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller |
721. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1 |
722. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
723. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001 |
724. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 |
725. Parameter Settings for User Entity Instance: ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_req_sync_uq1 |
726. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data |
727. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx |
728. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data |
729. Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx |
730. Port Connectivity Checks: "detector_tokens:m_x|bit_capture_control:capture_c" |
731. Port Connectivity Checks: "detector_tokens:m_x|bit_capture_data:capture_d" |
732. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller_001" |
733. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" |
734. Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller" |
735. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" |
736. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|altera_merlin_arb_adder:adder" |
737. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:dc_sub" |
738. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:db_sub" |
739. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:da_sub" |
740. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:bc_sub" |
741. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ac_sub" |
742. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub|altera_merlin_burst_adapter_adder:subtract" |
743. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min|altera_merlin_burst_adapter_subtractor:ab_sub" |
744. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_burst_adapter_min:the_min" |
745. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size" |
746. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002|ulight_fifo_mm_interconnect_0_router_002_default_decode:the_default_decode" |
747. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|ulight_fifo_mm_interconnect_0_router_default_decode:the_default_decode" |
748. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo" |
749. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo" |
750. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent" |
751. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo" |
752. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo" |
753. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent" |
754. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo" |
755. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo" |
756. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent" |
757. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo" |
758. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo" |
759. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent" |
760. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo" |
761. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo" |
762. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent" |
763. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo" |
764. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo" |
765. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent" |
766. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo" |
767. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo" |
768. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent" |
769. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo" |
770. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo" |
771. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent" |
772. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo" |
773. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo" |
774. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent" |
775. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo" |
776. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo" |
777. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent" |
778. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo" |
779. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo" |
780. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent" |
781. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo" |
782. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo" |
783. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent" |
784. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo" |
785. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo" |
786. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent" |
787. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo" |
788. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo" |
789. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent" |
790. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo" |
791. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo" |
792. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent" |
793. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo" |
794. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo" |
795. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent" |
796. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo" |
797. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo" |
798. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent" |
799. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo" |
800. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo" |
801. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent" |
802. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo" |
803. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo" |
804. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent" |
805. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo" |
806. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo" |
807. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent" |
808. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo" |
809. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo" |
810. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent" |
811. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo" |
812. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo" |
813. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent" |
814. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size" |
815. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent" |
816. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator" |
817. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator" |
818. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator" |
819. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator" |
820. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator" |
821. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator" |
822. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator" |
823. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator" |
824. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator" |
825. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator" |
826. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator" |
827. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator" |
828. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator" |
829. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator" |
830. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator" |
831. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator" |
832. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator" |
833. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator" |
834. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator" |
835. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator" |
836. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator" |
837. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator" |
838. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" |
839. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_pll_0:pll_0" |
840. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0" |
841. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" |
842. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" |
843. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ureset_n_pad" |
844. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ucmd_pad" |
845. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:ubank_pad" |
846. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_generic_ddio:uaddress_pad" |
847. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[22].acv_ac_ldc" |
848. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[21].acv_ac_ldc" |
849. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[20].acv_ac_ldc" |
850. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[19].acv_ac_ldc" |
851. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[18].acv_ac_ldc" |
852. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[17].acv_ac_ldc" |
853. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[16].acv_ac_ldc" |
854. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[15].acv_ac_ldc" |
855. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[14].acv_ac_ldc" |
856. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[13].acv_ac_ldc" |
857. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[12].acv_ac_ldc" |
858. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[11].acv_ac_ldc" |
859. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[10].acv_ac_ldc" |
860. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[9].acv_ac_ldc" |
861. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[8].acv_ac_ldc" |
862. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[7].acv_ac_ldc" |
863. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[6].acv_ac_ldc" |
864. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[5].acv_ac_ldc" |
865. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[4].acv_ac_ldc" |
866. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[3].acv_ac_ldc" |
867. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[2].acv_ac_ldc" |
868. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[1].acv_ac_ldc" |
869. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_acv_ldc:address_gen[0].acv_ac_ldc" |
870. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads" |
871. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads" |
872. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_ldc:memphy_ldc" |
873. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0" |
874. Port Connectivity Checks: "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst" |
875. Port Connectivity Checks: "ulight_fifo:u0" |
876. Post-Synthesis Netlist Statistics for Top Partition |
877. Post-Synthesis Netlist Statistics for Partition ulight_fifo_hps_0_hps_io_border:border |
878. Elapsed Time Per Partition |
879. Analysis & Synthesis Messages |
880. Analysis & Synthesis Suppressed Messages |
|
|
|
883,36 → 900,35
associated documentation or information are expressly subject |
to the terms and conditions of the Intel Program License |
Subscription Agreement, the Intel Quartus Prime License Agreement, |
the Intel MegaCore Function License Agreement, or other |
applicable license agreement, including, without limitation, |
that your use is for the sole purpose of programming logic |
devices manufactured by Intel and sold by Intel or its |
authorized distributors. Please refer to the applicable |
agreement for further details. |
the Intel FPGA IP License Agreement, or other applicable license |
agreement, including, without limitation, that your use is for |
the sole purpose of programming logic devices manufactured by |
Intel and sold by Intel or its authorized distributors. Please |
refer to the applicable agreement for further details. |
|
|
|
+-------------------------------------------------------------------------------+ |
; Analysis & Synthesis Summary ; |
+---------------------------------+---------------------------------------------+ |
; Analysis & Synthesis Status ; Successful - Fri Sep 15 08:13:05 2017 ; |
; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Logic utilization (in ALMs) ; N/A ; |
; Total registers ; 4692 ; |
; Total pins ; 15 ; |
; Total virtual pins ; 0 ; |
; Total block memory bits ; 0 ; |
; Total DSP Blocks ; 0 ; |
; Total HSSI RX PCSs ; 0 ; |
; Total HSSI PMA RX Deserializers ; 0 ; |
; Total HSSI TX PCSs ; 0 ; |
; Total HSSI PMA TX Serializers ; 0 ; |
; Total PLLs ; 1 ; |
; Total DLLs ; 0 ; |
+---------------------------------+---------------------------------------------+ |
+----------------------------------------------------------------------------------------+ |
; Analysis & Synthesis Summary ; |
+---------------------------------+------------------------------------------------------+ |
; Analysis & Synthesis Status ; Successful - Mon Feb 5 00:52:09 2018 ; |
; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ; |
; Revision Name ; spw_fifo_ulight ; |
; Top-level Entity Name ; SPW_ULIGHT_FIFO ; |
; Family ; Cyclone V ; |
; Logic utilization (in ALMs) ; N/A ; |
; Total registers ; 4628 ; |
; Total pins ; 15 ; |
; Total virtual pins ; 0 ; |
; Total block memory bits ; 0 ; |
; Total DSP Blocks ; 0 ; |
; Total HSSI RX PCSs ; 0 ; |
; Total HSSI PMA RX Deserializers ; 0 ; |
; Total HSSI TX PCSs ; 0 ; |
; Total HSSI PMA TX Serializers ; 0 ; |
; Total PLLs ; 1 ; |
; Total DLLs ; 0 ; |
+---------------------------------+------------------------------------------------------+ |
|
|
+---------------------------------------------------------------------------------------------------------------------------+ |
923,23 → 939,31
; Device ; 5CSEMA4U23C6 ; ; |
; Top-level entity name ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; |
; Family name ; Cyclone V ; Cyclone V ; |
; Restructure Multiplexers ; Off ; Auto ; |
; State Machine Processing ; One-Hot ; Auto ; |
; Safe State Machine ; On ; Off ; |
; Infer RAMs from Raw Logic ; Off ; On ; |
; Remove Duplicate Registers ; Off ; On ; |
; Optimization Technique ; Speed ; Balanced ; |
; Auto ROM Replacement ; Off ; On ; |
; Auto RAM Replacement ; Off ; On ; |
; Auto DSP Block Replacement ; Off ; On ; |
; Auto Shift Register Replacement ; Off ; Auto ; |
; Allow Shift Register Merging across Hierarchies ; Off ; Auto ; |
; Allow Synchronous Control Signals ; Off ; On ; |
; Auto Gated Clock Conversion ; On ; Off ; |
; SDC constraint protection ; On ; Off ; |
; Shift Register Replacement - Allow Asynchronous Clear Signal ; Off ; On ; |
; Disable Register Merging Across Hierarchies ; Off ; Auto ; |
; Resource Aware Inference For Block RAM ; Off ; On ; |
; Use smart compilation ; Off ; Off ; |
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; |
; Enable compact report table ; Off ; Off ; |
; Restructure Multiplexers ; Auto ; Auto ; |
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ; |
; Create Debugging Nodes for IP Cores ; Off ; Off ; |
; Preserve fewer node names ; On ; On ; |
; OpenCore Plus hardware evaluation ; Enable ; Enable ; |
; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; |
; Verilog Version ; Verilog_2001 ; Verilog_2001 ; |
; VHDL Version ; VHDL_1993 ; VHDL_1993 ; |
; Safe State Machine ; Off ; Off ; |
; Extract Verilog State Machines ; On ; On ; |
; Extract VHDL State Machines ; On ; On ; |
; Ignore Verilog initial constructs ; Off ; Off ; |
958,14 → 982,11
; Ignore LCELL Buffers ; Off ; Off ; |
; Ignore SOFT Buffers ; On ; On ; |
; Limit AHDL Integers to 32 Bits ; Off ; Off ; |
; Optimization Technique ; Balanced ; Balanced ; |
; Carry Chain Length ; 70 ; 70 ; |
; Auto Carry Chains ; On ; On ; |
; Auto Open-Drain Pins ; On ; On ; |
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; |
; Auto ROM Replacement ; On ; On ; |
; Auto RAM Replacement ; On ; On ; |
; Auto DSP Block Replacement ; On ; On ; |
; Auto Shift Register Replacement ; Auto ; Auto ; |
; Auto Clock Enable Replacement ; On ; On ; |
; Strict RAM Replacement ; Off ; Off ; |
; Force Use of Synchronous Clear Signals ; Off ; Off ; |
981,7 → 1002,7
; Report Connectivity Checks ; On ; On ; |
; Ignore Maximum Fan-Out Assignments ; Off ; Off ; |
; Synchronization Register Chain Length ; 3 ; 3 ; |
; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; |
; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; |
; HDL message level ; Level2 ; Level2 ; |
; Suppress Register Optimization Related Messages ; Off ; Off ; |
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; |
988,15 → 1009,10
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; |
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; |
; Clock MUX Protection ; On ; On ; |
; Auto Gated Clock Conversion ; Off ; Off ; |
; Block Design Naming ; Auto ; Auto ; |
; SDC constraint protection ; Off ; Off ; |
; Synthesis Effort ; Auto ; Auto ; |
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; |
; Pre-Mapping Resynthesis Optimization ; Off ; Off ; |
; Analysis & Synthesis Message Level ; Medium ; Medium ; |
; Disable Register Merging Across Hierarchies ; Auto ; Auto ; |
; Resource Aware Inference For Block RAM ; On ; On ; |
; Automatic Parallel Synthesis ; On ; On ; |
; Partial Reconfiguration Bitstream ID ; Off ; Off ; |
+---------------------------------------------------------------------------------+--------------------+--------------------+ |
1010,12 → 1026,12
; Number detected on machine ; 4 ; |
; Maximum allowed ; 2 ; |
; ; ; |
; Average used ; 1.31 ; |
; Average used ; 1.33 ; |
; Maximum used ; 2 ; |
; ; ; |
; Usage by Processor ; % Time Used ; |
; Processor 1 ; 100.0% ; |
; Processor 2 ; 31.2% ; |
; Processor 2 ; 32.8% ; |
+----------------------------+-------------+ |
|
|
1024,9 → 1040,20
+-----------------------------------------------------------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+ |
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; |
+-----------------------------------------------------------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+ |
; ../../rtl/DEBUG_VERILOG/detector_tokens.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v ; ; |
; ../../rtl/DEBUG_VERILOG/debounce.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v ; ; |
; ../../rtl/DEBUG_VERILOG/clock_reduce.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v ; ; |
; ../../rtl/RTL_VB/tx_fsm_m.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v ; ; |
; ../../rtl/RTL_VB/tx_fct_send.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v ; ; |
; ../../rtl/RTL_VB/tx_fct_counter.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v ; ; |
; ../../rtl/RTL_VB/tx_data_send.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v ; ; |
; ../../rtl/RTL_VB/rx_data_receive.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v ; ; |
; ../../rtl/RTL_VB/rx_data_control_p.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v ; ; |
; ../../rtl/RTL_VB/rx_data_buffer_data_w.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v ; ; |
; ../../rtl/RTL_VB/rx_control_data_rdy.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v ; ; |
; ../../rtl/RTL_VB/rx_buffer_fsm.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v ; ; |
; ../../rtl/RTL_VB/mem_data.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v ; ; |
; ../../rtl/RTL_VB/counter_neg.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v ; ; |
; ../../rtl/RTL_VB/bitc_capture_control.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v ; ; |
; ../../rtl/RTL_VB/bit_capture_data.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v ; ; |
; ../../rtl/RTL_VB/tx_spw.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v ; ; |
; ../../rtl/RTL_VB/top_spw_ultra_light.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v ; ; |
; ../../rtl/RTL_VB/spw_ulight_con_top_x.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v ; ; |
; ../../rtl/RTL_VB/rx_spw.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v ; ; |
1033,7 → 1060,9
; ../../rtl/RTL_VB/fsm_spw.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v ; ; |
; ../../rtl/RTL_VB/fifo_tx.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v ; ; |
; ../../rtl/RTL_VB/fifo_rx.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v ; ; |
; ../../rtl/RTL_VB/tx_spw.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v ; ; |
; ../../rtl/DEBUG_VERILOG/debounce.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v ; ; |
; ../../rtl/DEBUG_VERILOG/detector_tokens.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v ; ; |
; ../../rtl/DEBUG_VERILOG/clock_reduce.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v ; ; |
; ulight_fifo/synthesis/ulight_fifo.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v ; ulight_fifo ; |
; ulight_fifo/synthesis/submodules/altera_reset_controller.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v ; ulight_fifo ; |
; ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_synchronizer.v ; ulight_fifo ; |
1087,16 → 1116,16
; ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_clock_sel.v ; ulight_fifo ; |
; ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v ; ulight_fifo ; |
; top_rtl/spw_fifo_ulight.v ; yes ; User Verilog HDL File ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v ; ; |
; altddio_out.tdf ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altddio_out.tdf ; ; |
; aglobal170.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/aglobal170.inc ; ; |
; stratix_ddio.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/stratix_ddio.inc ; ; |
; cyclone_ddio.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/cyclone_ddio.inc ; ; |
; lpm_mux.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/lpm_mux.inc ; ; |
; stratix_lcell.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/stratix_lcell.inc ; ; |
; altddio_out.tdf ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altddio_out.tdf ; ; |
; aglobal171.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/aglobal171.inc ; ; |
; stratix_ddio.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/stratix_ddio.inc ; ; |
; cyclone_ddio.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/cyclone_ddio.inc ; ; |
; lpm_mux.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/lpm_mux.inc ; ; |
; stratix_lcell.inc ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/stratix_lcell.inc ; ; |
; db/ddio_out_uqe.tdf ; yes ; Auto-Generated Megafunction ; /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf ; ; |
; altera_pll.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v ; ; |
; altera_pll_dps_lcell_comb.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v ; ; |
; altera_cyclonev_pll.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v ; ; |
; altera_pll.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v ; ; |
; altera_pll_dps_lcell_comb.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll_dps_lcell_comb.v ; ; |
; altera_cyclonev_pll.v ; yes ; Megafunction ; /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v ; ; |
+-----------------------------------------------------------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+ |
|
|
1105,16 → 1134,16
+---------------------------------------------+--------------------+ |
; Resource ; Usage ; |
+---------------------------------------------+--------------------+ |
; Estimate of Logic utilization (ALMs needed) ; 3411 ; |
; Estimate of Logic utilization (ALMs needed) ; 3510 ; |
; ; ; |
; Combinational ALUT usage for logic ; 5227 ; |
; -- 7 input functions ; 59 ; |
; -- 6 input functions ; 1198 ; |
; -- 5 input functions ; 825 ; |
; -- 4 input functions ; 1419 ; |
; -- <=3 input functions ; 1726 ; |
; Combinational ALUT usage for logic ; 5406 ; |
; -- 7 input functions ; 72 ; |
; -- 6 input functions ; 1282 ; |
; -- 5 input functions ; 907 ; |
; -- 4 input functions ; 1517 ; |
; -- <=3 input functions ; 1628 ; |
; ; ; |
; Dedicated logic registers ; 4692 ; |
; Dedicated logic registers ; 4628 ; |
; ; ; |
; I/O pins ; 15 ; |
; ; ; |
1124,9 → 1153,9
; -- Fractional PLLs ; 1 ; |
; ; ; |
; Maximum fan-out node ; FPGA_CLK1_50~input ; |
; Maximum fan-out ; 3125 ; |
; Total fan-out ; 38933 ; |
; Average fan-out ; 3.91 ; |
; Maximum fan-out ; 3069 ; |
; Total fan-out ; 39569 ; |
; Average fan-out ; 3.93 ; |
+---------------------------------------------+--------------------+ |
|
|
1135,18 → 1164,35
+-----------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+ |
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ; |
+-----------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+--------------+ |
; |SPW_ULIGHT_FIFO ; 5227 (0) ; 4692 (0) ; 0 ; 0 ; 15 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ; |
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 76 (76) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ; |
; |debounce_db:db_system_spwulight_b| ; 38 (38) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ; |
; |detector_tokens:m_x| ; 58 (58) ; 106 (106) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ; |
; |spw_ulight_con_top_x:A_SPW_TOP| ; 980 (1) ; 1439 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ; |
; |fifo_rx:rx_data| ; 317 (317) ; 615 (615) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ; |
; |fifo_tx:tx_data| ; 297 (297) ; 608 (608) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ; |
; |top_spw_ultra_light:SPW| ; 365 (0) ; 216 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ; |
; |FSM_SPW:FSM| ; 125 (125) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ; |
; |RX_SPW:RX| ; 66 (66) ; 109 (109) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ; |
; |TX_SPW:TX| ; 174 (174) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ; |
; |ulight_fifo:u0| ; 4075 (0) ; 3105 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ; |
; |SPW_ULIGHT_FIFO ; 5406 (0) ; 4628 (0) ; 0 ; 0 ; 15 ; 0 ; |SPW_ULIGHT_FIFO ; SPW_ULIGHT_FIFO ; work ; |
; |clock_reduce:R_400_to_2_5_10_100_200_300MHZ| ; 175 (175) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ ; clock_reduce ; work ; |
; |debounce_db:db_system_spwulight_b| ; 37 (37) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b ; debounce_db ; work ; |
; |detector_tokens:m_x| ; 27 (17) ; 38 (16) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x ; detector_tokens ; work ; |
; |bit_capture_control:capture_c| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_control:capture_c ; bit_capture_control ; work ; |
; |bit_capture_data:capture_d| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|bit_capture_data:capture_d ; bit_capture_data ; work ; |
; |counter_neg:cnt_neg| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg ; counter_neg ; work ; |
; |spw_ulight_con_top_x:A_SPW_TOP| ; 1025 (1) ; 1499 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP ; spw_ulight_con_top_x ; work ; |
; |fifo_rx:rx_data| ; 340 (87) ; 633 (48) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data ; fifo_rx ; work ; |
; |mem_data:mem_dta_fifo_tx| ; 253 (253) ; 585 (585) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ; |
; |fifo_tx:tx_data| ; 299 (46) ; 627 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; fifo_tx ; work ; |
; |mem_data:mem_dta_fifo_tx| ; 253 (253) ; 585 (585) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ; mem_data ; work ; |
; |top_spw_ultra_light:SPW| ; 385 (0) ; 239 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW ; top_spw_ultra_light ; work ; |
; |FSM_SPW:FSM| ; 118 (118) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM ; FSM_SPW ; work ; |
; |RX_SPW:RX| ; 60 (2) ; 75 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX ; RX_SPW ; work ; |
; |bit_capture_control:capture_c| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c ; bit_capture_control ; work ; |
; |bit_capture_data:capture_d| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d ; bit_capture_data ; work ; |
; |counter_neg:cnt_neg| ; 12 (12) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg ; counter_neg ; work ; |
; |rx_buffer_fsm:buffer_fsm| ; 2 (2) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm ; rx_buffer_fsm ; work ; |
; |rx_control_data_rdy:control_data_rdy| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy ; rx_control_data_rdy ; work ; |
; |rx_data_buffer_data_w:buffer_data_flag| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag ; rx_data_buffer_data_w ; work ; |
; |rx_data_control_p:data_control| ; 9 (9) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control ; rx_data_control_p ; work ; |
; |rx_data_receive:rx_dtarcv| ; 28 (28) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ; rx_data_receive ; work ; |
; |TX_SPW:TX| ; 207 (0) ; 105 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX ; TX_SPW ; work ; |
; |tx_data_send:tx_data_snd| ; 30 (30) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd ; tx_data_send ; work ; |
; |tx_fsm_m:tx_fsm| ; 177 (125) ; 76 (43) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm ; tx_fsm_m ; work ; |
; |tx_fct_counter:tx_fct_cnt| ; 33 (33) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ; tx_fct_counter ; work ; |
; |tx_fct_send:tx_fct_snd| ; 19 (19) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ; tx_fct_send ; work ; |
; |ulight_fifo:u0| ; 4142 (0) ; 3049 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo ; ulight_fifo ; |
; |altera_reset_controller:rst_controller_001| ; 0 (0) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; altera_reset_controller ; ulight_fifo ; |
; |altera_reset_synchronizer:alt_rst_sync_uq1| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1 ; altera_reset_synchronizer ; ulight_fifo ; |
; |altera_reset_controller:rst_controller| ; 0 (0) ; 3 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; altera_reset_controller ; ulight_fifo ; |
1162,7 → 1208,7
; |ulight_fifo_counter_rx_fifo:counter_tx_fifo| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_counter_rx_fifo:fsm_info| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo_counter_rx_fifo ; ulight_fifo ; |
; |ulight_fifo_data_flag_rx:data_flag_rx| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo_data_flag_rx ; ulight_fifo ; |
; |ulight_fifo_data_info:data_info| ; 14 (14) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ; |
; |ulight_fifo_data_info:data_info| ; 3 (3) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo_data_info ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
; |ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo_fifo_empty_rx_status ; ulight_fifo ; |
1172,7 → 1218,7
; |ulight_fifo_hps_0:hps_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo_hps_0 ; ulight_fifo ; |
; |ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces ; ulight_fifo_hps_0_fpga_interfaces ; ulight_fifo ; |
; |ulight_fifo_led_pio_test:led_pio_test| ; 6 (6) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo_led_pio_test ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 3980 (0) ; 3014 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0:mm_interconnect_0| ; 4058 (0) ; 2969 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo_mm_interconnect_0 ; ulight_fifo ; |
; |altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo| ; 7 (7) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
1183,7 → 1229,7
; |altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo| ; 14 (14) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 19 (19) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo| ; 7 (7) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
1199,7 → 1245,7
; |altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo| ; 10 (10) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
1207,188 → 1253,188
; |altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo| ; 12 (12) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 12 (12) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo| ; 13 (13) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo| ; 25 (25) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 13 (13) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo| ; 14 (14) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 5 (5) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo| ; 6 (6) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo| ; 26 (26) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; altera_avalon_sc_fifo ; ulight_fifo ; |
; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 114 (55) ; 26 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ; |
; |altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent| ; 116 (57) ; 26 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; altera_merlin_axi_master_ni ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 59 (59) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 63 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 63 (62) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:auto_start_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 63 (0) ; 64 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 63 (62) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:clock_sel_s1_burst_adapter| ; 65 (0) ; 64 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 65 (64) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 55 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 55 (53) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 55 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 55 (53) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (48) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (48) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 62 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 62 (61) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_info_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (48) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (49) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (49) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 55 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 55 (53) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 53 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 53 (52) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:fsm_info_s1_burst_adapter| ; 59 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 59 (58) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 65 (0) ; 66 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 65 (64) ; 66 (66) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter| ; 67 (0) ; 66 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 66 (66) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 63 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 63 (62) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_disable_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 62 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 62 (61) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:link_start_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (48) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (49) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 63 (0) ; 69 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 63 (62) ; 69 (69) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter| ; 67 (0) ; 69 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 69 (69) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 63 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 63 (62) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter| ; 68 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 68 (67) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 50 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 50 (48) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 63 (0) ; 70 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 63 (62) ; 70 (70) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter| ; 58 (0) ; 60 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 58 (57) ; 60 (60) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter| ; 67 (0) ; 70 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 70 (70) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 62 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 62 (61) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter| ; 67 (0) ; 62 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; altera_merlin_burst_adapter ; ulight_fifo ; |
; |altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter| ; 67 (66) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter ; altera_merlin_burst_adapter_13_1 ; ulight_fifo ; |
; |altera_merlin_address_alignment:align_address_to_size| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|altera_merlin_address_alignment:align_address_to_size ; altera_merlin_address_alignment ; ulight_fifo ; |
; |altera_merlin_slave_agent:auto_start_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:auto_start_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:clock_sel_s1_agent| ; 27 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 16 (16) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_rx_fifo_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:counter_tx_fifo_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_flag_rx_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_info_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:data_read_en_rx_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_full_rx_status_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fifo_full_tx_status_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:fsm_info_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:led_pio_test_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_disable_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_disable_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_start_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:link_start_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_ready_rx_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_rx_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_data_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_enable_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 23 (6) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:timecode_tx_ready_s1_agent| ; 24 (7) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_data_fifo_tx_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 29 (12) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_slave_agent:write_en_tx_s1_agent| ; 28 (11) ; 7 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; altera_merlin_slave_agent ; ulight_fifo ; |
; |altera_merlin_burst_uncompressor:uncompressor| ; 17 (17) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor ; altera_merlin_burst_uncompressor ; ulight_fifo ; |
; |altera_merlin_slave_translator:auto_start_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:clock_sel_s1_translator| ; 5 (5) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 4 (4) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 4 (4) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 4 (4) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_info_s1_translator| ; 4 (4) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_rx_fifo_s1_translator| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:counter_tx_fifo_s1_translator| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_flag_rx_s1_translator| ; 2 (2) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_info_s1_translator| ; 2 (2) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:data_read_en_rx_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 4 (4) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 4 (4) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 4 (4) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 4 (4) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 4 (4) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_rx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fifo_full_tx_status_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:fsm_info_s1_translator| ; 2 (2) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:led_pio_test_s1_translator| ; 5 (5) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:link_disable_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:link_start_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 4 (4) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 4 (4) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_ready_rx_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_rx_s1_translator| ; 2 (2) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_data_s1_translator| ; 5 (5) ; 12 (12) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_enable_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 4 (4) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:timecode_tx_ready_s1_translator| ; 2 (2) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:write_data_fifo_tx_s1_translator| ; 5 (5) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_slave_translator:write_en_tx_s1_translator| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; altera_merlin_slave_translator ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 11 (11) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 12 (12) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 40 (40) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter| ; 12 (12) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter| ; 14 (14) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; altera_merlin_traffic_limiter ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001| ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux| ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo_mm_interconnect_0_cmd_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004| ; 33 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 33 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008| ; 33 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010| ; 42 (37) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 33 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011| ; 34 (29) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 41 (36) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014| ; 40 (35) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 32 (28) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 23 (23) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015| ; 33 (28) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 36 (31) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018| ; 35 (31) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021| ; 22 (22) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 37 (33) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 44 (44) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux| ; 37 (32) ; 5 (3) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo_mm_interconnect_0_cmd_mux ; ulight_fifo ; |
; |altera_merlin_arbitrator:arb| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb ; altera_merlin_arbitrator ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router_001| ; 40 (40) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_router:router| ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo_mm_interconnect_0_router ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
1399,7 → 1445,7
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo_mm_interconnect_0_rsp_demux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 300 (300) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001| ; 294 (294) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ; |
; |ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux| ; 88 (88) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo_mm_interconnect_0_rsp_mux ; ulight_fifo ; |
; |ulight_fifo_pll_0:pll_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo_pll_0 ; ulight_fifo ; |
; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i ; altera_pll ; work ; |
1417,268 → 1463,268
+--------+--------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+ |
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; |
+--------+--------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+ |
; N/A ; Qsys ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo.qsys ; |
; Altera ; altera_hps ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo.qsys ; |
; Altera ; altera_hps_io ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo.qsys ; |
; Altera ; altera_mm_interconnect ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_axi_master_ni ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_traffic_limiter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_traffic_limiter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_003 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_004 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_005 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_006 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_007 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_008 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_009 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_010 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_011 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_012 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_013 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_014 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_015 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_016 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_017 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_018 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_019 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_020 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_021 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_022 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_023 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_002 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_003 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_005 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_006 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_012 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_013 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_016 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_017 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_019 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_020 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_021 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_pll ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo.qsys ; |
; Altera ; altera_reset_controller ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; ulight_fifo.qsys ; |
; Altera ; altera_reset_controller ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.0 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo.qsys ; |
; N/A ; Qsys ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:auto_start ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_data_info:data_info ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:data_read_en_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info ; ulight_fifo.qsys ; |
; Altera ; altera_hps ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; ulight_fifo.qsys ; |
; Altera ; altera_hps_io ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_disable ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:link_start ; ulight_fifo.qsys ; |
; Altera ; altera_mm_interconnect ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_001|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_002|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_003|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_004|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_005|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_006|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_007|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_008|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_009|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_010|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_011|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_012|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_013|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_014|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_015|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_016|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_017|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_018|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_019|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_020|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_st_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021 ; ulight_fifo.qsys ; |
; Altera ; error_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter_021|ulight_fifo_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_demux:cmd_demux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_016 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_017 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_axi_master_ni ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_traffic_limiter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_rd_limiter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_traffic_limiter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_002 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_003 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_004 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_005 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_006 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_007 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_008 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_009 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_010 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_011 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_012 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_013 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_014 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_015 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_016 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_017 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_018 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_019 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_020 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_021 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_022 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_router ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router_002:router_023 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_002 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_003 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_004 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_005 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_006 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_007 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_008 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_009 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_010 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_011 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_012 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_013 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_014 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_015 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_016 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_017 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_018 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_019 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_020 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_demultiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_demux:rsp_demux_021 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_multiplexer ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_rsp_mux:rsp_mux_001 ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_agent ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_sc_fifo ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_burst_adapter ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter ; ulight_fifo.qsys ; |
; Altera ; altera_merlin_slave_translator ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator ; ulight_fifo.qsys ; |
; Altera ; altera_pll ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0 ; ulight_fifo.qsys ; |
; Altera ; altera_reset_controller ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller ; ulight_fifo.qsys ; |
; Altera ; altera_reset_controller ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|altera_reset_controller:rst_controller_001 ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:timecode_tx_enable ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx ; ulight_fifo.qsys ; |
; Altera ; altera_avalon_pio ; 17.1 ; N/A ; N/A ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_auto_start:write_en_tx ; ulight_fifo.qsys ; |
+--------+--------------------------------+---------+--------------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ |
1691,7 → 1737,7
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ |
1704,7 → 1750,7
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ |
1717,7 → 1763,7
+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+ |
1730,7 → 1776,7
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+ |
1743,7 → 1789,7
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+ |
1756,7 → 1802,7
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
1769,7 → 1815,7
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+ |
1782,7 → 1828,7
+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ |
1795,7 → 1841,7
+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+ |
1808,7 → 1854,7
+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+ |
1821,7 → 1867,7
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
1834,7 → 1880,7
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+ |
1847,7 → 1893,7
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+ |
1860,7 → 1906,7
+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+ |
1873,7 → 1919,7
+-----------------------------+---------------+-----------------------------+-----------------------+-------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ |
1886,7 → 1932,7
+-----------------------------+---------------+-----------------------------+-----------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+ |
1899,7 → 1945,7
+-----------------------------+---------------+-----------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ |
1912,7 → 1958,7
+-----------------------------+---------------+-----------------------------+-----------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+ |
1925,7 → 1971,7
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+ |
1938,7 → 1984,7
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+ |
1951,7 → 1997,7
+-----------------------------+---------------+-----------------------------+-----------------------+--------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state ; |
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+ |
1964,7 → 2010,54
+-----------------------------+---------------+-----------------------------+-----------------------+---------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process ; |
+-----------------------+-------------------------------------------------+ |
; Name ; state_data_process.01 ; |
+-----------------------+-------------------------------------------------+ |
; state_data_process.00 ; 0 ; |
; state_data_process.01 ; 1 ; |
+-----------------------+-------------------------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot ; |
+--------------------+--------------------+--------------------+----------------------------------+ |
; Name ; state_open_slot.00 ; state_open_slot.10 ; state_open_slot.01 ; |
+--------------------+--------------------+--------------------+----------------------------------+ |
; state_open_slot.00 ; 0 ; 0 ; 0 ; |
; state_open_slot.01 ; 1 ; 0 ; 1 ; |
; state_open_slot.10 ; 1 ; 1 ; 0 ; |
+--------------------+--------------------+--------------------+----------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+--------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write ; |
+---------------------+---------------------+---------------------+--------------------------------+ |
; Name ; state_data_write.00 ; state_data_write.10 ; state_data_write.01 ; |
+---------------------+---------------------+---------------------+--------------------------------+ |
; state_data_write.00 ; 0 ; 0 ; 0 ; |
; state_data_write.01 ; 1 ; 0 ; 1 ; |
; state_data_write.10 ; 1 ; 1 ; 0 ; |
+---------------------+---------------------+---------------------+--------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read ; |
+--------------------+--------------------+--------------------+----------------------------------+ |
; Name ; state_data_read.00 ; state_data_read.10 ; state_data_read.01 ; |
+--------------------+--------------------+--------------------+----------------------------------+ |
; state_data_read.00 ; 0 ; 0 ; 0 ; |
; state_data_read.01 ; 1 ; 0 ; 1 ; |
; state_data_read.10 ; 1 ; 1 ; 0 ; |
+--------------------+--------------------+--------------------+----------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state ; |
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+ |
1979,35 → 2072,100
+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+------------------------------------+-----------------------------------+ |
|
|
Encoding Type: One-Hot |
+---------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|state_tx ; |
+--------------------------+-----------------------+----------------------+--------------------------+----------------------+ |
; Name ; state_tx.tx_spw_start ; state_tx.tx_spw_full ; state_tx.tx_spw_null_fct ; state_tx.tx_spw_null ; |
+--------------------------+-----------------------+----------------------+--------------------------+----------------------+ |
; state_tx.tx_spw_start ; 0 ; 0 ; 0 ; 0 ; |
; state_tx.tx_spw_null ; 1 ; 0 ; 0 ; 1 ; |
; state_tx.tx_spw_null_fct ; 1 ; 0 ; 1 ; 0 ; |
; state_tx.tx_spw_full ; 1 ; 1 ; 0 ; 0 ; |
+--------------------------+-----------------------+----------------------+--------------------------+----------------------+ |
Encoding Type: Safe One-Hot |
+--------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read ; |
+--------------------+--------------------+--------------------+--------------------+--------------------+ |
; Name ; state_data_read.11 ; state_data_read.10 ; state_data_read.01 ; state_data_read.00 ; |
+--------------------+--------------------+--------------------+--------------------+--------------------+ |
; state_data_read.00 ; 0 ; 0 ; 0 ; 0 ; |
; state_data_read.01 ; 0 ; 0 ; 1 ; 1 ; |
; state_data_read.10 ; 0 ; 1 ; 0 ; 1 ; |
; state_data_read.11 ; 1 ; 0 ; 0 ; 1 ; |
+--------------------+--------------------+--------------------+--------------------+--------------------+ |
|
|
Encoding Type: One-Hot |
+---------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_type ; |
+-----------------+-----------------+----------------+---------------+---------------+---------------+----------------+ |
; Name ; last_type.TIMEC ; last_type.DATA ; last_type.EEP ; last_type.EOP ; last_type.FCT ; last_type.NULL ; |
+-----------------+-----------------+----------------+---------------+---------------+---------------+----------------+ |
; last_type.NULL ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; last_type.FCT ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; |
; last_type.EOP ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; |
; last_type.EEP ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; |
; last_type.DATA ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; |
; last_type.TIMEC ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; |
+-----------------+-----------------+----------------+---------------+---------------+---------------+----------------+ |
Encoding Type: Safe One-Hot |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx ; |
+-----------------------------+-----------------------------+--------------------------+------------------------+-----------------------+------------------------+---------------------+----------------------+-----------------------+ |
; Name ; state_tx.tx_spw_time_code_c ; state_tx.tx_spw_data_c_0 ; state_tx.tx_spw_data_c ; state_tx.tx_spw_fct_c ; state_tx.tx_spw_null_c ; state_tx.tx_spw_fct ; state_tx.tx_spw_null ; state_tx.tx_spw_start ; |
+-----------------------------+-----------------------------+--------------------------+------------------------+-----------------------+------------------------+---------------------+----------------------+-----------------------+ |
; state_tx.tx_spw_start ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; state_tx.tx_spw_null ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; |
; state_tx.tx_spw_fct ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; |
; state_tx.tx_spw_null_c ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; |
; state_tx.tx_spw_fct_c ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; |
; state_tx.tx_spw_data_c ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; |
; state_tx.tx_spw_data_c_0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; |
; state_tx.tx_spw_time_code_c ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; |
+-----------------------------+-----------------------------+--------------------------+------------------------+-----------------------+------------------------+---------------------+----------------------+-----------------------+ |
|
|
Encoding Type: One-Hot |
Encoding Type: Safe One-Hot |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send ; |
+--------------------+------------------------------------------------------------------------------------------------------------------------------------+ |
; Name ; state_fct_send.001 ; |
+--------------------+------------------------------------------------------------------------------------------------------------------------------------+ |
; state_fct_send.000 ; 0 ; |
; state_fct_send.001 ; 1 ; |
+--------------------+------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p ; |
+----------------------+----------------------+----------------------+--------------------------------------------------------------------------------------+ |
; Name ; state_fct_send_p.000 ; state_fct_send_p.010 ; state_fct_send_p.001 ; |
+----------------------+----------------------+----------------------+--------------------------------------------------------------------------------------+ |
; state_fct_send_p.001 ; 0 ; 0 ; 0 ; |
; state_fct_send_p.000 ; 1 ; 0 ; 1 ; |
; state_fct_send_p.010 ; 0 ; 1 ; 1 ; |
+----------------------+----------------------+----------------------+--------------------------------------------------------------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p ; |
+-----------------+-----------------+-----------------+-----------------+-----------------+---------------------------------------------------------------+ |
; Name ; state_fct_p.011 ; state_fct_p.010 ; state_fct_p.001 ; state_fct_p.000 ; state_fct_p.100 ; |
+-----------------+-----------------+-----------------+-----------------+-----------------+---------------------------------------------------------------+ |
; state_fct_p.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; state_fct_p.001 ; 0 ; 0 ; 1 ; 1 ; 0 ; |
; state_fct_p.010 ; 0 ; 1 ; 0 ; 1 ; 0 ; |
; state_fct_p.011 ; 1 ; 0 ; 0 ; 1 ; 0 ; |
; state_fct_p.100 ; 0 ; 0 ; 0 ; 1 ; 1 ; |
+-----------------+-----------------+-----------------+-----------------+-----------------+---------------------------------------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+--------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write ; |
+---------------------+---------------------+---------------------+--------------------------------+ |
; Name ; state_data_write.00 ; state_data_write.10 ; state_data_write.01 ; |
+---------------------+---------------------+---------------------+--------------------------------+ |
; state_data_write.00 ; 0 ; 0 ; 0 ; |
; state_data_write.01 ; 1 ; 0 ; 1 ; |
; state_data_write.10 ; 1 ; 1 ; 0 ; |
+---------------------+---------------------+---------------------+--------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive ; |
+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+---------------------------------------+ |
; Name ; state_fct_receive.011 ; state_fct_receive.010 ; state_fct_receive.001 ; state_fct_receive.000 ; state_fct_receive.100 ; |
+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+---------------------------------------+ |
; state_fct_receive.000 ; 0 ; 0 ; 0 ; 0 ; 0 ; |
; state_fct_receive.001 ; 0 ; 0 ; 1 ; 1 ; 0 ; |
; state_fct_receive.010 ; 0 ; 1 ; 0 ; 1 ; 0 ; |
; state_fct_receive.011 ; 1 ; 0 ; 0 ; 1 ; 0 ; |
; state_fct_receive.100 ; 0 ; 0 ; 0 ; 1 ; 1 ; |
+-----------------------+-----------------------+-----------------------+-----------------------+-----------------------+---------------------------------------+ |
|
|
Encoding Type: Safe One-Hot |
+---------------------------------------------------------------------------------------------------------------------------------------------------+ |
; State Machine - |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm ; |
+-----------------------+-----------------------+---------------+----------------------+-------------------+-----------------+----------------------+ |
2022,17 → 2180,198
+-----------------------+-----------------------+---------------+----------------------+-------------------+-----------------+----------------------+ |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Registers Protected by Synthesis ; |
+---------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ |
; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; |
+---------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; |
; Total number of protected registers is 4 ; ; ; |
+---------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Registers Protected by Synthesis ; |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ |
; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[5] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[4] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[3] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[2] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[1] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|rd_ptr[0] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[5] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[4] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[3] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[2] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[1] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|wr_ptr[0] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[5] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[4] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[3] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[2] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[1] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_writer[0] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[5] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[4] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[3] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[2] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[1] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|counter_reader[0] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.00 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.01 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.10 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read.11 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.01 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.10 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write.00 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.run ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c_0 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_null_c ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_fct_c ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_data_c ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_time_code_c ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx.tx_spw_start ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.connecting ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_wait ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.ready ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.started ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm.error_reset ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_COMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_TRANS ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_UNCOMP_WR_SUBBURST ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.011 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.001 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.010 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.000 ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state.ST_IDLE ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.010 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.100 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p.000 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p.001 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send.001 ; no ; yes ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_data ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_timec ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.001 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.100 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot.00 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot.01 ; no ; yes ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[0] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[1] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[2] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[3] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[4] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[5] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[6] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|timecode[7] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_error_c ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_error_d ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_control ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[0] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.000 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.010 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive.011 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read.00 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot.10 ; no ; yes ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; yes ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write.10 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read.01 ; no ; yes ; |
; detector_tokens:m_x|state_data_process.01 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read.10 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write.01 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write.00 ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[0] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[1] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[2] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[3] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[4] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[5] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[6] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[7] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[8] ; no ; yes ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_got_fct ; no ; yes ; |
; Total number of protected registers is 185 ; ; ; |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
2040,6 → 2379,7
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ |
; Register name ; Reason for Removal ; |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|state_data_process[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|locked[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|locked[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|locked[0,1] ; Stuck at GND due to stuck port data_in ; |
2609,6 → 2949,18
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|wait_latency_counter[1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count_zero_flag ; Stuck at VCC due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|top_priority_reg[0] ; Stuck at VCC due to stuck port data_in ; |
2655,67 → 3007,9
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|share_count[0] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|share_count[0] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count[0] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|control[0..3] ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|data[0..7] ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|info[6..9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
2745,67 → 3039,7
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[6..9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
2835,91 → 3069,16
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|timecode_s[10..12] ; Stuck at VCC due to stuck port data_in ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|timecode_s[8] ; Stuck at GND due to stuck port data_in ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|hold_time_code ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[6..9] ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|rx_got_null ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|rx_got_time_code ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|rx_got_fct ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|control_l_r[0..3] ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|info[0,1,3,10..13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[1,3,10..13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[1,3,10..13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[0] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[0] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
2978,204 → 3137,6
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
3234,138 → 3195,6
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
3394,6 → 3223,224
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
3425,6 → 3472,26
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
3550,34 → 3617,63
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
3609,6 → 3705,26
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
3734,52 → 3850,55
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; detector_tokens:m_x|data[9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
3806,52 → 3925,39
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
3878,76 → 3984,10
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
3960,24 → 4000,126
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
3990,12 → 4132,142
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
4008,18 → 4280,142
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
4032,6 → 4428,91
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_receive[0..2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4..6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
4038,163 → 4519,34
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][33] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][32] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][31] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][30] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][29] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][28] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][27] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][26] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][25] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][24] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][23] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][22] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][21] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][20] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][19] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][18] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][17] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][16] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][15] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][14] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][5] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][4] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][2] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; Lost fanout ; |
; detector_tokens:m_x|state_data_process~5 ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~2 ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~3 ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~4 ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state~5 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~2 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~3 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx~4 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send~3 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send~4 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p~6 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~2 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p~3 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~2 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive~3 ; Lost fanout ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm~9 ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_HIGH ; Stuck at GND due to stuck port clock ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_1 ; Stuck at GND due to stuck port clock ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_0 ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_2 ; Stuck at GND due to stuck port clock ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_3 ; Stuck at GND due to stuck port clock ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_4 ; Stuck at GND due to stuck port clock ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_0 ; Stuck at GND due to stuck port clock ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ; |
4205,8 → 4557,7
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
4219,8 → 4570,7
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[20..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
4227,8 → 4577,54
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; Total Number of Removed Registers = 4556 ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[20..29] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0,1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][0] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][0] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][1] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][3] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][6] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][7] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][8] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][9] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][10] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][11] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][12] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][13] ; Stuck at GND due to stuck port data_in ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_addr_masked[0,1] ; Lost fanout ; |
; Total Number of Removed Registers = 4651 ; ; |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------+ |
|
|
4237,63 → 4633,6
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Register name ; Reason for Removal ; Registers Removed due to This Register ; |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
4408,6 → 4747,177
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
4465,6 → 4975,63
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
4522,6 → 5089,63
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
4579,234 → 5203,168
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
4861,6 → 5419,222
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
4915,60 → 5689,6
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
5023,222 → 5743,6
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
5293,114 → 5797,6
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_byte_cnt_narrow_reg[4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[14], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[29] ; Lost Fanouts ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_nxt_addr_reg_dly[26], ; |
5462,6 → 5858,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4], ; |
5475,6 → 5872,21
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[20] ; |
; detector_tokens:m_x|control[2] ; Stuck at GND ; detector_tokens:m_x|info[8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[8], ; |
; ; ; detector_tokens:m_x|rx_got_null, detector_tokens:m_x|rx_got_time_code, ; |
; ; ; detector_tokens:m_x|rx_got_fct, detector_tokens:m_x|control_l_r[2], ; |
; ; ; detector_tokens:m_x|info[12], detector_tokens:m_x|info[3], ; |
; ; ; detector_tokens:m_x|info[1], detector_tokens:m_x|info[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[3], ; |
; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[3], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|saved_grant[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ; |
5482,19 → 5894,10
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|saved_grant[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|saved_grant[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ; |
5502,6 → 5905,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
5512,6 → 5916,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
5522,6 → 5927,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
5532,6 → 5938,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
5542,9 → 5949,21
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|saved_grant[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|locked[0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_traffic_limiter:hps_0_h2f_axi_master_wr_limiter|last_channel[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|saved_grant[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[68], ; |
5552,6 → 5971,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
5562,6 → 5982,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
5572,6 → 5993,7
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
5582,70 → 6004,93
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][68], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|wait_latency_counter[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_burstwrap_reg[4] ; |
; detector_tokens:m_x|control[0] ; Stuck at GND ; detector_tokens:m_x|info[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[6], ; |
; ; ; detector_tokens:m_x|control_l_r[0], detector_tokens:m_x|info[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[10] ; |
; detector_tokens:m_x|control[3] ; Stuck at GND ; detector_tokens:m_x|info[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[9], ; |
; ; ; detector_tokens:m_x|control_l_r[3], detector_tokens:m_x|info[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[13] ; |
; detector_tokens:m_x|control[1] ; Stuck at GND ; detector_tokens:m_x|info[7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[7], ; |
; ; ; detector_tokens:m_x|control_l_r[1], detector_tokens:m_x|info[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[11] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][69] ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|burst_bytecount[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][73], ; |
5654,30 → 6099,42
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][73], ; |
5686,22 → 6143,18
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][73], ; |
5710,32 → 6163,13
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][99], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[0][69], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][69] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_uncompressed_read_reg ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][73], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][72], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][73], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][72] ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_1 ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_0, ; |
; ; due to stuck port clock ; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_2, ; |
; ; ; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_3, ; |
; ; ; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_4 ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][2], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][30] ; |
5742,12 → 6176,15
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][27] ; |
5754,9 → 6191,6
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][26] ; |
5763,45 → 6197,60
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][15] ; |
5811,12 → 6260,6
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][12] ; |
5823,12 → 6266,6
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][10] ; |
5841,15 → 6278,12
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][23] ; |
5883,12 → 6317,12
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][12], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][10] ; |
5913,18 → 6347,18
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][3], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][2], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][17] ; |
5958,12 → 6392,12
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_tx_status|readdata[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|av_readdata_pre[4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][4], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][4] ; |
5994,12 → 6428,12
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_full_rx_status|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|av_readdata_pre[25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][8] ; |
6027,12 → 6461,12
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][28] ; |
6060,15 → 6494,18
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][29] ; |
6078,9 → 6515,6
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][26], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][25] ; |
6093,12 → 6527,12
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][19] ; |
6126,12 → 6560,12
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_tx_ready|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|av_readdata_pre[10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][19] ; |
6159,12 → 6593,12
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][11], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][8] ; |
6192,12 → 6626,12
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][17] ; |
6225,12 → 6659,12
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|av_readdata_pre[8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:fsm_info|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][30] ; |
6258,6 → 6692,9
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][22], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:timecode_ready_rx|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_tx_fifo|readdata[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|av_readdata_pre[13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][13], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][13] ; |
6400,8 → 6837,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1] ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ; |
6412,8 → 6849,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1] ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ; |
6433,8 → 6870,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1] ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ; |
6442,8 → 6879,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1] ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_byte_cnt_reg[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|int_bytes_remaining_reg[0], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|out_uncomp_byte_cnt_reg[0] ; |
6489,9 → 6926,9
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|av_readdata_pre[15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][15] ; |
6525,9 → 6962,6
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][7] ; |
6546,6 → 6980,9
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][2], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][1], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][31] ; |
6555,9 → 6992,9
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][8], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][27] ; |
6588,12 → 7025,9
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][31], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][29] ; |
6621,12 → 7055,12
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][21], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][19], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][20], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][18], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][18] ; |
6654,6 → 7088,9
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][10], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][9], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][16] ; |
6687,9 → 7124,9
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][15] ; |
6717,15 → 7154,15
; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][25], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][17], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_data_flag_rx:data_flag_rx|readdata[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|av_readdata_pre[24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][24], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][16], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][15], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][15] ; |
6753,6 → 7190,9
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][7], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_tx_status|readdata[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|av_readdata_pre[30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][30], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][5], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][5] ; |
6777,46 → 7217,11
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][29], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][27], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_fifo_empty_rx_status:fifo_empty_rx_status|readdata[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|av_readdata_pre[6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][6], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_data_info:data_info|readdata[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|av_readdata_pre[28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][28], ; |
; ; ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][7], ; |
6831,8 → 7236,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][28], ; |
6841,8 → 7246,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][23], ; |
6855,14 → 7260,18
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][31], ; |
6879,14 → 7288,14
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][19], ; |
6901,20 → 7310,16
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][18], ; |
6925,8 → 7330,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][12], ; |
6937,8 → 7342,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][30], ; |
6949,18 → 7354,20
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][11], ; |
6973,8 → 7380,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][99] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][4], ; |
6983,8 → 7390,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][30], ; |
6995,10 → 7402,20
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rsp_fifo|mem[1][99], ; |
7019,12 → 7436,12
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rsp_fifo|mem[1][95], ; |
7043,6 → 7460,10
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rsp_fifo|mem[1][98], ; |
7067,8 → 7488,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][99] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[0][99] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rsp_fifo|mem[1][98], ; |
7089,14 → 7510,10
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][96], ; |
7113,14 → 7530,14
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rsp_fifo|mem[1][97], ; |
7137,12 → 7554,14
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][99] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][99] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][99] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rsp_fifo|mem[1][97], ; |
7161,12 → 7580,12
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[99] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][99], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][99] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rsp_fifo|mem[1][95], ; |
7183,32 → 7602,18
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[98] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][98], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][98] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[97] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][97], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][97] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[96] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][96], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][96] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|in_data_reg[95] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[1][95], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rsp_fifo|mem[0][95] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][12], ; |
7229,34 → 7634,38
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][4], ; |
7273,36 → 7682,32
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][27], ; |
7309,48 → 7714,50
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][19], ; |
7371,22 → 7778,32
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][26], ; |
7395,10 → 7812,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][20], ; |
7411,8 → 7826,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][13], ; |
7419,46 → 7834,48
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][6], ; |
7465,24 → 7882,24
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][1], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[2] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][2], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][2] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][1], ; |
7489,10 → 7906,8
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][1] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][28], ; |
7509,34 → 7924,40
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][20], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][20] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[19] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][19], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][19] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[18] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][18], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][18] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[17] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][17], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][17] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[16] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][16], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][16] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[15] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][15], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][15] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[14] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][14], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][14] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][13], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[24] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][24], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][24] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[25] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][25], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][25] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[26] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][26], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][26] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[27] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][27], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][27] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[28] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][28], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][28] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[29] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][29], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][29] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[30] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][30], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][30] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[31] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][31], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][31] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][11], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][11] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[23] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][23], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][23] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[22] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][22], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][22] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[21] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][21], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][21] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[20] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][20], ; |
7557,47 → 7978,65
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][13] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][12], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][12] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][3], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][3] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[4] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][4], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][4] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][10], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][10] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][9], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][9] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][8], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][8] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[5] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][5], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][5] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][6], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][6] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|av_readdata_pre[7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][7], ; |
; ; due to stuck port data_in ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][7] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][12] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][12] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][13] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][13] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_ready_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][1] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][0] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_HIGH ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state.PHASE_DONE_LOW_0 ; |
; ; due to stuck port clock ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
7607,11 → 8046,11
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_013|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_flag_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_012|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_006|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_005|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][3] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][3] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
7619,14 → 8058,28
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][6] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][6] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][7] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][7] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][8] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][8] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][9] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][9] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][10] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][10] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][11] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][11] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_002|share_count[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_003|share_count[0] ; |
7645,9 → 8098,9
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_019|share_count[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_020|share_count[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_001|share_count[0] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|share_count[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|share_count[0] ; |
; ; due to stuck port data_in ; ; |
7669,30 → 8122,40
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|share_count_zero_flag ; Stuck at VCC ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|share_count[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|locked[1] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_021|altera_merlin_arbitrator:arb|top_priority_reg[0] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_rx_status_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_data_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_start_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_enable_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:auto_start_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:timecode_tx_ready_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_info_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:data_read_en_rx_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:clock_sel_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fsm_info_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_tx_status_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_en_tx_s1_agent_rdata_fifo|mem[0][33] ; |
7701,18 → 8164,16
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_full_tx_status_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:led_pio_test_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_tx_fifo_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:fifo_empty_rx_status_s1_agent_rdata_fifo|mem[0][33] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:link_disable_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][32] ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[1][32] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:write_data_fifo_tx_s1_agent_rdata_fifo|mem[0][32] ; |
; ; due to stuck port data_in ; ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[1][33] ; Stuck at GND ; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:counter_rx_fifo_s1_agent_rdata_fifo|mem[0][33] ; |
; ; due to stuck port data_in ; ; |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
7721,12 → 8182,12
+----------------------------------------------+-------+ |
; Statistic ; Value ; |
+----------------------------------------------+-------+ |
; Total registers ; 4692 ; |
; Total registers ; 4628 ; |
; Number of registers using Synchronous Clear ; 0 ; |
; Number of registers using Synchronous Load ; 0 ; |
; Number of registers using Asynchronous Clear ; 4613 ; |
; Number of registers using Asynchronous Clear ; 4451 ; |
; Number of registers using Asynchronous Load ; 0 ; |
; Number of registers using Clock Enable ; 3488 ; |
; Number of registers using Clock Enable ; 3301 ; |
; Number of registers using Preset ; 0 ; |
+----------------------------------------------+-------+ |
|
7736,71 → 8197,66
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ |
; Inverted Register ; Fan out ; |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|waitrequest_reset_override ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|sop_enable ; 63 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[2] ; 7 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[1] ; 8 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[0] ; 10 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|first_time ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_tx_status_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_read_en_rx_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_ready_rx_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_empty_rx_status_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_tx_status_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fsm_info_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:led_pio_test_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_rx_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_flag_rx_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:fifo_full_rx_status_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_ready_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_tx_fifo_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:data_info_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_start_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:counter_rx_fifo_s1_translator|waitrequest_reset_override ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|waitrequest_reset_override ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|sop_enable ; 61 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 2969 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 74 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out ; 3025 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 2 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_004|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_014|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_015|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_011|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_018|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 4 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_010|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_009|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_007|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 3 ; |
; ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_cmd_mux:cmd_mux_008|altera_merlin_arbitrator:arb|top_priority_reg[0] ; 4 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[2] ; 6 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[1] ; 6 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[0] ; 6 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[0] ; 1 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|f_empty ; 4 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|f_empty ; 4 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller_001|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; |
; ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain[1] ; 1 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5] ; 3 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[4] ; 4 ; |
; detector_tokens:m_x|counter_neg[0] ; 9 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[2] ; 3 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[1] ; 4 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[0] ; 5 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg[0] ; 10 ; |
; Total number of inverted registers = 52 ; ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[3] ; 6 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5] ; 5 ; |
; spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[4] ; 5 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|counter_neg[0] ; 10 ; |
; detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[0] ; 10 ; |
; Total number of inverted registers = 47 ; ; |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ |
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Multiplexer Restructuring Statistics (Restructuring Performed) ; |
; Multiplexer Restructuring Statistics (No Restructuring Performed) ; |
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; |
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:clock_sel_s1_translator|wait_latency_counter[1] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_enable_s1_translator|wait_latency_counter[0] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|wait_latency_counter[1] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|wait_latency_counter[0] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:timecode_tx_data_s1_translator|wait_latency_counter[0] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_en_tx_s1_translator|wait_latency_counter[1] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:write_data_fifo_tx_s1_translator|wait_latency_counter[0] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:link_disable_s1_translator|wait_latency_counter[1] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_translator:auto_start_s1_translator|wait_latency_counter[1] ; |
7863,26 → 8319,36
; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ; |
; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[2] ; |
; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|nxt_uncomp_subburst_byte_cnt[6] ; |
; 6:1 ; 3 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|src_data[100] ; |
; 6:1 ; 3 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|src_channel[18] ; |
; 8:1 ; 3 bits ; 15 LEs ; 15 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router|src_data[103] ; |
; 19:1 ; 4 bits ; 48 LEs ; 48 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|src_data[103] ; |
; 20:1 ; 2 bits ; 26 LEs ; 26 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|src_channel[16] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100[9] ; |
; 20:1 ; 2 bits ; 26 LEs ; 26 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|ulight_fifo_mm_interconnect_0_router:router_001|src_channel[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|counter[0] ; |
; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|parity_rec_d_gen ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b|aux_pb ; |
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b|counter[15] ; |
; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|credit_counter[5] ; |
; 64:1 ; 9 bits ; 378 LEs ; 378 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|data_out[8] ; |
; 17:1 ; 11 bits ; 121 LEs ; 22 LEs ; 99 LEs ; Yes ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter[8] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b|PB_down ; |
; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |SPW_ULIGHT_FIFO|debounce_db:db_system_spwulight_b|counter[13] ; |
; 64:1 ; 9 bits ; 378 LEs ; 378 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|data_out[3] ; |
; 7:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[0] ; |
; 7:1 ; 3 bits ; 12 LEs ; 9 LEs ; 3 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_counter_receive[5] ; |
; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|fct_flag[1] ; |
; 9:1 ; 4 bits ; 24 LEs ; 8 LEs ; 16 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|global_counter_transfer[0] ; |
; 8:1 ; 6 bits ; 30 LEs ; 24 LEs ; 6 LEs ; No ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|last_type ; |
; 64:1 ; 9 bits ; 378 LEs ; 378 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx|data_out[7] ; |
; 64:1 ; 2 bits ; 84 LEs ; 26 LEs ; 58 LEs ; Yes ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|counter_neg:cnt_neg|counter_neg[1] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|last_is_data ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control|parity_rec_c_gen ; |
; 5:1 ; 9 bits ; 27 LEs ; 18 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv|rx_data_flag[0] ; |
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|last_timein_control_flag_tx[1] ; |
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_sout_e ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|eop_eep_last ; |
; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|global_counter_transfer[3] ; |
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_tcode_in[6] ; |
; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in[8] ; |
; 3:1 ; 9 bits ; 18 LEs ; 9 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd|tx_data_in_0[6] ; |
; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag[0] ; |
; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|fct_counter_p[0] ; |
; 64:1 ; 9 bits ; 378 LEs ; 378 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx|data_out[1] ; |
; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|fct_flag_p[1] ; |
; 6:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|txdata_flagctrl_tx_last[3] ; |
; 5:1 ; 2 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|counter_aux[1] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|rp_data[124] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|rp_data[124] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|rp_data[125] ; |
7905,58 → 8371,58
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|rp_data[124] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|rp_data[124] ; |
; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|rp_data[124] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_data_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[5] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ; |
; 4:1 ; 24 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[29] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|Selector1 ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_rx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:counter_tx_fifo_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fsm_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:clock_sel_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_info_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_ready_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|last_is_timec ; |
; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|rx_got_time_code ; |
; 5:1 ; 9 bits ; 27 LEs ; 18 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|detector_tokens:m_x|data[5] ; |
; 4:1 ; 24 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|altera_merlin_address_alignment:align_address_to_size|address_burst[28] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|Selector6 ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_tx_enable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_tx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_en_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:write_data_fifo_tx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_disable_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[4] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:auto_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[2] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:link_start_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_empty_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:fifo_full_rx_status_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[5] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_read_en_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:data_flag_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[0] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_ready_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[7] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[5] ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[1] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:led_pio_test_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[3] ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|Selector11 ; |
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|last_is_data ; |
; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[0] ; |
; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns[0] ; |
; 5:1 ; 9 bits ; 27 LEs ; 18 LEs ; 9 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_flag[7] ; |
; 5:1 ; 12 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[4] ; |
; 13:1 ; 3 bits ; 24 LEs ; 18 LEs ; 6 LEs ; No ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector4 ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_slave_agent:timecode_rx_s1_agent|altera_merlin_burst_uncompressor:uncompressor|burst_uncompress_byte_counter[6] ; |
; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter_100[3] ; |
; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after64us[7] ; |
; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after850ns[9] ; |
; 5:1 ; 12 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|after128us[7] ; |
; 64:1 ; 2 bits ; 84 LEs ; 26 LEs ; 58 LEs ; Yes ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg|counter_neg[1] ; |
; 17:1 ; 11 bits ; 121 LEs ; 22 LEs ; 99 LEs ; Yes ; |SPW_ULIGHT_FIFO|clock_reduce:R_400_to_2_5_10_100_200_300MHZ|counter[10] ; |
; 13:1 ; 3 bits ; 24 LEs ; 18 LEs ; 6 LEs ; No ; |SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|Selector2 ; |
; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_axi_master_ni:hps_0_h2f_axi_master_agent|Selector8 ; |
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
|
|
7966,7 → 8432,7
; Assignment ; Value ; From ; To ; |
+---------------------------------------+-----------------------+------+----------------------------------------------------------------------------------------------------------+ |
; IP_TOOL_NAME ; altera_mem_if_hps_pll ; - ; - ; |
; IP_TOOL_VERSION ; 17.0 ; - ; - ; |
; IP_TOOL_VERSION ; 17.1 ; - ; - ; |
; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ; |
; ALLOW_SYNCH_CTRL_USAGE ; OFF ; - ; - ; |
; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; - ; |
7980,7 → 8446,7
; Assignment ; Value ; From ; To ; |
+---------------------------------------+----------------------------------+------+---------------------------------------------------------------------------------------------+ |
; IP_TOOL_NAME ; altera_mem_if_ddr3_hard_phy_core ; - ; - ; |
; IP_TOOL_VERSION ; 17.0 ; - ; - ; |
; IP_TOOL_VERSION ; 17.1 ; - ; - ; |
; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ; |
+---------------------------------------+----------------------------------+------+---------------------------------------------------------------------------------------------+ |
|
8048,7 → 8514,7
; Assignment ; Value ; From ; To ; |
+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------+ |
; IP_TOOL_NAME ; altera_mem_if_oct ; - ; - ; |
; IP_TOOL_VERSION ; 17.0 ; - ; - ; |
; IP_TOOL_VERSION ; 17.1 ; - ; - ; |
; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ; |
; ALLOW_SYNCH_CTRL_USAGE ; OFF ; - ; - ; |
; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; - ; |
8062,7 → 8528,7
; Assignment ; Value ; From ; To ; |
+---------------------------------------+-------------------+------+---------------------------------------------------------------------------------------------------------------------------+ |
; IP_TOOL_NAME ; altera_mem_if_dll ; - ; - ; |
; IP_TOOL_VERSION ; 17.0 ; - ; - ; |
; IP_TOOL_VERSION ; 17.1 ; - ; - ; |
; FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND ; 100 ; - ; - ; |
; ALLOW_SYNCH_CTRL_USAGE ; OFF ; - ; - ; |
; AUTO_CLOCK_ENABLE_RECOGNITION ; OFF ; - ; - ; |
8430,6 → 8896,103
+-------------------+-------+------+----------------------------------------------------------------------------------------------+ |
|
|
+-------------------------------------------------------------------------------------------------------------------+ |
; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv ; |
+-------------------------+-------------+------+--------------------------------------------------------------------+ |
; Assignment ; Value ; From ; To ; |
+-------------------------+-------------+------+--------------------------------------------------------------------+ |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; - ; |
+-------------------------+-------------+------+--------------------------------------------------------------------+ |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------+ |
; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt ; |
+-------------------------+-------------+------+------------------------------------------------------------------------------------+ |
; Assignment ; Value ; From ; To ; |
+-------------------------+-------------+------+------------------------------------------------------------------------------------+ |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.000 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.001 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.010 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.011 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_p.100 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.100 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.011 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.010 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.001 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_receive.000 ; |
+-------------------------+-------------+------+------------------------------------------------------------------------------------+ |
|
|
+--------------------------------------------------------------------------------------------------------------------------------+ |
; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd ; |
+-------------------------+-------------+------+---------------------------------------------------------------------------------+ |
; Assignment ; Value ; From ; To ; |
+-------------------------+-------------+------+---------------------------------------------------------------------------------+ |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send.000 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send.001 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send_p.000 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send_p.001 ; |
; ADV_NETLIST_OPT_ALLOWED ; Never Allow ; - ; state_fct_send_p.010 ; |
+-------------------------+-------------+------+---------------------------------------------------------------------------------+ |
|
|
+-----------------------------------------------------------------------+ |
; Source assignments for spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; |
+---------------------------+-------+------+----------------------------+ |
; Assignment ; Value ; From ; To ; |
+---------------------------+-------+------+----------------------------+ |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; - ; |
; PRESERVE_REGISTER ; on ; - ; wr_ptr[5] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[5] ; |
; PRESERVE_REGISTER ; on ; - ; wr_ptr[4] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[4] ; |
; PRESERVE_REGISTER ; on ; - ; wr_ptr[3] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[3] ; |
; PRESERVE_REGISTER ; on ; - ; wr_ptr[2] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[2] ; |
; PRESERVE_REGISTER ; on ; - ; wr_ptr[1] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[1] ; |
; PRESERVE_REGISTER ; on ; - ; wr_ptr[0] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; wr_ptr[0] ; |
; PRESERVE_REGISTER ; on ; - ; counter_writer[5] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[5] ; |
; PRESERVE_REGISTER ; on ; - ; counter_writer[4] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[4] ; |
; PRESERVE_REGISTER ; on ; - ; counter_writer[3] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[3] ; |
; PRESERVE_REGISTER ; on ; - ; counter_writer[2] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[2] ; |
; PRESERVE_REGISTER ; on ; - ; counter_writer[1] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[1] ; |
; PRESERVE_REGISTER ; on ; - ; counter_writer[0] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_writer[0] ; |
; PRESERVE_REGISTER ; on ; - ; counter_reader[5] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[5] ; |
; PRESERVE_REGISTER ; on ; - ; counter_reader[4] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[4] ; |
; PRESERVE_REGISTER ; on ; - ; counter_reader[3] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[3] ; |
; PRESERVE_REGISTER ; on ; - ; counter_reader[2] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[2] ; |
; PRESERVE_REGISTER ; on ; - ; counter_reader[1] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[1] ; |
; PRESERVE_REGISTER ; on ; - ; counter_reader[0] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; counter_reader[0] ; |
; PRESERVE_REGISTER ; on ; - ; rd_ptr[5] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[5] ; |
; PRESERVE_REGISTER ; on ; - ; rd_ptr[4] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[4] ; |
; PRESERVE_REGISTER ; on ; - ; rd_ptr[3] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[3] ; |
; PRESERVE_REGISTER ; on ; - ; rd_ptr[2] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[2] ; |
; PRESERVE_REGISTER ; on ; - ; rd_ptr[1] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[1] ; |
; PRESERVE_REGISTER ; on ; - ; rd_ptr[0] ; |
; PRESERVE_FANOUT_FREE_NODE ; on ; - ; rd_ptr[0] ; |
+---------------------------+-------+------+----------------------------+ |
|
|
+-------------------------------------------------------------------------------------+ |
; Parameter Settings for User Entity Instance: ulight_fifo:u0|ulight_fifo_hps_0:hps_0 ; |
+----------------+-------+------------------------------------------------------------+ |
9496,12 → 10059,12
+--------------------------------------+------------------------+---------------------------------------------+ |
; Parameter Name ; Value ; Type ; |
+--------------------------------------+------------------------+---------------------------------------------+ |
; reference_clock_frequency ; 100.0 MHz ; String ; |
; reference_clock_frequency ; 50.0 MHz ; String ; |
; fractional_vco_multiplier ; false ; String ; |
; pll_type ; Cyclone V ; String ; |
; pll_subtype ; General ; String ; |
; number_of_clocks ; 1 ; Signed Integer ; |
; operation_mode ; direct ; String ; |
; operation_mode ; normal ; String ; |
; deserialization_factor ; 4 ; Signed Integer ; |
; data_rate ; 0 ; Signed Integer ; |
; sim_additional_refclk_cycles_to_lock ; 0 ; Signed Integer ; |
9577,8 → 10140,8
; clock_name_global_6 ; false ; String ; |
; clock_name_global_7 ; false ; String ; |
; clock_name_global_8 ; false ; String ; |
; m_cnt_hi_div ; 2 ; Signed Integer ; |
; m_cnt_lo_div ; 2 ; Signed Integer ; |
; m_cnt_hi_div ; 4 ; Signed Integer ; |
; m_cnt_lo_div ; 4 ; Signed Integer ; |
; m_cnt_bypass_en ; false ; String ; |
; m_cnt_odd_div_duty_en ; false ; String ; |
; n_cnt_hi_div ; 256 ; Signed Integer ; |
9715,14 → 10278,14
; pll_slf_rst ; false ; String ; |
; pll_bw_sel ; low ; String ; |
; pll_output_clk_frequency ; 400.0 MHz ; String ; |
; pll_cp_current ; 30 ; Signed Integer ; |
; pll_bwctrl ; 2000 ; Signed Integer ; |
; pll_cp_current ; 20 ; Signed Integer ; |
; pll_bwctrl ; 4000 ; Signed Integer ; |
; pll_fractional_division ; 1 ; String ; |
; pll_fractional_cout ; 32 ; Signed Integer ; |
; pll_dsm_out_sel ; 1st_order ; String ; |
; mimic_fbclk_type ; none ; String ; |
; mimic_fbclk_type ; gclk ; String ; |
; pll_fbclk_mux_1 ; glb ; String ; |
; pll_fbclk_mux_2 ; m_cnt ; String ; |
; pll_fbclk_mux_2 ; fb_1 ; String ; |
; pll_m_cnt_in_src ; ph_mux_clk ; String ; |
; pll_vcoph_div ; 1 ; Signed Integer ; |
; refclk1_frequency ; 100.0 MHz ; String ; |
19890,6 → 20453,17
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". |
|
|
+----------------------------------------------------------------------------------------------------------------------+ |
; Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx ; |
+----------------+-------+---------------------------------------------------------------------------------------------+ |
; Parameter Name ; Value ; Type ; |
+----------------+-------+---------------------------------------------------------------------------------------------+ |
; DWIDTH ; 9 ; Signed Integer ; |
; AWIDTH ; 6 ; Signed Integer ; |
+----------------+-------+---------------------------------------------------------------------------------------------+ |
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". |
|
|
+---------------------------------------------------------------------------------------------+ |
; Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data ; |
+----------------+-------+--------------------------------------------------------------------+ |
19901,6 → 20475,43
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". |
|
|
+----------------------------------------------------------------------------------------------------------------------+ |
; Parameter Settings for User Entity Instance: spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|mem_data:mem_dta_fifo_tx ; |
+----------------+-------+---------------------------------------------------------------------------------------------+ |
; Parameter Name ; Value ; Type ; |
+----------------+-------+---------------------------------------------------------------------------------------------+ |
; DWIDTH ; 9 ; Signed Integer ; |
; AWIDTH ; 6 ; Signed Integer ; |
+----------------+-------+---------------------------------------------------------------------------------------------+ |
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". |
|
|
+-------------------------------------------------------------------------------------------------------------------+ |
; Port Connectivity Checks: "detector_tokens:m_x|bit_capture_control:capture_c" ; |
+---------+--------+----------+-------------------------------------------------------------------------------------+ |
; Port ; Type ; Severity ; Details ; |
+---------+--------+----------+-------------------------------------------------------------------------------------+ |
; bit_c_0 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_c_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
+---------+--------+----------+-------------------------------------------------------------------------------------+ |
|
|
+-------------------------------------------------------------------------------------------------------------------+ |
; Port Connectivity Checks: "detector_tokens:m_x|bit_capture_data:capture_d" ; |
+---------+--------+----------+-------------------------------------------------------------------------------------+ |
; Port ; Type ; Severity ; Details ; |
+---------+--------+----------+-------------------------------------------------------------------------------------+ |
; bit_d_0 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_d_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_d_2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_d_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_d_4 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_d_5 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_d_6 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
; bit_d_7 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; |
+---------+--------+----------+-------------------------------------------------------------------------------------+ |
|
|
+---------------------------------------------------------------------------------------+ |
; Port Connectivity Checks: "ulight_fifo:u0|altera_reset_controller:rst_controller_001" ; |
+----------------+--------+----------+--------------------------------------------------+ |
22615,11 → 23226,10
+-------------------------------------+---------------+ |
; Type ; Count ; |
+-------------------------------------+---------------+ |
; arriav_ff ; 4692 ; |
; CLR ; 1143 ; |
; ENA ; 18 ; |
; ENA CLR ; 3470 ; |
; plain ; 61 ; |
; arriav_ff ; 4628 ; |
; CLR ; 1150 ; |
; ENA CLR ; 3301 ; |
; plain ; 177 ; |
; arriav_hps_interface_boot_from_fpga ; 1 ; |
; arriav_hps_interface_clocks_resets ; 1 ; |
; arriav_hps_interface_dbg_apb ; 1 ; |
22627,23 → 23237,25
; arriav_hps_interface_fpga2sdram ; 1 ; |
; arriav_hps_interface_hps2fpga ; 1 ; |
; arriav_hps_interface_tpiu_trace ; 1 ; |
; arriav_lcell_comb ; 5228 ; |
; arith ; 220 ; |
; 1 data inputs ; 94 ; |
; 2 data inputs ; 90 ; |
; 3 data inputs ; 22 ; |
; arriav_lcell_comb ; 5407 ; |
; arith ; 219 ; |
; 1 data inputs ; 99 ; |
; 2 data inputs ; 89 ; |
; 3 data inputs ; 17 ; |
; 4 data inputs ; 13 ; |
; 5 data inputs ; 1 ; |
; extend ; 59 ; |
; 7 data inputs ; 59 ; |
; normal ; 4949 ; |
; extend ; 72 ; |
; 7 data inputs ; 72 ; |
; normal ; 5110 ; |
; 0 data inputs ; 1 ; |
; 1 data inputs ; 52 ; |
; 2 data inputs ; 549 ; |
; 3 data inputs ; 919 ; |
; 4 data inputs ; 1406 ; |
; 5 data inputs ; 824 ; |
; 6 data inputs ; 1198 ; |
; 1 data inputs ; 44 ; |
; 2 data inputs ; 483 ; |
; 3 data inputs ; 890 ; |
; 4 data inputs ; 1504 ; |
; 5 data inputs ; 906 ; |
; 6 data inputs ; 1282 ; |
; shared ; 6 ; |
; 2 data inputs ; 6 ; |
; boundary_port ; 15 ; |
; cyclonev_fractional_pll ; 1 ; |
; cyclonev_pll_output_counter ; 1 ; |
22650,8 → 23262,8
; cyclonev_pll_reconfig ; 1 ; |
; cyclonev_pll_refclk_select ; 1 ; |
; ; ; |
; Max LUT depth ; 8.00 ; |
; Average LUT depth ; 3.25 ; |
; Max LUT depth ; 7.00 ; |
; Average LUT depth ; 3.17 ; |
+-------------------------------------+---------------+ |
|
|
22700,8 → 23312,8
+----------------------------------------+--------------+ |
; Partition Name ; Elapsed Time ; |
+----------------------------------------+--------------+ |
; Top ; 00:00:32 ; |
; ulight_fifo_hps_0_hps_io_border:border ; 00:00:00 ; |
; Top ; 00:00:34 ; |
; ulight_fifo_hps_0_hps_io_border:border ; 00:00:01 ; |
+----------------------------------------+--------------+ |
|
|
22710,31 → 23322,63
+-------------------------------+ |
Info: ******************************************************************* |
Info: Running Quartus Prime Analysis & Synthesis |
Info: Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Info: Processing started: Fri Sep 15 08:07:41 2017 |
Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
Info: Processing started: Mon Feb 5 00:46:52 2018 |
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight |
Info (16303): High Performance Effort optimization mode selected -- timing performance will be prioritized at the potential cost of increased compilation time |
Info (16304): Mode behavior is affected by advanced setting Fitter Effort (default for this mode is Standard Fit) |
Info (16304): Mode behavior is affected by advanced setting Physical Synthesis Effort Level (default for this mode is Normal) |
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. |
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v |
Info (12023): Found entity 1: detector_tokens File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v |
Info (12023): Found entity 1: debounce_db File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v |
Info (12023): Found entity 1: clock_reduce File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v Line: 34 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v |
Info (12023): Found entity 1: tx_fsm_m File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 34 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v |
Info (12023): Found entity 1: tx_fct_send File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v |
Info (12023): Found entity 1: tx_fct_counter File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v |
Info (12023): Found entity 1: tx_data_send File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_data_send.v Line: 33 |
Warning (10890): Verilog HDL Attribute warning at rx_data_receive.v(64): overriding existing value for attribute "dont_replicate" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v Line: 64 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v |
Info (12023): Found entity 1: rx_data_receive File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_receive.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v |
Info (12023): Found entity 1: rx_data_control_p File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_control_p.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v |
Info (12023): Found entity 1: rx_data_buffer_data_w File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_data_buffer_data_w.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v |
Info (12023): Found entity 1: rx_control_data_rdy File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_control_data_rdy.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v |
Info (12023): Found entity 1: rx_buffer_fsm File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_buffer_fsm.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v |
Info (12023): Found entity 1: mem_data File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/mem_data.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v |
Info (12023): Found entity 1: counter_neg File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v |
Info (12023): Found entity 1: bit_capture_control File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bitc_capture_control.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v |
Info (12023): Found entity 1: bit_capture_data File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/bit_capture_data.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v |
Info (12023): Found entity 1: TX_SPW File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v Line: 36 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v |
Info (12023): Found entity 1: top_spw_ultra_light File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 36 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v |
Info (12023): Found entity 1: spw_ulight_con_top_x File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 33 |
Info (12023): Found entity 1: spw_ulight_con_top_x File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 36 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v |
Info (12023): Found entity 1: RX_SPW File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 36 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v |
Info (12023): Found entity 1: FSM_SPW File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v Line: 36 |
Warning (10890): Verilog HDL Attribute warning at fifo_tx.v(43): overriding existing value for attribute "syn_noprune" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 43 |
Warning (10890): Verilog HDL Attribute warning at fifo_tx.v(44): overriding existing value for attribute "syn_noprune" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 44 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v |
Info (12023): Found entity 1: fifo_tx File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v |
Info (12023): Found entity 1: fifo_rx File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v |
Info (12023): Found entity 1: TX_SPW File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v Line: 36 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v |
Info (12023): Found entity 1: debounce_db File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/debounce.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v |
Info (12023): Found entity 1: detector_tokens File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 33 |
Info (12021): Found 1 design units, including 1 entities, in source file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v |
Info (12023): Found entity 1: clock_reduce File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/clock_reduce.v Line: 34 |
Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/ulight_fifo.v |
Info (12023): Found entity 1: ulight_fifo File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 6 |
Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/altera_reset_controller.v |
22822,7 → 23466,7
Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_pll.sv |
Info (12023): Found entity 1: hps_sdram_pll File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv Line: 25 |
Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v |
Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 29 |
Info (12023): Found entity 1: hps_sdram_p0_clock_pair_generator File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v Line: 28 |
Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v |
Info (12023): Found entity 1: hps_sdram_p0_acv_hard_addr_cmd_pads File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 17 |
Info (12021): Found 1 design units, including 1 entities, in source file ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v |
22873,11 → 23517,11
Info (12023): Found entity 1: ulight_fifo_auto_start File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_auto_start.v Line: 21 |
Info (12021): Found 1 design units, including 1 entities, in source file top_rtl/spw_fifo_ulight.v |
Info (12023): Found entity 1: SPW_ULIGHT_FIFO File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 1 |
Warning (10236): Verilog HDL Implicit Net warning at spw_fifo_ulight.v(96): created implicit net for "top_tx_ready_tick" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 96 |
Warning (10236): Verilog HDL Implicit Net warning at spw_fifo_ulight.v(99): created implicit net for "top_tx_ready_tick" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 99 |
Warning (10236): Verilog HDL Implicit Net warning at hps_sdram_pll.sv(168): created implicit net for "pll_dr_clk" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_pll.sv Line: 168 |
Info (12127): Elaborating entity "SPW_ULIGHT_FIFO" for the top level hierarchy |
Warning (10034): Output port "LED[6]" at spw_fifo_ulight.v(17) has no driver File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 17 |
Info (12128): Elaborating entity "ulight_fifo" for hierarchy "ulight_fifo:u0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 102 |
Info (12128): Elaborating entity "ulight_fifo" for hierarchy "ulight_fifo:u0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 105 |
Info (12128): Elaborating entity "ulight_fifo_auto_start" for hierarchy "ulight_fifo:u0|ulight_fifo_auto_start:auto_start" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 174 |
Info (12128): Elaborating entity "ulight_fifo_clock_sel" for hierarchy "ulight_fifo:u0|ulight_fifo_clock_sel:clock_sel" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 185 |
Info (12128): Elaborating entity "ulight_fifo_counter_rx_fifo" for hierarchy "ulight_fifo:u0|ulight_fifo_counter_rx_fifo:counter_rx_fifo" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 193 |
22921,13 → 23565,12
Info (12134): Parameter "power_up_high" = "OFF" |
Info (12134): Parameter "width" = "1" |
Info (12021): Found 1 design units, including 1 entities, in source file db/ddio_out_uqe.tdf |
Info (12023): Found entity 1: ddio_out_uqe File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf Line: 28 |
Info (12128): Elaborating entity "ddio_out_uqe" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altddio_out.tdf Line: 101 |
Info (12023): Found entity 1: ddio_out_uqe File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/db/ddio_out_uqe.tdf Line: 27 |
Info (12128): Elaborating entity "ddio_out_uqe" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|altddio_out:clock_gen[0].umem_ck_pad|ddio_out_uqe:auto_generated" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altddio_out.tdf Line: 100 |
Info (12128): Elaborating entity "hps_sdram_p0_clock_pair_generator" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_acv_hard_addr_cmd_pads:uaddr_cmd_pads|hps_sdram_p0_clock_pair_generator:clock_gen[0].uclk_generator" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v Line: 337 |
Info (12128): Elaborating entity "hps_sdram_p0_altdqdqs" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_io_pads.v Line: 317 |
Info (12128): Elaborating entity "altdq_dqs2_acv_connect_to_hard_phy_cyclonev" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_p0:p0|hps_sdram_p0_acv_hard_memphy:umemphy|hps_sdram_p0_acv_hard_io_pads:uio_pads|hps_sdram_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_acv_connect_to_hard_phy_cyclonev:altdq_dqs2_inst" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_altdqdqs.v Line: 146 |
Info (12128): Elaborating entity "altera_mem_if_hhp_qseq_synth_top" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hhp_qseq_synth_top:seq" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 238 |
Warning (12158): Entity "altera_mem_if_hhp_qseq_synth_top" contains only dangling pins File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 238 |
Info (12128): Elaborating entity "altera_mem_if_hard_memory_controller_top_cyclonev" for hierarchy "ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_hps_io:hps_io|ulight_fifo_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|altera_mem_if_hard_memory_controller_top_cyclonev:c0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram.v Line: 794 |
Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1166): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1166 |
Warning (10230): Verilog HDL assignment warning at altera_mem_if_hard_memory_controller_top_cyclonev.sv(1167): truncated value with size 320 to match size of target (1) File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_mem_if_hard_memory_controller_top_cyclonev.sv Line: 1167 |
22940,17 → 23583,17
Info (12128): Elaborating entity "ulight_fifo_led_pio_test" for hierarchy "ulight_fifo:u0|ulight_fifo_led_pio_test:led_pio_test" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 339 |
Info (12128): Elaborating entity "ulight_fifo_pll_0" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 369 |
Info (12128): Elaborating entity "altera_pll" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v Line: 241 |
Warning (10034): Output port "lvds_clk" at altera_pll.v(320) has no driver File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 320 |
Warning (10034): Output port "loaden" at altera_pll.v(321) has no driver File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 321 |
Warning (10034): Output port "extclk_out" at altera_pll.v(322) has no driver File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 322 |
Warning (10034): Output port "lvds_clk" at altera_pll.v(319) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 319 |
Warning (10034): Output port "loaden" at altera_pll.v(320) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 320 |
Warning (10034): Output port "extclk_out" at altera_pll.v(321) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 321 |
Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus |
Info (12130): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v Line: 241 |
Info (12133): Instantiated megafunction "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" with the following parameter: File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_pll_0.v Line: 241 |
Info (12134): Parameter "fractional_vco_multiplier" = "false" |
Info (12134): Parameter "reference_clock_frequency" = "100.0 MHz" |
Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz" |
Info (12134): Parameter "pll_fractional_cout" = "32" |
Info (12134): Parameter "pll_dsm_out_sel" = "1st_order" |
Info (12134): Parameter "operation_mode" = "direct" |
Info (12134): Parameter "operation_mode" = "normal" |
Info (12134): Parameter "number_of_clocks" = "1" |
Info (12134): Parameter "output_clock_frequency0" = "400.000000 MHz" |
Info (12134): Parameter "phase_shift0" = "0 ps" |
23008,8 → 23651,8
Info (12134): Parameter "duty_cycle17" = "50" |
Info (12134): Parameter "pll_type" = "Cyclone V" |
Info (12134): Parameter "pll_subtype" = "General" |
Info (12134): Parameter "m_cnt_hi_div" = "2" |
Info (12134): Parameter "m_cnt_lo_div" = "2" |
Info (12134): Parameter "m_cnt_hi_div" = "4" |
Info (12134): Parameter "m_cnt_lo_div" = "4" |
Info (12134): Parameter "n_cnt_hi_div" = "256" |
Info (12134): Parameter "n_cnt_lo_div" = "256" |
Info (12134): Parameter "m_cnt_bypass_en" = "false" |
23143,13 → 23786,13
Info (12134): Parameter "c_cnt_bypass_en17" = "true" |
Info (12134): Parameter "c_cnt_odd_div_duty_en17" = "false" |
Info (12134): Parameter "pll_vco_div" = "2" |
Info (12134): Parameter "pll_cp_current" = "30" |
Info (12134): Parameter "pll_bwctrl" = "2000" |
Info (12134): Parameter "pll_cp_current" = "20" |
Info (12134): Parameter "pll_bwctrl" = "4000" |
Info (12134): Parameter "pll_output_clk_frequency" = "400.0 MHz" |
Info (12134): Parameter "pll_fractional_division" = "1" |
Info (12134): Parameter "mimic_fbclk_type" = "none" |
Info (12134): Parameter "mimic_fbclk_type" = "gclk" |
Info (12134): Parameter "pll_fbclk_mux_1" = "glb" |
Info (12134): Parameter "pll_fbclk_mux_2" = "m_cnt" |
Info (12134): Parameter "pll_fbclk_mux_2" = "fb_1" |
Info (12134): Parameter "pll_m_cnt_in_src" = "ph_mux_clk" |
Info (12134): Parameter "pll_slf_rst" = "false" |
Info (12134): Parameter "refclk1_frequency" = "100.0 MHz" |
23158,28 → 23801,28
Info (12134): Parameter "pll_auto_clk_sw_en" = "true" |
Info (12134): Parameter "pll_clkin_1_src" = "clk_1" |
Info (12134): Parameter "pll_clk_sw_dly" = "0" |
Info (12128): Elaborating entity "dps_extra_kick" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 769 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 769 |
Info (12128): Elaborating entity "dprio_init" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dprio_init:dprio_init_inst" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 784 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dprio_init:dprio_init_inst", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 784 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1961 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1961 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1972 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1972 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1983 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1983 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1994 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 1994 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2005 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2005 |
Info (12128): Elaborating entity "altera_cyclonev_pll" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2224 |
Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(632) has no driver File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 632 |
Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(637) has no driver File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 637 |
Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(641) has no driver File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 641 |
Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(642) has no driver File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 642 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2224 |
Info (12128): Elaborating entity "altera_cyclonev_pll_base" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1153 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1153 |
Info (12128): Elaborating entity "dps_extra_kick" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 768 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 768 |
Info (12128): Elaborating entity "dprio_init" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dprio_init:dprio_init_inst" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 783 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dprio_init:dprio_init_inst", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 783 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1960 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_0", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1960 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1971 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_1", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1971 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1982 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_2", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1982 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1993 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_3", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 1993 |
Info (12128): Elaborating entity "altera_pll_dps_lcell_comb" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2004 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_pll_dps_lcell_comb:lcell_cntsel_int_4", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2004 |
Info (12128): Elaborating entity "altera_cyclonev_pll" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223 |
Warning (10034): Output port "extclk" at altera_cyclonev_pll.v(631) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 631 |
Warning (10034): Output port "clkout[0]" at altera_cyclonev_pll.v(636) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 636 |
Warning (10034): Output port "loaden" at altera_cyclonev_pll.v(640) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 640 |
Warning (10034): Output port "lvdsclk" at altera_cyclonev_pll.v(641) has no driver File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 641 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223 |
Info (12128): Elaborating entity "altera_cyclonev_pll_base" for hierarchy "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152 |
Info (12131): Elaborated megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|altera_cyclonev_pll_base:fpll_0", which is child of megafunction instantiation "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_cyclonev_pll.v Line: 1152 |
Info (12128): Elaborating entity "ulight_fifo_timecode_rx" for hierarchy "ulight_fifo:u0|ulight_fifo_timecode_rx:timecode_rx" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 385 |
Info (12128): Elaborating entity "ulight_fifo_timecode_tx_data" for hierarchy "ulight_fifo:u0|ulight_fifo_timecode_tx_data:timecode_tx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 396 |
Info (12128): Elaborating entity "ulight_fifo_write_data_fifo_tx" for hierarchy "ulight_fifo:u0|ulight_fifo_write_data_fifo_tx:write_data_fifo_tx" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 426 |
23216,34 → 23859,89
Info (12128): Elaborating entity "altera_reset_controller" for hierarchy "ulight_fifo:u0|altera_reset_controller:rst_controller" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/ulight_fifo.v Line: 616 |
Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_sync_uq1" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v Line: 208 |
Info (12128): Elaborating entity "altera_reset_synchronizer" for hierarchy "ulight_fifo:u0|altera_reset_controller:rst_controller|altera_reset_synchronizer:alt_rst_req_sync_uq1" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_reset_controller.v Line: 220 |
Info (12128): Elaborating entity "spw_ulight_con_top_x" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 143 |
Info (12128): Elaborating entity "top_spw_ultra_light" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 133 |
Info (12128): Elaborating entity "FSM_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 113 |
Info (12128): Elaborating entity "RX_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 135 |
Info (10264): Verilog HDL Case Statement information at rx_spw.v(508): all case item expressions in this case statement are onehot File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 508 |
Info (12128): Elaborating entity "TX_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 158 |
Info (12128): Elaborating entity "fifo_rx" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 148 |
Info (12128): Elaborating entity "fifo_tx" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 162 |
Info (12128): Elaborating entity "debounce_db" for hierarchy "debounce_db:db_system_spwulight_b" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 150 |
Info (12128): Elaborating entity "clock_reduce" for hierarchy "clock_reduce:R_400_to_2_5_10_100_200_300MHZ" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 158 |
Info (12128): Elaborating entity "detector_tokens" for hierarchy "detector_tokens:m_x" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 165 |
Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(62): object "bit_c_ex" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 62 |
Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(103): object "rx_data_take_0" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 103 |
Info (10264): Verilog HDL Case Statement information at detector_tokens.v(271): all case item expressions in this case statement are onehot File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 271 |
Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic. File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2224 |
Info (12128): Elaborating entity "spw_ulight_con_top_x" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 148 |
Info (12128): Elaborating entity "top_spw_ultra_light" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 136 |
Info (12128): Elaborating entity "FSM_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 112 |
Info (12128): Elaborating entity "RX_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 134 |
Info (12128): Elaborating entity "rx_buffer_fsm" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_buffer_fsm:buffer_fsm" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 176 |
Info (12128): Elaborating entity "rx_data_buffer_data_w" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_buffer_data_w:buffer_data_flag" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 191 |
Info (12128): Elaborating entity "rx_control_data_rdy" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_control_data_rdy:control_data_rdy" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 213 |
Info (12128): Elaborating entity "rx_data_control_p" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_control_p:data_control" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 250 |
Info (12128): Elaborating entity "bit_capture_data" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_data:capture_d" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 270 |
Info (12128): Elaborating entity "bit_capture_control" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|bit_capture_control:capture_c" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 283 |
Info (12128): Elaborating entity "counter_neg" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|counter_neg:cnt_neg" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 291 |
Info (10264): Verilog HDL Case Statement information at counter_neg.v(58): all case item expressions in this case statement are onehot File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/counter_neg.v Line: 58 |
Info (12128): Elaborating entity "rx_data_receive" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|RX_SPW:RX|rx_data_receive:rx_dtarcv" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/rx_spw.v Line: 325 |
Info (12128): Elaborating entity "TX_SPW" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/top_spw_ultra_light.v Line: 157 |
Info (12128): Elaborating entity "tx_fsm_m" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v Line: 117 |
Info (12128): Elaborating entity "tx_fct_counter" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 789 |
Info (12128): Elaborating entity "tx_fct_send" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 797 |
Info (12128): Elaborating entity "tx_data_send" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_data_send:tx_data_snd" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_spw.v Line: 142 |
Info (12128): Elaborating entity "fifo_rx" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 151 |
Info (12128): Elaborating entity "mem_data" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|mem_data:mem_dta_fifo_tx" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 415 |
Info (12128): Elaborating entity "fifo_tx" for hierarchy "spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/spw_ulight_con_top_x.v Line: 165 |
Info (12128): Elaborating entity "debounce_db" for hierarchy "debounce_db:db_system_spwulight_b" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 155 |
Info (12128): Elaborating entity "clock_reduce" for hierarchy "clock_reduce:R_400_to_2_5_10_100_200_300MHZ" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 163 |
Info (12128): Elaborating entity "detector_tokens" for hierarchy "detector_tokens:m_x" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 170 |
Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(87): object "control_r" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 87 |
Warning (10858): Verilog HDL warning at detector_tokens.v(88): object control_p_r used but never assigned File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 88 |
Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(92): object "dta_timec" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 92 |
Warning (10858): Verilog HDL warning at detector_tokens.v(93): object dta_timec_p used but never assigned File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 93 |
Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(104): object "ready_control" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 104 |
Warning (10036): Verilog HDL or VHDL warning at detector_tokens.v(105): object "ready_data" assigned a value but never read File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 105 |
Warning (10030): Net "control_p_r" at detector_tokens.v(88) has no driver or initial value, using a default initial value '0' File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 88 |
Warning (10030): Net "dta_timec_p[7..0]" at detector_tokens.v(93) has no driver or initial value, using a default initial value '0' File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 93 |
Warning (12030): Port "extclk" on the entity instantiation of "cyclonev_pll" is connected to a signal of width 1. The formal width of the signal in the module is 2. The extra bits will be left dangling without any fan-out logic. File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2223 |
Warning (14284): Synthesized away the following node(s): |
Warning (14285): Synthesized away the following LCELL buffer node(s): |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[4]" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 425 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[3]" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 425 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[2]" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 425 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[1]" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 425 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[0]" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 425 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|gnd" File: /home/felipe/intelFPGA_lite/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 427 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[4]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[3]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[2]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[1]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|cntsel_temp[0]" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 424 |
Warning (14320): Synthesized away node "ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|gnd" File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 426 |
Info (13014): Ignored 2 buffer(s) |
Info (13019): Ignored 2 SOFT buffer(s) |
Warning (12241): 32 hierarchies have connectivity warnings - see the Connectivity Checks report folder |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_rx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:counter_tx_fifo_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fsm_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:clock_sel_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_info_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_ready_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_enable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_tx_data_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_tx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_en_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:write_data_fifo_tx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_disable_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:auto_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:link_start_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_empty_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:fifo_full_rx_status_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_read_en_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:data_flag_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_ready_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:timecode_rx_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_test_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv Line: 398 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|detector_tokens:m_x|state_data_process" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/DEBUG_VERILOG/detector_tokens.v Line: 51 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_open_slot" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 60 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_write" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 54 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_rx:rx_data|state_data_read" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_rx.v Line: 57 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|ulight_fifo:u0|ulight_fifo_pll_0:pll_0|altera_pll:altera_pll_i|dps_extra_kick:dps_extra_inst|dps_current_state" will be implemented as a safe state machine. File: /home/felipe/intelFPGA_lite/17.1/quartus/libraries/megafunctions/altera_pll.v Line: 2672 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_read" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 52 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|state_tx" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fsm_m.v Line: 92 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v Line: 45 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_send:tx_fct_snd|state_fct_send_p" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_send.v Line: 48 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_p" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v Line: 47 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|fifo_tx:tx_data|state_data_write" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fifo_tx.v Line: 49 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_fct_counter:tx_fct_cnt|state_fct_receive" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/tx_fct_counter.v Line: 44 |
Info (284007): State machine "|SPW_ULIGHT_FIFO|spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|FSM_SPW:FSM|state_fsm" will be implemented as a safe state machine. File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/rtl/RTL_VB/fsm_spw.v Line: 71 |
Warning (13024): Output pins are stuck at VCC or GND |
Warning (13410): Pin "LED[6]" is stuck at GND File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 17 |
Info (286031): Timing-Driven Synthesis is running on partition "Top" |
Info (17049): 1372 registers lost all their fanouts during netlist optimizations. |
Info (17049): 1382 registers lost all their fanouts during netlist optimizations. |
Info (286031): Timing-Driven Synthesis is running on partition "ulight_fifo_hps_0_hps_io_border:border" |
Info (144001): Generated suppressed messages file /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/output_files/spw_fifo_ulight.map.smsg |
Warning (35014): Found 1 partition definition(s) having no effect on incremental compilation |
23252,15 → 23950,15
Info (16011): Adding 15 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL |
Warning (21074): Design contains 1 input pin(s) that do not drive logic |
Warning (15610): No output dependent on input pin "KEY[0]" File: /home/felipe/Documentos/verilog_projects/GITHUBPROJECTS/SPACEWIRESYSTEMC/altera_work/spw_fifo_ulight/top_rtl/spw_fifo_ulight.v Line: 3 |
Info (21057): Implemented 8580 device resources after synthesis - the final resource count might be different |
Info (21057): Implemented 8595 device resources after synthesis - the final resource count might be different |
Info (21058): Implemented 5 input pins |
Info (21059): Implemented 10 output pins |
Info (21061): Implemented 8554 logic cells |
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 45 warnings |
Info: Peak virtual memory: 1351 megabytes |
Info: Processing ended: Fri Sep 15 08:13:05 2017 |
Info: Elapsed time: 00:05:24 |
Info: Total CPU time (on all processors): 00:06:00 |
Info (21061): Implemented 8569 logic cells |
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 53 warnings |
Info: Peak virtual memory: 1310 megabytes |
Info: Processing ended: Mon Feb 5 00:52:10 2018 |
Info: Elapsed time: 00:05:18 |
Info: Total CPU time (on all processors): 00:05:46 |
|
|
+------------------------------------------+ |
/spw_fifo_ulight.map.summary
1,10 → 1,10
Analysis & Synthesis Status : Successful - Fri Sep 15 08:13:05 2017 |
Quartus Prime Version : 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Analysis & Synthesis Status : Successful - Mon Feb 5 00:52:09 2018 |
Quartus Prime Version : 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
Revision Name : spw_fifo_ulight |
Top-level Entity Name : SPW_ULIGHT_FIFO |
Family : Cyclone V |
Logic utilization (in ALMs) : N/A |
Total registers : 4692 |
Total registers : 4628 |
Total pins : 15 |
Total virtual pins : 0 |
Total block memory bits : 0 |
/spw_fifo_ulight.pin
6,12 → 6,11
-- associated documentation or information are expressly subject |
-- to the terms and conditions of the Intel Program License |
-- Subscription Agreement, the Intel Quartus Prime License Agreement, |
-- the Intel MegaCore Function License Agreement, or other |
-- applicable license agreement, including, without limitation, |
-- that your use is for the sole purpose of programming logic |
-- devices manufactured by Intel and sold by Intel or its |
-- authorized distributors. Please refer to the applicable |
-- agreement for further details. |
-- the Intel FPGA IP License Agreement, or other applicable license |
-- agreement, including, without limitation, that your use is for |
-- the sole purpose of programming logic devices manufactured by |
-- Intel and sold by Intel or its authorized distributors. Please |
-- refer to the applicable agreement for further details. |
-- |
-- This is a Quartus Prime output file. It is for reporting purposes only, and is |
-- not intended for use as a Quartus Prime input file. This file cannot be used |
73,7 → 72,7
-- Pin directions (input, output or bidir) are based on device operating in user mode. |
--------------------------------------------------------------------------------- |
|
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
CHIP "spw_fifo_ulight" ASSIGNED TO AN: 5CSEMA4U23C6 |
|
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment |
/spw_fifo_ulight.sld
2,7 → 2,7
<sld_infos> |
<sld_info hpath="ulight_fifo:u0" name="u0"> |
<assignment_values> |
<assignment_value text="QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928"/> |
<assignment_value text="QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1516735843"/> |
</assignment_values> |
</sld_info> |
</sld_infos> |
/spw_fifo_ulight.sof
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/spw_fifo_ulight.sta.rpt
1,6 → 1,6
TimeQuest Timing Analyzer report for spw_fifo_ulight |
Fri Sep 15 08:19:10 2017 |
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Mon Feb 5 00:59:04 2018 |
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
|
|
--------------------- |
72,27 → 72,26
associated documentation or information are expressly subject |
to the terms and conditions of the Intel Program License |
Subscription Agreement, the Intel Quartus Prime License Agreement, |
the Intel MegaCore Function License Agreement, or other |
applicable license agreement, including, without limitation, |
that your use is for the sole purpose of programming logic |
devices manufactured by Intel and sold by Intel or its |
authorized distributors. Please refer to the applicable |
agreement for further details. |
the Intel FPGA IP License Agreement, or other applicable license |
agreement, including, without limitation, that your use is for |
the sole purpose of programming logic devices manufactured by |
Intel and sold by Intel or its authorized distributors. Please |
refer to the applicable agreement for further details. |
|
|
|
+-----------------------------------------------------------------------------+ |
; TimeQuest Timing Analyzer Summary ; |
+-----------------------+-----------------------------------------------------+ |
; Quartus Prime Version ; Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition ; |
; Timing Analyzer ; TimeQuest ; |
; Revision Name ; spw_fifo_ulight ; |
; Device Family ; Cyclone V ; |
; Device Name ; 5CSEMA4U23C6 ; |
; Timing Models ; Final ; |
; Delay Model ; Combined ; |
; Rise/Fall Delays ; Enabled ; |
+-----------------------+-----------------------------------------------------+ |
+--------------------------------------------------------------------------------------+ |
; TimeQuest Timing Analyzer Summary ; |
+-----------------------+--------------------------------------------------------------+ |
; Quartus Prime Version ; Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ; |
; Timing Analyzer ; TimeQuest ; |
; Revision Name ; spw_fifo_ulight ; |
; Device Family ; Cyclone V ; |
; Device Name ; 5CSEMA4U23C6 ; |
; Timing Models ; Final ; |
; Delay Model ; Combined ; |
; Rise/Fall Delays ; Enabled ; |
+-----------------------+--------------------------------------------------------------+ |
|
|
+------------------------------------------+ |
103,12 → 102,12
; Number detected on machine ; 4 ; |
; Maximum allowed ; 2 ; |
; ; ; |
; Average used ; 1.48 ; |
; Average used ; 1.17 ; |
; Maximum used ; 2 ; |
; ; ; |
; Usage by Processor ; % Time Used ; |
; Processor 1 ; 100.0% ; |
; Processor 2 ; 47.8% ; |
; Processor 2 ; 17.2% ; |
+----------------------------+-------------+ |
|
|
117,33 → 116,38
+--------------------------------------------------------------+--------+--------------------------+ |
; SDC File Path ; Status ; Read at ; |
+--------------------------------------------------------------+--------+--------------------------+ |
; sdc/spw_fifo_ulight.out.sdc ; OK ; Fri Sep 15 08:18:31 2017 ; |
; ulight_fifo/synthesis/submodules/altera_reset_controller.sdc ; OK ; Fri Sep 15 08:18:31 2017 ; |
; sdc/spw_fifo_ulight.out.sdc ; OK ; Mon Feb 5 00:57:55 2018 ; |
; ulight_fifo/synthesis/submodules/altera_reset_controller.sdc ; OK ; Mon Feb 5 00:57:55 2018 ; |
+--------------------------------------------------------------+--------+--------------------------+ |
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Clocks ; |
+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+ |
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; |
+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i } ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i } ; |
; din_a ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { din_a } ; |
; FPGA_CLK1_50 ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK1_50 } ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; Base ; 3.000 ; 333.33 MHz ; 0.000 ; 1.500 ; ; ; ; ; ; ; ; ; ; ; { spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e } ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0] ; { u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk } ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 2 ; 8 ; ; ; ; ; false ; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin ; { u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] } ; |
+----------------------------------------------------------------------------+-----------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------------+ |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Clocks ; |
+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+ |
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; |
+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; 10.000 ; 100.0 MHz ; 0.000 ; 5.000 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i } ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; ; ; ; ; ; ; ; ; ; ; { clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i } ; |
; din_a ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { din_a } ; |
; FPGA_CLK1_50 ; Base ; 20.000 ; 50.0 MHz ; 0.000 ; 10.000 ; ; ; ; ; ; ; ; ; ; ; { FPGA_CLK1_50 } ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; Base ; 4.000 ; 250.0 MHz ; 0.000 ; 2.000 ; ; ; ; ; ; ; ; ; ; ; { spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e } ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 1 ; 1 ; ; ; ; ; false ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|vco0ph[0] ; { u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk } ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; 2.500 ; 400.0 MHz ; 0.000 ; 1.250 ; 50.00 ; 2 ; 16 ; ; ; ; ; false ; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|refclkin ; { u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] } ; |
+--------------------------------------------------------------------------------------------+-----------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------------------------------+ |
|
|
+----------------------------------------------------+ |
; Slow 1100mV 85C Model Fmax Summary ; |
+------------+-----------------+--------------+------+ |
; Fmax ; Restricted Fmax ; Clock Name ; Note ; |
+------------+-----------------+--------------+------+ |
; 113.58 MHz ; 113.58 MHz ; FPGA_CLK1_50 ; ; |
+------------+-----------------+--------------+------+ |
+----------------------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 85C Model Fmax Summary ; |
+------------+-----------------+--------------------------------------------------------------------------------------------+------+ |
; Fmax ; Restricted Fmax ; Clock Name ; Note ; |
+------------+-----------------+--------------------------------------------------------------------------------------------+------+ |
; 82.1 MHz ; 82.1 MHz ; FPGA_CLK1_50 ; ; |
; 123.85 MHz ; 123.85 MHz ; din_a ; ; |
; 127.19 MHz ; 127.19 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; ; |
; 145.58 MHz ; 145.58 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; ; |
; 159.54 MHz ; 159.54 MHz ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; ; |
; 201.09 MHz ; 201.09 MHz ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; ; |
+------------+-----------------+--------------------------------------------------------------------------------------------+------+ |
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. |
|
|
153,55 → 157,69
HTML report is unavailable in plain text report export. |
|
|
+--------------------------------------+ |
; Slow 1100mV 85C Model Setup Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 1.196 ; 0.000 ; |
+--------------+-------+---------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 85C Model Setup Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -4.369 ; -113.702 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -3.697 ; -1112.931 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -3.138 ; -13.527 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -2.473 ; -27.460 ; |
; din_a ; -2.037 ; -45.867 ; |
; FPGA_CLK1_50 ; -1.110 ; -2.017 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+--------------------------------------+ |
; Slow 1100mV 85C Model Hold Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.271 ; 0.000 ; |
+--------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 85C Model Hold Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.322 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.336 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.393 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.470 ; 0.000 ; |
; din_a ; 0.547 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.624 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+----------------------------------------+ |
; Slow 1100mV 85C Model Recovery Summary ; |
+--------------+-------+-----------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+-----------------+ |
; FPGA_CLK1_50 ; 4.785 ; 0.000 ; |
+--------------+-------+-----------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 85C Model Recovery Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -0.289 ; -4.795 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 5.248 ; 0.000 ; |
; FPGA_CLK1_50 ; 14.466 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+---------------------------------------+ |
; Slow 1100mV 85C Model Removal Summary ; |
+--------------+-------+----------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+----------------+ |
; FPGA_CLK1_50 ; 0.979 ; 0.000 ; |
+--------------+-------+----------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 85C Model Removal Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.563 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.308 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.746 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+----------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 85C Model Minimum Pulse Width Summary ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.538 ; 0.000 ; |
; din_a ; 0.597 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.657 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.679 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.084 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; FPGA_CLK1_50 ; 4.202 ; 0.000 ; |
+----------------------------------------------------------------------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 85C Model Minimum Pulse Width Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.533 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.575 ; 0.000 ; |
; din_a ; 0.994 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.301 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 3.952 ; 0.000 ; |
; FPGA_CLK1_50 ; 9.195 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
----------------------------------------------- |
208,73 → 226,92
; Slow 1100mV 85C Model Metastability Summary ; |
----------------------------------------------- |
The design MTBF is not calculated because there are no specified synchronizers in the design. |
Number of Synchronizer Chains Found: 59 |
Number of Synchronizer Chains Found: 49 |
Shortest Synchronizer Chain: 2 Registers |
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Worst Case Available Settling Time: 12.106 ns |
Worst Case Available Settling Time: 12.091 ns |
|
|
|
|
+----------------------------------------------------+ |
; Slow 1100mV 0C Model Fmax Summary ; |
+------------+-----------------+--------------+------+ |
; Fmax ; Restricted Fmax ; Clock Name ; Note ; |
+------------+-----------------+--------------+------+ |
; 113.69 MHz ; 113.69 MHz ; FPGA_CLK1_50 ; ; |
+------------+-----------------+--------------+------+ |
+----------------------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 0C Model Fmax Summary ; |
+------------+-----------------+--------------------------------------------------------------------------------------------+------+ |
; Fmax ; Restricted Fmax ; Clock Name ; Note ; |
+------------+-----------------+--------------------------------------------------------------------------------------------+------+ |
; 84.77 MHz ; 84.77 MHz ; FPGA_CLK1_50 ; ; |
; 127.58 MHz ; 127.58 MHz ; din_a ; ; |
; 130.77 MHz ; 130.77 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; ; |
; 149.1 MHz ; 149.1 MHz ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; ; |
; 159.18 MHz ; 159.18 MHz ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; ; |
; 205.8 MHz ; 205.8 MHz ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; ; |
+------------+-----------------+--------------------------------------------------------------------------------------------+------+ |
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. |
|
|
+--------------------------------------+ |
; Slow 1100mV 0C Model Setup Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 1.204 ; 0.000 ; |
+--------------+-------+---------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 0C Model Setup Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -4.207 ; -109.829 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -3.461 ; -1038.103 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -2.976 ; -12.650 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -2.359 ; -27.122 ; |
; din_a ; -1.919 ; -41.436 ; |
; FPGA_CLK1_50 ; -0.765 ; -1.140 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+--------------------------------------+ |
; Slow 1100mV 0C Model Hold Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.253 ; 0.000 ; |
+--------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 0C Model Hold Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.211 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.325 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.388 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.478 ; 0.000 ; |
; din_a ; 0.530 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.599 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+---------------------------------------+ |
; Slow 1100mV 0C Model Recovery Summary ; |
+--------------+-------+----------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+----------------+ |
; FPGA_CLK1_50 ; 4.852 ; 0.000 ; |
+--------------+-------+----------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 0C Model Recovery Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -0.346 ; -5.707 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 5.377 ; 0.000 ; |
; FPGA_CLK1_50 ; 14.772 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+--------------------------------------+ |
; Slow 1100mV 0C Model Removal Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.920 ; 0.000 ; |
+--------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 0C Model Removal Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.464 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.288 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.777 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+----------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 0C Model Minimum Pulse Width Summary ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.465 ; 0.000 ; |
; din_a ; 0.633 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.663 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.716 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.117 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; FPGA_CLK1_50 ; 4.284 ; 0.000 ; |
+----------------------------------------------------------------------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Slow 1100mV 0C Model Minimum Pulse Width Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.499 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.523 ; 0.000 ; |
; din_a ; 0.986 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.324 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 3.980 ; 0.000 ; |
; FPGA_CLK1_50 ; 9.277 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
---------------------------------------------- |
281,63 → 318,77
; Slow 1100mV 0C Model Metastability Summary ; |
---------------------------------------------- |
The design MTBF is not calculated because there are no specified synchronizers in the design. |
Number of Synchronizer Chains Found: 59 |
Number of Synchronizer Chains Found: 49 |
Shortest Synchronizer Chain: 2 Registers |
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Worst Case Available Settling Time: 12.241 ns |
Worst Case Available Settling Time: 12.233 ns |
|
|
|
|
+--------------------------------------+ |
; Fast 1100mV 85C Model Setup Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 4.542 ; 0.000 ; |
+--------------+-------+---------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 85C Model Setup Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -2.086 ; -3.029 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -1.935 ; -13.800 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -1.826 ; -329.386 ; |
; din_a ; -1.068 ; -12.429 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -0.558 ; -5.149 ; |
; FPGA_CLK1_50 ; -0.405 ; -0.405 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+--------------------------------------+ |
; Fast 1100mV 85C Model Hold Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.162 ; 0.000 ; |
+--------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 85C Model Hold Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.122 ; 0.000 ; |
; FPGA_CLK1_50 ; 0.175 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.179 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.217 ; 0.000 ; |
; din_a ; 0.242 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.302 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+----------------------------------------+ |
; Fast 1100mV 85C Model Recovery Summary ; |
+--------------+-------+-----------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+-----------------+ |
; FPGA_CLK1_50 ; 6.857 ; 0.000 ; |
+--------------+-------+-----------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 85C Model Recovery Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.648 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 6.842 ; 0.000 ; |
; FPGA_CLK1_50 ; 16.136 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+---------------------------------------+ |
; Fast 1100mV 85C Model Removal Summary ; |
+--------------+-------+----------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+----------------+ |
; FPGA_CLK1_50 ; 0.574 ; 0.000 ; |
+--------------+-------+----------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 85C Model Removal Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.424 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.665 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.750 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+----------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 85C Model Minimum Pulse Width Summary ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.799 ; 0.000 ; |
; din_a ; 0.812 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.897 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.920 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.333 ; 0.000 ; |
; FPGA_CLK1_50 ; 4.076 ; 0.000 ; |
+----------------------------------------------------------------------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 85C Model Minimum Pulse Width Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.732 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.833 ; 0.000 ; |
; din_a ; 1.215 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.480 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 4.240 ; 0.000 ; |
; FPGA_CLK1_50 ; 9.073 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
----------------------------------------------- |
344,63 → 395,77
; Fast 1100mV 85C Model Metastability Summary ; |
----------------------------------------------- |
The design MTBF is not calculated because there are no specified synchronizers in the design. |
Number of Synchronizer Chains Found: 59 |
Number of Synchronizer Chains Found: 49 |
Shortest Synchronizer Chain: 2 Registers |
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Worst Case Available Settling Time: 15.202 ns |
Worst Case Available Settling Time: 14.729 ns |
|
|
|
|
+--------------------------------------+ |
; Fast 1100mV 0C Model Setup Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 5.038 ; 0.000 ; |
+--------------+-------+---------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 0C Model Setup Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -1.794 ; -2.071 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -1.717 ; -6.939 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -1.507 ; -230.983 ; |
; din_a ; -0.704 ; -5.641 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -0.395 ; -3.443 ; |
; FPGA_CLK1_50 ; -0.113 ; -0.113 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+--------------------------------------+ |
; Fast 1100mV 0C Model Hold Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.146 ; 0.000 ; |
+--------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 0C Model Hold Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.104 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.164 ; 0.000 ; |
; FPGA_CLK1_50 ; 0.166 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.199 ; 0.000 ; |
; din_a ; 0.208 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.263 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+---------------------------------------+ |
; Fast 1100mV 0C Model Recovery Summary ; |
+--------------+-------+----------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+----------------+ |
; FPGA_CLK1_50 ; 7.031 ; 0.000 ; |
+--------------+-------+----------------+ |
+---------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 0C Model Recovery Summary ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.654 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 7.148 ; 0.000 ; |
; FPGA_CLK1_50 ; 16.628 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+--------+---------------+ |
|
|
+--------------------------------------+ |
; Fast 1100mV 0C Model Removal Summary ; |
+--------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.524 ; 0.000 ; |
+--------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 0C Model Removal Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; FPGA_CLK1_50 ; 0.327 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 0.616 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 0.684 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
+----------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 0C Model Minimum Pulse Width Summary ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+----------------------------------------------------------------------------+-------+---------------+ |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.793 ; 0.000 ; |
; din_a ; 0.828 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; 0.961 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.969 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1.399 ; 0.000 ; |
; FPGA_CLK1_50 ; 4.039 ; 0.000 ; |
+----------------------------------------------------------------------------+-------+---------------+ |
+--------------------------------------------------------------------------------------------------------------------+ |
; Fast 1100mV 0C Model Minimum Pulse Width Summary ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; Clock ; Slack ; End Point TNS ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0.757 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 0.823 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; 1.250 ; 0.000 ; |
; din_a ; 1.293 ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1.525 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 4.335 ; 0.000 ; |
; FPGA_CLK1_50 ; 9.039 ; 0.000 ; |
+--------------------------------------------------------------------------------------------+-------+---------------+ |
|
|
---------------------------------------------- |
407,36 → 472,36
; Fast 1100mV 0C Model Metastability Summary ; |
---------------------------------------------- |
The design MTBF is not calculated because there are no specified synchronizers in the design. |
Number of Synchronizer Chains Found: 59 |
Number of Synchronizer Chains Found: 49 |
Shortest Synchronizer Chain: 2 Registers |
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Worst Case Available Settling Time: 15.621 ns |
Worst Case Available Settling Time: 15.223 ns |
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------+ |
; Multicorner Timing Analysis Summary ; |
+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+ |
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; |
+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+ |
; Worst-case Slack ; 1.196 ; 0.146 ; 4.785 ; 0.524 ; 0.465 ; |
; FPGA_CLK1_50 ; 1.196 ; 0.146 ; 4.785 ; 0.524 ; 4.039 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; N/A ; N/A ; N/A ; N/A ; 1.084 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.657 ; |
; din_a ; N/A ; N/A ; N/A ; N/A ; 0.597 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; N/A ; N/A ; N/A ; N/A ; 0.679 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; N/A ; N/A ; N/A ; N/A ; 0.465 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.250 ; |
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; |
; FPGA_CLK1_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; N/A ; N/A ; N/A ; N/A ; 0.000 ; |
; din_a ; N/A ; N/A ; N/A ; N/A ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; N/A ; N/A ; N/A ; N/A ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; N/A ; N/A ; N/A ; N/A ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; |
+-----------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+ |
+------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Multicorner Timing Analysis Summary ; |
+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+ |
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; |
+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+ |
; Worst-case Slack ; -4.369 ; 0.104 ; -0.346 ; 0.327 ; 0.499 ; |
; FPGA_CLK1_50 ; -1.110 ; 0.166 ; 14.466 ; 0.327 ; 9.039 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -3.697 ; 0.164 ; 5.248 ; 0.616 ; 3.952 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -4.369 ; 0.104 ; N/A ; N/A ; 0.523 ; |
; din_a ; -2.037 ; 0.208 ; N/A ; N/A ; 0.986 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -3.138 ; 0.263 ; -0.346 ; 0.684 ; 1.301 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -2.473 ; 0.199 ; N/A ; N/A ; 0.499 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 1.250 ; |
; Design-wide TNS ; -1315.504 ; 0.0 ; -5.707 ; 0.0 ; 0.0 ; |
; FPGA_CLK1_50 ; -2.017 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; -1112.931 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; -113.702 ; 0.000 ; N/A ; N/A ; 0.000 ; |
; din_a ; -45.867 ; 0.000 ; N/A ; N/A ; 0.000 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; -13.527 ; 0.000 ; -5.707 ; 0.000 ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; -27.460 ; 0.000 ; N/A ; N/A ; 0.000 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; N/A ; N/A ; N/A ; N/A ; 0.000 ; |
+---------------------------------------------------------------------------------------------+-----------+-------+----------+---------+---------------------+ |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
444,10 → 509,10
+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ |
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; |
+-----------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ |
; LED[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
; LED[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
; dout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; |
; sout_a ; LVDS ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; 100 Ohm ; n/a ; n/a ; n/a ; |
; LED[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
; LED[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
; LED[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
; LED[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
; LED[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; |
479,10 → 544,10
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; |
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; |
; dout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; |
; sout_a ; LVDS ; 0 s ; 0 s ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; 0.377 V ; -0.377 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.36e-10 s ; Yes ; Yes ; |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.257 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; |
; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; |
; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; 3.08 V ; 3.35e-07 V ; 3.14 V ; -0.258 V ; 0.13 V ; 0.399 V ; 4.27e-10 s ; 1.5e-10 s ; Yes ; No ; |
; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; |
499,10 → 564,10
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; |
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; |
; dout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; |
; sout_a ; LVDS ; 0 s ; 0 s ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.343 V ; -0.343 V ; - ; - ; - ; - ; 1.4e-10 s ; 1.44e-10 s ; Yes ; Yes ; |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.136 V ; 0.025 V ; 0.167 V ; 4.92e-10 s ; 3.12e-10 s ; Yes ; No ; |
; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; |
; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; 3.08 V ; 3.19e-05 V ; 3.1 V ; -0.133 V ; 0.025 V ; 0.169 V ; 4.92e-10 s ; 3.13e-10 s ; Yes ; No ; |
; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; |
519,10 → 584,10
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; |
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; |
; dout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; |
; sout_a ; LVDS ; 0 s ; 0 s ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; 0.534 V ; -0.534 V ; - ; - ; - ; - ; 1.33e-10 s ; 1.37e-10 s ; Yes ; Yes ; |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.621 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; |
; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; |
; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; 3.63 V ; 4.72e-06 V ; 3.7 V ; -0.49 V ; 0.117 V ; 0.622 V ; 3.84e-10 s ; 1.48e-10 s ; Yes ; No ; |
; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; |
539,10 → 604,10
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; |
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; |
; dout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; |
; sout_a ; LVDS ; 0 s ; 0 s ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; 0.488 V ; -0.488 V ; - ; - ; - ; - ; 1.41e-10 s ; 1.44e-10 s ; Yes ; Yes ; |
; LED[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; |
; LED[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.319 V ; 0.041 V ; 0.528 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; |
; LED[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; |
; LED[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; 3.63 V ; 0.000229 V ; 3.65 V ; -0.316 V ; 0.041 V ; 0.53 V ; 4.29e-10 s ; 1.87e-10 s ; Yes ; No ; |
; LED[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; |
554,91 → 619,89
+-----------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Setup Transfers ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; false path ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0 ; false path ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; false path ; 0 ; 0 ; |
; din_a ; din_a ; false path ; false path ; false path ; false path ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; din_a ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 198264 ; 0 ; 0 ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ; |
; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; false path ; false path ; false path ; |
; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+ |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Setup Transfers ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 10902 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 15 ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 598 ; 18 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 165 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1991 ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1 ; 1 ; 0 ; 0 ; |
; din_a ; din_a ; 275 ; 167 ; 12 ; 61 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 30 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; 1 ; 0 ; 0 ; 0 ; |
; din_a ; FPGA_CLK1_50 ; 8 ; 1 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 221232 ; 0 ; 0 ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; FPGA_CLK1_50 ; 3 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1 ; 0 ; 0 ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 34 ; 15 ; 4 ; 90 ; |
; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 60 ; 0 ; 0 ; 0 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 1600 ; 0 ; 0 ; 0 ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+ |
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Hold Transfers ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; false path ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 0 ; false path ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; false path ; 0 ; 0 ; |
; din_a ; din_a ; false path ; false path ; false path ; false path ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; din_a ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 198264 ; 0 ; 0 ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; FPGA_CLK1_50 ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ; |
; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; false path ; false path ; false path ; |
; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; false path ; 0 ; 0 ; 0 ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+------------+------------+------------+------------+ |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Hold Transfers ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 10902 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 15 ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 598 ; 18 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 165 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1991 ; 0 ; 0 ; 0 ; |
; din_a ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; false path ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 1 ; 1 ; 0 ; 0 ; |
; din_a ; din_a ; 275 ; 167 ; 12 ; 61 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; FPGA_CLK1_50 ; 30 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; FPGA_CLK1_50 ; 1 ; 0 ; 0 ; 0 ; |
; din_a ; FPGA_CLK1_50 ; 8 ; 1 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 221232 ; 0 ; 0 ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; FPGA_CLK1_50 ; 3 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 1 ; 0 ; 0 ; 0 ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 34 ; 15 ; 4 ; 90 ; |
; FPGA_CLK1_50 ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 60 ; 0 ; 0 ; 0 ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; 1600 ; 0 ; 0 ; 0 ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+------------+----------+ |
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Recovery Transfers ; |
+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 100 ; 0 ; 69 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3102 ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ; |
+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+ |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Recovery Transfers ; |
+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1258 ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 7 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 58 ; 0 ; 17 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3051 ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 20 ; 0 ; 18 ; 0 ; |
+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+ |
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Removal Transfers ; |
+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 100 ; 0 ; 69 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3102 ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; false path ; 0 ; false path ; 0 ; |
+---------------------------------------------------------------+----------------------------------------------------------------------------+------------+----------+------------+----------+ |
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Removal Transfers ; |
+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+ |
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; |
+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+ |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; 1258 ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; false path ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; 7 ; 0 ; 0 ; 0 ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; din_a ; 58 ; 0 ; 17 ; 0 ; |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; 3051 ; 0 ; 0 ; 0 ; |
; FPGA_CLK1_50 ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; 20 ; 0 ; 18 ; 0 ; |
+---------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+----------+----------+ |
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. |
|
|
662,25 → 725,25
; Illegal Clocks ; 0 ; 0 ; |
; Unconstrained Clocks ; 0 ; 0 ; |
; Unconstrained Input Ports ; 2 ; 2 ; |
; Unconstrained Input Port Paths ; 36 ; 36 ; |
; Unconstrained Input Port Paths ; 34 ; 34 ; |
; Unconstrained Output Ports ; 10 ; 10 ; |
; Unconstrained Output Port Paths ; 10 ; 10 ; |
+---------------------------------+-------+------+ |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Clock Status Summary ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+ |
; Target ; Clock ; Type ; Status ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+ |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; Base ; Constrained ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; Constrained ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; Constrained ; |
; din_a ; din_a ; Base ; Constrained ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e ; Base ; Constrained ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; Constrained ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; Constrained ; |
+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------+-------------+ |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |
; Clock Status Summary ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+ |
; Target ; Clock ; Type ; Status ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+ |
; FPGA_CLK1_50 ; FPGA_CLK1_50 ; Base ; Constrained ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i ; Base ; Constrained ; |
; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i ; Base ; Constrained ; |
; din_a ; din_a ; Base ; Constrained ; |
; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e ; Base ; Constrained ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk ; Generated ; Constrained ; |
; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] ; Generated ; Constrained ; |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-----------+-------------+ |
|
|
+---------------------------------------------------------------------------------------------------+ |
744,21 → 807,19
+------------------------------------+ |
Info: ******************************************************************* |
Info: Running Quartus Prime TimeQuest Timing Analyzer |
Info: Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition |
Info: Processing started: Fri Sep 15 08:18:16 2017 |
Info: Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition |
Info: Processing started: Mon Feb 5 00:57:45 2018 |
Info: Command: quartus_sta spw_fifo_ulight -c spw_fifo_ulight |
Info: qsta_default_script.tcl version: #1 |
Info: qsta_default_script.tcl version: #3 |
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. |
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected |
Info (21077): Low junction temperature is 0 degrees C |
Info (21077): High junction temperature is 85 degrees C |
Info (334003): Started post-fitting delay annotation |
Info (334004): Delay annotation completed successfully |
Info (332104): Reading SDC File: 'sdc/spw_fifo_ulight.out.sdc' |
Info (332104): Reading SDC File: 'ulight_fifo/synthesis/submodules/altera_reset_controller.sdc' |
Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. |
Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: combout |
Info (332098): Cell: m_x|always3~0 from: dataf to: combout |
Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: combout |
Info (332098): Cell: m_x|comb from: dataa to: combout |
Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457 |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout |
766,177 → 827,239
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command |
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON |
Info: Analyzing Slow 1100mV 85C Model |
Info (332146): Worst-case setup slack is 1.196 |
Critical Warning (332148): Timing requirements not met |
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. |
Info (332146): Worst-case setup slack is -4.369 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 1.196 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.271 |
Info (332119): -4.369 -113.702 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): -3.697 -1112.931 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): -3.138 -13.527 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): -2.473 -27.460 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): -2.037 -45.867 din_a |
Info (332119): -1.110 -2.017 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.322 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.271 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case recovery slack is 4.785 |
Info (332119): 0.322 0.000 FPGA_CLK1_50 |
Info (332119): 0.336 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.393 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.470 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.547 0.000 din_a |
Info (332119): 0.624 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case recovery slack is -0.289 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 4.785 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.979 |
Info (332119): -0.289 -4.795 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 5.248 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 14.466 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.563 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.979 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case minimum pulse width slack is 0.538 |
Info (332119): 0.563 0.000 FPGA_CLK1_50 |
Info (332119): 1.308 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 1.746 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case minimum pulse width slack is 0.533 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.538 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.597 0.000 din_a |
Info (332119): 0.657 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.679 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e |
Info (332119): 1.084 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.533 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.575 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.994 0.000 din_a |
Info (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] |
Info (332119): 4.202 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 59 synchronizer chains. |
Info (332119): 1.301 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 3.952 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 9.195 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 49 synchronizer chains. |
Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. |
Info (332114): Number of Synchronizer Chains Found: 59 |
Info (332114): Number of Synchronizer Chains Found: 49 |
Info (332114): Shortest Synchronizer Chain: 2 Registers |
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Info (332114): Worst Case Available Settling Time: 12.106 ns |
Info (332114): Worst Case Available Settling Time: 12.091 ns |
Info (332114): |
Info: Analyzing Slow 1100mV 0C Model |
Info (334003): Started post-fitting delay annotation |
Info (334004): Delay annotation completed successfully |
Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. |
Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: combout |
Info (332098): Cell: m_x|always3~0 from: dataf to: combout |
Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: combout |
Info (332098): Cell: m_x|comb from: dataa to: combout |
Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457 |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk |
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command |
Info (332146): Worst-case setup slack is 1.204 |
Critical Warning (332148): Timing requirements not met |
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. |
Info (332146): Worst-case setup slack is -4.207 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 1.204 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.253 |
Info (332119): -4.207 -109.829 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): -3.461 -1038.103 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): -2.976 -12.650 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): -2.359 -27.122 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): -1.919 -41.436 din_a |
Info (332119): -0.765 -1.140 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.211 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.253 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case recovery slack is 4.852 |
Info (332119): 0.211 0.000 FPGA_CLK1_50 |
Info (332119): 0.325 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.388 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.478 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.530 0.000 din_a |
Info (332119): 0.599 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case recovery slack is -0.346 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 4.852 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.920 |
Info (332119): -0.346 -5.707 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 5.377 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 14.772 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.464 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.920 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case minimum pulse width slack is 0.465 |
Info (332119): 0.464 0.000 FPGA_CLK1_50 |
Info (332119): 1.288 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 1.777 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case minimum pulse width slack is 0.499 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.465 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.633 0.000 din_a |
Info (332119): 0.663 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.716 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e |
Info (332119): 1.117 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.499 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.523 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.986 0.000 din_a |
Info (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] |
Info (332119): 4.284 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 59 synchronizer chains. |
Info (332119): 1.324 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 3.980 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 9.277 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 49 synchronizer chains. |
Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. |
Info (332114): Number of Synchronizer Chains Found: 59 |
Info (332114): Number of Synchronizer Chains Found: 49 |
Info (332114): Shortest Synchronizer Chain: 2 Registers |
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Info (332114): Worst Case Available Settling Time: 12.241 ns |
Info (332114): Worst Case Available Settling Time: 12.233 ns |
Info (332114): |
Info: Analyzing Fast 1100mV 85C Model |
Info (334003): Started post-fitting delay annotation |
Info (334004): Delay annotation completed successfully |
Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. |
Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: combout |
Info (332098): Cell: m_x|always3~0 from: dataf to: combout |
Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: combout |
Info (332098): Cell: m_x|comb from: dataa to: combout |
Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457 |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk |
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command |
Info (332146): Worst-case setup slack is 4.542 |
Critical Warning (332148): Timing requirements not met |
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. |
Info (332146): Worst-case setup slack is -2.086 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 4.542 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.162 |
Info (332119): -2.086 -3.029 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): -1.935 -13.800 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): -1.826 -329.386 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): -1.068 -12.429 din_a |
Info (332119): -0.558 -5.149 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): -0.405 -0.405 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.122 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.162 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case recovery slack is 6.857 |
Info (332119): 0.122 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.175 0.000 FPGA_CLK1_50 |
Info (332119): 0.179 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.217 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.242 0.000 din_a |
Info (332119): 0.302 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case recovery slack is 0.648 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 6.857 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.574 |
Info (332119): 0.648 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 6.842 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 16.136 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.424 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.574 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case minimum pulse width slack is 0.799 |
Info (332119): 0.424 0.000 FPGA_CLK1_50 |
Info (332119): 0.665 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.750 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case minimum pulse width slack is 0.732 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.799 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.812 0.000 din_a |
Info (332119): 0.897 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e |
Info (332119): 0.920 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.732 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.833 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 1.215 0.000 din_a |
Info (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] |
Info (332119): 1.333 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 4.076 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 59 synchronizer chains. |
Info (332119): 1.480 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 4.240 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 9.073 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 49 synchronizer chains. |
Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. |
Info (332114): Number of Synchronizer Chains Found: 59 |
Info (332114): Number of Synchronizer Chains Found: 49 |
Info (332114): Shortest Synchronizer Chain: 2 Registers |
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Info (332114): Worst Case Available Settling Time: 15.202 ns |
Info (332114): Worst Case Available Settling Time: 14.729 ns |
Info (332114): |
Info: Analyzing Fast 1100mV 0C Model |
Info (334003): Started post-fitting delay annotation |
Info (334004): Delay annotation completed successfully |
Info (332097): The following timing edges are non-unate. TimeQuest will assume pos-unate behavior for these edges in the clock network. |
Info (332098): Cell: A_SPW_TOP|SPW|RX|always3~0 from: dataf to: combout |
Info (332098): Cell: m_x|always3~0 from: dataf to: combout |
Info (332098): Cell: A_SPW_TOP|SPW|RX|comb from: dataf to: combout |
Info (332098): Cell: m_x|comb from: dataa to: combout |
Info (332098): From: u0|hps_0|fpga_interfaces|hps2fpga|clk to: ulight_fifo:u0|ulight_fifo_hps_0:hps_0|ulight_fifo_hps_0_fpga_interfaces:fpga_interfaces|hps2fpga~FF_3457 |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter from: vco0ph[0] to: divclk |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|REFCLK_SELECT from: clkin[0] to: clkout |
Info (332098): Cell: u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll from: refclkin to: fbclk |
Info (332152): The following assignments are ignored by the derive_clock_uncertainty command |
Info (332146): Worst-case setup slack is 5.038 |
Critical Warning (332148): Timing requirements not met |
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer. |
Info (332146): Worst-case setup slack is -1.794 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 5.038 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.146 |
Info (332119): -1.794 -2.071 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): -1.717 -6.939 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): -1.507 -230.983 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): -0.704 -5.641 din_a |
Info (332119): -0.395 -3.443 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): -0.113 -0.113 FPGA_CLK1_50 |
Info (332146): Worst-case hold slack is 0.104 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.146 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case recovery slack is 7.031 |
Info (332119): 0.104 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.164 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.166 0.000 FPGA_CLK1_50 |
Info (332119): 0.199 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.208 0.000 din_a |
Info (332119): 0.263 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case recovery slack is 0.654 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 7.031 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.524 |
Info (332119): 0.654 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 7.148 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 16.628 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case removal slack is 0.327 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.524 0.000 FPGA_CLK1_50 |
Info (332146): Worst-case minimum pulse width slack is 0.793 |
Info (332119): 0.327 0.000 FPGA_CLK1_50 |
Info (332119): 0.616 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 0.684 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332146): Worst-case minimum pulse width slack is 0.757 |
Info (332119): Slack End Point TNS Clock |
Info (332119): ========= =================== ===================== |
Info (332119): 0.793 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 0.828 0.000 din_a |
Info (332119): 0.961 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e |
Info (332119): 0.969 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.757 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i |
Info (332119): 0.823 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk |
Info (332119): 1.250 0.000 u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0] |
Info (332119): 1.399 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 4.039 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 59 synchronizer chains. |
Info (332119): 1.293 0.000 din_a |
Info (332119): 1.525 0.000 spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e |
Info (332119): 4.335 0.000 clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i |
Info (332119): 9.039 0.000 FPGA_CLK1_50 |
Info (332114): Report Metastability: Found 49 synchronizer chains. |
Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design. |
Info (332114): Number of Synchronizer Chains Found: 59 |
Info (332114): Number of Synchronizer Chains Found: 49 |
Info (332114): Shortest Synchronizer Chain: 2 Registers |
Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 |
Info (332114): Worst Case Available Settling Time: 15.621 ns |
Info (332114): Worst Case Available Settling Time: 15.223 ns |
Info (332114): |
Info (332102): Design is not fully constrained for setup requirements |
Info (332102): Design is not fully constrained for hold requirements |
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 1 warning |
Info: Peak virtual memory: 1351 megabytes |
Info: Processing ended: Fri Sep 15 08:19:10 2017 |
Info: Elapsed time: 00:00:54 |
Info: Total CPU time (on all processors): 00:01:15 |
Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings |
Info: Peak virtual memory: 1444 megabytes |
Info: Processing ended: Mon Feb 5 00:59:04 2018 |
Info: Elapsed time: 00:01:19 |
Info: Total CPU time (on all processors): 00:01:24 |
|
|
/spw_fifo_ulight.sta.summary
2,40 → 2,88
TimeQuest Timing Analyzer Summary |
------------------------------------------------------------ |
|
Type : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : -4.369 |
TNS : -113.702 |
|
Type : Slow 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : -3.697 |
TNS : -1112.931 |
|
Type : Slow 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : -3.138 |
TNS : -13.527 |
|
Type : Slow 1100mV 85C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : -2.473 |
TNS : -27.460 |
|
Type : Slow 1100mV 85C Model Setup 'din_a' |
Slack : -2.037 |
TNS : -45.867 |
|
Type : Slow 1100mV 85C Model Setup 'FPGA_CLK1_50' |
Slack : 1.196 |
TNS : 0.000 |
Slack : -1.110 |
TNS : -2.017 |
|
Type : Slow 1100mV 85C Model Hold 'FPGA_CLK1_50' |
Slack : 0.271 |
Slack : 0.322 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.336 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.393 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 0.470 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Hold 'din_a' |
Slack : 0.547 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.624 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : -0.289 |
TNS : -4.795 |
|
Type : Slow 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 5.248 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Recovery 'FPGA_CLK1_50' |
Slack : 4.785 |
Slack : 14.466 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Removal 'FPGA_CLK1_50' |
Slack : 0.979 |
Slack : 0.563 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.538 |
Type : Slow 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 1.308 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'din_a' |
Slack : 0.597 |
Type : Slow 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 1.746 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.657 |
Slack : 0.533 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e' |
Slack : 0.679 |
Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.575 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 1.084 |
Type : Slow 1100mV 85C Model Minimum Pulse Width 'din_a' |
Slack : 0.994 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]' |
42,44 → 90,100
Slack : 1.250 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 1.301 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 3.952 |
TNS : 0.000 |
|
Type : Slow 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50' |
Slack : 4.202 |
Slack : 9.195 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : -4.207 |
TNS : -109.829 |
|
Type : Slow 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : -3.461 |
TNS : -1038.103 |
|
Type : Slow 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : -2.976 |
TNS : -12.650 |
|
Type : Slow 1100mV 0C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : -2.359 |
TNS : -27.122 |
|
Type : Slow 1100mV 0C Model Setup 'din_a' |
Slack : -1.919 |
TNS : -41.436 |
|
Type : Slow 1100mV 0C Model Setup 'FPGA_CLK1_50' |
Slack : 1.204 |
TNS : 0.000 |
Slack : -0.765 |
TNS : -1.140 |
|
Type : Slow 1100mV 0C Model Hold 'FPGA_CLK1_50' |
Slack : 0.253 |
Slack : 0.211 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.325 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.388 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 0.478 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Hold 'din_a' |
Slack : 0.530 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.599 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : -0.346 |
TNS : -5.707 |
|
Type : Slow 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 5.377 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Recovery 'FPGA_CLK1_50' |
Slack : 4.852 |
Slack : 14.772 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Removal 'FPGA_CLK1_50' |
Slack : 0.920 |
Slack : 0.464 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.465 |
Type : Slow 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 1.288 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'din_a' |
Slack : 0.633 |
Type : Slow 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 1.777 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.663 |
Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.499 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e' |
Slack : 0.716 |
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.523 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 1.117 |
Type : Slow 1100mV 0C Model Minimum Pulse Width 'din_a' |
Slack : 0.986 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]' |
86,84 → 190,196
Slack : 1.250 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 1.324 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 3.980 |
TNS : 0.000 |
|
Type : Slow 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50' |
Slack : 4.284 |
Slack : 9.277 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : -2.086 |
TNS : -3.029 |
|
Type : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : -1.935 |
TNS : -13.800 |
|
Type : Fast 1100mV 85C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : -1.826 |
TNS : -329.386 |
|
Type : Fast 1100mV 85C Model Setup 'din_a' |
Slack : -1.068 |
TNS : -12.429 |
|
Type : Fast 1100mV 85C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : -0.558 |
TNS : -5.149 |
|
Type : Fast 1100mV 85C Model Setup 'FPGA_CLK1_50' |
Slack : 4.542 |
Slack : -0.405 |
TNS : -0.405 |
|
Type : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.122 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Hold 'FPGA_CLK1_50' |
Slack : 0.162 |
Slack : 0.175 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 0.179 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.217 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Hold 'din_a' |
Slack : 0.242 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.302 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.648 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 6.842 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Recovery 'FPGA_CLK1_50' |
Slack : 6.857 |
Slack : 16.136 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Removal 'FPGA_CLK1_50' |
Slack : 0.574 |
Slack : 0.424 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.799 |
Type : Fast 1100mV 85C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 0.665 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'din_a' |
Slack : 0.812 |
Type : Fast 1100mV 85C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.750 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e' |
Slack : 0.897 |
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.732 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.920 |
Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.833 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'din_a' |
Slack : 1.215 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]' |
Slack : 1.250 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 1.480 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 1.333 |
Slack : 4.240 |
TNS : 0.000 |
|
Type : Fast 1100mV 85C Model Minimum Pulse Width 'FPGA_CLK1_50' |
Slack : 4.076 |
Slack : 9.073 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Setup 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : -1.794 |
TNS : -2.071 |
|
Type : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : -1.717 |
TNS : -6.939 |
|
Type : Fast 1100mV 0C Model Setup 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : -1.507 |
TNS : -230.983 |
|
Type : Fast 1100mV 0C Model Setup 'din_a' |
Slack : -0.704 |
TNS : -5.641 |
|
Type : Fast 1100mV 0C Model Setup 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : -0.395 |
TNS : -3.443 |
|
Type : Fast 1100mV 0C Model Setup 'FPGA_CLK1_50' |
Slack : 5.038 |
Slack : -0.113 |
TNS : -0.113 |
|
Type : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.104 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Hold 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 0.164 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Hold 'FPGA_CLK1_50' |
Slack : 0.146 |
Slack : 0.166 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Hold 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.199 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Hold 'din_a' |
Slack : 0.208 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Hold 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.263 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Recovery 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.654 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Recovery 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 7.148 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Recovery 'FPGA_CLK1_50' |
Slack : 7.031 |
Slack : 16.628 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Removal 'FPGA_CLK1_50' |
Slack : 0.524 |
Slack : 0.327 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.793 |
Type : Fast 1100mV 0C Model Removal 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 0.616 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'din_a' |
Slack : 0.828 |
Type : Fast 1100mV 0C Model Removal 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 0.684 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_dout_e' |
Slack : 0.961 |
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.757 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_reduced_i' |
Slack : 0.969 |
Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk' |
Slack : 0.823 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'u0|pll_0|altera_pll_i|cyclonev_pll|fpll_0|fpll|vcoph[0]' |
170,12 → 386,20
Slack : 1.250 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'din_a' |
Slack : 1.293 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'spw_ulight_con_top_x:A_SPW_TOP|top_spw_ultra_light:SPW|TX_SPW:TX|tx_fsm_m:tx_fsm|tx_dout_e' |
Slack : 1.525 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'clock_reduce:R_400_to_2_5_10_100_200_300MHZ|clk_100_reduced_i' |
Slack : 1.399 |
Slack : 4.335 |
TNS : 0.000 |
|
Type : Fast 1100mV 0C Model Minimum Pulse Width 'FPGA_CLK1_50' |
Slack : 4.039 |
Slack : 9.039 |
TNS : 0.000 |
|
------------------------------------------------------------ |