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trunk/doc/Design and Implementation of a Lightweight SPI Master IP for Low Cost FPGAs.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/lic/lgpl.txt =================================================================== --- trunk/lic/lgpl.txt (nonexistent) +++ trunk/lic/lgpl.txt (revision 2) @@ -0,0 +1,165 @@ +GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. 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Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. \ No newline at end of file Index: trunk/rtl/lw_spi_master.vhd =================================================================== --- trunk/rtl/lw_spi_master.vhd (nonexistent) +++ trunk/rtl/lw_spi_master.vhd (revision 2) @@ -0,0 +1,253 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity lw_spi_master is +generic ( + c_clkfreq : integer := 50_000_000; + c_sclkfreq : integer := 5_000_000; + c_cpol : std_logic := '0'; + c_cpha : std_logic := '0' +); +Port ( + clk_i : in STD_LOGIC; + en_i : in STD_LOGIC; + mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0); + miso_data_o : out STD_LOGIC_VECTOR (7 downto 0); + data_ready_o : out STD_LOGIC; + cs_o : out STD_LOGIC; + sclk_o : out STD_LOGIC; + mosi_o : out STD_LOGIC; + miso_i : in STD_LOGIC +); +end lw_spi_master; + +architecture Behavioral of lw_spi_master is + +signal write_reg : std_logic_vector (7 downto 0) := (others => '0'); +signal read_reg : std_logic_vector (7 downto 0) := (others => '0'); + +signal sclk_en : std_logic := '0'; +signal sclk : std_logic := '0'; +signal sclk_prev : std_logic := '0'; +signal sclk_rise : std_logic := '0'; +signal sclk_fall : std_logic := '0'; + +signal pol_phase : std_logic_vector (1 downto 0) := (others => '0'); +signal mosi_en : std_logic := '0'; +signal miso_en : std_logic := '0'; + +constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2); +signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0; + +signal cntr : integer range 0 to 15 := 0; + +type states is (S_IDLE, S_TRANSFER); +signal state : states := S_IDLE; + +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +begin + +pol_phase <= c_cpol & c_cpha; + +P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin + + case pol_phase is + + when "00" => + + mosi_en <= sclk_fall; + miso_en <= sclk_rise; + + when "01" => + + mosi_en <= sclk_rise; + miso_en <= sclk_fall; + + when "10" => + + mosi_en <= sclk_rise; + miso_en <= sclk_fall; + + when "11" => + + mosi_en <= sclk_fall; + miso_en <= sclk_rise; + + when others => + + end case; + +end process; + +P_RISEFALL_DETECT : process (sclk, sclk_prev) begin + + if (sclk = '1' and sclk_prev = '0') then + sclk_rise <= '1'; + else + sclk_rise <= '0'; + end if; + + if (sclk = '0' and sclk_prev = '1') then + sclk_fall <= '1'; + else + sclk_fall <= '0'; + end if; + +end process; + + +P_MAIN : process (clk_i) begin +if (rising_edge(clk_i)) then + + sclk_prev <= sclk; + + case state is + + when S_IDLE => + + cs_o <= '1'; + mosi_o <= '0'; + data_ready_o <= '0'; + sclk_en <= '0'; + cntr <= 0; + + if (c_cpol = '0') then + sclk_o <= '0'; + else + sclk_o <= '1'; + end if; + + if (en_i = '1') then + state <= S_TRANSFER; + sclk_en <= '1'; + write_reg <= mosi_data_i; + mosi_o <= mosi_data_i(7); + read_reg <= x"00"; + end if; + + when S_TRANSFER => + + cs_o <= '0'; + mosi_o <= write_reg(7); + + + if (c_cpha = '1') then + + if (cntr = 0) then + sclk_o <= sclk; + if (miso_en = '1') then + read_reg(0) <= miso_i; + read_reg(7 downto 1) <= read_reg(6 downto 0); + cntr <= cntr + 1; + end if; + elsif (cntr = 8) then + data_ready_o <= '1'; + miso_data_o <= read_reg; + if (mosi_en = '1') then + data_ready_o <= '0'; + if (en_i = '1') then + write_reg <= mosi_data_i; + mosi_o <= mosi_data_i(7); + sclk_o <= sclk; + cntr <= 0; + else + state <= S_IDLE; + cs_o <= '1'; + end if; + end if; + elsif (cntr = 9) then + if (miso_en = '1') then + state <= S_IDLE; + cs_o <= '1'; + end if; + else + sclk_o <= sclk; + if (miso_en = '1') then + read_reg(0) <= miso_i; + read_reg(7 downto 1) <= read_reg(6 downto 0); + cntr <= cntr + 1; + end if; + if (mosi_en = '1') then + mosi_o <= write_reg(7); + write_reg(7 downto 1) <= write_reg(6 downto 0); + end if; + end if; + + else -- c_cpha = '0' + + if (cntr = 0) then + sclk_o <= sclk; + if (miso_en = '1') then + read_reg(0) <= miso_i; + read_reg(7 downto 1) <= read_reg(6 downto 0); + cntr <= cntr + 1; + end if; + elsif (cntr = 8) then + + data_ready_o <= '1'; + miso_data_o <= read_reg; + sclk_o <= sclk; + if (mosi_en = '1') then + data_ready_o <= '0'; + if (en_i = '1') then + write_reg <= mosi_data_i; + mosi_o <= mosi_data_i(7); + cntr <= 0; + else + cntr <= cntr + 1; + end if; + if (miso_en = '1') then + state <= S_IDLE; + cs_o <= '1'; + end if; + end if; + elsif (cntr = 9) then + if (miso_en = '1') then + state <= S_IDLE; + cs_o <= '1'; + end if; + else + sclk_o <= sclk; + if (miso_en = '1') then + read_reg(0) <= miso_i; + read_reg(7 downto 1) <= read_reg(6 downto 0); + cntr <= cntr + 1; + end if; + if (mosi_en = '1') then + write_reg(7 downto 1) <= write_reg(6 downto 0); + end if; + end if; + + end if; + + end case; + +end if; +end process; + +P_SCLK_GEN : process (clk_i) begin +if (rising_edge(clk_i)) then + + if (sclk_en = '1') then + if edgecntr = c_edgecntrlimdiv2-1 then + sclk <= not sclk; + edgecntr <= 0; + else + edgecntr <= edgecntr + 1; + end if; + else + edgecntr <= 0; + if (c_cpol = '0') then + sclk <= '0'; + else + sclk <= '1'; + end if; + end if; + +end if; +end process; + +end Behavioral; \ No newline at end of file Index: trunk/sim/tb_lw_spi_master.vhd =================================================================== --- trunk/sim/tb_lw_spi_master.vhd (nonexistent) +++ trunk/sim/tb_lw_spi_master.vhd (revision 2) @@ -0,0 +1,233 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +ENTITY tb_lw_spi_master IS +END tb_lw_spi_master; + +ARCHITECTURE behavior OF tb_lw_spi_master IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT lw_spi_master + PORT( + clk_i : IN std_logic; + en_i : IN std_logic; + mosi_data_i : IN std_logic_vector(7 downto 0); + miso_data_o : OUT std_logic_vector(7 downto 0); + data_ready_o : OUT std_logic; + cs_o : OUT std_logic; + sclk_o : OUT std_logic; + mosi_o : OUT std_logic; + miso_i : IN std_logic + ); + END COMPONENT; + + + --Inputs + signal clk_i : std_logic := '0'; + signal en_i : std_logic := '0'; + signal mosi_data_i : std_logic_vector(7 downto 0) := (others => '0'); + signal miso_i : std_logic := '0'; + + --Outputs + signal miso_data_o : std_logic_vector(7 downto 0); + signal data_ready_o : std_logic; + signal cs_o : std_logic; + signal sclk_o : std_logic; + signal mosi_o : std_logic; + + -- Clock period definitions +-- Clock period definitions +constant clk_i_period : time := 20 ns; +constant sckPeriod : time := 200 ns; + +signal SPISIGNAL : std_logic_vector(7 downto 0) := (others => '0'); +signal spiWrite : std_logic := '0'; +signal spiWriteDone : std_logic := '0'; + +BEGIN + + + +-- Instantiate the Unit Under Test (UUT) +uut: lw_spi_master PORT MAP ( +clk_i => clk_i, +en_i => en_i, +mosi_data_i => mosi_data_i, +miso_data_o => miso_data_o, +data_ready_o => data_ready_o, +cs_o => cs_o, +sclk_o => sclk_o, +mosi_o => mosi_o, +miso_i => miso_i +); + +-- Clock process definitions +clk_i_process :process +begin + clk_i <= '0'; + wait for clk_i_period/2; + clk_i <= '1'; + wait for clk_i_period/2; +end process; + +SPIWRITE_P : process begin + + wait until rising_edge(spiWrite); + + -- for cpol = 1 cpha = 1 + -- for cpol = 0 cpha = 0 + + miso_i <= SPISIGNAL(7); + wait until falling_edge(sclk_o); + miso_i <= SPISIGNAL(6); + wait until falling_edge(sclk_o); + miso_i <= SPISIGNAL(5); + wait until falling_edge(sclk_o); + miso_i <= SPISIGNAL(4); + wait until falling_edge(sclk_o); + miso_i <= SPISIGNAL(3); + wait until falling_edge(sclk_o); + miso_i <= SPISIGNAL(2); + wait until falling_edge(sclk_o); + miso_i <= SPISIGNAL(1); + wait until falling_edge(sclk_o); + miso_i <= SPISIGNAL(0); + + -- for cpol = 0 cpha = 1 + -- for cpol = 1 cpha = 0 + + -- miso_i <= SPISIGNAL(7); + -- wait until rising_edge(sclk_o); + -- miso_i <= SPISIGNAL(6); + -- wait until rising_edge(sclk_o); + -- miso_i <= SPISIGNAL(5); + -- wait until rising_edge(sclk_o); + -- miso_i <= SPISIGNAL(4); + -- wait until rising_edge(sclk_o); + -- miso_i <= SPISIGNAL(3); + -- wait until rising_edge(sclk_o); + -- miso_i <= SPISIGNAL(2); + -- wait until rising_edge(sclk_o); + -- miso_i <= SPISIGNAL(1); + -- wait until rising_edge(sclk_o); + -- miso_i <= SPISIGNAL(0); + + spiWriteDone <= '1'; + wait for 1 ps; + spiWriteDone <= '0'; + +end process; + + +-- Stimulus process +stim_proc: process +begin + -- hold reset state for 100 ns. + wait for 100 ns; + + wait for clk_i_period*10; + + -- insert stimulus here + +---------------------------------------------------------------- +-- -- CPOL,CPHA = 00 + en_i <= '1'; + + -- write 0xA7, read 0xB2 + mosi_data_i <= x"A7"; + wait until falling_edge(cs_o); + SPISIGNAL <= x"B2"; + spiWrite <= '1'; + wait until rising_edge(spiWriteDone); + spiWrite <= '0'; + + -- write 0xB8, read 0xC3 + wait until rising_edge(data_ready_o); + mosi_data_i <= x"B8"; + wait until falling_edge(data_ready_o); + SPISIGNAL <= x"C3"; + spiWrite <= '1'; + wait until rising_edge(spiWriteDone); + spiWrite <= '0'; + en_i <= '0'; + +---------------------------------------------------------------- +-- -- CPOL,CPHA = 10 +-- en_i <= '1'; +-- +-- -- write 0xA7, read 0xB2 +-- mosi_data_i <= x"A7"; +-- wait until falling_edge(cs_o); +-- wait for 50 ns; +-- SPISIGNAL <= x"B2"; +-- spiWrite <= '1'; +-- wait until rising_edge(spiWriteDone); +-- spiWrite <= '0'; +-- +-- -- write 0xB8, read 0xC3 +-- wait until rising_edge(data_ready_o); +-- mosi_data_i <= x"B8"; +-- wait until falling_edge(data_ready_o); +-- SPISIGNAL <= x"C3"; +-- spiWrite <= '1'; +-- wait until rising_edge(spiWriteDone); +-- spiWrite <= '0'; +-- en_i <= '0'; + +---------------------------------------------------------------- + -- CPOL,CPHA = 01 +-- en_i <= '1'; +-- +-- -- write 0xA7, read 0xB2 +-- mosi_data_i <= x"A7"; +-- wait until falling_edge(cs_o); +-- wait until rising_edge(sclk_o); +-- SPISIGNAL <= x"B2"; +-- spiWrite <= '1'; +-- wait until rising_edge(spiWriteDone); +-- spiWrite <= '0'; +-- +-- -- write 0xB8, read 0xC3 +-- wait until rising_edge(data_ready_o); +-- mosi_data_i <= x"B8"; +-- wait until rising_edge(sclk_o); +-- SPISIGNAL <= x"C3"; +-- spiWrite <= '1'; +-- wait until rising_edge(spiWriteDone); +-- spiWrite <= '0'; +-- en_i <= '0'; + +---------------------------------------------------------------- +-- -- CPOL,CPHA = 11 +-- en_i <= '1'; +-- +-- -- write 0xA7, read 0xB2 +-- mosi_data_i <= x"A7"; +-- wait until falling_edge(cs_o); +-- wait until falling_edge(sclk_o); +-- SPISIGNAL <= x"B2"; +-- spiWrite <= '1'; +-- wait until rising_edge(spiWriteDone); +-- spiWrite <= '0'; +-- +-- -- write 0xB8, read 0xC3 +-- wait until rising_edge(data_ready_o); +-- mosi_data_i <= x"B8"; +-- wait until falling_edge(sclk_o); +-- SPISIGNAL <= x"C3"; +-- spiWrite <= '1'; +-- wait until rising_edge(spiWriteDone); +-- spiWrite <= '0'; +-- en_i <= '0'; + + + + wait for 1 us; + + assert false + report "SIM DONE" + severity failure; +end process; + +END;