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/trunk/Opencores/testbench/dac_tb.vhd
0,0 → 1,92
-----------------------------------------------------------------------------------------
-- Engineer: Armandas Jarušauskas (jarusauskas@gmail.com www.armandas.lt)
--
-- Create date: 2010-08-03
-- Design name: Testbench for LTC2624 Quad 12 Bit DAC Controller
-----------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity dac_tb is
end dac_tb;
 
architecture behaviour of dac_tb is
constant T: time := 20 ns;
signal clk, reset: std_logic;
 
signal mosi, sck, cs, ready: std_logic;
signal data, old_data: std_logic_vector(31 downto 0);
begin
 
-- clock generator
process
begin
clk <= '1';
wait for T / 2;
clk <= '0';
wait for T / 2;
end process;
 
-- initial reset
reset <= '1', '0' after T / 2;
 
testbench:
process
variable value: std_logic_vector(11 downto 0);
variable addr: std_logic_vector(3 downto 0);
variable command: std_logic_vector(3 downto 0);
begin
value := "010000000000";
addr := "0010";
command := "0011";
data <= "00000000" & command & addr & value & "0000";
old_data <= "00000000" & command & addr & value & "0000";
 
 
-- testing bit order in the 32-bit word
for i in 31 downto 0 loop
wait until rising_edge(sck);
 
assert mosi = data(i)
report "Bit mismatch! (Order)"
severity error;
end loop;
 
-- testing data latching
for i in 31 downto 0 loop
wait until rising_edge(sck);
 
if i = 24 then
data <= "10010101110101101010101110100110"; --(others => '1');
end if;
 
assert mosi = old_data(i)
report "Bit mismatch! (Latching)"
severity error;
end loop;
 
-- what's happening after that?
for i in 63 downto 0 loop
wait until rising_edge(sck);
end loop;
 
-- end of simulation
assert false
report "Simulation completed."
severity failure;
end process;
 
uut: entity work.dac_control
port map(
clk => clk,
rst => reset,
dac_mosi => mosi,
dac_sck => sck,
dac_cs => cs,
rdy => ready,
dac_data => data
);
 
end behaviour;
/trunk/Opencores/DAC_Control.vhd
0,0 → 1,76
-----------------------------------------------------------------------------------------
-- Engineer: Tomas Daujotas (mailsoc@gmail.com www.scrts.net)
--
-- Create Date: 2010-07-21
-- Design Name: Control of LTC2624 Quad 12 bit DAC on Spartan-3E Starter Kit (32bit mode)
-----------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity DAC_Control is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DAC_DATA : in STD_LOGIC_VECTOR(31 downto 0);
DAC_MOSI : out STD_LOGIC;
DAC_SCK : out STD_LOGIC;
DAC_CS : out STD_LOGIC;
RDY : out STD_LOGIC);
end DAC_Control;
 
architecture DAC_Control of DAC_Control is
 
type state_type is (idle,ready,send,dummy,check);
signal state : state_type;
signal DAC_SEND : std_logic_vector(31 downto 0);
 
begin
process(DAC_DATA)
begin
for i in 31 downto 0 loop
DAC_SEND(i) <= DAC_DATA(31 - i); -- The data must be MSB first
end loop;
end process;
process(CLK,RST)
variable index : integer range 0 to 32 := 0;
begin
if (RST = '1') then
index := 0;
elsif rising_edge(CLK) then
case state is
when idle =>
DAC_SCK <= '0';
DAC_CS <= '1';
index := 0;
DAC_MOSI <= '0';
RDY <= '1';
state <= ready;
when ready =>
RDY <= '0';
DAC_CS <= '0';
DAC_SCK <= '0';
DAC_MOSI <= DAC_SEND(index);
state <= dummy;
when dummy =>
state <= send;
when send =>
DAC_SCK <= '1';
state <= check;
index := index + 1;
when check =>
DAC_SCK <= '1';
if (index = 32) then
state <= idle;
else
state <= ready;
end if;
end case;
end if;
end process;
 
end DAC_Control;
 
/trunk/Opencores/DAC_TOP.vhd
0,0 → 1,87
-----------------------------------------------------------------------------------------
-- Engineer: Tomas Daujotas (mailsoc@gmail.com www.scrts.net)
--
-- Create Date: 2010-07-21
-- Design Name: Control of LTC2624 Quad 12 bit DAC on Spartan-3E Starter Kit (32bit mode)
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
 
entity DAC_TOP is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DAC_MOSI : out STD_LOGIC;
DAC_CLR : out STD_LOGIC;
DAC_SCK : out STD_LOGIC;
DAC_CS : out STD_LOGIC;
SPI_SS_B : out STD_LOGIC; -- Serial Flash
AMP_CS : out STD_LOGIC; -- Amplifier for ADC
AD_CONV : out STD_LOGIC; -- ADC Conversion start
SF_CE0 : out STD_LOGIC; -- StrataFlash
FPGA_INIT_B : out STD_LOGIC); -- Platform Flash
end DAC_TOP;
 
architecture DAC of DAC_TOP is
 
signal rdy,daccs,dacsck,dacmosi : std_logic;
signal command : std_logic_vector(3 downto 0);
signal address : std_logic_vector(3 downto 0);
signal dacdata : std_logic_vector(31 downto 0);
signal pattern : std_logic_vector(11 downto 0);
 
component DAC_Control
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
DAC_DATA : in STD_LOGIC_VECTOR(31 downto 0);
DAC_MOSI : out STD_LOGIC;
DAC_SCK : out STD_LOGIC;
DAC_CS : out STD_LOGIC;
RDY : out STD_LOGIC);
end component;
 
begin
U1 : DAC_Control
Port map ( CLK => CLK,
RST => RST,
DAC_MOSI => dacmosi,
DAC_SCK => dacsck,
DAC_CS => daccs,
RDY => RDY,
DAC_DATA => dacdata);
process(RST,CLK,daccs,dacsck,dacmosi)
begin
if (RST='1') then
DAC_MOSI <= '0';
DAC_CLR <= '0';
DAC_SCK <= '0';
DAC_CS <= '1';
elsif rising_edge(CLK) then
if rdy = '1' then -- Check if first 32 bits is sent and proceed to the next
command <= "0011"; -- Set the command register
address <= "1111"; -- Set the address register
pattern <= "100000000000"; -- 12 bit value (refer to LTC2624 datasheet page 10 for Vout)
dacdata(31 downto 24) <= (others => '0'); -- Don't care (refer to LTC2624 datasheet page 13)
dacdata(23 downto 20) <= command;
dacdata(19 downto 16) <= address;
dacdata(15 downto 4) <= pattern;
dacdata(3 downto 0) <= (others => '0'); -- Don't care
end if;
DAC_CLR <= '1';
end if;
DAC_CS <= daccs;
DAC_SCK <= dacsck;
DAC_MOSI <= dacmosi;
end process;
 
----- Disabling not required devices -----
SPI_SS_B <= '1';
AMP_CS <= '1';
AD_CONV <= '0';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
 
end DAC;
 

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