URL
https://opencores.org/ocsvn/sport/sport/trunk
Subversion Repositories sport
Compare Revisions
- This comparison shows the changes necessary to convert path
/sport
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/trunk/sim/vsim.do
0,0 → 1,?rev2len?
vsim -gui work.testbench_top work.testcase |
/trunk/sim/sport.cr.mti
0,0 → 1,13
C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v {1 {vlog -work work C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v |
Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013 |
|
} {} {}} C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v {1 {vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v |
Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 Jun 12 2013 |
-- Compiling module fifo_sport |
-- Compiling module custom_fifo_dp |
-- Compiling module mem_byte |
|
Top level modules: |
fifo_sport |
|
} {} {}} |
/trunk/sim/work/wb_interface_sport/_primary.vhd
0,0 → 1,35
library verilog; |
use verilog.vl_types.all; |
entity wb_interface_sport is |
port( |
wb_rst_i : in vl_logic; |
wb_clk_i : in vl_logic; |
wb_stb_i : in vl_logic; |
wb_ack_o : out vl_logic; |
wb_addr_i : in vl_logic_vector(5 downto 0); |
wb_we_i : in vl_logic; |
wb_dat_i : in vl_logic_vector(31 downto 0); |
wb_sel_i : in vl_logic_vector(3 downto 0); |
wb_dat_o : out vl_logic_vector(31 downto 0); |
wb_cyc_i : in vl_logic; |
wb_cti_i : in vl_logic_vector(2 downto 0); |
wb_err_o : out vl_logic; |
wb_rty_o : out vl_logic; |
rxsampleCnt : out vl_logic_vector(4 downto 0); |
rxpacketCnt : out vl_logic_vector(9 downto 0); |
txsampleCnt : out vl_logic_vector(4 downto 0); |
txpacketCnt : out vl_logic_vector(9 downto 0); |
dat_i : in vl_logic_vector(31 downto 0); |
dat_o : out vl_logic_vector(31 downto 0); |
rxsecEn : out vl_logic; |
rxlateFS_earlyFSn: out vl_logic; |
txsecEn : out vl_logic; |
txlateFS_earlyFSn: out vl_logic; |
tx_actHi : out vl_logic; |
rx_actHi : out vl_logic; |
msbFirst : out vl_logic; |
tx_start : out vl_logic; |
rx_start : out vl_logic; |
rx_int : out vl_logic |
); |
end wb_interface_sport; |
/trunk/sim/work/wb_interface_sport/verilog.psm
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Index: trunk/sim/work/wb_interface_sport/_primary.dat
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--- trunk/sim/work/wb_interface_sport/_primary.dat (nonexistent)
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trunk/sim/work/wb_interface_sport/_primary.dat
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--- trunk/sim/work/wb_interface_sport/_primary.dbs (nonexistent)
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trunk/sim/work/wb_interface_sport/_primary.dbs
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trunk/sim/work/wb_interface_sport/verilog.prw
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Index: trunk/sim/work/custom_fifo_dp/_primary.vhd
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--- trunk/sim/work/custom_fifo_dp/_primary.vhd (nonexistent)
+++ trunk/sim/work/custom_fifo_dp/_primary.vhd (revision 5)
@@ -0,0 +1,15 @@
+library verilog;
+use verilog.vl_types.all;
+entity custom_fifo_dp is
+ port(
+ clk_rd : in vl_logic;
+ clk_wr : in vl_logic;
+ d_i : in vl_logic_vector(7 downto 0);
+ d_o : out vl_logic_vector(7 downto 0);
+ rst : in vl_logic;
+ wr_en : in vl_logic;
+ rd_en : in vl_logic;
+ full : out vl_logic;
+ empty : out vl_logic
+ );
+end custom_fifo_dp;
Index: trunk/sim/work/custom_fifo_dp/verilog.psm
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trunk/sim/work/custom_fifo_dp/verilog.psm
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--- trunk/sim/work/custom_fifo_dp/_primary.dat (nonexistent)
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trunk/sim/work/custom_fifo_dp/_primary.dat
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--- trunk/sim/work/custom_fifo_dp/_primary.dbs (nonexistent)
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--- trunk/sim/work/custom_fifo_dp/verilog.prw (nonexistent)
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trunk/sim/work/custom_fifo_dp/verilog.prw
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Index: trunk/sim/work/mem_byte/_primary.vhd
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--- trunk/sim/work/mem_byte/_primary.vhd (nonexistent)
+++ trunk/sim/work/mem_byte/_primary.vhd (revision 5)
@@ -0,0 +1,12 @@
+library verilog;
+use verilog.vl_types.all;
+entity mem_byte is
+ port(
+ rst : in vl_logic;
+ clk : in vl_logic;
+ din : in vl_logic_vector(7 downto 0);
+ dout : out vl_logic_vector(7 downto 0);
+ wen : in vl_logic;
+ ren : in vl_logic
+ );
+end mem_byte;
Index: trunk/sim/work/mem_byte/verilog.psm
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trunk/sim/work/mem_byte/verilog.psm
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trunk/sim/work/mem_byte/_primary.dat
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trunk/sim/work/mem_byte/_primary.dbs
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trunk/sim/work/mem_byte/verilog.prw
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Index: trunk/sim/work/testbench_top/_primary.vhd
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--- trunk/sim/work/testbench_top/_primary.vhd (nonexistent)
+++ trunk/sim/work/testbench_top/_primary.vhd (revision 5)
@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity testbench_top is
+end testbench_top;
Index: trunk/sim/work/testbench_top/verilog.psm
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--- trunk/sim/work/testbench_top/_primary.dat (nonexistent)
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trunk/sim/work/testbench_top/_primary.dat
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Index: trunk/sim/work/_vmake
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+m255
+K3
+cModel Technology
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Index: trunk/sim/work/_temp/vlogndjx7y
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlogndjx7y
===================================================================
--- trunk/sim/work/_temp/vlogndjx7y (nonexistent)
+++ trunk/sim/work/_temp/vlogndjx7y (revision 5)
trunk/sim/work/_temp/vlogndjx7y
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlogb0czc4
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlogb0czc4
===================================================================
--- trunk/sim/work/_temp/vlogb0czc4 (nonexistent)
+++ trunk/sim/work/_temp/vlogb0czc4 (revision 5)
trunk/sim/work/_temp/vlogb0czc4
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlog0tkt21
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlog0tkt21
===================================================================
--- trunk/sim/work/_temp/vlog0tkt21 (nonexistent)
+++ trunk/sim/work/_temp/vlog0tkt21 (revision 5)
trunk/sim/work/_temp/vlog0tkt21
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlog419frw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlog419frw
===================================================================
--- trunk/sim/work/_temp/vlog419frw (nonexistent)
+++ trunk/sim/work/_temp/vlog419frw (revision 5)
trunk/sim/work/_temp/vlog419frw
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlogsmy8q3
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlogsmy8q3
===================================================================
--- trunk/sim/work/_temp/vlogsmy8q3 (nonexistent)
+++ trunk/sim/work/_temp/vlogsmy8q3 (revision 5)
trunk/sim/work/_temp/vlogsmy8q3
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlogaz49a3
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlogaz49a3
===================================================================
--- trunk/sim/work/_temp/vlogaz49a3 (nonexistent)
+++ trunk/sim/work/_temp/vlogaz49a3 (revision 5)
trunk/sim/work/_temp/vlogaz49a3
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlogb00ac7
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlogb00ac7
===================================================================
--- trunk/sim/work/_temp/vlogb00ac7 (nonexistent)
+++ trunk/sim/work/_temp/vlogb00ac7 (revision 5)
trunk/sim/work/_temp/vlogb00ac7
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlog3q55fi
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlog3q55fi
===================================================================
--- trunk/sim/work/_temp/vlog3q55fi (nonexistent)
+++ trunk/sim/work/_temp/vlog3q55fi (revision 5)
trunk/sim/work/_temp/vlog3q55fi
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlog7trdgy
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlog7trdgy
===================================================================
--- trunk/sim/work/_temp/vlog7trdgy (nonexistent)
+++ trunk/sim/work/_temp/vlog7trdgy (revision 5)
trunk/sim/work/_temp/vlog7trdgy
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlogtx39z3
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlogtx39z3
===================================================================
--- trunk/sim/work/_temp/vlogtx39z3 (nonexistent)
+++ trunk/sim/work/_temp/vlogtx39z3 (revision 5)
trunk/sim/work/_temp/vlogtx39z3
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlog9gzh7n
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlog9gzh7n
===================================================================
--- trunk/sim/work/_temp/vlog9gzh7n (nonexistent)
+++ trunk/sim/work/_temp/vlog9gzh7n (revision 5)
trunk/sim/work/_temp/vlog9gzh7n
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_temp/vlogssb8fa
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/_temp/vlogssb8fa
===================================================================
--- trunk/sim/work/_temp/vlogssb8fa (nonexistent)
+++ trunk/sim/work/_temp/vlogssb8fa (revision 5)
trunk/sim/work/_temp/vlogssb8fa
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/sport_top/_primary.vhd
===================================================================
--- trunk/sim/work/sport_top/_primary.vhd (nonexistent)
+++ trunk/sim/work/sport_top/_primary.vhd (revision 5)
@@ -0,0 +1,28 @@
+library verilog;
+use verilog.vl_types.all;
+entity sport_top is
+ port(
+ DTxPRI : out vl_logic;
+ DTxSEC : out vl_logic;
+ TSCLKx : out vl_logic;
+ TFSx : out vl_logic;
+ DRxPRI : in vl_logic;
+ DRxSEC : in vl_logic;
+ RSCLKx : out vl_logic;
+ RFSx : out vl_logic;
+ rx_int : out vl_logic;
+ rxclk : in vl_logic;
+ txclk : in vl_logic;
+ wb_clk_i : in vl_logic;
+ wb_rst_i : in vl_logic;
+ wb_dat_i : in vl_logic_vector(31 downto 0);
+ wb_dat_o : out vl_logic_vector(31 downto 0);
+ wb_cyc_i : in vl_logic;
+ wb_stb_i : in vl_logic;
+ wb_we_i : in vl_logic;
+ wb_adr_i : in vl_logic_vector(5 downto 0);
+ wb_ack_o : out vl_logic;
+ wb_err_o : out vl_logic;
+ wb_rty_o : out vl_logic
+ );
+end sport_top;
Index: trunk/sim/work/sport_top/verilog.psm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/sport_top/verilog.psm
===================================================================
--- trunk/sim/work/sport_top/verilog.psm (nonexistent)
+++ trunk/sim/work/sport_top/verilog.psm (revision 5)
trunk/sim/work/sport_top/verilog.psm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/sport_top/_primary.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/sport_top/_primary.dat
===================================================================
--- trunk/sim/work/sport_top/_primary.dat (nonexistent)
+++ trunk/sim/work/sport_top/_primary.dat (revision 5)
trunk/sim/work/sport_top/_primary.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/sport_top/_primary.dbs
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/sport_top/_primary.dbs
===================================================================
--- trunk/sim/work/sport_top/_primary.dbs (nonexistent)
+++ trunk/sim/work/sport_top/_primary.dbs (revision 5)
trunk/sim/work/sport_top/_primary.dbs
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/sport_top/verilog.prw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/sport_top/verilog.prw
===================================================================
--- trunk/sim/work/sport_top/verilog.prw (nonexistent)
+++ trunk/sim/work/sport_top/verilog.prw (revision 5)
trunk/sim/work/sport_top/verilog.prw
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/_info
===================================================================
--- trunk/sim/work/_info (nonexistent)
+++ trunk/sim/work/_info (revision 5)
@@ -0,0 +1,146 @@
+m255
+K3
+13
+cModel Technology
+Z0 dC:\Users\jeffA\Desktop\rtl\wiegand\trunk\sim
+vcustom_fifo_dp
+Z1 !s100 m]aGki5RGY2OHWVPI[4883
+Z2 IkdK[W8m_`^CcaOD?N=dO:3
+Z3 VM`n_ide9aJf9Y;?kT2G`D1
+Z4 dC:\Users\jeffA\Desktop\rtl\sport\trunk\sim
+Z5 w1424266427
+Z6 8C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
+Z7 FC:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
+Z8 L0 130
+Z9 OV;L;10.1e;51
+r1
+31
+Z10 !s108 1424460650.362000
+Z11 !s107 C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/SPORT_defines.v|C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/timescale.v|C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v|
+Z12 !s90 -reportprogress|300|-work|work|+incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog|C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v|
+Z13 o-work work -O0
+Z14 !s92 -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog -O0
+!i10b 1
+!s85 0
+!s101 -O0
+vfifo_sport
+Z15 !s100 6:21=68f:W4R=VCI<]Z?G1
+Z16 Ig;6ceN[A]4?Ck3eN^2
+Z17 VP]Ym3bAd=kd>2:46SaPf?0
+R4
+R5
+R6
+R7
+L0 71
+R9
+r1
+31
+R10
+R11
+R12
+R13
+R14
+!i10b 1
+!s85 0
+!s101 -O0
+vmem_byte
+Z18 !s100 49c3_ZgEn_W3e1g4>RUKT0
+Z19 I83lgE9J3>3UlDN9f1hB:V0
+Z20 VgaOB8W3I_jB>W:E4I1<^a3
+R4
+R5
+R6
+R7
+Z21 L0 204
+R9
+r1
+31
+R10
+R11
+R12
+R13
+R14
+!i10b 1
+!s85 0
+!s101 -O0
+vsport_top
+Z22 IaJmWkKYHGP4[JR7BU0h9S0
+Z23 VJ__`b[Tf@^hT292dH8KIm2
+R4
+Z24 w1424460645
+Z25 8C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
+Z26 FC:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
+L0 60
+R9
+r1
+31
+Z27 !s90 -reportprogress|300|-work|work|+incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog|C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v|
+R13
+R14
+Z28 !s100 R`A_RQ@HDi`C0hN^j?bH11
+Z29 !s108 1424460650.534000
+Z30 !s107 C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v|C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/timescale.v|C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v|
+!i10b 1
+!s85 0
+!s101 -O0
+vtestbench_top
+!i10b 1
+!s100 QZ4G90Qnl`ol^gaWd5g0a2
+IMG5SQc2FF8=6^QXifC[jY3
+Z31 V<2E8UnRl_M9?W9=EhO0:_0
+R4
+Z32 w1424456428
+Z33 FC:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testbench_top.v
+Z34 8C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase_1.v
+Z35 FC:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase_1.v
+L0 57
+R9
+r1
+!s85 0
+31
+Z36 !s108 1424460650.752000
+Z37 !s107 C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testbench_top.v|C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v|C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/timescale.v|C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase_1.v|
+Z38 !s90 -reportprogress|300|-work|work|+incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench|+incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog|C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase_1.v|
+!s101 -O0
+R13
+Z39 !s92 -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog -O0
+vtestcase_1
+!i10b 1
+Z40 !s100 ?Fbfjl=jdBBO1F0Bol?011
+Z41 IelL^hLN02f3QXJle04gO=1
+Z42 V?^>il8M_7lM
trunk/sim/work/fifo_sport/verilog.psm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/fifo_sport/_primary.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/fifo_sport/_primary.dat
===================================================================
--- trunk/sim/work/fifo_sport/_primary.dat (nonexistent)
+++ trunk/sim/work/fifo_sport/_primary.dat (revision 5)
trunk/sim/work/fifo_sport/_primary.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/fifo_sport/_primary.dbs
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/fifo_sport/_primary.dbs
===================================================================
--- trunk/sim/work/fifo_sport/_primary.dbs (nonexistent)
+++ trunk/sim/work/fifo_sport/_primary.dbs (revision 5)
trunk/sim/work/fifo_sport/_primary.dbs
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/fifo_sport/verilog.prw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/fifo_sport/verilog.prw
===================================================================
--- trunk/sim/work/fifo_sport/verilog.prw (nonexistent)
+++ trunk/sim/work/fifo_sport/verilog.prw (revision 5)
trunk/sim/work/fifo_sport/verilog.prw
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/testcase_1/_primary.vhd
===================================================================
--- trunk/sim/work/testcase_1/_primary.vhd (nonexistent)
+++ trunk/sim/work/testcase_1/_primary.vhd (revision 5)
@@ -0,0 +1,4 @@
+library verilog;
+use verilog.vl_types.all;
+entity testcase_1 is
+end testcase_1;
Index: trunk/sim/work/testcase_1/verilog.psm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/testcase_1/verilog.psm
===================================================================
--- trunk/sim/work/testcase_1/verilog.psm (nonexistent)
+++ trunk/sim/work/testcase_1/verilog.psm (revision 5)
trunk/sim/work/testcase_1/verilog.psm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/testcase_1/_primary.dat
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/testcase_1/_primary.dat
===================================================================
--- trunk/sim/work/testcase_1/_primary.dat (nonexistent)
+++ trunk/sim/work/testcase_1/_primary.dat (revision 5)
trunk/sim/work/testcase_1/_primary.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/testcase_1/_primary.dbs
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/testcase_1/_primary.dbs
===================================================================
--- trunk/sim/work/testcase_1/_primary.dbs (nonexistent)
+++ trunk/sim/work/testcase_1/_primary.dbs (revision 5)
trunk/sim/work/testcase_1/_primary.dbs
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/work/testcase_1/verilog.prw
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/sim/work/testcase_1/verilog.prw
===================================================================
--- trunk/sim/work/testcase_1/verilog.prw (nonexistent)
+++ trunk/sim/work/testcase_1/verilog.prw (revision 5)
trunk/sim/work/testcase_1/verilog.prw
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/sim/compile_hw.do.bak
===================================================================
--- trunk/sim/compile_hw.do.bak (nonexistent)
+++ trunk/sim/compile_hw.do.bak (revision 5)
@@ -0,0 +1,8 @@
+# hardware
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
+
+# testbench stuff
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testbench_top.v
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase.v
Index: trunk/sim/compile_hw.do
===================================================================
--- trunk/sim/compile_hw.do (nonexistent)
+++ trunk/sim/compile_hw.do (revision 5)
@@ -0,0 +1,8 @@
+# hardware
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
+
+# testbench stuff
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testbench_top.v
+vlog -work work +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase_1.v
Index: trunk/sim/compile_hw.tcl
===================================================================
--- trunk/sim/compile_hw.tcl (nonexistent)
+++ trunk/sim/compile_hw.tcl (revision 5)
@@ -0,0 +1 @@
+vlog -reportprogress 300 -work work C:/Users/janderson/Desktop/wiegand/trunk/rtl/verilog/wiegand_defines.v
\ No newline at end of file
Index: trunk/sim/sport.mpf
===================================================================
--- trunk/sim/sport.mpf (nonexistent)
+++ trunk/sim/sport.mpf (revision 5)
@@ -0,0 +1,464 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+
+; Altera Primitive libraries
+;
+; VHDL Section
+;
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+maxv = $MODEL_TECH/../altera/vhdl/maxv
+fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+arriaii = $MODEL_TECH/../altera/vhdl/arriaii
+arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
+arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
+arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
+arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
+arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
+stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
+stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
+stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
+cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
+cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
+cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
+cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
+stratixv = $MODEL_TECH/../altera/vhdl/stratixv
+stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
+stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
+arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
+arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
+arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
+arriav = $MODEL_TECH/../altera/vhdl/arriav
+cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
+;
+; Verilog Section
+;
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+maxv_ver = $MODEL_TECH/../altera/verilog/maxv
+fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
+arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
+arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
+arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
+arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
+arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
+stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
+stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
+stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
+stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
+stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
+stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
+arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
+arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
+arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
+arriav_ver = $MODEL_TECH/../altera/verilog/arriav
+arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
+arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
+cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
+cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
+cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
+cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
+cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
+cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
+cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Default or value of 3 or 2008 for VHDL-2008.
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turn on incremental compilation of modules. Default is off.
+; Incremental = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license
+; License = plus
+
+; Stop the simulator after a VHDL/Verilog assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing VHDL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type). Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave
+; DefaultRestartOptions = -force
+
+; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
+; (> 500 megabyte memory footprint). Default is disabled.
+; Specify number of megabytes to lock.
+; LockedMemory = 1000
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+[lmc]
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: = [,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; The command verror can be used to get the complete
+; description of a message.
+
+; Control transcripting of elaboration/runtime messages.
+; The default is to have messages appear in the transcript and
+; recorded in the wlf file (messages that are recorded in the
+; wlf file can be viewed in the MsgViewer). The other settings
+; are to send messages only to the transcript or only to the
+; wlf file. The valid values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+[Project]
+; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 6
+Project_File_0 = C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_defines.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/wb_interface.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testbench_top.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/sport_top.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 0 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog/fifos.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1424266427 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/rtl/verilog compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = C:/Users/jeffA/Desktop/rtl/sport/trunk/bench/testcase_1.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+C:/Users/jeffA/Desktop/rtl/sport/trunk/bench compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick =
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick =
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick =
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick =
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick =
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick =
+Project_Major_Version = 10
+Project_Minor_Version = 1
Index: trunk/sim/vsim.do.bak
===================================================================
--- trunk/sim/vsim.do.bak (nonexistent)
+++ trunk/sim/vsim.do.bak (revision 5)
@@ -0,0 +1 @@
+vsim -gui work.testbench_top work.testcase_1
\ No newline at end of file