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URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

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  • This comparison shows the changes necessary to convert path 
    /ssbcc
    from Rev 9 to Rev 10
    ↔ Reverse comparison
  •

Rev 9 → Rev 10

/trunk/lib/9x8/cmp_8bit_uu.s
1,7 → 1,10
; Copyright 2013, Sinclair R.F., Inc.
; Copyright 2013, 2015, Sinclair R.F., Inc.
;
; 8-bit unsigned vs. unsigned comparison operators
 
.IFNDEF D__INCLUDED__CMP_8BIT_UU_S__
.define D__INCLUDED__CMP_8BIT_UU_S__
 
; Compare two unsigned 8-bit values for equality.
; ( u1 u2 - f"u1 = u2" )
.function cmp_8bit_uu_eq
56,3 → 59,5
&
; ( u1 uX - min(u1,u2) )
.return(+)
 
.ENDIF ; D__INCLUDED__CMP_8BIT_UU_S__
/trunk/lib/9x8/math.s
1,7 → 1,10
; Copyright 2014, Sinclair R.F., Inc.
; Copyright 2014-2015, Sinclair R.F., Inc.
;
; Unsigned arithmetic operations.
 
.IFNDEF D__INCLUDED__MATH_S__
.define D__INCLUDED__MATH_S__
 
; Notation:
; ux_n is the n'th byte of ux where n=0 is the LSB
; example: ( u0_0 u0_1 ) are the LSB and MSB of a 2-byte 16-bit value.
74,3 → 77,5
.function math__add_u32_u32_u32
>r .call(math__add_u32_u24_u32)
r> .return(+)
 
.ENDIF ; D__INCLUDED__MATH_S__
/trunk/lib/9x8/char.s
1,9 → 1,9
; Copyright 2013, Sinclair R.F., Inc.
; Copyright 2013, 2015, Sinclair R.F., Inc.
;
; Character manipulation functions
 
.IFNDEF C__INCLUDED__CHAR_S__
.constant C__INCLUDED__CHAR_S__ 0
.IFNDEF D__INCLUDED__CHAR_S__
.define D__INCLUDED__CHAR_S__
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
86,4 → 86,4
'f' over - 0x80 & .jumpc(error) ${ord('a')-10} - .return(0)
:error .return(0xFF)
 
.ENDIF ; C__INCLUDED__CHAR_S__
.ENDIF ; D__INCLUDED__CHAR_S__
/trunk/core/9x8/peripherals/monitor_stack.v
1,5 → 1,6
//
// monitor_stack peripheral
// Copyright 2013, Sinclair R.F., Inc.
//
// Note: The validity of N and T are not monitored for invalid operations. For
// example, if N is not valid and a "swap" is performed, then the data
/trunk/core/9x8/peripherals/timer.v
1,5 → 1,6
//
// PERIPHERAL timer: @NAME@
// Copyright 2013, Sinclair R.F., Inc.
//
localparam L__COUNT = @RATEMETHOD@-1;
localparam L__COUNT_NBITS = $clog2(L__COUNT);
/trunk/core/9x8/peripherals/stepper_motor.py
56,7 → 56,6
Or:\n
PERIPHERAL stepper_motor basename=name \\
master=mastername \\
outcontrol=O_name \\
outrecord=O_name \\
outrun=O_name \\
indone=I_name \\
74,6 → 73,8
specifies a preceding stepper_motor peripheral to use for the internal
clock and to use for the accleration, rate, angle accumulator, and mode
sizes
Note: The "outcontrol" port from the master peripheral is used to queue
the control words for its slaves.
outcontrol=O_name
specifies the port used to assemble 8-bit control values into the stepper
motor control word
290,7 → 291,6
periperal.\n
PERIPHERAL stepper_motor basename=slave \\
master=stepper \\
outcontrol=O_slave_control \\
outrecord=O_slave_wr \\
outrun=O_slave_go \\
indone=I_slave_done \\
337,6 → 337,7
'accumres',
'countwidth',
'modewidth',
'outcontrol',
'ratemethod',
'rateres',
'ratescale',
346,7 → 347,6
'basename',
'indone',
'inerror',
'outcontrol',
'outrecord',
'outrun',
)
394,10 → 394,11
config.AddIO('i_%s_error' % self.basename, 1, 'input', loc)
config.AddSignal('s__%s__done' % self.basename, 1, loc)
self.ix_outcontrol = config.NOutports()
config.AddOutport((self.outcontrol,
False,
# empty list
),loc)
if not hasattr(self,'master'):
config.AddOutport((self.outcontrol,
False,
# empty list
),loc)
self.ix_outrecord = config.NOutports()
config.AddOutport((self.outrecord,
True,
441,6 → 442,7
else:
body = re.sub(r'@OUTMODE_BEGIN@\n','',body)
body = re.sub(r'@OUTMODE_END@\n','',body)
masterBasename = self.basename if not hasattr(self,'master') else self.master.basename
for subpair in (
( r'@ACCEL_WIDTH@', str(self.accelwidth), ),
( r'@ACCEL_RES@', str(self.accelres), ),
469,7 → 471,8
( r'\bi__', 'i_%s_' % self.basename, ),
( r'\bo__', 'o_%s_' % self.basename, ),
( r'\bs__', 's__%s__' % self.basename, ),
( r'@S__CLK_EN@', 's__%s__clk_en' % (self.basename if not hasattr(self,'master') else self.master.basename), ),
( r'@S__CLK_EN@', 's__%s__clk_en' % masterBasename, ),
( r'@S__INPUT_CONTROL_WORD_PACKED@', 's__%s__input_control_word_packed' % masterBasename, ),
):
body = re.sub(subpair[0],subpair[1],body)
body = self.GenVerilogFinal(config,body)
/trunk/core/9x8/peripherals/AXI4_Lite_Slave_DualPortRAM.v
1,5 → 1,6
//
// PERIPHERAL: AXI4-Lite slave dual-port-RAM interface
// Copyright 2014, Sinclair R.F., Inc.
//
// Note: While the AXI4-Lite protocol allows simultaneous read and write
// operations, only one side of the dual-port RAM is available to the AXI4-lite
/trunk/core/9x8/peripherals/servo_motor.v
1,5 → 1,6
//
// PERIPHERAL servo_motor: @NAME@
// Copyright 2015, Sinclair R.F., Inc.
//
generate
reg [@NBITS_PWM@-1:0] s__pwm_count_init = @DEFAULT_PWM@;
/trunk/core/9x8/peripherals/PWM_8bit.v
1,5 → 1,6
//
// PERIPHERAL PWM_8bit: @NAME@
// Copyright 2013, Sinclair R.F., Inc.
//
localparam L__COUNT = @COUNT@-1;
localparam L__COUNT_NBITS = $clog2(L__COUNT+1);
/trunk/core/9x8/peripherals/latch.v
1,5 → 1,6
//
// latch peripheral for @INSIGNAL@
// Copyright 2013, Sinclair R.F., Inc.
//
generate
// Register the input signal when commanded.
/trunk/core/9x8/peripherals/AXI4_Lite_Master.v
1,5 → 1,6
//
// PERIPHERAL: AXI4-Lite Master
// Copyright 2014, Sinclair R.F., Inc.
//
generate
localparam L__ADDRESS_WIDTH = @ADDRESS_WIDTH@;
/trunk/core/9x8/peripherals/stepper_motor.v
2,11 → 2,10
// PERIPHERAL stepper_motor: @NAME@
// Copyright 2015, Sinclair R.F., Inc.
//
// Assemble the byes of the control word from the input bytes.
@MASTER_BEGIN@
localparam L__RATEMETHOD_MINUS_1 = @RATEMETHOD@ - 1;
localparam L__NBITS_RATEMETHOD = clog2(L__RATEMETHOD_MINUS_1);
@MASTER_END@
// Assemble the byes of the control word from the input bytes.
reg [@CONTROL_WIDTH@-1:0] s__input_control_word = {(@CONTROL_WIDTH@){1'b0}};
always @ (posedge i_clk)
if (i_rst)
23,6 → 22,7
, s__input_control_word[0+:@MODE_WIDTH@]
@OUTMODE_END@
};
@MASTER_END@
// Instantiate the control word FIFO and operate its input side.
reg s__FIFO_wr = 1'b0;
always @ (posedge i_clk)
39,7 → 39,7
reg [@CONTROL_WIDTH_PACKED@-1:0] s__FIFO[@FIFO_DEPTH@-1:0];
always @ (posedge i_clk)
if (s__FIFO_wr)
s__FIFO[s__FIFO_in_addr[0+:@NBITS_FIFO_DEPTH@]] <= s__input_control_word_packed;
s__FIFO[s__FIFO_in_addr[0+:@NBITS_FIFO_DEPTH@]] <= @S__INPUT_CONTROL_WORD_PACKED@;
// Operate the output side of the FIFO and translate the packed controls into
// individual signals.
reg s__FIFO_rd = 1'b0;
/trunk/core/9x8/peripherals/inFIFO_async.v
1,5 → 1,6
//
// PERIPHERAL inFIFO_async: @NAME@
// Copyright 2014, Sinclair R.F., Inc.
//
generate
// FIFO memory
/trunk/core/9x8/peripherals/outFIFO_async.v
1,5 → 1,6
//
// PERIPHERAL outFIFO_async: @NAME@
// Copyright 2014, Sinclair R.F., Inc.
//
generate
// FIFO memory
/trunk/ssbccConfig.py
640,7 → 640,7
alreadyUsed = [memName for memName in mems if self.IsCombined(memName)];
if alreadyUsed:
raise SSBCCException('"%s" already used in COMBINE configuration command before %s' % (alreadyUsed[0],loc,));
repeated = [mems[ix] for ix in range(len(mems)-1) if mems[ix] in mems[ix+1]];
repeated = [mems[ix] for ix in range(len(mems)-1) if mems[ix] in mems[ix+1:]];
if repeated:
raise SSBCCException('"%s" repeated in COMBINE configuration command on %s' % (repeated[0],loc,));
# Count the number of the different memory types being combined and validate the combination.

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