URL
https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
Subversion Repositories t6507lp
Compare Revisions
- This comparison shows the changes necessary to convert path
/t6507lp/trunk
- from Rev 245 to Rev 246
- ↔ Reverse comparison
Rev 245 → Rev 246
/rtl/verilog/t6507lp_fsm_tb.v
97,11 → 97,18
fake_mem[my_i]=8'h00; |
end |
|
fake_mem[0] = ASL_ACC; // testing ACC mode |
fake_mem[0] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed; |
fake_mem[1] = 8'h00; |
fake_mem[2] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed; |
fake_mem[3] = 8'h04; |
fake_mem[4] = 8'hFF; |
|
|
/*fake_mem[0] = ASL_ACC; // testing ACC mode |
fake_mem[1] = ADC_IMM; // testing IMM mode |
fake_mem[2] = 8'h27; |
fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type |
fake_mem[4] = 8'h09; |
fake_mem[4] = 8'h09;*/ |
fake_mem[5] = 8'h00; |
fake_mem[6] = ASL_ACC; // wont be executed |
fake_mem[7] = ASL_ACC; // wont be executed |
/rtl/verilog/t6507lp_fsm.v
150,6 → 150,8
reg txs; |
reg nop; |
|
reg invalid; |
|
wire [ADDR_SIZE_:0] next_pc; // a simple logic to add one to the PC |
assign next_pc = pc + 13'b0000000000001; |
|
338,6 → 340,10
address <= sp; |
mem_rw <= MEM_READ; |
end |
else if (invalid) begin |
address <= pc; |
mem_rw <= MEM_READ; |
end |
else begin // jsr |
address <= sp; |
mem_rw <= MEM_READ; |
526,7 → 532,7
mem_rw <= MEM_READ; |
end |
end |
PUSH_PCH: begin |
PUSH_PCH: begin // this is probably wrong |
pc <= pc; |
address <= sp_minus_one; |
data_out <= pc[7:0]; |
616,7 → 622,10
alu_enable = 1'b0; |
next_state = RESET; // these lines prevents latches |
|
case (state) |
if (invalid == 1'b1) begin |
next_state = FETCH_OP; |
end |
else case (state) |
RESET: begin |
if (rst_counter == 3'd6) begin |
next_state = FETCH_OP; |
931,6 → 940,8
txs = 1'b0; |
nop = 1'b0; |
|
invalid = 1'b0; |
|
case (ir) |
CLC_IMP, CLD_IMP, CLI_IMP, CLV_IMP, DEX_IMP, DEY_IMP, INX_IMP, INY_IMP, SEC_IMP, SED_IMP, SEI_IMP, TAX_IMP, |
TAY_IMP, TXA_IMP, TYA_IMP: begin |
1112,6 → 1123,7
end |
JSR_ABS: begin |
jsr = 1'b1; |
jump = 1'b1; |
end |
TSX_IMP: begin |
tsx = 1'b1; |
1123,6 → 1135,7
index_is_x = 1'b1; |
//$write("state : %b", state); |
if (reset_n == 1'b1 && state != FETCH_OP_FIX_PC) begin // the processor is NOT being reset neither it is fixing the pc |
invalid = 1'b1; |
//$write("\nunknown OPCODE!!!!! 0x%h\n", ir); |
//$finish(); |
end |
/rtl/verilog/video.v
444,7 → 444,13
// 3 BL, PF |
// 4 BK |
if (CTRLPF[0] == 1'b1) begin// reflected PF |
if (ENABL == 1'b1) begin // the ball is enabled |
if (vert_counter == p0 || vert_counter == m0) begin |
pixel = COLUP0; |
end |
else if (vert_counter == p1 || vert_counter == m1) begin |
pixel = COLUP1; |
end |
else if (ENABL == 1'b1) begin // the ball is enabled |
if (vert_counter == bl_position) begin |
pixel = COLUPF; |
end |
/syn/cadence/scripts/rc_script.cmd
0,0 → 1,21
# Cadence Encounter(R) RTL Compiler |
# version v07.20-s009_1 (32-bit) built Feb 7 2008 |
# |
# Run with the following arguments: |
# -logfile rc.log |
# -cmdfile rc_script.cmd |
read_hdl t6507lp.v t6507lp_alu.v t6507lp_fsm.v -v2001 |
set_attr lib_search_path /home/nscad/samuel/Desktop/libs/xc06/ |
set_attr library D_CELLS_3_3V.lib |
elaborate |
define_clock -period 1000000 -name 1MHz [find [ find / -design t6507lp] -port clk] |
#set_attribute lp_insert_operand_isolation true |
#set_attr lp_insert_clock_gating true |
#synthesize -effort high |
synthesize -to_generic |
synthesize -to_mapped |
synthesize -to_placed |
|
write_hdl t6507lp > t6507lp.vg |
|
exit |