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URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

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    /t6507lp/trunk
    from Rev 257 to Rev 258
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Rev 257 → Rev 258

/rtl/verilog/stubs.v
89,7 → 89,7
input VDD;
endmodule
 
module FILLERP_110 (GND5O, GND5R, VDD5O, VDD5R, CLAMPC);
/*module FILLERP_110 (GND5O, GND5R, VDD5O, VDD5R, CLAMPC);
input CLAMPC;
input VDD5O;
input VDD5R;
96,3 → 96,4
input GND5O;
input GND5R;
endmodule
*/
/rtl/verilog/t6507lp_io.v
41,7 → 41,7
 
`include "timescale.v"
`include "stubs.v"
module t6507lp_io(clk, reset_n, data_in, rw_mem, data_out, address);
module t6507lp_io(clk, reset_n, scan_enable, data_in, rw_mem, data_out, address);
parameter [3:0] DATA_SIZE = 4'd8;
parameter [3:0] ADDR_SIZE = 4'd13;
 
54,6 → 54,9
input reset_n;
wire reset_nIO;
 
input scan_enable;
wire scan_enableIO;
 
input [DATA_SIZE_:0] data_in;
reg [DATA_SIZE_:0] data_inIO;
 
66,8 → 69,7
output [ADDR_SIZE_:0] address;
reg [ADDR_SIZE_:0] addressIO;
 
wire clampc;
wire pipo1, pipo2, pipo3, pipo4, pipo5, pipo6, pipo7, pipo8, pipo9, chainfinal;
wire pipo0, pipo1, pipo2, pipo3, pipo4, pipo5, pipo6, pipo7, pipo8, pipo9, pipo10, chainfinal;
 
wire muxed;
 
80,19 → 82,41
.address (addressIO)
);
 
assign muxed = (reset_nIO == 0) ? chainfinal : rw_memIO;
wire vdd, gnd, dummy_clampc;
 
wire dummy_vdd, dummy_gnd, dummy_clampc;
ICP scan_pad(
.PAD (scan_enable),
.PI (pipo10),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (chain_final),
.Y (scan_enableIO)
);
 
/* ICP test_pad(
.PAD (pintest),
.PI (1'b1),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo0),
.Y (pintestIO)
);
*/
ICP clk_pad(
.PAD (clk),
.PI (pipo9),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (chain_final),
.PO (pipo10),
.Y (clkIO)
);
 
99,10 → 123,10
ICP reset_n_pad(
.PAD (reset_n),
.PI (pipo8),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo9),
.Y (reset_nIO)
111,10 → 135,10
ICP data_in_pad0(
.PAD (data_in[0]),
.PI (pipo7),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo8),
.Y (data_inIO[0])
123,10 → 147,10
ICP data_in_pad1(
.PAD (data_in[1]),
.PI (pipo6),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo7),
.Y (data_inIO[1])
135,10 → 159,10
ICP data_in_pad2(
.PAD (data_in[2]),
.PI (pipo5),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo6),
.Y (data_inIO[2])
147,10 → 171,10
ICP data_in_pad3(
.PAD (data_in[3]),
.PI (pipo4),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo5),
.Y (data_inIO[3])
159,10 → 183,10
ICP data_in_pad4(
.PAD (data_in[4]),
.PI (pipo3),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo4),
.Y (data_inIO[4])
171,10 → 195,10
ICP data_in_pad5(
.PAD (data_in[5]),
.PI (pipo2),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo3),
.Y (data_inIO[5])
183,10 → 207,10
ICP data_in_pad6(
.PAD (data_in[6]),
.PI (pipo1),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo2),
.Y (data_inIO[6])
194,11 → 218,11
 
ICP data_in_pad7(
.PAD (data_in[7]),
.PI (dummy_vdd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.PI (pipo0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PO (pipo1),
.Y (data_inIO[7])
206,11 → 230,11
 
BT4P rw_mem_pad(
.A (muxed),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (rw_mem)
);
217,11 → 241,11
 
BT4P data_out_pad0(
.A (data_outIO[0]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[0])
);
228,11 → 252,11
 
BT4P data_out_pad1(
.A (data_outIO[1]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[1])
);
239,11 → 263,11
 
BT4P data_out_pad2(
.A (data_outIO[2]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[2])
);
250,11 → 274,11
 
BT4P data_out_pad3(
.A (data_outIO[3]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[3])
);
261,11 → 285,11
 
BT4P data_out_pad4(
.A (data_outIO[4]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[4])
);
272,11 → 296,11
 
BT4P data_out_pad5(
.A (data_outIO[5]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[5])
);
283,11 → 307,11
 
BT4P data_out_pad6(
.A (data_outIO[6]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[6])
);
294,11 → 318,11
 
BT4P data_out_pad7(
.A (data_outIO[7]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (data_out[7])
);
305,11 → 329,11
 
BT4P address_pad0(
.A (addressIO[0]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[0])
);
316,111 → 340,111
 
BT4P address_pad1(
.A (addressIO[1]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[1])
);
BT4P address_pad2(
.A (addressIO[2]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[2])
);
BT4P address_pad3(
.A (addressIO[3]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[3])
);
BT4P address_pad4(
.A (addressIO[4]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[4])
);
BT4P address_pad5(
.A (addressIO[5]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[5])
);
BT4P address_pad6(
.A (addressIO[6]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[6])
);
BT4P address_pad7(
.A (addressIO[7]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[7])
);
BT4P address_pad8(
.A (addressIO[8]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[8])
);
BT4P address_pad9(
.A (addressIO[9]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[9])
);
BT4P address_pad10(
.A (addressIO[10]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[10])
);
BT4P address_pad11(
.A (addressIO[11]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[11])
);
427,11 → 451,11
 
BT4P address_pad12(
.A (addressIO[12]),
.EN (dummy_gnd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.EN (1'b0),
.GND5O (gnd),
.GND5R (gnd),
.VDD5O (vdd),
.VDD5R (vdd),
.CLAMPC (dummy_clampc),
.PAD (address[12])
);
438,105 → 462,109
 
CORNERCLMP left_up_pad (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND5O (gnd),
.GND5R (gnd)
);
 
CORNERCLMP left_down_pad (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND5O (gnd),
.GND5R (gnd)
);
 
CORNERCLMP right_up_pad (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND5O (gnd),
.GND5R (gnd)
);
 
CORNERCLMP right_down_pad (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND5O (gnd),
.GND5R (gnd)
);
 
GND5ALLPADP gnd_pad_left (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND (gnd)
);
 
GND5ALLPADP gnd_pad_right (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND (gnd)
);
 
GND5ALLPADP gnd_pad_up (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND (gnd)
);
 
GND5ALLPADP gnd_pad_down (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND (gnd)
);
 
VDD5ALLPADP vdd_pad_left (
.CLAMPC (dummy_clampc),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD (dummy_vdd)
.GND5O (gnd),
.GND5R (gnd),
.VDD (vdd)
);
 
VDD5ALLPADP vdd_pad_right (
.CLAMPC (dummy_clampc),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD (dummy_vdd)
.GND5O (gnd),
.GND5R (gnd),
.VDD (vdd)
);
 
VDD5ALLPADP vdd_pad_up (
.CLAMPC (dummy_clampc),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD (dummy_vdd)
.GND5O (gnd),
.GND5R (gnd),
.VDD (vdd)
);
 
VDD5ALLPADP vdd_pad_down (
.CLAMPC (dummy_clampc),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd),
.VDD (dummy_vdd)
.GND5O (gnd),
.GND5R (gnd),
.VDD (vdd)
);
 
assign muxed = (reset_nIO == 1'b1) ? chainfinal : rw_memIO;
 
FILLERP_110 filler0 (
/* FILLERP_110 filler0 (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND5O (gnd),
.GND5R (gnd)
);
 
FILLERP_110 filler1 (
.CLAMPC (dummy_clampc),
.VDD5O (dummy_vdd),
.VDD5R (dummy_vdd),
.GND5O (dummy_gnd),
.GND5R (dummy_gnd)
.VDD5O (vdd),
.VDD5R (vdd),
.GND5O (gnd),
.GND5R (gnd)
);
*/
endmodule

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