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\documentclass[a4paper,BCOR7mm,12pt,pointlessnumbers,bibtotoc]{scrartcl}
 
\usepackage{amsmath,epsfig}
\usepackage{amssymb,amsfonts}
\usepackage{color}
\usepackage{array,booktabs}
\usepackage{graphicx}
\usepackage{caption}
\usepackage[hypcap=true,labelformat=simple]{subcaption}
\renewcommand{\thesubfigure}{(\alph{subfigure})}
\usepackage{tikz}
\usetikzlibrary{arrows,automata}
\usepackage{listings}
\usepackage{hyperref}
\usepackage{enumitem}
 
\newcolumntype{C}[1]{>{\centering\arraybackslash}p{#1}} % centering column type with fixed width
\newcolumntype{R}[1]{>{\raggedleft\arraybackslash}p{#1}} % right aligned column type with fixed width
\newcolumntype{L}[1]{>{\raggedright\arraybackslash}p{#1}} % left aligned column type with fixed width
 
\newcommand{\ceil}[1]{\left\lceil #1 \right\rceil} %\left\lceil #1 \right\rceil
 
\begin{document}
%\maketitle
\begin{center}
\Large Ternary Adder IP Cores\\[0.4cm]
\large Martin Kumm, Jens Willkomm \\[0.5cm]
\large \today \\[0.5cm]
\end{center}
 
\section{Introduction}
 
This IP core provides resource efficient ternary adders, i.\,e., adders with three inputs performing $s = x + y + z$, for the Altera and Xilinx platforms.
Resource efficient means that they need exactly the same resources on modern FPGAs as two-input adders, but are slightly slower.
The Xilinx core (\verb|ternary_adder_xilinx.vhd|) is a low-level implementation, following an US patent from Xilinx \cite{sp07}. It directly uses the Xilinx primitives (\verb|CARRY4|, \verb|LUT6_2| and \verb|FDCE|). It is suitable for all FPGAs providing 6-input LUTs. Today, these are the Virtex~5-7, Spartan~6, Kintex~7 and Artix~7 families. The Altera core (\verb|ternary_adder_altera.vhd|) is a high-level implementation using the '+' operator. However, the ternary subtract operations ($x - y + z$, $x + y - z$ and $x - y - z$) are not supported by a high-level description; so this is realized by extending the word size of the ternary adders and setting the lower bits to appropriate constant values.
They can be mapped very resource efficient for all Altera FPGAs providing adaptive logic modules (ALMs), today, these are the Arria I,II,V and Stratix II-V FPGAs.
 
\section{Interface}
 
The generics as well as the port are identical for the Altera and Xilinx implementation and are described in Table~\ref{tab:generics} and Table~\ref{tab:port}, respectively.
 
\begin{table}[!h]
\renewcommand{\arraystretch}{1.1}
\caption{Description of the generics}
\label{tab:generics}
\centering
\begin{tabular}{lccL{7cm}}
\toprule
Generic & Type & Default & Description\\
\cmidrule(rl){1-1} \cmidrule(rl){2-2} \cmidrule(rl){3-3} \cmidrule(rl){4-4}
\verb|input_word_size| & integer & 10 & Input word size of the inputs $x$,$y$ and $z$. The output word size is automatically set to \verb|input_word_size+2|\\
\verb|subtract_y| & boolean & false & Input $y$ is negated, realizing $s = x - y \pm z$\\
\verb|subtract_z| & boolean & false & Input $z$ is negated, realizing $s = x \pm y - z$\\
\verb|use_output_ff| & boolean & true & If true, the adder uses flip flops at the output (without extra slice or ALM resources)\\
\bottomrule
\end{tabular}
\end{table}
 
\begin{table}[!h]
\renewcommand{\arraystretch}{1.1}
\caption{Description of the port}
\label{tab:port}
\centering
\begin{tabular}{lcccL{5cm}}
\toprule
Generic & Direction & Type & Word Size & Description\\
\cmidrule(rl){1-1} \cmidrule(rl){2-2} \cmidrule(rl){3-3} \cmidrule(rl){4-4} \cmidrule(rl){5-5}
\verb|clk_i| & in & \verb|sl| & 1 & Clock input (used when \verb|use_output_ff=true|)\\
\verb|rst_i| & in & \verb|sl| & 1 & Reset input (used when \verb|use_output_ff=true|)\\
\verb|x_i| & in & \verb|slv| & \verb|input_word_size| & Input $x$\\
\verb|y_i| & in & \verb|slv| & \verb|input_word_size| & Input $y$\\
\verb|z_i| & in & \verb|slv| & \verb|input_word_size| & Input $z$\\
\verb|sum_o| & out & \verb|slv| & \verb|input_word_size + 2| & Sum output $s$\\
\bottomrule
\end{tabular}
\end{table}
 
\section{Implementation}
 
Both implementations uses a carry save adder (CSA) tree with three inputs and a final ripple carry adder as vector merging adder (VMA). One stage of full adders (FAs) is used to realize a 3:2 compressor, i.\,e., the three input bit vectors are compressed to two bit vectors which are obtained by the sum and carry outputs. A second stage of FAs merges these two bit vectors to a single result.
 
For Altera, the 3:2 compressor can be directly mapped to the ALM LUT, realizing the sum $s'_i = x_i \oplus y_i \oplus z_i$ and carry $c'_i = x_i y_i + x_i z_i + y_i z_i$. The full adders of the ALM are used for the VMA.
To include both stages in a single ALM stage, each ALM has to be configured to the shared arithmetic mode \cite{blsy09} in which the output of one LUT is connected to the FA input of the next higher bit. The resulting ternary adder structure is shown in \figurename~\ref{fig:ternary_adder_stratix}.
 
For Xilinx, the FA for the 3:2 compressor is also realized in the FPGA LUT \cite{sp07}. In addition to that, one additional XOR gate has to be realized in the same LUT to complete the fast carry chain resources to a ripple carry adder for the VMA. The carry output of the first FA (realized in the LUT) must be routed to the next higher FA input using the FPGA routing fabric.
The resulting slice configuration is shown in \figurename~\ref{fig:ternary_adder_virtex_5_6_7}.
 
 
\begin{figure}[!h]
\centering
% \subfigure[]{\scalebox{1}{\includegraphics{images/ternary_adder_generic}\label{fig:ternary_adder_generic}}}
% \subfigure[]{\scalebox{1}{\includegraphics{images/ternary_adder_3_2_comp}\label{fig:ternary_adder_3_2_comp}}}
\begin{subfigure}[c]{\columnwidth}
\centering
\scalebox{1.2}{\includegraphics{images/ternary_adder_altera}}
\caption{}
\label{fig:ternary_adder_stratix}
\end{subfigure}
\begin{subfigure}[c]{\columnwidth}
\centering
\scalebox{1.2}{\includegraphics{images/ternary_adder_xilinx}}
\caption{}
\label{fig:ternary_adder_virtex_5_6_7}
\end{subfigure}
\caption{Realization of ternary adders
%(a) generic architecture using two ripple carry adders
on
(a) Altera Stratix II-V ALMs (b) Xilinx Virtex 5-7 Slices}
\label{fig:ternary_adders}
\end{figure}
 
\section{Resource Consumption}
 
For Altera, each ALM can compute two output bits. As the output word size is two bits more than the input word size, there are
\begin{align}
N_{\text{ALM},++} = \ceil{\frac{\text{input\_word\_size}+2}{2}}
\end{align}
ALMs needed for a pure addition ($s = x + y + z$). If one input is subtracted (setting one of \verb|subtract_y| or \verb|subtract_y| to true), the word length has to be extended by one bit leading to:
\begin{align}
N_{\text{ALM},+-} = \ceil{\frac{\text{input\_word\_size}+3}{2}}
\end{align}
Finally, if two inputs are subtracted, the word length has to be further increased leading to:
\begin{align}
N_{\text{ALM},--} = \ceil{\frac{\text{input\_word\_size}+4}{2}}
\end{align}
 
For Xilinx, four output bits can be computed in each slice. Thus, the number of slices is given by:
\begin{align}
N_{\text{Slices}} = \ceil{\frac{\text{input\_word\_size}+2}{4}}
\end{align}
The slice usage is independent of the operation performed. If a slice is not fully utilized, the remaining LUTs can still be used for other functionallities.
 
\section{Performance}
 
To estimate the performance, the maximum clock frequencies ($f_\text{max}$) were obtained by synthesis experiments for Altera Stratix~IV (EP4SGX230KF40C2) using Quartus-II~10.1 and Xilinx Virtex~6 (XC6VLX75T-2FF484) using ISE 13.4, both after place \& route. The resulting clock frequencies with output word sizes from 16 up to 64\,bit are shown in Table~\ref{tab:performance}.
 
\begin{table}[!h]
\renewcommand{\arraystretch}{1.1}
\caption{Performance of the IP Cores}
\label{tab:performance}
\centering
\begin{tabular}{ccc}
\toprule
output word size & $f_\text{max}$ Stratix IV [MHz] & $f_\text{max}$ Virtex 6 [MHz]\\
\cmidrule(rl){1-1} \cmidrule(rl){2-2} \cmidrule(rl){3-3}
16 & 708 & 450\\
32 & 565 & 379\\
48 & 479 & 312 \\
64 & 423 & 292\\
\bottomrule
\end{tabular}
\end{table}
 
\section{Simulation \& Test}
 
The simulation and automated tests were performed using Modelsim. For that, a testbench (\verb|tb_ternary_adder.vhd|) was created which uses a random number generator together with assert statements to verify the designs. To automate the different FPGA targets the do-file \verb|batch_sim.do| was created which compiles the designs and applies the tests for each target as specified in the do-file \verb|sim_single_inst.do|. These tests include different word sizes, subtractions and the output flip flop functionality. All tests can be started from command line using \verb|vsim -c -do 'do batch_sim.do'| (as defined in \verb|modelsim_batch_sim.sh|).
 
\bibliographystyle{alpha}
\bibliography{ternary_adder}
 
\end{document}
 
 
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + FA + + + + + + FA + + + + + + + + + + + + + + + + + + + + + FA + + + FA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FA + + + + + + + FA + + + + + + + + + + + + + + + + ALMLUT + + + + FA + + + + + + + + + + + + + + + + + + + + FA + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/doc/images/ternary_adder_xilinx.svg =================================================================== --- trunk/doc/images/ternary_adder_xilinx.svg (nonexistent) +++ trunk/doc/images/ternary_adder_xilinx.svg (revision 2) @@ -0,0 +1,5578 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + + + 0 + 1 + + + + SliceLUT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 0 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FA + + + + + + + + + + + + + + + + + 0 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CarryLogic + + + + + + 0 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/doc/ternary_adder.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/ternary_adder.pdf =================================================================== --- trunk/doc/ternary_adder.pdf (nonexistent) +++ trunk/doc/ternary_adder.pdf (revision 2)
trunk/doc/ternary_adder.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/ternary_adder.bib =================================================================== --- trunk/doc/ternary_adder.bib (nonexistent) +++ trunk/doc/ternary_adder.bib (revision 2) @@ -0,0 +1,32 @@ +% This file was created with JabRef 2.6. +% Encoding: UTF8 + +@ARTICLE{blsy09, + author = {Baeckler, Gregg and Langhammer, Martin and Schleicher, James and + Yuan, Richard}, + title = {{Logic Cell Supporting Addition of Three Binary Words}}, + journal = {US Patent No 7565388, Altera Coop.}, + year = {2009}, + owner = {pluto}, + timestamp = {2013.02.25} +} + +@ARTICLE{sp07, + author = {Simkins, James M and Philofsky, Brian D}, + title = {{Structures and Methods for Implementing Ternary Adders/Subtractors + in Programmable Logic Devices}}, + journal = {US Patent No 7274211, Xilinx Inc.}, + year = {2006}, + month = mar, + owner = {pluto}, + timestamp = {2013.02.20} +} + +@comment{jabref-meta: selector_publisher:} + +@comment{jabref-meta: selector_author:} + +@comment{jabref-meta: selector_journal:} + +@comment{jabref-meta: selector_keywords:} +
trunk/doc/ternary_adder.bib Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/sim_single_inst.do =================================================================== --- trunk/sim/sim_single_inst.do (nonexistent) +++ trunk/sim/sim_single_inst.do (revision 2) @@ -0,0 +1,50 @@ +echo Testing different word lengths... +vsim -novopt -quiet -Ginput_word_size=2 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=3 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=4 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=5 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=6 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=8 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=10 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=12 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=21 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=30 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +echo Testing subtractions... + +vsim -novopt -quiet -Ginput_word_size=20 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=20 -Gsubtract_y=false -Gsubtract_z=true -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=20 -Gsubtract_y=true -Gsubtract_z=false -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +vsim -novopt -quiet -Ginput_word_size=20 -Gsubtract_y=true -Gsubtract_z=true -Guse_output_ff=false work.tb_ternary_adder; +run $simtime + +echo Testing output FF... + +vsim -novopt -quiet -Ginput_word_size=13 -Gsubtract_y=false -Gsubtract_z=false -Guse_output_ff=true work.tb_ternary_adder; +run $simtime + Index: trunk/sim/batch_sim.do =================================================================== --- trunk/sim/batch_sim.do (nonexistent) +++ trunk/sim/batch_sim.do (revision 2) @@ -0,0 +1,21 @@ +echo Batch script for simulating all test cases... +echo Simulating Altera implementation + +echo Compiling Sources +vcom -work work -2002 -explicit -vopt ../vhdl/ternary_adder_altera.vhd +vcom -work work -2002 -explicit -vopt ../vhdl/tb_ternary_adder.vhd + +set simtime 1us + +do sim_single_inst.do + + +echo Simulating Xilinx implementation + +echo Compiling Sources +vcom -work work -2002 -explicit -vopt ../vhdl/ternary_adder_xilinx.vhd +vcom -work work -2002 -explicit -vopt ../vhdl/tb_ternary_adder.vhd + +do sim_single_inst.do + +quit \ No newline at end of file Index: trunk/sim/modelsim_batch_sim.sh =================================================================== --- trunk/sim/modelsim_batch_sim.sh (nonexistent) +++ trunk/sim/modelsim_batch_sim.sh (revision 2) @@ -0,0 +1,2 @@ +#!/bin/bash +vsim -c -do 'do batch_sim.do'
trunk/sim/modelsim_batch_sim.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/copying =================================================================== --- trunk/copying (nonexistent) +++ trunk/copying (revision 2) @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. 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Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. \ No newline at end of file Index: trunk/vhdl/tb_ternary_adder.vhd =================================================================== --- trunk/vhdl/tb_ternary_adder.vhd (nonexistent) +++ trunk/vhdl/tb_ternary_adder.vhd (revision 2) @@ -0,0 +1,111 @@ +--------------------------------------------------------------------------------------------- +-- Author: Martin Kumm +-- Contact: kumm@uni-kassel.de +-- License: LGPL +-- Date: 04.04.2013 +-- +-- Description: +-- Testbench for testing a single ternary adder component +--------------------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; -- for uniform, trunc functions + +entity tb_ternary_adder is + generic( + input_word_size : integer := 15; + subtract_y : boolean := false; + subtract_z : boolean := true; + use_output_ff : boolean := false + ); +end tb_ternary_adder; + +architecture tb_ternary_adder_arch of tb_ternary_adder is + +signal clk, rst : std_logic := '0'; +signal x,y,z : std_logic_vector(input_word_size-1 downto 0) := (others => '0'); +signal sum : std_logic_vector(input_word_size+1 downto 0) := (others => '0'); + +signal sum_ref,sum_dut: integer := 0; + +begin + dut: entity work.ternary_adder + generic map ( + input_word_size => input_word_size, + subtract_y => subtract_y, + subtract_z => subtract_z, + use_output_ff => use_output_ff + ) + port map ( + clk_i => clk, + rst_i => rst, + x_i => x, + y_i => y, + z_i => z, + sum_o => sum + ); + + clk <= not clk after 5 ns; -- 100 MHz + rst <= '1', '0' after 5 ns; + + process + variable seed1,seed2: positive; + variable rand : real; + variable x_int,y_int,z_int : integer; + begin + uniform(seed1, seed2, rand); + x_int := integer(trunc(rand*real(2**(input_word_size-2)-1))); + uniform(seed1, seed2, rand); + y_int := integer(trunc(rand*real(2**(input_word_size-2)-1))); + uniform(seed1, seed2, rand); + z_int := integer(trunc(rand*real(2**(input_word_size-2)-1))); + x <= std_logic_vector(to_signed(x_int, x'length)); -- rescale, quantize and convert + y <= std_logic_vector(to_signed(y_int, y'length)); -- rescale, quantize and convert + z <= std_logic_vector(to_signed(z_int, z'length)); -- rescale, quantize and convert + wait until clk'event and clk='1'; + end process; + + process(clk,rst,x,y,z) + variable y_sgn,z_sgn,sum_ref_unsync : integer; + begin + if subtract_y = true then + y_sgn := -1*to_integer(signed(y)); + else + y_sgn := to_integer(signed(y)); + end if; + if subtract_z = true then + z_sgn := -1*to_integer(signed(z)); + else + z_sgn := to_integer(signed(z)); + end if; + sum_ref_unsync := to_integer(signed(x)) + y_sgn + z_sgn; + + if use_output_ff = false then + sum_ref <= sum_ref_unsync; + else + if clk'event and clk='1' then + sum_ref <= sum_ref_unsync; + end if; + end if; + + end process; + + process(clk,rst,sum_ref) + begin + end process; + + sum_dut <= to_integer(signed(sum)); + + process + begin + wait for 50 ns; + loop + wait until clk'event and clk='0'; + assert (sum_dut = sum_ref) report "Test failure" severity failure; + wait until clk'event and clk='1'; + end loop; + end process; + +end architecture; \ No newline at end of file
trunk/vhdl/tb_ternary_adder.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/vhdl/ternary_adder_altera.vhd =================================================================== --- trunk/vhdl/ternary_adder_altera.vhd (nonexistent) +++ trunk/vhdl/ternary_adder_altera.vhd (revision 2) @@ -0,0 +1,95 @@ +--------------------------------------------------------------------------------------------- +-- Author: Martin Kumm +-- Contact: kumm@uni-kassel.de +-- License: LGPL +-- Date: 03.04.2013 +-- Compatibility: Altera Arria I,II,V and Stratix II-V FPGAs +-- +-- Description: +-- Implementation of a ternary adder including subtraction of up to two inputs. +-- The output coresponds to sum_o = x_i + y_i + z_i, where the inputs have a word size of +-- 'input_word_size' while the output has a word size of input_word_size+2. +-- +-- Flipflops at the outputs can be activated by setting 'use_output_ff' to true. +-- Signed operation is activated by using the 'is_signed' generic. +-- The inputs y_i and z_i can be negated by setting 'subtract_y' or 'subtract_z' +-- to realize sum_o = x_i +/- y_i +/- z_i. The negation requires no extra resources. +--------------------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ternary_adder is + generic( + input_word_size : integer := 10; + subtract_y : boolean := false; + subtract_z : boolean := false; + use_output_ff : boolean := true + ); + port( + clk_i : in std_logic; + rst_i : in std_logic; + x_i : in std_logic_vector((input_word_size - 1) downto 0); + y_i : in std_logic_vector((input_word_size - 1) downto 0); + z_i : in std_logic_vector((input_word_size - 1) downto 0); + sum_o : out std_logic_vector((input_word_size + 1) downto 0) + ); +end entity; + + +architecture behavior of ternary_adder is + + signal sum : std_logic_vector(input_word_size + 1 downto 0); + signal sum_tmp : std_logic_vector(input_word_size+3 downto 0); + signal x_i_ext : std_logic_vector(input_word_size+1 downto 0); + signal y_i_ext : std_logic_vector(input_word_size+1 downto 0); + signal z_i_ext : std_logic_vector(input_word_size+1 downto 0); + +begin + + add_sub_case1_gen: if subtract_y = false and subtract_z = false generate + sum <= std_logic_vector(resize(signed(x_i),input_word_size+2) + resize(signed(y_i),input_word_size+2) + resize(signed(z_i),input_word_size+2)); + end generate; + + add_sub_case2_gen: if subtract_y = false and subtract_z = true generate + x_i_ext <= x_i & "00"; + y_i_ext <= y_i & "10"; + z_i_ext <= (not z_i) & "10"; + sum_tmp <= std_logic_vector(resize(signed(x_i_ext),input_word_size+4) + resize(signed(y_i_ext),input_word_size+4) + resize(signed(z_i_ext),input_word_size+4)); + sum <= sum_tmp(input_word_size+3 downto 2); + end generate; + + add_sub_case3_gen: if subtract_y = true and subtract_z = false generate + x_i_ext <= x_i & "00"; + y_i_ext <= (not y_i) & "10"; + z_i_ext <= z_i & "10"; + sum_tmp <= std_logic_vector(resize(signed(x_i_ext),input_word_size+4) + resize(signed(y_i_ext),input_word_size+4) + resize(signed(z_i_ext),input_word_size+4)); + sum <= sum_tmp(input_word_size+3 downto 2); + end generate; + + add_sub_case4_gen: if subtract_y = true and subtract_z = true generate + x_i_ext <= x_i & "11"; + y_i_ext <= (not y_i) & "11"; + z_i_ext <= (not z_i) & "11"; + sum_tmp <= std_logic_vector(resize(signed(x_i_ext),input_word_size+4) + resize(signed(y_i_ext),input_word_size+4) + resize(signed(z_i_ext),input_word_size+4)); + sum <= sum_tmp(input_word_size+3 downto 2); + end generate; + + use_output_ff_gen: if use_output_ff = true generate + process(clk_i,rst_i) + begin + if rst_i = '1' then + sum_o <= (others => '0'); + elsif clk_i'event and clk_i='1' then + sum_o <= sum; + end if; + end process; + end generate; + + dont_use_output_ff_gen: if use_output_ff = false generate + sum_o <= sum; + end generate; + + +end architecture;
trunk/vhdl/ternary_adder_altera.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/vhdl/ternary_adder_xilinx.vhd =================================================================== --- trunk/vhdl/ternary_adder_xilinx.vhd (nonexistent) +++ trunk/vhdl/ternary_adder_xilinx.vhd (revision 2) @@ -0,0 +1,478 @@ +--------------------------------------------------------------------------------------------- +-- Author: Jens Willkomm, Martin Kumm +-- Contact: jens.willkomm@student.uni-kassel.de, kumm@uni-kassel.de +-- License: LGPL +-- Date: 15.03.2013 +-- Compatibility: Xilinx FPGAs of Virtex 5-7, Spartan 6 and Series 7 architectures +-- +-- Description: +-- Low level implementation of a ternary adder according to U.S. Patent No 7274211 +-- from Xilinx, which uses the same no of slices than a two input adder. +-- The output coresponds to sum_o = x_i + y_i + z_i, where the inputs have a word size of +-- 'input_word_size' while the output has a word size of input_word_size+2. +-- +-- Flipflops at the outputs can be activated by setting 'use_output_ff' to true. +-- Signed operation is activated by using the 'is_signed' generic. +-- The inputs y_i and z_i can be negated by setting 'subtract_y' or 'subtract_z' +-- to realize sum_o = x_i +/- y_i +/- z_i. The negation requires no extra resources. +--------------------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; + +entity ternary_add_sub_prim is + generic( + input_word_size : integer := 10; + subtract_y : boolean := false; + subtract_z : boolean := false; + use_output_ff : boolean := true; + is_signed : boolean := true + ); + port( + clk_i : in std_logic; + rst_i : in std_logic; + x_i : in std_logic_vector((input_word_size - 1) downto 0); + y_i : in std_logic_vector((input_word_size - 1) downto 0); + z_i : in std_logic_vector((input_word_size - 1) downto 0); + sum_o : out std_logic_vector((input_word_size + 1) downto 0) + ); +end entity; + +architecture behavior of ternary_add_sub_prim is + -- this function calculates the initial carry bit for the bbus + function bbus_init + return std_logic is + variable result : std_logic; + begin + result := '0'; + + if subtract_y or subtract_z then + result := '1'; + end if; + + return result; + end function; + + -- this function calculates the initial carry bit for the carry chain + function cc_init + return std_logic is + variable result : std_logic; + begin + result := '0'; + + if subtract_y and subtract_z then + result := '1'; + end if; + + return result; + end function; + + component slice_setup + generic( + input_word_size : integer := 4; + use_output_ff : boolean := false; + is_initial_slice : boolean := true; + subtract_y : boolean := false; + subtract_z : boolean := false + ); + port( + -- signals for a synchronous circuit + clock : in std_logic; + clock_enable : in std_logic; + clear : in std_logic; + -- the three addends + x_in : in std_logic_vector((input_word_size - 1) downto 0); + y_in : in std_logic_vector((input_word_size - 1) downto 0); + z_in : in std_logic_vector((input_word_size - 1) downto 0); + -- the upper entity is mapping the bbus correctly + -- in initial slice bbus(0) ^= sub / ~add + bbus_in : in std_logic_vector((input_word_size - 1) downto 0); + bbus_out : out std_logic_vector((input_word_size - 1) downto 0); + -- both carrys are for and from the carry chain + -- in the initial slice use carry_in <= '0' always + -- sub/add is done by the bbus(0) from the initial slice + carry_in : in std_logic; + carry_out : out std_logic; + -- the sum of the three addends (x_in + y_in + z_in) + sum_out : out std_logic_vector((input_word_size - 1) downto 0) + ); + end component; + + -- calculate the needed number of slices + constant num_slices : integer := ((input_word_size + 1) / 4) + 1; + + -- defines the initial carry values + -- in the pure addition mode both constants are '0' + -- if one of the input signal is subtracted the carry_bbus is '1' + -- if two input signal are subtracted both constants are '1' + constant carry_bbus : std_logic := bbus_init; + constant carry_cc : std_logic := cc_init; + + -- the input addends with sign extention + signal x : std_logic_vector((input_word_size + 1) downto 0); + signal y : std_logic_vector((input_word_size + 1) downto 0); + signal z : std_logic_vector((input_word_size + 1) downto 0); + + -- the bbus that is routed around the slice + -- this bbus differs from the one in the xilinx paper, + -- per position the input is bbus(n) and the output is bbus(n + 1) + -- this is because of the sub/~add, which is bbus(0) and all the other + -- bbus signals are scrolled one position up + signal bbus : std_logic_vector(input_word_size + 2 downto 0); + -- the carry from every slice to the next one + -- the last slice gives the carry output for the adder + -- carry(n) is the carry of the carry chain of slice n + signal carry : std_logic_vector((num_slices - 1) downto 0); +begin + -- checking the parameter input_word_size + assert (input_word_size > 0) report "an adder with a bit width of " + & integer'image(input_word_size) & " is not possible." severity failure; + + -- adding two bit sign extention to the input addends + extention_signed: if is_signed = true generate + x <= x_i(input_word_size - 1) & x_i(input_word_size - 1) & x_i; + y <= y_i(input_word_size - 1) & y_i(input_word_size - 1) & y_i; + z <= z_i(input_word_size - 1) & z_i(input_word_size - 1) & z_i; + end generate; + + extention_unsigned: if is_signed = false generate + x <= '0' & '0' & x_i; + y <= '0' & '0' & y_i; + z <= '0' & '0' & z_i; + end generate; + + -- the initial bbus carry signal + bbus(0) <= carry_bbus; + + -- generating the slice setups + -- getting all signals into one slice + single_slice: if num_slices = 1 generate + slice_i: slice_setup + generic map( + input_word_size => input_word_size + 2, + use_output_ff => use_output_ff, + is_initial_slice => true, + subtract_y => subtract_y, + subtract_z => subtract_z + ) + port map( + clock => clk_i, + clock_enable => '1', + clear => rst_i, + x_in => x, + y_in => y, + z_in => z, + bbus_in => bbus(input_word_size + 1 downto 0), + -- scrolling bbus_out one position up + bbus_out => bbus(input_word_size + 2 downto 1), + carry_in => carry_cc, + carry_out => carry(0), + sum_out => sum_o(input_word_size + 1 downto 0) + ); + end generate; + + -- make more slices to calculate all signals + multiple_slices: if num_slices > 1 generate + slices: for i in 0 to (num_slices - 1) generate + -- generate the first slice + first_slice: if i = 0 generate + slice_i: slice_setup + generic map( + input_word_size => 4, + use_output_ff => use_output_ff, + is_initial_slice => true, + subtract_y => subtract_y, + subtract_z => subtract_z + ) + port map( + clock => clk_i, + clock_enable => '1', + clear => rst_i, + x_in => x(3 downto 0), + y_in => y(3 downto 0), + z_in => z(3 downto 0), + bbus_in => bbus(3 downto 0), + -- scrolling bbus_out one position upwards + bbus_out => bbus(4 downto 1), + carry_in => carry_cc, + carry_out => carry(0), + sum_out => sum_o(3 downto 0) + ); + end generate; + + -- generate all full slices + full_slice: if i > 0 and i < (num_slices - 1) generate + slice_i: slice_setup + generic map( + input_word_size => 4, + use_output_ff => use_output_ff, + is_initial_slice => false, + subtract_y => subtract_y, + subtract_z => subtract_z + ) + port map( + clock => clk_i, + clock_enable => '1', + clear => rst_i, + x_in => x((4 * i) + 3 downto 4 * i), + y_in => y((4 * i) + 3 downto 4 * i), + z_in => z((4 * i) + 3 downto 4 * i), + bbus_in => bbus((4 * i) + 3 downto 4 * i), + -- scrolling bbus_out one position upwards + bbus_out => bbus((4 * i) + 4 downto (4 * i) + 1), + carry_in => carry(i - 1), + carry_out => carry(i), + sum_out => sum_o((4 * i) + 3 downto 4 * i) + ); + end generate; + + -- generate the last slice + last_slice: if i = (num_slices - 1) generate + slice_i: slice_setup + generic map( + input_word_size => (input_word_size + 2) - (i * 4), + use_output_ff => use_output_ff, + is_initial_slice => false, + subtract_y => subtract_y, + subtract_z => subtract_z + ) + port map( + clock => clk_i, + clock_enable => '1', + clear => rst_i, + x_in => x(input_word_size + 1 downto 4 * i), + y_in => y(input_word_size + 1 downto 4 * i), + z_in => z(input_word_size + 1 downto 4 * i), + bbus_in => bbus(input_word_size + 1 downto 4 * i), + -- scrolling bbus_out one position up + bbus_out => bbus(input_word_size + 2 downto (4 * i) + 1), + carry_in => carry(i - 1), + carry_out => carry(i), + sum_out => sum_o(input_word_size + 1 downto 4 * i) + ); + end generate; + end generate; + end generate; +end architecture; + +--- Definition of the slice_setup component which configures a single slice --- + +library unisim; +use unisim.vcomponents.all; -- loading xilinx primitives + +library ieee; +use ieee.std_logic_1164.all; -- loading std_logic & std_logic_vector + +entity slice_setup is + generic( + input_word_size : integer := 4; + use_output_ff : boolean := false; + is_initial_slice : boolean := true; + subtract_y : boolean := false; + subtract_z : boolean := false + ); + port( + -- signals for a synchronous circuit + clock : in std_logic; + clock_enable : in std_logic; + clear : in std_logic; + -- the three addends + x_in : in std_logic_vector((input_word_size - 1) downto 0); + y_in : in std_logic_vector((input_word_size - 1) downto 0); + z_in : in std_logic_vector((input_word_size - 1) downto 0); + -- the upper entity is mapping the bbus correctly + -- in initial slice bbus(0) ^= sub / ~add + bbus_in : in std_logic_vector((input_word_size - 1) downto 0); + bbus_out : out std_logic_vector((input_word_size - 1) downto 0); + -- both carrys are for and from the carry chain + -- in the initial slice use carry_in <= '0' always + -- sub/add is done by the bbus(0) from the initial slice + carry_in : in std_logic; + carry_out : out std_logic; + -- the sum of the three addends (x_in + y_in + z_in) + sum_out : out std_logic_vector((input_word_size - 1) downto 0) + ); +end entity; + +architecture behavior of slice_setup is + -- this function returns the lut initialization + function get_lut_init + return bit_vector is + -- defines several lut configurations + -- for init calculation see "initializing_primitives.ods" + constant lut_init_no_sub : bit_vector(63 downto 0) := x"3cc3c33cfcc0fcc0"; + constant lut_init_sub_y : bit_vector(63 downto 0) := x"c33c3cc3cf0ccf0c"; + constant lut_init_sub_z : bit_vector(63 downto 0) := x"c33c3cc3f330f330"; + constant lut_init_sub_yz : bit_vector(63 downto 0) := x"3cc3c33c3f033f03"; + variable curr_lut : bit_vector(63 downto 0) := lut_init_no_sub; + begin + curr_lut := lut_init_no_sub; + + if subtract_y then + curr_lut := lut_init_sub_y; + end if; + + if subtract_z then + curr_lut := lut_init_sub_z; + end if; + + if subtract_y and subtract_z then + curr_lut := lut_init_sub_yz; + end if; + + return curr_lut; + end function; + + -- calculate how many bits to fill up with zeros for the carry chain + constant fillup_width : integer := 4 - input_word_size; + + -- holds the lut configuration used in this slice + constant current_lut_init : bit_vector := get_lut_init; + + -- output o6 of the luts + signal lut_o6 : std_logic_vector((input_word_size - 1) downto 0); + -- the signals for and from the carry chain have to be wrapped into signals + -- with a width of four, to fill them up with zeros and prevent synthesis + -- warnings when doing this in the port map of the carry chain + -- input di of the carry chain (have to be four bits width) + signal cc_di : std_logic_vector(3 downto 0); + -- input s of the carry chain (have to be four bits width) + signal cc_s : std_logic_vector(3 downto 0); + -- output o of the carry chain (have to be four bits width) + signal cc_o : std_logic_vector(3 downto 0); + -- output co of the carry chain (have to be four bits width) + signal cc_co : std_logic_vector(3 downto 0); +begin + -- check the generic parameter + assert (input_word_size > 0 and input_word_size < 5) report "a slice with a bit width of " + & integer'image(input_word_size) & " is not possible." severity failure; + + -- prepairing singals for the carry chain + full_slice_assignment: if input_word_size = 4 generate + cc_di <= bbus_in; + cc_s <= lut_o6; + end generate; + + last_slice_assignment: if input_word_size < 4 generate + cc_di <= (fillup_width downto 1 => '0') & bbus_in; + cc_s <= (fillup_width downto 1 => '0') & lut_o6; + end generate; + + -- creating the lookup tables + luts: for i in 0 to (input_word_size - 1) generate + -- lut6_2 primitive is described in virtex 6 user guide on page 215: + -- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf + lut_bit_i: lut6_2 + generic map( + init => current_lut_init + ) + ------------------------------------------------------------------- + -- table of names and connections + -- user guide us 7,274,211 usage in adder + -- ---------- ------------ -------------- + -- i0 in1 gnd + -- i1 in2 z(n) + -- i2 in3 y(n) + -- i3 in4 x(n) + -- i4 in5 bbus(n-1) + -- i5 in6 vdd + -- o5 o5 + -- o6 o6 + ------------------------------------------------------------------- + port map( + i0 => '0', + i1 => z_in(i), + i2 => y_in(i), + i3 => x_in(i), + i4 => bbus_in(i), + i5 => '1', + o5 => bbus_out(i), + o6 => lut_o6(i) + ); + end generate; + + -- creating the carry chain + -- carry4 primitive is described in virtex 6 user guide on page 108: + -- http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/virtex6_hdl.pdf + initial_slice: if is_initial_slice = true generate + init_cc: carry4 + ------------------------------------------------------------------- + -- table of names and connections + -- user guide usage in adder + -- ---------- -------------- + -- co msb is carry out, rest is not connected + -- o sum + -- ci in the initial slice: not connected + -- cyinit in the initial slice: add / ~sub + -- di bbus(n-1) + -- s lut_o6(n) + ------------------------------------------------------------------- + port map( + co => cc_co, + o => cc_o, + cyinit => '0', + ci => carry_in, + di => cc_di, + s => cc_s + ); + end generate; + + further_slice: if is_initial_slice = false generate + further_cc: carry4 + ------------------------------------------------------------------- + -- table of names and connections + -- user guide usage in adder + -- ---------- -------------- + -- co msb is carry out, rest is not connected + -- o sum + -- ci carry from previous slice + -- cyinit in further slices: not connected + -- di bbus(n-1) + -- s lut_o6(n) + ------------------------------------------------------------------- + port map( + co => cc_co, + o => cc_o, + cyinit => '0', + ci => carry_in, + di => cc_di, + s => cc_s + ); + end generate; + + -- connect the last used output of the carry chain to the slice output + carry_out <= cc_co(input_word_size - 1); + + -- creating the flip flops + sum_register: if use_output_ff = true generate + ffs: for i in 0 to (input_word_size - 1) generate + ff_i: fdce + generic map( + -- initialize all flip flops with '0' + init => '0' + ) + ------------------------------------------------------------------- + -- table of names and connections + -- user guide usage in adder + -- ---------- -------------- + -- clr clear + -- ce clock_enable, always '1' + -- d cc_o + -- c clock + -- q sum(n) + ------------------------------------------------------------------- + port map( + clr => clear, + ce => clock_enable, + d => cc_o(i), + c => clock, + q => sum_out(i) + ); + end generate; + end generate; + + -- bypassing the flip flops in case of a asynchronous circuit + bypass: if use_output_ff = false generate + sum_out <= cc_o(input_word_size - 1 downto 0); + end generate; +end architecture;
trunk/vhdl/ternary_adder_xilinx.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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