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URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

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  • This comparison shows the changes necessary to convert path 
    /tinycpu/trunk
    from Rev 37 to Rev 38
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Rev 37 → Rev 38

/src/memory.vhd
81,7 → 81,7
end if;
end process;
assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address)
assignram: process (we, datawrite, addr, r1out, port0, WriteEnable, Address, Clock)
variable tmp: integer;
variable tmp2: integer;
variable found: boolean := false;
89,47 → 89,55
tmp := to_integer(unsigned(addr));
tmp2 := to_integer(unsigned(Address));
if tmp2 <= 15 then --internal registers/mapped IO
if WriteWord='0' then
if tmp2=0 then
dataread <= x"0000";
gen: for I in 0 to 7 loop
if rising_edge(Clock) then
if WriteWord='0' then
if tmp2=0 then
dataread <= x"0000";
gen: for I in 0 to 7 loop
if WriteEnable='1' then
if port0we(I)='1' then --1-bit port set to WRITE mode
port0(I) <= DataIn(I);
port0temp(I) <= DataIn(I);
else
port0(I) <= 'Z';
end if;
else --not WE
if port0we(I)='0' then --1-bit-port set to READ mode
dataread(I) <= port0(I);
else
dataread(I) <= port0temp(I);
end if;
end if;
end loop gen;
elsif tmp2=1 then
dataread <= x"00" & port0we;
if WriteEnable='1' then
if port0we(I)='1' then --1-bit port set to WRITE mode
port0(I) <= DataIn(I);
port0temp(I) <= DataIn(I);
else
port0(I) <= 'Z';
end if;
else --not WE
if port0we(I)='0' then --1-bit-port set to READ mode
dataread(I) <= port0(I);
else
dataread(I) <= port0temp(I);
end if;
port0we <= DataIn(7 downto 0);
setwe: for I in 0 to 7 loop
if DataIn(I)='0' then
port0(I) <= 'Z';
end if;
end loop setwe;
else
dataread <= x"00" & port0we;
end if;
end loop gen;
elsif tmp2=1 then
dataread <= x"00" & port0we;
if WriteEnable='1' then
port0we <= DataIn(7 downto 0);
setwe: for I in 0 to 7 loop
if DataIn(I)='0' then
port0(I) <= 'Z';
end if;
end loop setwe;
else
dataread <= x"00" & port0we;
--synthesis off
report "Memory address is outside of bounds of RAM and registers" severity warning;
--synthesis on
end if;
else
--synthesis off
report "Memory address is outside of bounds of RAM and registers" severity warning;
report "WriteWord is not allowed in register area. Ignoring access" severity warning;
--synthesis on
end if;
else
--synthesis off
report "WriteWord is not allowed in register area. Ignoring access" severity warning;
--synthesis on
end if;
R1en <= '0';
R1we <= "00";
R1in <= x"0000";
R1addr <= x"00";
elsif tmp >= R1START and tmp <= R1END then --RAM bank1
--map all to R1
found := true;
/assembler/asm.rb
18,6 → 18,19
end
end
 
class OpcodeByte2
attr_accessor :cond, :reg2, :useextra, :reg3;
def to_hex
s=(cond << 8 | reg2.number << 5 | useextra << 4 | reg3.number).to_s(16);
if s.length == 1
"0"+s;
elsif s.length==0
"00";
else
s;
end
end
end
 
class Register8
26,6 → 39,12
@number=num
end
end
class OpcodeOption
attr_accessor :number
def initialize(num)
@number=num;
end
end
 
$iftr = 0; #0 for no condition, 1 for if TR, 2 for if not TR
$useextra = 0;
54,6 → 73,7
puts PREFIX + o.to_hex + imm.to_s(16) + SUFFIX;
puts SEPERATOR;
end
def
 
def mov(arg1,arg2)
81,7 → 101,12
r1=Register8.new(1)
r2=Register8.new(2)
r3=Register8.new(3)
r4=Register8.new(4)
r5=Register8.new(5)
sp=Register8.new(6)
ip=Register8.new(7)
 
 
#test code follows. Only do it here for convenience.. real usage should prefix assembly files with `require "asm.rb"`
if_tr_set{
mov r1,0x10

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