URL
https://opencores.org/ocsvn/trigonometric_functions_in_double_fpu/trigonometric_functions_in_double_fpu/trunk
Subversion Repositories trigonometric_functions_in_double_fpu
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/trigonometric_functions_in_double_fpu
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/simulation/fpu.vcd
0,0 → 1,2255
$date |
Thu Jun 20 13:36:24 2013 |
$end |
|
$version |
Synopsys VCS version E-2011.03 |
$end |
|
$timescale |
100ps |
$end |
|
$comment Csum: 1 2f950e5beda142b3 $end |
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$scope module $unit $end |
$upscope $end |
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$scope module top_tb $end |
$var reg 1 ! enable $end |
$var reg 32 " degrees [31:0] $end |
$var reg 1 # rst $end |
$var reg 3 $ actv [2:0] $end |
$var reg 1 % clk $end |
$var wire 64 & data1 [63:0] $end |
|
$scope module u1 $end |
$var wire 1 ! enable $end |
$var wire 32 " degrees [31:0] $end |
$var wire 1 # rst $end |
$var wire 3 $ actv [2:0] $end |
$var wire 1 % clk $end |
$var reg 64 ' data1 [63:0] $end |
$var reg 64 ( data [63:0] $end |
$var reg 32 ) half_wave [31:0] $end |
$var reg 32 * full_wave [31:0] $end |
$var reg 64 + data_tmp [63:0] $end |
$var reg 32 , degrees_tmp1 [31:0] $end |
$var reg 32 - degrees_tmp2 [31:0] $end |
$var reg 2 . quad [1:0] $end |
$var reg 1 / sin_enable $end |
$var reg 1 0 cos_enable $end |
$var reg 1 1 tan_enable $end |
$var reg 1 2 csc_enable $end |
$var reg 1 3 sec_enable $end |
$var reg 1 4 cot_enable $end |
$var wire 64 5 data_sin [63:0] $end |
$var wire 64 6 data_cos [63:0] $end |
$var wire 64 7 data_tan [63:0] $end |
$var wire 64 8 data_csc [63:0] $end |
$var wire 64 9 data_sec [63:0] $end |
$var wire 64 : data_cot [63:0] $end |
$var wire 32 ; divider_out [31:0] $end |
|
$scope module a1 $end |
$var wire 2 . quad [1:0] $end |
$var wire 1 / enable $end |
$var wire 1 # rst $end |
$var wire 32 - degrees [31:0] $end |
$var wire 1 % clk $end |
$var reg 64 < data [63:0] $end |
$upscope $end |
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|
$scope module a2 $end |
$var wire 2 . quad [1:0] $end |
$var wire 1 0 enable $end |
$var wire 1 # rst $end |
$var wire 32 - degrees [31:0] $end |
$var wire 1 % clk $end |
$var reg 64 = data [63:0] $end |
$upscope $end |
|
|
$scope module a3 $end |
$var wire 2 . quad [1:0] $end |
$var wire 1 1 enable $end |
$var wire 1 # rst $end |
$var wire 1 % clk $end |
$var wire 32 - degrees [31:0] $end |
$var reg 64 > data [63:0] $end |
$upscope $end |
|
|
$scope module a4 $end |
$var wire 2 . quad [1:0] $end |
$var wire 1 2 enable $end |
$var wire 1 # rst $end |
$var wire 32 - degrees [31:0] $end |
$var wire 1 % clk $end |
$var reg 64 ? data [63:0] $end |
$upscope $end |
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|
$scope module a5 $end |
$var wire 2 . quad [1:0] $end |
$var wire 1 3 enable $end |
$var wire 1 # rst $end |
$var wire 32 - degrees [31:0] $end |
$var wire 1 % clk $end |
$var reg 64 @ data [63:0] $end |
$upscope $end |
|
|
$scope module a6 $end |
$var wire 2 . quad [1:0] $end |
$var wire 1 4 enable $end |
$var wire 1 # rst $end |
$var wire 32 - degrees [31:0] $end |
$var wire 1 % clk $end |
$var reg 64 A data [63:0] $end |
$upscope $end |
|
|
$scope module a7 $end |
$var wire 1 % clk $end |
$var wire 32 " inp [31:0] $end |
$var wire 1 # rst $end |
$var reg 32 B out [31:0] $end |
$upscope $end |
|
$upscope $end |
|
$upscope $end |
|
$enddefinitions $end |
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trunk/simulation/simuation for u1 instantiation.jpg
Property changes :
Added: svn:mime-type
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Index: trunk/simulation/simulation for top.jpg
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/simulation/simulation for top.jpg
===================================================================
--- trunk/simulation/simulation for top.jpg (nonexistent)
+++ trunk/simulation/simulation for top.jpg (revision 10)
trunk/simulation/simulation for top.jpg
Property changes :
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## -0,0 +1 ##
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