URL
https://opencores.org/ocsvn/uart16750/uart16750/trunk
Subversion Repositories uart16750
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- This comparison shows the changes necessary to convert path
/uart16750
- from Rev 23 to Rev 24
- ↔ Reverse comparison
Rev 23 → Rev 24
/trunk/rtl/vhdl/uart_16750.vhd
3,7 → 3,7
-- |
-- Author: Sebastian Witt |
-- Date: 29.01.2008 |
-- Version: 1.4 |
-- Version: 1.5 |
-- |
-- History: 1.0 - Initial version |
-- 1.1 - THR empty interrupt register connected to RST |
10,6 → 10,7
-- 1.2 - Registered outputs |
-- 1.3 - Automatic flow control |
-- 1.4 - De-assert IIR FIFO64 when FIFO is disabled |
-- 1.5 - Inverted low active outputs when RST is active |
-- |
-- |
-- This code is free software; you can redistribute it and/or |
971,13 → 972,13
UART_OUTREGS: process (CLK, RST) |
begin |
if (RST = '1') then |
DDIS <= '0'; |
BAUDOUTN <= '0'; |
OUT1N <= '0'; |
OUT2N <= '0'; |
RTSN <= '0'; |
DTRN <= '0'; |
SOUT <= '0'; |
DDIS <= '1'; |
BAUDOUTN <= '1'; |
OUT1N <= '1'; |
OUT2N <= '1'; |
RTSN <= '1'; |
DTRN <= '1'; |
SOUT <= '1'; |
elsif (CLK'event and CLK = '1') then |
-- Default values |
DDIS <= '0'; |