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URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

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  • This comparison shows the changes necessary to convert path
    /uart2bus_testbench/trunk/tb/test
    from Rev 13 to Rev 14
    Reverse comparison

Rev 13 → Rev 14

/uart_test.svh
20,6 → 20,7
// 1 HANY SALAH 10012016 FILE CREATION
// 2 HANY SALAH 20012016 ADD BINARY MODE TESTS AND INVALID TESTS
// 3 HANY SALAH 12022016 IMPROVE BLOCK DESCRIPTION & ADD COMMENTS
// 4 HANY SALAH 26062017 ADD COVERAGE DRIVEN TEST
//-------------------------------------------------------------------------------------------------
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION
65,6 → 66,10
int matched ;
 
uvm_report_server report_server;
 
int hit_text_cov=90;
int hit_bin_cov=90;
int hit_mode_cov=90;
`uvm_component_utils_begin(uart_base_test)
`uvm_field_int(matched,UVM_ALL_ON)
86,7 → 91,9
env_configuration();
TE_configuration();
uvm_config_db#(uart_config)::set(this,"*","UART_CONFIGURATION",_config);
uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","text_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","binary_coverage",0,null);
uvm_resource_db #(int)::set("coverage_cloud","general_coverage",0,null);
endfunction:build_phase
 
function void connect_phase (uvm_phase phase);
635,7 → 642,7
//
//-------------------------------------------------------------------------------------------------
 
class all_tests extends uart_base_test;
class cover_driven_test extends uart_base_test;
 
rand int unsigned testnumber;
643,7 → 650,7
 
int iteration=0;
parameter MAX_ITER=10000;
parameter MAX_ITER=500;
// Text write tests
seq_1p1 seq1;
704,10 → 711,14
seq_7p2 seq45;
 
`uvm_component_utils(all_tests)
`uvm_component_utils(cover_driven_test)
 
constraint validtest{testnumber inside{[0:45]};
testnumber != 13;}
testnumber != 13;
testnumber != 9;
testnumber != 19;
testnumber != 21;
testnumber != 24;}
function new (string name,uvm_component parent);
super.new(name,parent);
766,7 → 777,8
task run_phase (uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
while(coverage_hit==1'b0 && (iteration < MAX_ITER) ) begin
while(coverage_hit==1'b0 && (iteration < MAX_ITER)) begin
// while(iteration < 1000) begin
iteration++;
randomize();
case(testnumber)
965,19 → 977,32
endtask // run_phase
function void evaluate_coverage();
int text_coverage;
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_coverage);
if(text_coverage >= 80) coverage_hit=1'b1;
int text_cov;
int bin_cov;
int mode_cov;
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
if((text_cov >= hit_text_cov) &&
(bin_cov >= hit_bin_cov) &&
(mode_cov >= hit_mode_cov)) coverage_hit=1'b1;
endfunction // evaluate_coverage
 
function void report_phase(uvm_phase phase);
int coverage;
int text_cov;
int mode_cov;
int bin_cov;
super.report_phase(phase);
if(!(iteration<MAX_ITER))
begin
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",coverage);
`uvm_warning("SIM",$sformatf("coverage not hit and reached %0d",coverage));
uvm_resource_db#(int)::read_by_name("coverage_cloud","text_coverage",text_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","binary_coverage",bin_cov);
uvm_resource_db#(int)::read_by_name("coverage_cloud","general_coverage",mode_cov);
`uvm_warning("SIM",$sformatf("coverage not hit and reached \n textcov:%0d\nmodecov:%0d\nbincov:%0d",text_cov,mode_cov,bin_cov));
end
else begin
`uvm_info("SIM",$sformatf("Simulation hit the coverage successfully by %0d transactions",iteration),UVM_NONE);
end
endfunction // report_phase
endclass // all_tests
endclass // cover_driven_test

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