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https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk
Subversion Repositories uart2bus_testbench
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/uart2bus_testbench/trunk/tb
- from Rev 3 to Rev 4
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Rev 3 → Rev 4
/agent/coverage/uart_coverage.svh
0,0 → 1,129
//------------------------------------------------------------------------------------------------- |
// |
// UART2BUS VERIFICATION |
// |
//------------------------------------------------------------------------------------------------- |
// CREATOR : HANY SALAH |
// PROJECT : UART2BUS UVM TEST BENCH |
// UNIT : AGENT |
//------------------------------------------------------------------------------------------------- |
// TITLE : UART Coverage |
// DESCRIPTION: THIS BLOCK INCLUDES ALL THE COVERPINS THAT ARE SAMPLED EACH STIMULUS |
//------------------------------------------------------------------------------------------------- |
// LOG DETAILS |
//------------- |
// VERSION NAME DATE DESCRIPTION |
// 1 HANY SALAH 08022016 FILE CREATION |
// 2 HANY SALAH 11022016 IMPROVE BLOCK DESCRIPTION & ADD CODE COMMENTS |
//------------------------------------------------------------------------------------------------- |
// ALL COPYRIGHTS ARE RESERVED FOR THE PRODUCER ONLY .THIS FILE IS PRODUCED FOR OPENCORES MEMBERS |
// ONLY AND IT IS PROHIBTED TO USE THIS MATERIAL WITHOUT THE CREATOR'S PERMISSION |
//------------------------------------------------------------------------------------------------- |
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class uart_coverage extends uvm_component; |
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`uvm_component_utils(uart_coverage) |
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uart_transaction trans,_trans; |
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uvm_analysis_export #(uart_transaction) cov_mon; |
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uvm_tlm_analysis_fifo #(uart_transaction) mon_fifo; |
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covergroup trans_attrib; |
communication_mode: |
coverpoint trans._mode{ |
bins valid_mode = {text,binary}; |
bins invalid_mode = {wrong_mode_text,wrong_mode_bin}; |
} |
address: |
coverpoint trans.address; |
false_data: |
coverpoint trans.false_data_en; |
unknown_prefix: |
coverpoint trans.wrong_prefix; |
endgroup:trans_attrib |
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covergroup text_mode_cov; |
command: |
coverpoint trans._command{ |
bins valid_command ={read,write}; |
illegal_bins invalid_command={nop,invalid_read,invalid_write}; |
} |
first_white_space_field: |
coverpoint trans._spacetype1; |
second_white_space_field: |
coverpoint trans._spacetype2; |
end_of_line_field: |
coverpoint trans._eoltype; |
prefix_character_type: |
coverpoint trans._chartype; |
endgroup:text_mode_cov |
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covergroup binary_mode_cov; |
command: |
coverpoint trans._command{ |
bins normal_command={read,write,nop}; |
bins wrong_command ={invalid_read,invalid_write}; |
} |
acknowledge_requirement: |
coverpoint trans._reqack; |
incremental_address_requirement: |
coverpoint trans._reqinc; |
Length_of_data: |
coverpoint trans.length_data{ |
bins zero = {0}; |
bins valid = {[1:256]}; |
illegal_bins invalid= {[257:$]}; |
} |
endgroup:binary_mode_cov |
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function new (string name, uvm_component parent); |
super.new(name,parent); |
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trans_attrib = new(); |
text_mode_cov = new(); |
binary_mode_cov = new(); |
endfunction:new |
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extern function void build_phase(uvm_phase phase); |
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extern function void connect_phase (uvm_phase phase); |
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extern task run_phase (uvm_phase); |
endclass:uart_coverage |
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function void uart_coverage::build_phase (uvm_phase phase); |
super.build_phase(phase); |
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trans = uart_transaction::type_id::create("trans"); |
_trans = uart_transaction::type_id::create("_trans"); |
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cov_mon = new ("cov_mon",this); |
mon_fifo = new ("mon_fifo",this); |
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endfunction:build_phase |
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function void uart_coverage::connect_phase(uvm_phase phase); |
cov_mon.connect(mon_fifo.analysis_export); |
endfunction:connect_phase |
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task uart_coverage::run_phase(uvm_phase phase); |
forever |
begin |
mon_fifo.get(_trans); |
$cast(trans,_trans.clone()); |
trans_attrib.sample(); |
if(trans._mode == text) |
begin |
text_mode_cov.sample(); |
end |
else if (trans._mode == binary) |
begin |
binary_mode_cov.sample(); |
end |
end |
endtask:run_phase |