OpenCores

/trunk/rtl/top/top.v

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/trunk/verif/log/run_modelsim.log

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/trunk/verif/models/st_m25p16/parameter.v

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/trunk/verif/models/st_m25p16/release notes.txt

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/trunk/verif/models/st_m25p16/m25p16_driver.v

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/trunk/verif/models/st_m25p16/readme.txt

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/trunk/verif/models/st_m25p16/acdc_check.v

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/trunk/verif/models/st_m25p16/memory_access.v

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trunk/verif/models/st_m25p16/memory_access.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/models/st_m25p16/internal_logic.v =================================================================== --- trunk/verif/models/st_m25p16/internal_logic.v (nonexistent) +++ trunk/verif/models/st_m25p16/internal_logic.v (revision 3) @@ -0,0 +1,1597 @@ +// Author: Hugues CREUSY modified by Xue feng +// June 2004 +// Verilog model +// project: M25P16 50 MHz, +// release: 1.2 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns +`include "parameter.v" + +module internal_logic (c, d, w, s, hold, data_to_read, q, data_to_write, page_add_index, add_mem, write_op, read_op, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, srwd_wrsr,write_protect, wrsr); + //////////////////////////////// + // declaration of the parameters + //////////////////////////////// + input c; + input d; + input w; + input s; + input hold; + input[(`NB_BIT_DATA - 1):0] data_to_read; + + output q; + reg q; + + output[(`NB_BIT_DATA - 1):0] data_to_write; + reg[(`NB_BIT_DATA - 1):0] data_to_write; + + output[(`LSB_TO_CODE_PAGE - 1):0] page_add_index; // position to write data_to_write inside the page + reg[(`LSB_TO_CODE_PAGE - 1):0] page_add_index; + + output[(`NB_BIT_ADD_MEM - 1):0] add_mem; + reg[(`NB_BIT_ADD_MEM - 1):0] add_mem; + + output write_op; + reg write_op; + + output read_op; + reg read_op; + + output be_enable; + reg be_enable; + + output se_enable; + reg se_enable; + + output add_pp_enable; + reg add_pp_enable; + + output pp_enable; + reg pp_enable; + + output read_enable; + reg read_enable; + + output data_request; + reg data_request; + + output srwd_wrsr; + reg srwd_wrsr; + + output write_protect; + reg write_protect; + + output wrsr; + reg wrsr; + + + /////////////////////////////////////////////// + // declaration of internal variables + /////////////////////////////////////////////// + reg only_rdsr; + reg only_res; + //reg write_protect; + reg write_protect_toggle; + reg select_ok; + reg raz; + reg byte_ok; + reg wren; + reg wrdi; + reg rdsr; + // reg wrsr; + reg read_data; + reg fast_read; + reg pp; + reg se; + reg be; + reg dp; + reg res; + reg rdid; + reg q_bis; + reg protect; + reg wr_cycle; + reg hold_cond; + reg inhib_wren; + reg inhib_wrdi; + reg inhib_rdsr; + reg inhib_wrsr; + reg inhib_read; + reg inhib_pp; + reg inhib_se; + reg inhib_be; + reg inhib_dp; + reg inhib_res; + reg inhib_rdid; + reg reset_wel; + reg wel; + reg wip; + reg c_int; + reg[4:0] bit_id; //modified by xue-feng hu + reg [23:0] id; //modified by xue-feng hu + + reg [2:0] cpt; + reg [2:0] bit_index; // to allow shift inside a byte + reg [2:0] bit_res; // to allow shift inside signature + reg [2:0] bit_register; // to allow shift inside status register + reg [2:0] k; // to allow shift inside a byte + + reg [7:0] data; + reg [7:0] adress_1; + reg [7:0] adress_2; + reg [7:0] adress_3; + reg [7:0] sr_mask; + reg [7:0] signature; + reg [7:0] manufacturerID; + reg [7:0] memtype; + reg [7:0] density; + + + reg [(`NB_BIT_DATA-1):0] wr_latch; + reg [(`NB_BIT_DATA-1):0] page_ini; + reg [(`NB_BIT_DATA-1):0] data_latch; + reg [(`NB_BIT_DATA-1):0] register_bis; + reg [(`NB_BIT_DATA-1):0] register_temp; + reg [(`NB_BIT_DATA-1):0] status_register; + + reg [(`NB_BPI-1):0] bp; + reg [(`NB_BIT_ADD_MEM-1):0] adress; + reg [(`BIT_TO_CODE_MEM-1):0] cut_add; + reg [(`LSB_TO_CODE_PAGE -1) :0] lsb_adress; + + integer byte_cpt; + integer int_add; + integer i,j; + integer count_enable; + + time t_only_res ; + time t_write_protect_toggle; + + initial + begin + //////////////////////////////////////////// + // Initialization of the internal variables + //////////////////////////////////////////// + only_rdsr = `FALSE; + only_res = `FALSE; + write_protect = `FALSE; + select_ok = `FALSE; + raz = `FALSE; + byte_ok = `FALSE; + + cpt = 0; + byte_cpt = 0; + + data_to_write = 8'bxxxxxxxx; + data_latch = 8'bxxxxxxxx; + data_request <= `FALSE; + + wren = `FALSE; + wrdi = `FALSE; + rdsr = `FALSE; + wrsr = `FALSE; + read_data = `FALSE; + fast_read = `FALSE; + pp = `FALSE; + se = `FALSE; + be = `FALSE; + dp = `FALSE; + res = `FALSE; + rdid = `FALSE; + + q_bis = 1'bz; + + register_bis = 8'b00000000; + wr_latch = 8'b00000000; + + protect = `FALSE; + wr_cycle = `FALSE; + hold_cond = `FALSE; + write_op = `FALSE; + read_op = `FALSE; + + inhib_wren = `FALSE; + inhib_wrdi = `FALSE; + inhib_rdsr = `FALSE; + inhib_wrsr = `FALSE; + inhib_read = `FALSE; + inhib_pp = `FALSE; + inhib_se = `FALSE; + inhib_be = `FALSE; + inhib_dp = `FALSE; + inhib_res = `FALSE; + inhib_rdid = `FALSE; + + add_pp_enable = `FALSE; + read_enable = `FALSE; + pp_enable = `FALSE; + be_enable = `FALSE; + se_enable = `FALSE; + + + count_enable = `FALSE; + data = 8'b00000000; + + // decode process + bit_index = 8'b00000000; + bit_res = 8'b00000000; + bit_register = 8'b00000000; + k = 8'b00000000; + + + bp = `NB_BPI'h0 ; + + int_add = 0; + sr_mask = 8'b10000000; + page_ini = 8'b11111111; + + reset_wel = 1'b0; + wel = 1'b0; + wip = 1'b0; + + signature = `SIGNATURE ; + manufacturerID = `manufacturerID; + memtype = `memtype; + density = `density; + ///////////////////////////////////////////////////////// + id = {manufacturerID,memtype,density}; //modified by xue-feng hu + bit_id = 5'b00000; //modified by xue-feng hu + ////////////////////////////////////////////////////////// + end // initial + + always @(register_bis) status_register = register_bis ; + //assign status_register = register_bis ; // Continuous Assignment + + //----------------------------------------------------------- + // This process generates the Hold condition when it is valid + always + begin : hold_com + @(hold); + begin + if ((hold == 1'b0) && (s == 1'b0)) + begin + if (c == 1'b0) + begin + hold_cond <= `TRUE; + if ($time != 0) $display("%t: NOTE: COMMUNICATION PAUSED",$realtime); + end + else + begin + @(c or hold); + if (c == 1'b0) + begin + hold_cond <= `TRUE; + if ($time != 0) $display("%t: NOTE: COMMUNICATION PAUSED",$realtime); + end + end + end + else if (hold == 1'b1) + begin + if (c == 1'b0) + begin + hold_cond <= `FALSE; + if ($time != 0) $display("%t: NOTE: COMMUNICATION (RE)STARTED",$realtime); + end + else + begin + @(c or hold); + if (c == 1'b0) + begin + hold_cond <= `FALSE; + if ($time != 0) $display("%t: NOTE: COMMUNICATION (RE)STARTED",$realtime); + end + end + end + end + end + + //---------------------------------------------------------------------- + // This process inhibits the internal clock when hold condition is valid + always + begin : horloge + @(c); + begin + if (!hold_cond) + begin + c_int <= c ; + end + else + begin + c_int <= 1'b0 ; + end + end + end + + //--------------------------------------------------------------- + // This process inhibits data output when hold condition is valid + always @(posedge hold_cond ) q <= #`THLQZ 1'bz ; + + always @(negedge hold_cond) q <= #`THHQX q_bis ; + + always @ (q_bis or s) + if (!hold_cond) + begin + q <= q_bis ; + end + + //---------------------------------------------------------- + // This process increments 2 counters: one bit counter (cpt) + // one byte counter (byte_cpt) + always + begin : count_bit_raz + @(raz); + begin + if (raz || !select_ok) + begin + cpt <= 0 ; + byte_cpt <= 0 ; + count_enable = `FALSE; + end + end + end + + always + begin : count_bit_enable + @(posedge c_int or negedge raz); + begin + if (!raz && select_ok) + begin + // count enable is an intermediate variable which allows cpt to be + // constant during a whole period + count_enable = `TRUE; + end + end + end + + + always + begin : count_bit + @(negedge c_int); + begin + if (!raz && select_ok) + begin + if (count_enable) + begin + cpt <= cpt + 1 ; + end + end + end + end + + always @(negedge c_int) + if (byte_ok) + begin + //byte_cpt = (byte_cpt + 1) ; + byte_cpt <= (byte_cpt + 1) ; + end + + //--------------------------------------------------------------------- + // This process latches every byte of data received and returns byte_ok + always + begin : data_in_reset + + @(c_int or select_ok); + begin + if (!select_ok) + begin + raz <= `TRUE ; + byte_ok <= `FALSE ; + data_latch <= 8'b00000000 ; + data = 8'b00000000; + end + end + end + + always + begin : data_in + + @(posedge c_int); + begin + if (select_ok) + begin + raz <= `FALSE ; + if (cpt == 0) + begin + data_latch <= 8'b00000000 ; + byte_ok <= `FALSE ; + end + data[7 - cpt] = d; + if (cpt == 7) + begin + byte_ok <= `TRUE ; + data_latch <= data ; + end + else data_latch <= 8'bxxxxxxxx; + end + end + end + + //------------------------------------------------------------- + //--------------- ASYNCHRONOUS DECODE PROCESS ----------------- + //------------------------------------------------------------- + always + begin : decode + //------------------------- + // status register mask ini + //------------------------- + for(i = 0; i <= (`NB_BPI - 1); i = i + 1) + begin + sr_mask[i + 2] = 1'b1; + end + + + @(byte_ok); + if (byte_ok == 1'b1) + begin + //----------------------------------------------------------- + //-- op_code decode + //----------------------------------------------------------- + if (byte_cpt == 0) + begin + if (data_latch == 8'b00000110) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR :This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + wren <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b00000100) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + wrdi <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b00000101) + begin + if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + rdsr <= `TRUE ; + end + end + else if (data_latch == 8'b00000001) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + wrsr <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b00000011) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + read_data <= `TRUE ; + read_op <= `TRUE ; + end + end + else if (data_latch == 8'b00001011) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + fast_read <= `TRUE ; + end + end + else if (data_latch == 8'b00000010) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + pp <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b11011000) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + se <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b11000111) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + be <= `TRUE ; + write_op <= `TRUE ; + for(i = 0; i <= (`NB_BPI - 1); i = i + 1) + begin + bp[i] = status_register[i + 2]; + end + if (bp != 3'b000) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + end + else if (data_latch == 8'b10111001) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + dp <= `TRUE ; + end + end + else if (data_latch == 8'b10101011) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else + begin + res <= `TRUE ; + end + end + else if (data_latch == 8'b10011111) + begin + if (only_rdsr) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a Prog. Cycle ",$realtime); + end + else if (only_res) + begin + if ($time != 0) $display("%t: ERROR : This Opcode is not decoded during a DEEP POWER DOWN ",$realtime); + end + else + begin + rdid <= `TRUE ; + end + end + else + begin + if ($time != 0) $display("%t: ERROR : False instruction, please retry ",$realtime); + end + end + //--------------------------------------------------------------------- + // addresses and data reception and treatment + //--------------------------------------------------------------------- + if ( (byte_cpt == 1) && (!only_rdsr) && (!only_res)) + begin + if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr)) + begin + adress_1 = data_latch; + end + else if (wrsr && (!rdsr)) + begin + wr_latch <= data_latch ; + end + end + + if ((byte_cpt == 2) && (!only_rdsr) && (!only_res)) + begin + if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr)) + begin + adress_2 = data_latch; + end + end + if ((byte_cpt == 3) && (!only_rdsr) && (!only_res)) + begin + if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr)) + begin + adress_3 = data_latch; + for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1) + begin + adress[i] = adress_3[i]; + adress[i + `NB_BIT_ADD] = adress_2[i]; + adress[i + 2 * `NB_BIT_ADD] = adress_1[i]; + add_mem <= adress ; + end + for(i = (`LSB_TO_CODE_PAGE - 1); i >= 0; i = i - 1) + begin + lsb_adress[i] = adress[i]; + end + end + if ((se || pp) && (!rdsr)) + begin + //----------------------------------------- + // To ignore don't care MSB of the adress + //----------------------------------------- + for(i = 0; i <= `BIT_TO_CODE_MEM -1; i = i + 1) + begin + cut_add[i] = adress[i]; + end + int_add = cut_add; + //------------------------------------------------ + // Sector protection detection + //------------------------------------------------ + for(i = 0; i <= (`NB_BPI - 1); i = i + 1) + begin + bp[i] = status_register[i + 2]; + end + if (bp == 3'b111 || bp == 3'b110) //whole memory write protected + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + else if (bp == 3'b101) // address 100000 to 1FFFFF write protected + begin + if (int_add >= ((`TOP_MEM + 1) / 2)) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + else if (bp == 3'b100) // address 180000 to 1FFFFF write protected + begin + if (int_add >= ((`TOP_MEM + 1) / 4 * 3)) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + else if (bp == 3'b011) //address 1C0000 to 1FFFFF write protected + begin + if (int_add >= ((`TOP_MEM + 1) * 7 / 8)) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + else if (bp == 3'b010) //address 1E0000 to 1FFFFF write protected + begin + if (int_add >= ((`TOP_MEM + 1) * 15 / 16)) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + else if (bp == 3'b001) //address 1F0000 to 1FFFFF write protected + begin + if (int_add >= ((`TOP_MEM + 1) * 31 / 32)) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + else + begin + protect <= `FALSE ; + end + end + end + //--------------------------------------------------------------------------- + // PAGE PROGRAM + // The adress's LSBs necessary to code a whole page are converted to a natural + // and used to fullfill the page buffer p_prog the same way as the memory page + // will be fullfilled. + //-------------------------------------------------------------------------- + if ( (byte_cpt >= 4) && (pp) && (!only_rdsr) && (!rdsr)) + begin + data_to_write = data_latch ; + page_add_index = (byte_cpt - 1 - (`NB_BIT_ADD_MEM / `NB_BIT_ADD) + lsb_adress); + end + else + begin + data_to_write = 8'bxxxxxxxx; + page_add_index = 8'bxxxxxxxx; + end + + // to launch adress treatment in memory access + if (( read_data && (byte_cpt == 3)) || (fast_read && (byte_cpt == 4))) + begin + read_enable <= `TRUE ; + end + // to send a request for the data pointed by the adress + if (( read_data && (byte_cpt >= 3)) || ( fast_read && (byte_cpt >= 4))) + begin + data_request <= `TRUE ; + end + end //(if byte_ok) + end //(process decode) + + //----------------------------------------- + // adresses initialization and reset + //----------------------------------------- + always @(posedge select_ok) + begin + for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1) + begin + adress_1[i] = 1'b0; + adress_2[i] = 1'b0; + adress_3[i] = 1'b0; + end + for(i = 0; i <= (`NB_BIT_ADD_MEM - 1); i = i + 1) + begin + adress[i] = 1'b0; + end + add_mem <= adress ; + end + + + always @(negedge byte_ok) + begin + if ((read_data && (byte_cpt > 3) ) || (fast_read && (byte_cpt > 4) )) + begin + data_request <= `FALSE ; + + end + end + + always @(posedge inhib_read) + begin + read_op <= `FALSE ; + read_data <= `FALSE ; + fast_read <= `FALSE ; + read_enable <= `FALSE ; + data_request <= `FALSE ; + + end + //------------------------------------------------------ + // STATUS REGISTER INSTRUCTIONS + //------------------------------------------------------ + // WREN/WRDI instructions + //----------------------- + always @(posedge wel) + begin + register_bis[1] <= 1'b1 ; + + end + + always @(posedge inhib_wren) + begin + wren <= `FALSE ; + write_op <= `FALSE ; + end + + always @(posedge inhib_wrdi) + begin + wrdi <= `FALSE ; + write_op <= `FALSE ; + end + + //---------------------- + // RESET WEL instruction + //---------------------- + always @(posedge reset_wel) + begin + register_bis[1] <= 1'b0 ; + end + //------------------- + // WRSR instructions + //------------------- + always @(posedge wr_cycle) + begin + if ($time != 0) $display("%t: NOTE : Write status register cycle has begun ",$realtime); + register_bis <= ((register_bis) | (8'b00000011)) ; + end + always @(negedge wr_cycle) + begin + if ($time != 0) $display("%t: NOTE : Write status register cycle is finished",$realtime); + register_bis <= ((wr_latch) & sr_mask) ; + wrsr <= `FALSE ; + end + + always @(posedge inhib_wrsr) wrsr <= `FALSE ; + + always @(negedge wrsr) wr_latch <= 8'b00000000 ; + + //------ + // PROG + //------ + always @(wip) + begin + if (wip == 1'b1) + begin + register_bis[0] <= 1'b1 ; + end + else + begin + register_bis[0] <= 1'b0 ; + write_op <= `FALSE ; + + end + end + //------------------ + // rdsr instruction + //------------------ + always @(posedge inhib_rdsr) rdsr <= `FALSE ; + //---------------------------------------------------------- + // BULK/SECTOR ERASE INSTRUCTIONS + //---------------------------------------------------------- + always @(posedge inhib_be) + begin + protect <= `FALSE ; + be <= `FALSE ; + end + always @(posedge inhib_se) + begin + protect <= `FALSE ; + se <= `FALSE ; + end + //---------------------------------------------------------- + //PAGE PROGRAM INSTRUCTIONS + //---------------------------------------------------------- + always @(posedge inhib_pp) + begin + protect <= `FALSE ; + pp <= `FALSE ; + end + //---------------------------------------------------------- + // DEEP POWER DOWN + // RELEASE FROM DEEP POWER DOWN AND READ ELECTRONIC SIGNATURE + //----------------------------------------------------------- + always @(posedge inhib_dp) dp <= `FALSE ; + + always @(posedge inhib_res) res <= `FALSE ; + + //-------------------------------------- + // READ JEDEC ID + //-------------------------------------- + always @(posedge inhib_rdid) rdid <= `FALSE; + //-------------------------------------------------------- + //--------------- SYNCHRONOUS PROCESS ---------------- + //-------------------------------------------------------- + always + @(c_int or select_ok) + begin + wel <= 1'b0 ; + reset_wel <= 1'b0 ; + end + + //------------------------------------------- + // READ_data + //------------------------------------------- + always + @(c_int or select_ok) + begin + if ((!read_data) && (!fast_read)) + begin + inhib_read <= `FALSE ; + end + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && (cpt != 7))) && read_data && (!select_ok)) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is deselected",$realtime); + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + end + if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4))) + begin + if (!select_ok) + begin + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + q_bis <= #`TSHQZ 1'bz ; + end + end + end + + always + @(negedge c_int) + begin + if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4))) + begin + + if (select_ok) + begin + q_bis <= #`TCLQV data_to_read[7 - bit_index] ; + bit_index = bit_index + 1; + end + end + end + + //------------------------------------------------------------------ + // Fast_Read + //------------------------------------------------------------------ + always + @(c_int or select_ok) + begin + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && (cpt != 7))) && fast_read && (!select_ok)) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is deselected",$realtime); + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + end + if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5))) + begin + if (!select_ok) + begin + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + q_bis <= #`TSHQZ 1'bz ; + end + end + end + + always + @(negedge c_int) + begin + if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5))) + begin + if (select_ok) + begin + q_bis <= #`TCLQV data_to_read[7 - bit_index] ; + bit_index = bit_index + 1 ; + end + end + end + + //----------------------------------------- + // Write_enable + //----------------------------------------- + always + @(c_int or select_ok) + begin + if (!wren) + begin + inhib_wren <= `FALSE ; + end + if (wren && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + wel <= 1'b1 ; + inhib_wren <= `TRUE ; + end + end + end + + always + @(posedge c_int) + begin + if (wren && (!only_rdsr) && (!only_res) && select_ok) + begin + inhib_wren <= `TRUE ; + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is still selected",$realtime); + end + end + + //------------------------------------------- + // Write_disable + //------------------------------------------- + always + @(c_int or select_ok) + begin + if (!wrdi) + begin + inhib_wrdi <= `FALSE ; + end + if (wrdi && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + reset_wel <= 1'b1 ; + inhib_wrdi <= `TRUE ; + end + end + end + + always + @(posedge c_int) + begin + if (wrdi && (!only_rdsr) && (!only_res) && select_ok) + begin + inhib_wrdi <= `TRUE ; + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is still selected",$realtime); + end + end + + //----------------------------------------- + // Write_status_register + //----------------------------------------- + always + @(c_int or select_ok) + begin + if (!wrsr) + begin + inhib_wrsr <= `FALSE ; + srwd_wrsr <= `FALSE; + end + if (wrsr && (!only_rdsr) && (!only_res)) + begin + if ((byte_cpt == 1) && ((cpt != 7) || (!byte_ok)) && (!wr_cycle)) + begin + if (!select_ok) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is deselected",$realtime); + inhib_wrsr <= `TRUE ; + end + end + else if ((byte_cpt == 1) && (cpt == 7) && byte_ok) + begin + if (write_protect) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because status register is hardware protected",$realtime); + inhib_wrsr <= `TRUE ; + srwd_wrsr <= `FALSE; + end + end + end + end + + //------------------------------------------------------------------------------------------- + // this process returns an error if SRWD=1 and Wc has been switched during a WRSR instruction HC 20/01/03 + always + @(wrsr or write_protect_toggle) + begin + if (wrsr && write_protect_toggle) + begin + if ($time != 0) $display("%d", t_write_protect_toggle,": ERROR : It is not allowed to switch the Wc pin during a WRSR instruction"); + $finish; + end + if (wrsr && (status_register[7]) == 1'b1) + begin + srwd_wrsr <= `TRUE; // becomes one when WRSR is decoded and WIP=1 + end + end + + + always + @(negedge select_ok) + begin + if (wrsr && (!only_rdsr) && (!only_res)) + begin + if ((byte_cpt == 1) && (cpt == 7) && byte_ok && (!write_protect)) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because WEL is reset",$realtime); + inhib_wrsr <= `TRUE ; + end + else + begin + wr_cycle <= `TRUE ; + wip <= 1'b1 ; + #`TW; + wip <= 1'b0 ; + wr_cycle <= `FALSE ; + end + end + else if (byte_cpt == 2) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because WEL is reset",$realtime); + inhib_wrsr <= `TRUE ; + end + else + begin + wr_cycle <= `TRUE ; + wip <= 1'b1 ; + #`TW; + wr_cycle <= `FALSE ; + wip <= 1'b0 ; + end + end + end + end + + always @(posedge c_int) + begin + if (wrsr && (!only_rdsr) && (!only_res)) + if (byte_cpt == 2 && !rdsr) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected",$realtime); + inhib_wrsr <= `TRUE ; + end + end + + //------------------------------------------- + // Bulk_erase + //------------------------------------------- + always @( c_int or select_ok) + begin + if (!be) + begin + inhib_be <= `FALSE ; + end + if (be && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because WEL is reset",$realtime); + be_enable <= `FALSE ; + inhib_be <= `TRUE ; + end + else if (protect && be) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because at least one sector is protected",$realtime); + be_enable <= `FALSE ; + inhib_be <= `TRUE ; + end + else + begin + if ($time != 0) $display("%t: NOTE : Bulk erase cycle has begun",$realtime); + be_enable <= `TRUE ; + wip <= 1'b1 ; + for(j = 1; j <= `TBE; j = j + 1) // Bulk erase duration = TBExTbase = TBE x 1s (to avoid number wider thab 32 bit) + begin + #`Tbase ; + end + if ($time != 0) $display("%t: NOTE : Bulk erase cycle is finished",$realtime); + be_enable <= `FALSE ; + inhib_be <= `TRUE ; + wip <= 1'b0 ; + reset_wel <= 1'b1 ; + end + end + end + end + + always @(posedge c_int) + begin + if (be && (!only_rdsr) && (!only_res)) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is still selected",$realtime); + inhib_be <= `TRUE ; + end + end + + //------------------------------------------- + // Sector_erase + //------------------------------------------- + always @( c_int or select_ok) + begin + if (!se) + begin + inhib_se <= `FALSE ; + end + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && ((cpt != 7) || !byte_ok))) && se && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is deselected",$realtime); + inhib_se <= `TRUE ; + end + end + if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because WEL is reset",$realtime); + se_enable <= `FALSE ; + inhib_se <= `TRUE ; + end + else if (protect && se) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the SE sector is protected",$realtime); + se_enable <= `FALSE ; + inhib_se <= `TRUE ; + end + else + begin + if ($time != 0) $display("%t: NOTE : Sector erase cycle has begun",$realtime); + se_enable <= `TRUE ; + wip <= 1'b1 ; + for(j = 1; j <= `TSE; j = j + 1) // Sector erase duration = TSE x Tbase = TSE x 1s (to avoid number wider thab 32 bit) + begin + #`Tbase ; + end + if ($time != 0) $display("%t: NOTE : Sector erase cycle is finished",$realtime); + se_enable <= `FALSE ; + inhib_se <= `TRUE ; + wip <= 1'b0 ; + reset_wel <= 1'b1 ; + end + end + end + end + + always @(posedge c_int) + begin + if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res)) + begin + if (byte_cpt == 4 && select_ok) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is still selected",$realtime); + inhib_se <= `TRUE ; + end + end + end + + //------------------------------------------- + // Page_Program + //------------------------------------------- + always @(c_int or select_ok) + begin + if (!pp) + begin + inhib_pp <= `FALSE ; + add_pp_enable <= `FALSE ; + pp_enable <= `FALSE ; + end + + if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res)) + begin + add_pp_enable <= `TRUE ; + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because WEL is reset",$realtime); + pp_enable <= `FALSE ; + inhib_pp <= `TRUE ; + end + else if (protect && pp) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the PP sector is protected",$realtime); + pp_enable <= `FALSE ; + inhib_pp <= `TRUE ; + end + end + end + + always @(negedge select_ok) + begin + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt != 7) || !byte_ok))) && pp && (!only_rdsr) && (!only_res) && (!select_ok)) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is deselected",$realtime); + inhib_pp <= `TRUE ; + end + if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res)) + begin + add_pp_enable <= `TRUE ; + if (pp) + begin + if ($time != 0) $display("%t: NOTE : Page program cycle is started",$realtime); + wip <= 1'b1 ; + #`TPP; + if ($time != 0) $display("%t: NOTE : Page program cycle is finished",$realtime); + pp_enable <= `TRUE ; + wip <= 1'b0 ; + inhib_pp <= `TRUE ; + reset_wel <= 1'b1 ; + end + end + if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && byte_ok) + begin + if ($time != 0) $display("%t: NOTE : Page program cycle is started",$realtime); + wip <= 1'b1 ; + #`TPP; + if ($time != 0) $display("%t: NOTE : Page program cycle is finished",$realtime); + pp_enable <= `TRUE ; + wip <= 1'b0 ; + inhib_pp <= `TRUE ; + reset_wel <= 1'b1 ; + end + if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && (!byte_ok)) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is deselected",$realtime); + inhib_pp <= `TRUE ; + pp_enable <= `FALSE ; + end + end + + //----------------------------------------- + // Deep Power Down + //----------------------------------------- + always @(c_int or select_ok) + begin + if (!dp) + begin + inhib_dp <= `FALSE ; + only_res <= `FALSE ; + t_only_res = 0; + end + end + + always @(posedge c_int) + begin + if (dp && (!only_rdsr) && (!only_res) && (!res)) + begin + if ($time != 0) $display("%t: WARNING : Instruction canceled because the chip is still selected",$realtime); + inhib_dp <= `TRUE ; + only_res <= `FALSE ; + t_only_res = 0; + end + end + + always @(negedge select_ok) + begin + if (dp && (!only_rdsr) && (!only_res) && (!res)) + begin + if ($time != 0) $display("%t: NOTE : Chip is entering deep power down mode",$realtime); + // useful when chip is selected again to inhib every op_code except RES + // and to check tDP + t_only_res = $time; + only_res <= `TRUE ; + + end + end + + //--------------------------------------------------------------------- + // Release from Deep Power Down Mode and Read Electronic Signature + //--------------------------------------------------------------------- + always @(select_ok or c_int) + begin + if (!res) + begin + inhib_res <= `FALSE ; + bit_res <= 0; + end + + if (res && ((byte_cpt == 1) && (cpt == 0)) && (!only_rdsr) && (!select_ok)) + begin + if (only_res) + begin + if ($time != 0) $display("%t: NOTE : The chip is releasing from DEEP POWER DOWN",$realtime); + inhib_res <= `FALSE; inhib_dp <= `FALSE; #`TRES1; + inhib_res <= `TRUE; inhib_dp <= `TRUE; + end + else inhib_res <= `TRUE; inhib_dp <= `TRUE; + end + else if ((((byte_cpt == 1) && (cpt > 0)) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt < 7) || (!byte_ok)))) && res && (!only_rdsr) && (!select_ok)) + begin + if ($time != 0) $display("%t: ERROR : Electronic Signature must be read at least once. Instruction not valid",$realtime); + end + else if ((((byte_cpt == 4) && (cpt == 7) && byte_ok) || (byte_cpt > 4)) && res && (!only_rdsr) && (!select_ok)) + begin + if (only_res) + begin + if ($time != 0) $display("%t: NOTE : The Chip is releasing from DEEP POWER DOWN",$realtime); + inhib_res <= `FALSE ; inhib_dp <= `FALSE ;#`TRES2; + inhib_res <= `TRUE ; inhib_dp <= `TRUE; + end + else inhib_res <= `TRUE ; inhib_dp <= `TRUE; + q_bis <= 1'bz ; + end + end + + + always @(negedge c_int) + begin + if ((((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)) && res && (!only_rdsr) ) + begin + q_bis <= #`TCLQV signature[7 - bit_res] ; + bit_res = bit_res + 1; + end + end + + + /////////////////////////////////////////////////////// //modified by xue-feng hu 06/04/04 + // This process shifts out identification on data output + always + @(c_int or select_ok or rdid) + begin + if (!rdid) + begin + inhib_rdid <= `FALSE; + end + if(rdid && (!select_ok)) + begin + bit_id <= 0; + q_bis <= #`TSHQZ 1'bz; + inhib_rdid <= `TRUE; + end + end + always + @(negedge c_int) + begin + if(rdid && (select_ok)) + begin + q_bis <= #`TCLQV id[23 - bit_id]; + bit_id = bit_id + 1; + if(bit_id > 23) bit_id = 0; + end + end + //--------------------- + // READ JEDEC ID //HC 18/02/04 + //--------------------- + //always @(select_ok or c_int) + //begin + // if (!rdid) + // begin + // inhib_rdid <= `FALSE; + // end + // if (rdid && ((byte_cpt==0 && cpt==7) || byte_cpt >=1)) + // begin + // if (!select_ok) + // begin + // inhib_rdid <= `TRUE; + // k <= 0; + // q_bis <= #`TSHQZ 1'bz; + // end + // else if (c_int == 0 && byte_cpt ==1) + // begin + // q_bis <= #`TCLQV manufacturerID[7-k]; + // k= k+1; + // end + // else if (c_int == 0 && byte_cpt == 2) + // begin + // q_bis <= #`TCLQV memtype[7-k]; + // k= k+1; + // end + // else if (c_int == 0 && byte_cpt == 3) + // begin + // q_bis <= #`TCLQV density[7-k]; + // k= k+1; + // end + // else if (c_int == 0 && byte_cpt >= 4) + // begin + // q_bis <= #`TCLQV 1'b0; + // end + // end + // end + + + //------------------------------------------------------- + // This process shifts out status register on data output + always + @(c_int or select_ok or rdsr) + begin + if (!rdsr) + begin + inhib_rdsr <= `FALSE ; + end + if (rdsr && (!select_ok)) + begin + bit_register <= 0; + q_bis <= #`TSHQZ 1'bz ; + inhib_rdsr <= `TRUE ; + end + end + + always + @(negedge c_int) + begin + if (rdsr && (select_ok)) + begin + q_bis <= #`TCLQV status_register[7 - bit_register] ; + bit_register = bit_register + 1; + end + end + //-------------------------------------------------------------------------------------- + // This process checks select and deselect conditions. Some other conditions are tested: + // prog cycle, deep power down mode and read electronic signature. + always + begin : pin_s + @(s); + begin + if (s == 1'b0) + begin + if (res && only_res) + begin + if ($time != 0) $display("%t: ERROR : The chip must not be selected until tRES",$realtime); + end + else if (dp) + begin + if (($time - t_only_res) < `TDP) + begin + if ($time != 0) $display("%t: ERROR : The chip must not be selected until tDP",$realtime); + end + else + begin + if ($time != 0) $display("%t: NOTE : Only a Read Electronic Signature instruction will be valid",$realtime); + end + end + select_ok <= `TRUE ; + if (pp || wrsr || be || se) + begin + if ($time != 0) $display("%t: NOTE : Only a Read Status Register instruction will be valid",$realtime); + only_rdsr <= `TRUE ; + end + end + else + begin + select_ok <= `FALSE ; + only_rdsr <= `FALSE ; + end + end + end + + //-------------------------------------------------------------- + // This Process detects the hardware protection mode + always + @(w or c_int) + begin + if ((w == 1'b0) && ((status_register[7]) == 1'b1)) + begin + write_protect <= `TRUE ; + end + if (w == 1'b1) + begin + write_protect <= `FALSE ; + end + end + + + //-------------------------------------------------------------- + // this process detects if write_protect toggles during an instruction + always + @(select_ok) + begin + if (select_ok) + begin + @(write_protect) + write_protect_toggle <= `TRUE; + if ($time != 0) + begin + t_write_protect_toggle = $time; + end + end + if (!select_ok) + begin + write_protect_toggle <= `FALSE; + end + end +endmodule + + Index: trunk/verif/models/st_m25p16/M25p16.v =================================================================== --- trunk/verif/models/st_m25p16/M25p16.v (nonexistent) +++ trunk/verif/models/st_m25p16/M25p16.v (revision 3) @@ -0,0 +1,58 @@ +// Author: Hugues CREUSY modified by Xue feng +// June 2004 +// Verilog model +// project: M25P16 50 MHz, +// release: 1.2 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns +`include "parameter.v" + +module m25p16(c,data_in,s,w,hold,data_out); + input c; + input data_in; + input s; + input w; + input hold; + + output data_out; + ///reg data_out; + + wire [(`NB_BIT_ADD_MEM-1):0] adresse; + wire [(`NB_BIT_DATA-1):0] dtr; + wire [(`NB_BIT_DATA-1):0] data_to_write; + wire [(`LSB_TO_CODE_PAGE-1):0] page_index; + + wire wr_op; + wire rd_op; + wire s_en; + wire b_en; + wire add_pp_en; + wire pp_en; + wire r_en; + wire d_req; + wire clck; + wire srwd_wrsr; + wire write_protect; + wire wrsr; + + + assign clck = c ; + + + memory_access mem_access(adresse, b_en, s_en, add_pp_en, pp_en, r_en, d_req, data_to_write, page_index, dtr); + + acdc_check acdc_watch(clck, data_in, s, hold, wr_op, rd_op,srwd_wrsr,write_protect, wrsr); + + internal_logic spi_decoder(clck, data_in, w, s, hold, dtr, data_out, data_to_write, page_index, adresse, wr_op, rd_op, b_en, s_en, add_pp_en, pp_en, r_en, d_req,srwd_wrsr,write_protect, wrsr); + +endmodule Index: trunk/verif/models/st_m25p20a/parameter_fast.v =================================================================== --- trunk/verif/models/st_m25p20a/parameter_fast.v (nonexistent) +++ trunk/verif/models/st_m25p20a/parameter_fast.v (revision 3) @@ -0,0 +1,67 @@ +// Author: Mehdi SEBBANE +// May 2002 +// Verilog model +// project: M25P20 25 MHz, +// release: 1.4.1 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns + +`define SIZE 2097152 // 2Mbit +`define PLENGTH 256 // page length +`define SSIZE 524288 // Sector size +`define NB_BPI 2 // number of BPi bits +`define SIGNATURE 8'b00010001 // electronic signature +`define BIT_TO_CODE_MEM 18 // number of bit to code a 2Mbits memory +`define LSB_TO_CODE_PAGE 8 // number of bit to code a PLENGTH page + +`define NB_BIT_ADD_MEM 24 +`define NB_BIT_ADD 8 +`define NB_BIT_DATA 8 +`define TOP_MEM (`SIZE/`NB_BIT_DATA)-1 + +`define MASK_SECTOR 24'hFF0000 // anded with address to find first sector adress to erase + +`define TRUE 1'b1 +`define FALSE 1'b0 + + +`define TC 40 // Minimum Clock period +`define TR 50 // Minimum Clock period for read instruction +`define TSLCH 10 // notS active setup time (relative to C) +`define TCHSL 10 // notS not active hold time +`define TCH 18 // Clock high time +`define TCL 18 // Clock low time +`define TDVCH 5 // Data in Setup Time +`define TCHDX 5 // Data in Hold Time +`define TCHSH 10 // notS active hold time (relative to C) +`define TSHCH 10 // notS not active setup time (relative to C) +`define TSHSL 100 // /S deselect time +`define TSHQZ 15 // Output disable Time +`define TCLQV 15 // clock low to output valid +`define THLCH 10 // NotHold active setup time +`define TCHHH 10 // NotHold not active hold time +`define THHCH 10 // NotHold not active setup time +`define TCHHL 10 // NotHold active hold time +`define THHQX 15 // NotHold high to Output Low-Z +`define THLQZ 20 // NotHold low to Output High-Z +`define TDP 3000 // notS high to deep power down mode +`define TRES1 3000 // notS high to Stand-By power mode w-o ID Read +`define TRES2 1800 // notS high to Stand-By power mode with ID Read +//`define TW 15000000 // write status register cycle time (15ms) +//`define TPP 5000000 // page program cycle time (5ms) +//`define TSE 3000000000 // sector erase cycle time (3s) +//`define TBE 6000000000 // bulk erase cycle time (6s) +`define TW 15000 // write status register cycle time (.015ms) +`define TPP 5000 // page program cycle time (.005ms) +`define TSE 30000 // sector erase cycle time (.00003s) +`define TBE 60000 // bulk erase cycle time (.00006s)

trunk/verif/models/st_m25p20a/parameter_fast.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/models/st_m25p20a/parameter.v =================================================================== --- trunk/verif/models/st_m25p20a/parameter.v (nonexistent) +++ trunk/verif/models/st_m25p20a/parameter.v (revision 3) @@ -0,0 +1,63 @@ +// Author: Mehdi SEBBANE +// May 2002 +// Verilog model +// project: M25P20 25 MHz, +// release: 1.4.1 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns + +`define SIZE 2097152 // 2Mbit +`define PLENGTH 256 // page length +`define SSIZE 524288 // Sector size +`define NB_BPI 2 // number of BPi bits +`define SIGNATURE 8'b00010001 // electronic signature +`define BIT_TO_CODE_MEM 18 // number of bit to code a 2Mbits memory +`define LSB_TO_CODE_PAGE 8 // number of bit to code a PLENGTH page + +`define NB_BIT_ADD_MEM 24 +`define NB_BIT_ADD 8 +`define NB_BIT_DATA 8 +`define TOP_MEM (`SIZE/`NB_BIT_DATA)-1 + +`define MASK_SECTOR 24'hFF0000 // anded with address to find first sector adress to erase + +`define TRUE 1'b1 +`define FALSE 1'b0 + + +`define TC 40 // Minimum Clock period +`define TR 50 // Minimum Clock period for read instruction +`define TSLCH 10 // notS active setup time (relative to C) +`define TCHSL 10 // notS not active hold time +`define TCH 18 // Clock high time +`define TCL 18 // Clock low time +`define TDVCH 5 // Data in Setup Time +`define TCHDX 5 // Data in Hold Time +`define TCHSH 10 // notS active hold time (relative to C) +`define TSHCH 10 // notS not active setup time (relative to C) +`define TSHSL 100 // /S deselect time +`define TSHQZ 15 // Output disable Time +`define TCLQV 15 // clock low to output valid +`define THLCH 10 // NotHold active setup time +`define TCHHH 10 // NotHold not active hold time +`define THHCH 10 // NotHold not active setup time +`define TCHHL 10 // NotHold active hold time +`define THHQX 15 // NotHold high to Output Low-Z +`define THLQZ 20 // NotHold low to Output High-Z +`define TDP 3000 // notS high to deep power down mode +`define TRES1 3000 // notS high to Stand-By power mode w-o ID Read +`define TRES2 1800 // notS high to Stand-By power mode with ID Read +`define TW 15000000 // write status register cycle time (15ms) +`define TPP 5000000 // page program cycle time (5ms) +`define TSE 3000000000 // sector erase cycle time (3s) +`define TBE 6000000000 // bulk erase cycle time (6s)

trunk/verif/models/st_m25p20a/parameter.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/models/st_m25p20a/M25P20.v =================================================================== --- trunk/verif/models/st_m25p20a/M25P20.v (nonexistent) +++ trunk/verif/models/st_m25p20a/M25P20.v (revision 3) @@ -0,0 +1,58 @@ +// Author: Mehdi SEBBANE +// May 2002 +// Verilog model +// project: M25P20 25 MHz, +// release: 1.4.1 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns +`ifdef SFLASH_SPDUP +`include "parameter_fast.v" +`else +`include "parameter.v" +`endif + +module m25p20(c,data_in,s,w,hold,data_out); + input c; + input data_in; + input s; + input w; + input hold; + + output data_out; + ///reg data_out; + + wire [(`NB_BIT_ADD_MEM-1):0] adresse; + wire [(`NB_BIT_DATA-1):0] dtr; + wire [(`NB_BIT_DATA-1):0] data_to_write; + wire [(`LSB_TO_CODE_PAGE-1):0] page_index; + + wire wr_op; + wire rd_op; + wire s_en; + wire b_en; + wire add_pp_en; + wire pp_en; + wire r_en; + wire d_req; + wire clck; + + assign clck = c ; + + + memory_access mem_access(adresse, b_en, s_en, add_pp_en, pp_en, r_en, d_req, data_to_write, page_index, dtr); + + acdc_check acdc_watch(clck, data_in, s, hold, wr_op, rd_op); + + internal_logic spi_decoder(clck, data_in, w, s, hold, dtr, data_out, data_to_write, page_index, adresse, wr_op, rd_op, b_en, s_en, add_pp_en, pp_en, r_en, d_req); + +endmodule

trunk/verif/models/st_m25p20a/M25P20.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/models/st_m25p20a/acdc_check.v =================================================================== --- trunk/verif/models/st_m25p20a/acdc_check.v (nonexistent) +++ trunk/verif/models/st_m25p20a/acdc_check.v (revision 3) @@ -0,0 +1,269 @@ +// Author: Mehdi SEBBANE +// May 2002 +// Verilog model +// project: M25P20 25 MHz, +// release: 1.4.1 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns +`ifdef SFLASH_SPDUP +`include "parameter_fast.v" +`else +`include "parameter.v" +`endif + +module acdc_check (c, d, s, hold, write_op, read_op); + + input c; + input d; + input s; + input hold; + input write_op; + input read_op; + + //////////////// + // TIMING VALUES + //////////////// + time t_C_rise; + time t_C_fall; + time t_H_rise; + time t_H_fall; + time t_S_rise; + time t_S_fall; + time t_D_change; + time high_time; + time low_time; + //////////////// + + reg toggle; + + initial + begin + high_time = 100000; + low_time = 100000; + toggle = 1'b0; + end + + //-------------------------------------------- + // This process checks pulses length on pin /S + //-------------------------------------------- + always + begin : shsl_watch + @(posedge s); + begin + if ($time != 0) + begin + t_S_rise = $time; + @(negedge s); + t_S_fall = $time; + if ((t_S_fall - t_S_rise) < `TSHSL) + begin + $display("ERROR : tSHSL condition violated"); + end + end + end + end + + //---------------------------------------------------- + // This process checks select and deselect setup + // and hold timings + //---------------------------------------------------- + always + begin : s_watch + @(s); + if ((s == 1'b0) && (hold != 1'b0)) + begin + if ($time != 0) + begin + t_S_fall = $time; + if (c == 1'b1) + begin + if ( ($time - t_C_rise) < `TCHSL) + begin + $display("ERROR :tCHSL condition violated"); + end + end + else if (c == 1'b0) + begin + @(c); + if ( ($time - t_S_fall) < `TSLCH) + begin + $display("ERROR :tSLCH condition violated"); + end + end + end + end + if ((s == 1'b1) && (hold != 1'b0)) + begin + if ($time != 0) + begin + t_S_rise = $time; + if (c == 1'b1) + begin + if ( ($time - t_C_rise) < `TCHSH) + begin + $display("ERROR :tCHSH condition violated"); + end + end + else if (c == 1'b0) + begin + @(c); + if ( ($time - t_S_rise) < `TSHCH ) + begin + $display("ERROR :tSHCH condition violated"); + end + end + end + end + end + + //--------------------------------- + // This process checks hold timings + //--------------------------------- + always + begin : hold_watch + @(hold); + if ((hold == 1'b0) && (s == 1'b0)) + begin + if ($time != 0) + begin + t_H_fall = $time ; + if ( (t_H_fall - t_C_rise) < `TCHHL) + begin + $display("ERROR : tCHHL condition violated"); + end + + @(posedge c); + if( ($time - t_H_fall) < `THLCH) + begin + $display("ERROR : tHLCH condition violated"); + end + end + end + + + if ((hold == 1'b1) && (s == 1'b0)) + begin + if ($time != 0) + begin + t_H_rise = $time ; + if ( (t_H_rise - t_C_rise) < `TCHHH) + begin + $display("ERROR : tCHHH condition violated"); + end + @(posedge c); + if( ($time - t_H_fall) < `THHCH) + begin + $display("ERROR : tHHCH condition violated"); + end + end + end + end + + //-------------------------------------------------- + // This process checks data hold and setup timings + //-------------------------------------------------- + always + begin : d_watch + @(d); + if ($time != 0) + begin + t_D_change = $time; + if (c == 1'b1) + begin + if ( ($time - t_C_rise) < `TCHDX) + begin + $display("ERROR : tCHDX condition violated"); + end + end + else if (c == 1'b0) + begin + @(c); + if ( ($time - t_D_change) < `TDVCH) + begin + $display("ERROR : tDVCH condition violated"); + end + end + end + end + + //------------------------------------- + // This process checks clock high time + //------------------------------------- + always + begin : c_high_watch + @(c); + if ($time != 0) + begin + if (c == 1'b1) + begin + t_C_rise = $time; + @(negedge c); + t_C_fall = $time; + high_time = t_C_fall - t_C_rise; + toggle = ~toggle; + if ((t_C_fall - t_C_rise) < `TCH) + begin + $display("ERROR : tCH condition violated"); + end + end + end + end + + //------------------------------------- + // This process checks clock low time + //------------------------------------- + always + begin : c_low_watch + @(c); + if ($time != 0) + begin + if (c == 1'b0) + begin + t_C_fall = $time; + @(posedge c); + t_C_rise = $time; + low_time = t_C_rise - t_C_fall; + toggle = ~toggle; + if ((t_C_rise - t_C_fall) < `TCL) + begin + $display("ERROR : tCL condition violated"); + end + end + end + end + + //----------------------------------------------- + // This process checks clock frequency + //----------------------------------------------- +// always @(high_time or low_time or read_op) + always @(toggle or read_op) + begin : freq_watch + if ($time != 0) + begin + if (s == 1'b0) + begin + if (read_op) + begin + if ((high_time + low_time) < `TR) + begin + $display("ERROR : Clock frequency condition violated for READ instruction: fR>20MHz"); + end + end + else if ((high_time + low_time) < `TC) + begin + $display("ERROR : Clock frequency condition violated: fC>25MHz"); + end + end + end + end +endmodule

trunk/verif/models/st_m25p20a/acdc_check.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/models/st_m25p20a/memory_access.v =================================================================== --- trunk/verif/models/st_m25p20a/memory_access.v (nonexistent) +++ trunk/verif/models/st_m25p20a/memory_access.v (revision 3) @@ -0,0 +1,212 @@ +// Author: Mehdi SEBBANE +// May 2002 +// Verilog model +// project: M25P20 25 MHz, +// release: 1.4.1 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns +`ifdef SFLASH_SPDUP +`include "parameter_fast.v" +`else +`include "parameter.v" +`endif + +module memory_access (add_mem, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request, data_to_write, page_add_index, data_to_read); + + input[(`NB_BIT_ADD_MEM - 1):0] add_mem; + input be_enable; + input se_enable; + input add_pp_enable; + input pp_enable; + input read_enable; + input data_request; + input[(`NB_BIT_DATA - 1):0] data_to_write; + input[(`LSB_TO_CODE_PAGE-1):0] page_add_index; + + output[(`NB_BIT_DATA - 1):0] data_to_read; + reg[(`NB_BIT_DATA - 1):0] data_to_read; + + reg[(`NB_BIT_DATA - 1):0] p_prog[0:(`PLENGTH-1)]; + reg[(`NB_BIT_DATA - 1):0] content[0:`TOP_MEM]; + reg[`BIT_TO_CODE_MEM - 1:0] cut_add; + + integer i; + integer deb_zone; + integer int_add; + integer int_add_mem; + + initial + begin + cut_add = 0; + deb_zone = 0; + int_add = 0; + int_add_mem = `BIT_TO_CODE_MEM ; + + + //------------------------------- + // initialisation of memory array + //------------------------------- + $display("NOTE : Load memory with Initial delivery content"); + for(i = 0; i <= `TOP_MEM; i = i + 1) + begin + content[i] = 8'b11111111 ; + end + $display("NOTE : Initial Load End"); + + for(i = 0; i <= (`PLENGTH-1); i = i + 1) + begin + p_prog[i] = 8'b11111111 ; + end + + //Added to Preload Data + `ifdef PRELOAD_SPI_FLASH + if(`SPI_PRELOAD_FNAME !== "") begin + $display("Load Memory from file: %s",`SPI_PRELOAD_FNAME); + $readmemh (`SPI_PRELOAD_FNAME, content); + end // if (`SPI_PRELOAD_FNAME !== "") + else $display("Warning: File: %s not found",`SPI_PRELOAD_FNAME); + `endif + end + + //-------------------------------------------------- + // PROCESS MEMORY + //-------------------------------------------------- + + always + begin + @(negedge add_pp_enable ) + + for(i = 0; i <= (`PLENGTH-1); i = i + 1) + begin + p_prog[i] = 8'b11111111 ; + end + end + + always + begin + @(page_add_index) + if ($time != 0) + begin + if (page_add_index !== 8'bxxxxxxxx) + begin + if (add_pp_enable == 1'b1 && pp_enable == 1'b0) + begin + p_prog[page_add_index] <= data_to_write ; + end + end + end + end + + always + @(posedge se_enable or posedge read_enable or add_pp_enable) + if ($time != 0) + begin + for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1) + begin + cut_add[i] = add_mem[i]; + end + end + + always + @(posedge data_request) + if ($time != 0) + begin + if (read_enable) + begin + int_add = cut_add; + //--------------------------------------------------------- + // Read instruction + //--------------------------------------------------------- + if (int_add > `TOP_MEM) + begin + for(i = 0; i <= `BIT_TO_CODE_MEM - 1; i = i + 1) + begin + cut_add[i] = 1'b0; + end + int_add = 0; // roll over at the end of mem array + end + data_to_read <= content[int_add] ; + cut_add <= cut_add + 1; // next address + end + end + + always + @(negedge read_enable) + if ($time != 0) + begin + for(i = 0; i <= `NB_BIT_DATA - 1; i = i + 1) + begin + data_to_read[i] <= 1'b0 ; + end + end + + //-------------------------------------------------------- + // Page program instruction + // To find the first adress of the memory to be programmed + //-------------------------------------------------------- + always + @(add_pp_enable) + if (add_pp_enable == 1'b1) + begin + int_add_mem = cut_add; + int_add = `TOP_MEM + 1; + while (int_add > int_add_mem) + begin + int_add = int_add - `PLENGTH ; + end + end + + //---------------------------------------------------- + // Sector erase instruction + // To find the first adress of the sector to be erased + //---------------------------------------------------- + wire #1 se_enable_dly = se_enable; + always + @(posedge se_enable_dly) + begin + int_add = cut_add & `MASK_SECTOR ; + end + //---------------------------------------------------- + // Write or erase cycle execution + //---------------------------------------------------- + always + @(posedge pp_enable) + if ($time != 0) // to avoid any corruption at initialization of variables + begin + for(i = 0; i <= (`PLENGTH - 1); i = i + 1) + begin + content[int_add + i] = p_prog[i] & content[int_add + i]; + end + end + + always + @(negedge be_enable) + if ($time != 0) // to avoid any corruption at initialization of variables + begin + for(i = 0; i <= `TOP_MEM; i = i + 1) + begin + content[i] = 8'b11111111; + end + end + + always + @(negedge se_enable) + if ($time != 0) // to avoid any corruption at initialization of variables + begin + for(i = int_add; i <= (int_add + (`SSIZE / `NB_BIT_DATA) - 1); i = i + 1) + begin + content[i] = 8'b11111111; + end + end + +endmodule

trunk/verif/models/st_m25p20a/memory_access.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/models/st_m25p20a/internal_logic.v =================================================================== --- trunk/verif/models/st_m25p20a/internal_logic.v (nonexistent) +++ trunk/verif/models/st_m25p20a/internal_logic.v (revision 3) @@ -0,0 +1,1416 @@ +// Author: Mehdi SEBBANE +// May 2002 +// Verilog model +// project: M25P20 25 MHz, +// release: 1.4.1 + + + +// These Verilog HDL models are provided "as is" without warranty +// of any kind, included but not limited to, implied warranty +// of merchantability and fitness for a particular purpose. + + + + + +`timescale 1ns/1ns +`ifdef SFLASH_SPDUP +`include "parameter_fast.v" +`else +`include "parameter.v" +`endif + +module internal_logic (c, d, w, s, hold, data_to_read, q, data_to_write, page_add_index, add_mem, write_op, read_op, be_enable, se_enable, add_pp_enable, pp_enable, read_enable, data_request); + //////////////////////////////// + // declaration of the parameters + //////////////////////////////// + input c; + input d; + input w; + input s; + input hold; + input[(`NB_BIT_DATA - 1):0] data_to_read; + + output q; + reg q; + + output[(`NB_BIT_DATA - 1):0] data_to_write; + reg[(`NB_BIT_DATA - 1):0] data_to_write; + + output[(`LSB_TO_CODE_PAGE - 1):0] page_add_index; // position to write data_to_write inside the page + reg[(`LSB_TO_CODE_PAGE - 1):0] page_add_index; + + output[(`NB_BIT_ADD_MEM - 1):0] add_mem; + reg[(`NB_BIT_ADD_MEM - 1):0] add_mem; + + output write_op; + reg write_op; + + output read_op; + reg read_op; + + output be_enable; + reg be_enable; + + output se_enable; + reg se_enable; + + output add_pp_enable; + reg add_pp_enable; + + output pp_enable; + reg pp_enable; + + output read_enable; + reg read_enable; + + output data_request; + reg data_request; + + + /////////////////////////////////////////////// + // declaration of internal variables + /////////////////////////////////////////////// + reg only_rdsr; + reg only_res; + reg write_protect; + reg select_ok; + reg raz; + reg byte_ok; + reg wren; + reg wrdi; + reg rdsr; + reg wrsr; + reg read_data; + reg fast_read; + reg pp; + reg se; + reg be; + reg dp; + reg res; + reg q_bis; + reg protect; + reg wr_cycle; + reg hold_cond; + reg inhib_wren; + reg inhib_wrdi; + reg inhib_rdsr; + reg inhib_wrsr; + reg inhib_read; + reg inhib_pp; + reg inhib_se; + reg inhib_be; + reg inhib_dp; + reg inhib_res; + reg reset_wel; + reg wel; + reg wip; + reg c_int; + + reg [2:0] cpt; + reg [2:0] bit_index; // to allow shift inside a byte + reg [2:0] bit_res; // to allow shift inside signature + reg [2:0] bit_register; // to allow shift inside status register + + reg [7:0] data; + reg [7:0] adress_1; + reg [7:0] adress_2; + reg [7:0] adress_3; + reg [7:0] sr_mask; + reg [7:0] signature; + + reg [(`NB_BIT_DATA-1):0] wr_latch; + reg [(`NB_BIT_DATA-1):0] page_ini; + reg [(`NB_BIT_DATA-1):0] data_latch; + reg [(`NB_BIT_DATA-1):0] register_bis; + reg [(`NB_BIT_DATA-1):0] register_temp; + reg [(`NB_BIT_DATA-1):0] status_register; + + reg [(`NB_BPI-1):0] bp; + reg [(`NB_BIT_ADD_MEM-1):0] adress; + reg [(`BIT_TO_CODE_MEM-1):0] cut_add; + reg [(`LSB_TO_CODE_PAGE -1) :0] lsb_adress; + + integer byte_cpt; + integer int_add; + integer i; + integer count_enable; + + time t_only_res ; + + initial + begin + //////////////////////////////////////////// + // Initialization of the internal variables + //////////////////////////////////////////// + only_rdsr = `FALSE; + only_res = `FALSE; + write_protect = `FALSE; + select_ok = `FALSE; + raz = `FALSE; + byte_ok = `FALSE; + + cpt = 0; + byte_cpt = 0; + + data_to_write = 8'bxxxxxxxx; + data_latch = 8'bxxxxxxxx; + data_request <= `FALSE; + + wren = `FALSE; + wrdi = `FALSE; + rdsr = `FALSE; + wrsr = `FALSE; + read_data = `FALSE; + fast_read = `FALSE; + pp = `FALSE; + se = `FALSE; + be = `FALSE; + dp = `FALSE; + res = `FALSE; + + q_bis = 1'bz; + + register_bis = 8'b00000000; + wr_latch = 8'b00000000; + + protect = `FALSE; + wr_cycle = `FALSE; + hold_cond = `FALSE; + write_op = `FALSE; + read_op = `FALSE; + + inhib_wren = `FALSE; + inhib_wrdi = `FALSE; + inhib_rdsr = `FALSE; + inhib_wrsr = `FALSE; + inhib_read = `FALSE; + inhib_pp = `FALSE; + inhib_se = `FALSE; + inhib_be = `FALSE; + inhib_dp = `FALSE; + inhib_res = `FALSE; + + add_pp_enable = `FALSE; + read_enable = `FALSE; + pp_enable = `FALSE; + be_enable = `FALSE; + se_enable = `FALSE; + + + count_enable = `FALSE; + data = 8'b00000000; + + // decode process + bit_index = 8'b00000000; + bit_res = 8'b00000000; + bit_register = 8'b00000000; + + bp = `NB_BPI'h0 ; + + int_add = 0; + sr_mask = 8'b10000000; + page_ini = 8'b11111111; + + reset_wel = 1'b0; + wel = 1'b0; + wip = 1'b0; + + signature = `SIGNATURE ; + end // initial + + always @(register_bis) status_register = register_bis ; + //assign status_register = register_bis ; // Continuous Assignment + + //----------------------------------------------------------- + // This process generates the Hold condition when it is valid + always + begin : hold_com + @(hold); + begin + if ((hold == 1'b0) && (s == 1'b0)) + begin + if (c == 1'b0) + begin + hold_cond <= `TRUE; + if ($time != 0) $display("NOTE: COMMUNICATION PAUSED"); + end + else + begin + @(c or hold); + if (c == 1'b0) + begin + hold_cond <= `TRUE; + if ($time != 0) $display("NOTE: COMMUNICATION PAUSED"); + end + end + end + else if (hold == 1'b1) + begin + if (c == 1'b0) + begin + hold_cond <= `FALSE; + if ($time != 0) $display("NOTE: COMMUNICATION (RE)STARTED"); + end + else + begin + @(c or hold); + if (c == 1'b0) + begin + hold_cond <= `FALSE; + if ($time != 0) $display("NOTE: COMMUNICATION (RE)STARTED"); + end + end + end + end + end + + //---------------------------------------------------------------------- + // This process inhibits the internal clock when hold condition is valid + always + begin : horloge + @(c); + begin + if (!hold_cond) + begin + c_int <= c ; + end + else + begin + c_int <= 1'b0 ; + end + end + end + + //--------------------------------------------------------------- + // This process inhibits data output when hold condition is valid + always @(posedge hold_cond ) q <= #`THLQZ 1'bz ; + + always @(negedge hold_cond) q <= #`THHQX q_bis ; + + always @ (q_bis or s) + if (!hold_cond) + begin + q <= q_bis ; + end + + //---------------------------------------------------------- + // This process increments 2 counters: one bit counter (cpt) + // one byte counter (byte_cpt) + always + begin : count_bit_raz + @(raz); + begin + if (raz || !select_ok) + begin + cpt <= 0 ; + byte_cpt <= 0 ; + count_enable = `FALSE; + end + end + end + + always + begin : count_bit_enable + @(posedge c_int or negedge raz); + begin + if (!raz && select_ok) + begin + // count enable is an intermediate variable which allows cpt to be + // constant during a whole period + count_enable = `TRUE; + end + end + end + + + always + begin : count_bit + @(negedge c_int); + begin + if (!raz && select_ok) + begin + if (count_enable) + begin + cpt <= cpt + 1 ; + end + end + end + end + + always @(negedge c_int) + if (byte_ok) + begin + //byte_cpt = (byte_cpt + 1) ; + byte_cpt <= (byte_cpt + 1) ; + end + + //--------------------------------------------------------------------- + // This process latches every byte of data received and returns byte_ok + always + begin : data_in_reset + + @(c_int or select_ok); + begin + if (!select_ok) + begin + raz <= `TRUE ; + byte_ok <= `FALSE ; + data_latch <= 8'b00000000 ; + data = 8'b00000000; + end + end + end + + always + begin : data_in + + @(posedge c_int); + begin + if (select_ok) + begin + raz <= `FALSE ; + if (cpt == 0) + begin + data_latch <= 8'b00000000 ; + byte_ok <= `FALSE ; + end + data[7 - cpt] = d; + if (cpt == 7) + begin + byte_ok <= `TRUE ; + data_latch <= data ; + end + else data_latch <= 8'bxxxxxxxx; + end + end + end + + //------------------------------------------------------------- + //--------------- ASYNCHRONOUS DECODE PROCESS ----------------- + //------------------------------------------------------------- + always + begin : decode + //------------------------- + // status register mask ini + //------------------------- + for(i = 0; i <= (`NB_BPI - 1); i = i + 1) + begin + sr_mask[i + 2] = 1'b1; + end + + + @(byte_ok); + if (byte_ok == 1'b1) + begin + //----------------------------------------------------------- + //-- op_code decode + //----------------------------------------------------------- + if (byte_cpt == 0) + begin + if (data_latch == 8'b00000110) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle"); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR :This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + wren <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b00000100) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + wrdi <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b00000101) + begin + if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + rdsr <= `TRUE ; + end + end + else if (data_latch == 8'b00000001) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + wrsr <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b00000011) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + read_data <= `TRUE ; + read_op <= `TRUE ; + end + end + else if (data_latch == 8'b00001011) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + fast_read <= `TRUE ; + end + end + else if (data_latch == 8'b00000010) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + pp <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b11011000) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + se <= `TRUE ; + write_op <= `TRUE ; + end + end + else if (data_latch == 8'b11000111) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + be <= `TRUE ; + write_op <= `TRUE ; + for(i = 0; i <= (`NB_BPI - 1); i = i + 1) + begin + bp[i] = status_register[i + 2]; + end + if (bp != 2'b00) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + end + else if (data_latch == 8'b10111001) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else if (only_res) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a DEEP POWER DOWN "); + end + else + begin + dp <= `TRUE ; + end + end + else if (data_latch == 8'b10101011) + begin + if (only_rdsr) + begin + if ($time != 0) $display("ERROR : This Opcode is not decoded during a Prog. Cycle "); + end + else + begin + res <= `TRUE ; + end + end + else + begin + if ($time != 0) $display("ERROR : False instruction, please retry "); + end + end + //--------------------------------------------------------------------- + // addresses and data reception and treatment + //--------------------------------------------------------------------- + if ( (byte_cpt == 1) && (!only_rdsr) && (!only_res)) + begin + if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr)) + begin + adress_1 = data_latch; + end + else if (wrsr && (!rdsr)) + begin + wr_latch <= data_latch ; + end + end + + if ((byte_cpt == 2) && (!only_rdsr) && (!only_res)) + begin + if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr)) + begin + adress_2 = data_latch; + end + end + if ((byte_cpt == 3) && (!only_rdsr) && (!only_res)) + begin + if (((read_data) || (fast_read) || (se) || (pp)) && (!rdsr)) + begin + adress_3 = data_latch; + for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1) + begin + adress[i] = adress_3[i]; + adress[i + `NB_BIT_ADD] = adress_2[i]; + adress[i + 2 * `NB_BIT_ADD] = adress_1[i]; + add_mem <= adress ; + end + for(i = (`LSB_TO_CODE_PAGE - 1); i >= 0; i = i - 1) + begin + lsb_adress[i] = adress[i]; + end + end + if ((se || pp) && (!rdsr)) + begin + //----------------------------------------- + // To ignore don't care MSB of the adress + //----------------------------------------- + for(i = 0; i <= `BIT_TO_CODE_MEM -1; i = i + 1) + begin + cut_add[i] = adress[i]; + end + int_add = cut_add; + //------------------------------------------------ + // Sector protection detection + //------------------------------------------------ + for(i = 0; i <= (`NB_BPI - 1); i = i + 1) + begin + bp[i] = status_register[i + 2]; + end + if (bp == 2'b11) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + else if (bp == 2'b10) + begin + if (int_add >= ((`TOP_MEM + 1) / 2)) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + else if (bp == 2'b01) + begin + if (int_add >= ((`TOP_MEM + 1) * 3 / 4)) + begin + protect <= `TRUE ; + write_op <= `FALSE ; + end + end + else + begin + protect <= `FALSE ; + end + end + end + //--------------------------------------------------------------------------- + // PAGE PROGRAM + // The adress's LSBs necessary to code a whole page are converted to a natural + // and used to fullfill the page buffer p_prog the same way as the memory page + // will be fullfilled. + //-------------------------------------------------------------------------- + if ( (byte_cpt >= 4) && (pp) && (!only_rdsr) && (!rdsr)) + begin + data_to_write = data_latch ; + page_add_index = (byte_cpt - 1 - (`NB_BIT_ADD_MEM / `NB_BIT_ADD) + lsb_adress); + end + else + begin + data_to_write = 8'bxxxxxxxx; + page_add_index = 8'bxxxxxxxx; + end + + // to launch adress treatment in memory access + if (( read_data && (byte_cpt == 3)) || (fast_read && (byte_cpt == 4))) + begin + read_enable <= `TRUE ; + end + // to send a request for the data pointed by the adress + if (( read_data && (byte_cpt >= 3)) || ( fast_read && (byte_cpt >= 4))) + begin + data_request <= `TRUE ; + end + end //(if byte_ok) + end //(process decode) + + //----------------------------------------- + // adresses initialization and reset + //----------------------------------------- + always @(posedge select_ok) + begin + for(i = 0; i <= (`NB_BIT_ADD - 1); i = i + 1) + begin + adress_1[i] = 1'b0; + adress_2[i] = 1'b0; + adress_3[i] = 1'b0; + end + for(i = 0; i <= (`NB_BIT_ADD_MEM - 1); i = i + 1) + begin + adress[i] = 1'b0; + end + add_mem <= adress ; + end + + + always @(negedge byte_ok) + begin + if ((read_data && (byte_cpt > 3) ) || (fast_read && (byte_cpt > 4) )) + begin + data_request <= `FALSE ; + + end + end + + always @(posedge inhib_read) + begin + read_op <= `FALSE ; + read_data <= `FALSE ; + fast_read <= `FALSE ; + read_enable <= `FALSE ; + data_request <= `FALSE ; + + end + //------------------------------------------------------ + // STATUS REGISTER INSTRUCTIONS + //------------------------------------------------------ + // WREN/WRDI instructions + //----------------------- + always @(posedge wel) + begin + register_bis[1] <= 1'b1 ; + + end + + always @(posedge inhib_wren) + begin + wren <= `FALSE ; + write_op <= `FALSE ; + end + + always @(posedge inhib_wrdi) + begin + wrdi <= `FALSE ; + write_op <= `FALSE ; + end + + //---------------------- + // RESET WEL instruction + //---------------------- + always @(posedge reset_wel) + begin + register_bis[1] <= 1'b0 ; + end + //------------------- + // WRSR instructions + //------------------- + always @(posedge wr_cycle) + begin + if ($time != 0) $display("NOTE : Write status register cycle has begun "); + register_bis <= ((register_bis) | (8'b00000011)) ; + end + always @(negedge wr_cycle) + begin + if ($time != 0) $display("NOTE : Write status register cycle is finished"); + register_bis <= ((wr_latch) & sr_mask) ; + wrsr <= `FALSE ; + end + + always @(posedge inhib_wrsr) wrsr <= `FALSE ; + + always @(negedge wrsr) wr_latch <= 8'b00000000 ; + + //------ + // PROG + //------ + always @(wip) + begin + if (wip == 1'b1) + begin + register_bis[0] <= 1'b1 ; + end + else + begin + register_bis[0] <= 1'b0 ; + write_op <= `FALSE ; + + end + end + //------------------ + // rdsr instruction + //------------------ + always @(posedge inhib_rdsr) rdsr <= `FALSE ; + //---------------------------------------------------------- + // BULK/SECTOR ERASE INSTRUCTIONS + //---------------------------------------------------------- + always @(posedge inhib_be) + begin + protect <= `FALSE ; + be <= `FALSE ; + end + always @(posedge inhib_se) + begin + protect <= `FALSE ; + se <= `FALSE ; + end + //---------------------------------------------------------- + //PAGE PROGRAM INSTRUCTIONS + //---------------------------------------------------------- + always @(posedge inhib_pp) + begin + protect <= `FALSE ; + pp <= `FALSE ; + end + //---------------------------------------------------------- + // DEEP POWER DOWN + // RELEASE FROM DEEP POWER DOWN AND READ ELECTRONIC SIGNATURE + //----------------------------------------------------------- + always @(posedge inhib_dp) dp <= `FALSE ; + + always @(posedge inhib_res) res <= `FALSE ; + + //-------------------------------------------------------- + //--------------- SYNCHRONOUS PROCESS ---------------- + //-------------------------------------------------------- + always + @(c_int or select_ok) + begin + wel <= 1'b0 ; + reset_wel <= 1'b0 ; + end + + //------------------------------------------- + // READ_data + //------------------------------------------- + always + @(c_int or select_ok) + begin + if ((!read_data) && (!fast_read)) + begin + inhib_read <= `FALSE ; + end + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && (cpt != 7))) && read_data && (!select_ok)) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected"); + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + end + if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4))) + begin + if (!select_ok) + begin + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + q_bis <= #`TSHQZ 1'bz ; + end + end + end + + always + @(negedge c_int) + begin + if (read_data && (((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4))) + begin + + if (select_ok) + begin + q_bis <= #`TCLQV data_to_read[7 - bit_index] ; + bit_index = bit_index + 1; + end + end + end + + //------------------------------------------------------------------ + // Fast_Read + //------------------------------------------------------------------ + always + @(c_int or select_ok) + begin + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && (cpt != 7))) && fast_read && (!select_ok)) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected"); + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + end + if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5))) + begin + if (!select_ok) + begin + inhib_read <= `TRUE ; + bit_index <= 8'b00000000; + q_bis <= #`TSHQZ 1'bz ; + end + end + end + + always + @(negedge c_int) + begin + if (fast_read && (((byte_cpt == 4) && (cpt == 7)) || (byte_cpt >= 5))) + begin + if (select_ok) + begin + q_bis <= #`TCLQV data_to_read[7 - bit_index] ; + bit_index = bit_index + 1 ; + end + end + end + + //----------------------------------------- + // Write_enable + //----------------------------------------- + always + @(c_int or select_ok) + begin + if (!wren) + begin + inhib_wren <= `FALSE ; + end + if (wren && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + wel <= 1'b1 ; + inhib_wren <= `TRUE ; + end + end + end + + always + @(posedge c_int) + begin + if (wren && (!only_rdsr) && (!only_res) && select_ok) + begin + inhib_wren <= `TRUE ; + if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected"); + end + end + + //------------------------------------------- + // Write_disable + //------------------------------------------- + always + @(c_int or select_ok) + begin + if (!wrdi) + begin + inhib_wrdi <= `FALSE ; + end + if (wrdi && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + reset_wel <= 1'b1 ; + inhib_wrdi <= `TRUE ; + end + end + end + + always + @(posedge c_int) + begin + if (wrdi && (!only_rdsr) && (!only_res) && select_ok) + begin + inhib_wrdi <= `TRUE ; + if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected"); + end + end + + //----------------------------------------- + // Write_status_register + //----------------------------------------- + always + @(c_int or select_ok) + begin + if (!wrsr) + begin + inhib_wrsr <= `FALSE ; + end + if (wrsr && (!only_rdsr) && (!only_res)) + begin + if ((byte_cpt == 1) && ((cpt != 7) || (!byte_ok)) && (!wr_cycle)) + begin + if (!select_ok) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected"); + inhib_wrsr <= `TRUE ; + end + end + else if ((byte_cpt == 1) && (cpt == 7) && byte_ok) + begin + if (write_protect) + begin + if ($time != 0) $display("WARNING : Instruction canceled because status register is hardware protected"); + inhib_wrsr <= `TRUE ; + end + end + end + end + + always + @(negedge select_ok) + begin + if (wrsr && (!only_rdsr) && (!only_res)) + begin + if ((byte_cpt == 1) && (cpt == 7) && byte_ok && (!write_protect)) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset"); + inhib_wrsr <= `TRUE ; + end + else + begin + wr_cycle <= `TRUE ; + wip <= 1'b1 ; + #`TW; + wip <= 1'b0 ; + wr_cycle <= `FALSE ; + end + end + else if (byte_cpt == 2) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset"); + inhib_wrsr <= `TRUE ; + end + else + begin + wr_cycle <= `TRUE ; + wip <= 1'b1 ; + #`TW; + wr_cycle <= `FALSE ; + wip <= 1'b0 ; + end + end + end + end + + always @(posedge c_int) + begin + if (wrsr && (!only_rdsr) && (!only_res)) + if (byte_cpt == 2 && !rdsr) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected"); + inhib_wrsr <= `TRUE ; + end + end + + //------------------------------------------- + // Bulk_erase + //------------------------------------------- + always @( c_int or select_ok) + begin + if (!be) + begin + inhib_be <= `FALSE ; + end + if (be && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset"); + be_enable <= `FALSE ; + inhib_be <= `TRUE ; + end + else if (protect && be) + begin + if ($time != 0) $display("WARNING : Instruction canceled because at least one sector is protected"); + be_enable <= `FALSE ; + inhib_be <= `TRUE ; + end + else + begin + if ($time != 0) $display("NOTE : Bulk erase cycle has begun"); + be_enable <= `TRUE ; + wip <= 1'b1 ; + // We can't use `TBE since it wider than a 32bits number + // and the delay instruction can only manage 32bits wide number + #`TSE ; + #`TSE ; + if ($time != 0) $display("NOTE : Bulk erase cycle is finished"); + be_enable <= `FALSE ; + inhib_be <= `TRUE ; + wip <= 1'b0 ; + reset_wel <= 1'b1 ; + end + end + end + end + + always @(posedge c_int) + begin + if (be && (!only_rdsr) && (!only_res)) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected"); + inhib_be <= `TRUE ; + end + end + + //------------------------------------------- + // Sector_erase + //------------------------------------------- + always @( c_int or select_ok) + begin + if (!se) + begin + inhib_se <= `FALSE ; + end + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || ((byte_cpt == 3) && ((cpt != 7) || !byte_ok))) && se && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected"); + inhib_se <= `TRUE ; + end + end + if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res)) + begin + if (!select_ok) + begin + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset"); + se_enable <= `FALSE ; + inhib_se <= `TRUE ; + end + else if (protect && se) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the SE sector is protected"); + se_enable <= `FALSE ; + inhib_se <= `TRUE ; + end + else + begin + if ($time != 0) $display("NOTE : Sector erase cycle has begun"); + se_enable <= `TRUE ; + wip <= 1'b1 ; + #`TSE ; + if ($time != 0) $display("NOTE : Sector erase cycle is finished"); + se_enable <= `FALSE ; + inhib_se <= `TRUE ; + wip <= 1'b0 ; + reset_wel <= 1'b1 ; + end + end + end + end + + always @(posedge c_int) + begin + if ( ((byte_cpt == 4) || ((byte_cpt == 3) && (cpt == 7) && byte_ok)) && se && (!only_rdsr) && (!only_res)) + begin + if (byte_cpt == 4 && select_ok) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected"); + inhib_se <= `TRUE ; + end + end + end + + //------------------------------------------- + // Page_Program + //------------------------------------------- + always @(c_int or select_ok) + begin + if (!pp) + begin + inhib_pp <= `FALSE ; + add_pp_enable <= `FALSE ; + pp_enable <= `FALSE ; + end + + if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res)) + begin + add_pp_enable <= `TRUE ; + if ((status_register[1]) == 1'b0) + begin + if ($time != 0) $display("WARNING : Instruction canceled because WEL is reset"); + pp_enable <= `FALSE ; + inhib_pp <= `TRUE ; + end + else if (protect && pp) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the PP sector is protected"); + pp_enable <= `FALSE ; + inhib_pp <= `TRUE ; + end + end + end + + always @(negedge select_ok) + begin + if (((byte_cpt == 0) || (byte_cpt == 1) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt != 7) || !byte_ok))) && pp && (!only_rdsr) && (!only_res) && (!select_ok)) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected"); + inhib_pp <= `TRUE ; + end + if (((byte_cpt == 5) || ((byte_cpt == 4) && (cpt == 7))) && pp && (!only_rdsr) && (!only_res)) + begin + add_pp_enable <= `TRUE ; + if (pp) + begin + if ($time != 0) $display("NOTE : Page program cycle is started"); + wip <= 1'b1 ; + #`TPP; + if ($time != 0) $display("NOTE : Page program cycle is finished"); + pp_enable <= `TRUE ; + wip <= 1'b0 ; + inhib_pp <= `TRUE ; + reset_wel <= 1'b1 ; + end + end + if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && byte_ok) + begin + if ($time != 0) $display("NOTE : Page program cycle is started"); + wip <= 1'b1 ; + #`TPP; + if ($time != 0) $display("NOTE : Page program cycle is finished"); + pp_enable <= `TRUE ; + wip <= 1'b0 ; + inhib_pp <= `TRUE ; + reset_wel <= 1'b1 ; + end + if ((byte_cpt > 5) && pp && (!only_rdsr) && (!only_res) && (!byte_ok)) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is deselected"); + inhib_pp <= `TRUE ; + pp_enable <= `FALSE ; + end + end + + //----------------------------------------- + // Deep Power Down + //----------------------------------------- + always @(c_int or select_ok) + begin + if (!dp) + begin + inhib_dp <= `FALSE ; + only_res <= `FALSE ; + t_only_res = 0; + end + end + + always @(posedge c_int) + begin + if (dp && (!only_rdsr) && (!only_res) && (!res)) + begin + if ($time != 0) $display("WARNING : Instruction canceled because the chip is still selected"); + inhib_dp <= `TRUE ; + only_res <= `FALSE ; + t_only_res = 0; + end + end + + always @(negedge select_ok) + begin + if (dp && (!only_rdsr) && (!only_res) && (!res)) + begin + if ($time != 0) $display("NOTE : Chip is entering deep power down mode"); + // useful when chip is selected again to inhib every op_code except RES + // and to check tDP + t_only_res = $time; + only_res <= `TRUE ; + + end + end + + //--------------------------------------------------------------------- + // Release from Deep Power Down Mode and Read Electronic Signature + //--------------------------------------------------------------------- + always @(select_ok or c_int) + begin + if (!res) + begin + inhib_res <= `FALSE ; + bit_res <= 0; + end + + if (res && ((byte_cpt == 1) && (cpt == 0)) && (!only_rdsr) && (!select_ok)) + begin + if (only_res) + begin + if ($time != 0) $display("NOTE : The chip is releasing from DEEP POWER DOWN"); + end + inhib_res <= `FALSE; + inhib_dp <= `FALSE; + #`TRES1; + inhib_res <= `TRUE; + inhib_dp <= `TRUE; + end + else if ((((byte_cpt == 1) && (cpt > 0)) || (byte_cpt == 2) || (byte_cpt == 3) || ((byte_cpt == 4) && ((cpt < 7) || (!byte_ok)))) && res && (!only_rdsr) && (!select_ok)) + begin + if ($time != 0) $display("ERROR : Electronic Signature must be read at least once. Instruction not valid"); + end + else if ((((byte_cpt == 4) && (cpt == 7) && byte_ok) || (byte_cpt > 4)) && res && (!only_rdsr) && (!select_ok)) + begin + #`TRES2; + inhib_res <= `TRUE ; + inhib_dp <= `TRUE ; + if (only_res) + begin + if ($time != 0) $display("NOTE : The Chip is releasing from DEEP POWER DOWN"); + end + q_bis <= 1'bz ; + end + end + + always @(negedge c_int) + begin + if ((((byte_cpt == 3) && (cpt == 7)) || (byte_cpt >= 4)) && res && (!only_rdsr) ) + begin + q_bis <= #`TCLQV signature[7 - bit_res] ; + bit_res = bit_res + 1; + end + end + + //------------------------------------------------------- + // This process shifts out status register on data output + always + @(c_int or select_ok or rdsr) + begin + if (!rdsr) + begin + inhib_rdsr <= `FALSE ; + end + if (rdsr && (!select_ok)) + begin + bit_register <= 0; + q_bis <= #`TSHQZ 1'bz ; + inhib_rdsr <= `TRUE ; + end + end + + always + @(negedge c_int) + begin + if (rdsr && (select_ok)) + begin + q_bis <= #`TCLQV status_register[7 - bit_register] ; + bit_register = bit_register + 1; + end + end + //-------------------------------------------------------------------------------------- + // This process checks select and deselect conditions. Some other conditions are tested: + // prog cycle, deep power down mode and read electronic signature. + always + begin : pin_s + @(s); + begin + if (s == 1'b0) + begin + if (res && only_res) + begin + if ($time != 0) $display("ERROR : The chip must not be selected until tRES"); + end + else if (dp) + begin + if (($time - t_only_res) < `TDP) + begin + if ($time != 0) $display("ERROR : The chip must not be selected until tDP"); + end + else + begin + if ($time != 0) $display("NOTE : Only a Read Electronic Signature instruction will be valid"); + end + end + select_ok <= `TRUE ; + if (pp || wrsr || be || se) + begin + if ($time != 0) $display("NOTE : Only a Read Status Register instruction will be valid"); + only_rdsr <= `TRUE ; + end + end + else + begin + select_ok <= `FALSE ; + only_rdsr <= `FALSE ; + end + end + end + + //-------------------------------------------------------------- + // This Process detects the hardware protection mode + always + @(w or c_int) + begin + if ((w == 1'b0) && ((status_register[7]) == 1'b1)) + begin + write_protect <= `TRUE ; + end + if (w == 1'b1) + begin + write_protect <= `FALSE ; + end + end +endmodule

trunk/verif/models/st_m25p20a/internal_logic.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/run/file.f =================================================================== --- trunk/verif/run/file.f (nonexistent) +++ trunk/verif/run/file.f (revision 3) @@ -0,0 +1,21 @@ ++define+SFLASH_SPDUP ++incdir+../models/st_m25p16 ++incdir+../tb +./time_scale.v +../rtl/top/top.v +../rtl/uart_core/uart_core.v +../rtl/uart_core/clk_ctl.v +../rtl/uart_core/uart_rxfsm.v +../rtl/uart_core/uart_txfsm.v +../rtl/msg_hand/uart_msg_handler.v +../rtl/spi/spi_core.v +../rtl/spi/spi_ctl.v +../rtl/spi/spi_if.v +../rtl/spi/spi_cfg.v +../rtl/lib/registers.v +../tb/tb_top.v +../models/st_m25p16/acdc_check.v +../models/st_m25p16/internal_logic.v +../models/st_m25p16/memory_access.v +../models/st_m25p16/M25p16.v +../tb/uart_agent.v

trunk/verif/run/file.f Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/run/run_nc =================================================================== --- trunk/verif/run/run_nc (nonexistent) +++ trunk/verif/run/run_nc (revision 3) @@ -0,0 +1,5 @@ +ncprep -f file.f +noupdate +overwrite +ncdebug + +./RUN_NC + +

trunk/verif/run/run_nc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/run/run.do =================================================================== --- trunk/verif/run/run.do (nonexistent) +++ trunk/verif/run/run.do (revision 3) @@ -0,0 +1 @@ +run -all

trunk/verif/run/run.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/run/time_scale.v =================================================================== --- trunk/verif/run/time_scale.v (nonexistent) +++ trunk/verif/run/time_scale.v (revision 3) @@ -0,0 +1,2 @@ + +`timescale 1ns/1ps

trunk/verif/run/time_scale.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/run/modelsim.do =================================================================== --- trunk/verif/run/modelsim.do (nonexistent) +++ trunk/verif/run/modelsim.do (revision 3) @@ -0,0 +1 @@ +run -all

trunk/verif/run/modelsim.do Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/run/run_modelsim =================================================================== --- trunk/verif/run/run_modelsim (nonexistent) +++ trunk/verif/run/run_modelsim (revision 3) @@ -0,0 +1,34 @@ +#!/bin/csh -f +# +# test for uart +# + +echo " Compiling with MODELSIM " + +if(! -e work) then + vlib work +endif +vlog -work work +define+SFLASH_SPDUP \ ++incdir+../models/st_m25p16 \ ++incdir+../tb \ +./time_scale.v \ +../../rtl/top/top.v \ +../../rtl/uart_core/uart_core.v \ +../../rtl/uart_core/clk_ctl.v \ +../../rtl/uart_core/uart_rxfsm.v \ +../../rtl/uart_core/uart_txfsm.v \ +../../rtl/msg_hand/uart_msg_handler.v \ +../../rtl/spi/spi_core.v \ +../../rtl/spi/spi_ctl.v \ +../../rtl/spi/spi_if.v \ +../../rtl/spi/spi_cfg.v \ +../../rtl/lib/registers.v \ +../tb/tb_top.v \ +../models/st_m25p16/acdc_check.v \ +../models/st_m25p16/internal_logic.v \ +../models/st_m25p16/memory_access.v \ +../models/st_m25p16/M25p16.v \ +../tb/uart_agent.v \ +-l ../log/compile_modelsim.log + +vsim -do modelsim.do -c tb_top | tee ../log/run_modelsim.log

trunk/verif/run/run_modelsim Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/tb/uart_tasks.v =================================================================== --- trunk/verif/tb/uart_tasks.v (nonexistent) +++ trunk/verif/tb/uart_tasks.v (revision 3) @@ -0,0 +1,138 @@ + +task reg_write; +input [15:0] addr; +input [31:0] data; +reg [7:0] read_data; +reg flag; +begin + fork + begin : loop_1 + tb_top.tb_uart.write_char("w"); + tb_top.tb_uart.write_char("m"); + tb_top.tb_uart.write_char(" "); + tb_top.tb_uart.write_char(hex2char(addr[15:12])); + tb_top.tb_uart.write_char(hex2char(addr[11:8])); + tb_top.tb_uart.write_char(hex2char(addr[7:4])); + tb_top.tb_uart.write_char(hex2char(addr[3:0])); + tb_top.tb_uart.write_char(" "); + tb_top.tb_uart.write_char(hex2char(data[31:28])); + tb_top.tb_uart.write_char(hex2char(data[27:24])); + tb_top.tb_uart.write_char(hex2char(data[23:20])); + tb_top.tb_uart.write_char(hex2char(data[19:16])); + tb_top.tb_uart.write_char(hex2char(data[15:12])); + tb_top.tb_uart.write_char(hex2char(data[11:8])); + tb_top.tb_uart.write_char(hex2char(data[7:4])); + tb_top.tb_uart.write_char(hex2char(data[3:0])); + tb_top.tb_uart.write_char("\n"); + end + begin : loop_2 + // Wait for sucess command + flag = 0; + while(flag == 0) + begin + tb_top.tb_uart.read_char(read_data,flag); + //$write ("%c",read_data); + end + end + join +end +endtask + +task reg_read; +input [15:0] addr; +output [31:0] data; +reg [7:0] read_data; +reg flag; +integer i; +begin + fork + begin : loop_1 + tb_top.tb_uart.write_char("r"); + tb_top.tb_uart.write_char("m"); + tb_top.tb_uart.write_char(" "); + tb_top.tb_uart.write_char(hex2char(addr[15:12])); + tb_top.tb_uart.write_char(hex2char(addr[11:8])); + tb_top.tb_uart.write_char(hex2char(addr[7:4])); + tb_top.tb_uart.write_char(hex2char(addr[3:0])); + tb_top.tb_uart.write_char(" "); + tb_top.tb_uart.write_char("\n"); + end + begin : loop_2 + // Wait for sucess command + flag = 0; + i = 0; + while(flag == 0) + begin + tb_top.tb_uart.read_char(read_data,flag); + //$write ("%d:%c",i,read_data); + case (i) + 8'd10 : data[31:28] = char2hex(read_data); + 8'd11 : data[27:24] = char2hex(read_data); + 8'd12 : data[23:20] = char2hex(read_data); + 8'd13 : data[19:16] = char2hex(read_data); + 8'd14 : data[15:12] = char2hex(read_data); + 8'd15 : data[11:8] = char2hex(read_data); + 8'd16 : data[7:4] = char2hex(read_data); + 8'd17 : data[3:0] = char2hex(read_data); + endcase + i = i+1; + end + end + join + //$display("Receoved Data: %x",data); + +end +endtask + +// Character to hex number +function [3:0] char2hex; +input [7:0] data_in; +case (data_in) + 8'h30: char2hex = 4'h0; // character '0' + 8'h31: char2hex = 4'h1; // character '1' + 8'h32: char2hex = 4'h2; // character '2' + 8'h33: char2hex = 4'h3; // character '3' + 8'h34: char2hex = 4'h4; // character '4' + 8'h35: char2hex = 4'h5; // character '5' + 8'h36: char2hex = 4'h6; // character '6' + 8'h37: char2hex = 4'h7; // character '7' + 8'h38: char2hex = 4'h8; // character '8' + 8'h39: char2hex = 4'h9; // character '9' + 8'h41: char2hex = 4'hA; // character 'A' + 8'h42: char2hex = 4'hB; // character 'B' + 8'h43: char2hex = 4'hC; // character 'C' + 8'h44: char2hex = 4'hD; // character 'D' + 8'h45: char2hex = 4'hE; // character 'E' + 8'h46: char2hex = 4'hF; // character 'F' + 8'h61: char2hex = 4'hA; // character 'a' + 8'h62: char2hex = 4'hB; // character 'b' + 8'h63: char2hex = 4'hC; // character 'c' + 8'h64: char2hex = 4'hD; // character 'd' + 8'h65: char2hex = 4'hE; // character 'e' + 8'h66: char2hex = 4'hF; // character 'f' + default : char2hex = 4'hF; + endcase +endfunction + +// Hex to Asci Character +function [7:0] hex2char; +input [3:0] data_in; +case (data_in) + 4'h0: hex2char = 8'h30; // character '0' + 4'h1: hex2char = 8'h31; // character '1' + 4'h2: hex2char = 8'h32; // character '2' + 4'h3: hex2char = 8'h33; // character '3' + 4'h4: hex2char = 8'h34; // character '4' + 4'h5: hex2char = 8'h35; // character '5' + 4'h6: hex2char = 8'h36; // character '6' + 4'h7: hex2char = 8'h37; // character '7' + 4'h8: hex2char = 8'h38; // character '8' + 4'h9: hex2char = 8'h39; // character '9' + 4'hA: hex2char = 8'h41; // character 'A' + 4'hB: hex2char = 8'h42; // character 'B' + 4'hC: hex2char = 8'h43; // character 'C' + 4'hD: hex2char = 8'h44; // character 'D' + 4'hE: hex2char = 8'h45; // character 'E' + 4'hF: hex2char = 8'h46; // character 'F' + endcase +endfunction Index: trunk/verif/tb/spi_tasks.v =================================================================== --- trunk/verif/tb/spi_tasks.v (nonexistent) +++ trunk/verif/tb/spi_tasks.v (revision 3) @@ -0,0 +1,291 @@ + +// ################################################################# +// Module: spi tasks +// +// Description : All ST and ATMEL commands are made into tasks +// ################################################################# + +event spi_error_detected; +reg [1:0] spi_chip_no; + +integer spi_err_cnt; + +task spi_init; +begin + spi_err_cnt = 0; + spi_chip_no = 0; +end +endtask + + +always @spi_error_detected +begin + //`TB_GLBL.test_err; + spi_err_cnt = spi_err_cnt + 1; +end + +// Write One Byte +task spi_write_byte; + input [7:0] datain; + reg [31:0] read_data; + begin + + @(posedge tb_top.xtal_clk) + tb_top.reg_write('h4,{datain,24'h0}); + tb_top.reg_write('h0,{1'b1,6'h0, + spi_chip_no[1:0], + 2'b0, // Write Operatopm + 2'b0, // Single Transfer + 6'h10, // sck clock period + 5'h2, // cs setup/hold period + 8'h40 }); // cs bit information + + tb_top.reg_read('h0,read_data); + while(read_data[31]) begin + @(posedge tb_top.xtal_clk) ; + tb_top.reg_read('h0,read_data); + end + end +endtask + +//***** ST : Write Enable task ******// +task spi_write_dword; + input [31:0] cmd; + input [7:0] cs_byte; + reg [31:0] read_data; + begin + @(posedge tb_top.xtal_clk) + tb_top.reg_write('h4,{cmd}); + tb_top.reg_write('h0,{1'b1,6'h0, + spi_chip_no[1:0], + 2'b0, // Write Operatopm + 2'h3, // 4 Transfer + 6'h10, // sck clock period + 5'h2, // cs setup/hold period + cs_byte[7:0] }); // cs bit information + + tb_top.reg_read('h0,read_data); + while(read_data[31]) begin + @(posedge tb_top.xtal_clk) ; + tb_top.reg_read('h0,read_data); + end + end +endtask + + +//***** ST : Write Enable task ******// +task spi_read_dword; + output [31:0] dataout; + input [7:0] cs_byte; + reg [31:0] read_data; + begin + + @(posedge tb_top.xtal_clk) + tb_top.reg_write('h0,{1'b1,6'h0, + spi_chip_no[1:0], + 2'b1, // Read Operatopm + 2'h3, // 4 Transfer + 6'h10, // sck clock period + 5'h2, // cs setup/hold period + cs_byte[7:0] }); // cs bit information + + tb_top.reg_read('h0,read_data); + + while(read_data[31]) begin + @(posedge tb_top.xtal_clk) ; + tb_top.reg_read('h0,read_data); + end + + tb_top.reg_read('h8,dataout); + + end +endtask + + + +task spi_sector_errase; + input [23:0] address; + reg [31:0] read_data; + begin + + @(posedge tb_top.xtal_clk) ; + tb_top.reg_write('h4,{8'hD8,address[23:0]}); + tb_top.reg_write('h0,{1'b1,6'h0, + spi_chip_no[1:0], + 2'b0, // Write Operatopm + 2'h3, // 4 Transfer + 6'h10, // sck clock period + 5'h2, // cs setup/hold period + 8'h1 }); // cs bit information + + tb_top.reg_read('h0,read_data); + + $display("%t : %m : Sending Sector Errase for Address : %x",$time,address); + + + tb_top.reg_read('h0,read_data); + while(read_data[31]) begin + @(posedge tb_top.xtal_clk) ; + tb_top.reg_read('h0,read_data); + end + end +endtask + + +task spi_page_write; + input [23:0] address; + reg [7:0] i; + reg [31:0] write_data; + begin + + spi_write_dword({8'h02,address[23:0]},8'h0); + + for(i = 0; i < 252 ; i = i + 4) begin + write_data [31:24] = i; + write_data [23:16] = i+1; + write_data [15:8] = i+2; + write_data [7:0] = i+3; + spi_write_dword(write_data,8'h0); + $display("%m : Writing Data-%d : %x",i,write_data); + end + + // Writting last 4 byte with de-selecting the chip select + write_data [31:24] = i; + write_data [23:16] = i+1; + write_data [15:8] = i+2; + write_data [7:0] = i+3; + spi_write_dword(write_data,8'h1); + $display("%m : Writing Data-%d : %x",i,write_data); + + end +endtask + + +task spi_page_read_verify; + input [23:0] address; + reg [31:0] read_data; + reg [7:0] i; + reg [31:0] exp_data; + begin + + spi_write_dword({8'h03,address[23:0]},8'h0); + + for(i = 0; i < 252 ; i = i + 4) begin + exp_data [31:24] = i; + exp_data [23:16] = i+1; + exp_data [15:8] = i+2; + exp_data [7:0] = i+3; + spi_read_dword(read_data,8'h0); + if(read_data != exp_data) begin + -> spi_error_detected; + $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data); + end else begin + $display("%m : STATUS : Data:%d Matched : %x ",i,read_data); + end + + end + + // Reading last 4 byte with de-selecting the chip select + exp_data [31:24] = i; + exp_data [23:16] = i+1; + exp_data [15:8] = i+2; + exp_data [7:0] = i+3; + + spi_read_dword(read_data,8'h0); + if(read_data != exp_data) begin + -> spi_error_detected; + $display("%m : ERROR : Data:%d-> Exp : %x Rxd : %x",i,exp_data,read_data); + end else begin + $display("%m : STATUS : Data:%d Matched : %x ",i,read_data); + end + + end +endtask + + + + +task spi_op_over; + reg [31:0] read_data; + begin + tb_top.reg_read('h0,read_data); + while(read_data[31]) begin + @(posedge tb_top.xtal_clk) ; + tb_top.reg_read('h0,read_data); + end + #100; + end +endtask + +task spi_wait_busy; + reg [31:0] read_data; + reg exit_flag; + integer pretime; + begin + + read_data = 1; + pretime = $time; + + + exit_flag = 1; + while(exit_flag == 1) begin + + tb_top.reg_write('h4,{8'h05,24'h0}); + tb_top.reg_write('h0,{1'b1,6'h0, + spi_chip_no[1:0], + 2'b0, // Write Operation + 2'b0, // 1 Transfer + 6'h10, // sck clock period + 5'h2, // cs setup/hold period + 8'h0 }); // cs bit information + + + tb_top.reg_read('h0,read_data); + while(read_data[31]) begin + @(posedge tb_top.xtal_clk) ; + tb_top.reg_read('h0,read_data); + end + + // Send Status Request Cmd + + + tb_top.reg_write('h0,{1'b1,6'h0, + spi_chip_no[1:0], + 2'b1, // Read Operation + 2'b0, // 1 Transfer + 6'h10, // sck clock period + 5'h2, // cs setup/hold period + 8'h40 }); // cs bit information + + + tb_top.reg_read('h0,read_data); + while(read_data[31]) begin + @(posedge tb_top.xtal_clk) ; + tb_top.reg_read('h0,read_data); + end + + tb_top.reg_read('h8,read_data); + exit_flag = read_data[24]; + $display("Total time Elapsed: %0t(us): %m : Checking the SPI RDStatus : %x",($time - pretime)/1000000 ,read_data); + repeat (1000) @ (posedge tb_top.xtal_clk) ; + end + end +endtask + + + +task spi_tb_status; +begin + + $display("#############################"); + $display(" Test Statistic "); + if(spi_err_cnt >0) begin + $display("TEST STATUS : FAILED "); + $display("TOTAL ERROR COUNT : %d ",spi_err_cnt); + end else begin + $display("TEST STATUS : PASSED "); + end + $display("#############################"); +end +endtask +

trunk/verif/tb/spi_tasks.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/tb/tb_top.v =================================================================== --- trunk/verif/tb/tb_top.v (nonexistent) +++ trunk/verif/tb/tb_top.v (revision 3) @@ -0,0 +1,173 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// UART2SPI Test Bench Top Module //// +//// //// +//// This file is part of the uart2spi cores project //// +//// http://www.opencores.org/cores/uart2spi/ //// +//// //// +//// Description: //// +//// Uart2SPI testbench top level integration. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +module tb_top; + +parameter XTAL_CLK_PERIOD = 20; // 50Mhz + +reg reset_n; +reg xtal_clk; +initial begin + xtal_clk = 1'b0; + forever #(XTAL_CLK_PERIOD/2.0) xtal_clk = ~xtal_clk; +end + +//------------------------------------- +// Spi I/F +//------------------------------------- +wire spi_sck ; // clock out +wire spi_so ; // serial data out +wire spi_si ; // serial data in +wire [3:0] spi_cs_n ; // cs_n + +top u_uart_top ( + .line_reset_n (reset_n), + .line_clk (xtal_clk), + + // configuration control + .cfg_tx_enable (1'b1), // Enable Transmit Path + .cfg_rx_enable (1'b1), // Enable Received Path + .cfg_stop_bit (1'b1), // 0 -> 1 Start , 1 -> 2 Stop Bits + .cfg_pri_mod (2'b0), // priority mode, 0 -> nop, 1 -> Even, 2 -> Odd + .cfg_baud_16x (12'hA0), + + + // Status information + .frm_error (), + .par_error (), + .baud_clk_16x(uart_clk_16x), + + + // Line Interface + .rxd (rxd), + .txd (txd), + + // line interface + .sck (spi_sck ), + .so (spi_so ), + .si (spi_si ), + .cs_n (spi_cs_n ) + + ); + + +uart_agent tb_uart ( + . test_clk (uart_clk_16x ), + . sin (rxd ), + . dsr_n ( ), + . cts_n ( ), + . dcd_n ( ), + + . sout (txd ), + . dtr_n (1'b0 ), + . rts_n (1'b0 ), + . out1_n (1'b0 ), + . out2_n (1'b0 ) + ); + + + +//----------------------- SPI Agents + +m25p16 i_m25p16_0 ( + .c (spi_sck ), + .s (spi_cs_n[0] ), // Include selection logic + .w (1'b1 ), // Write protect is always disabled + .hold (1'b1 ), // Hold support not used + .data_in (spi_so ), + .data_out (spi_si ) + ); + +reg fifo_enable ; // fifo mode disable +reg [15:0] timeout ;// wait time limit +reg parity_en ; // parity enable +reg stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; +reg [1:0] data_bit ; +reg flag; +reg [7:0] read_data; +reg even_odd_parity ; // 0: odd parity; 1: even parity +initial begin + + reset_n = 1; + #100 reset_n = 0; + #100 reset_n = 1; + + tb_uart.uart_init; + data_bit = 2'b11; + stop_bits = 1'b1; + parity_en = 1'b0; + even_odd_parity = 1'b1; + timeout = 500; + fifo_enable = 0; + tb_top.tb_uart.control_setup (data_bit, stop_bits, parity_en, even_odd_parity, timeout, fifo_enable); + + $write ("\n(%t)Received Character:\n",$time); + flag = 0; + while(flag == 0) + begin + tb_top.tb_uart.read_char(read_data,flag); + //$write ("%c",read_data); + end + + +// uart_test; + spi_test; + + #1000 $finish; +end +//initial begin +//$dumpfile ("spi.vcd"); +//$dumpvars(0); +//end + +//initial begin +//$shm_open("verilog.trn"); +//$shm_probe("tb_top"); +//end +`include "uart_tasks.v" +`include "spi_tasks.v" +`include "uart_test.v" +`include "spi_test.v" + +endmodule + +

trunk/verif/tb/tb_top.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/tb/uart_agent.v =================================================================== --- trunk/verif/tb/uart_agent.v (nonexistent) +++ trunk/verif/tb/uart_agent.v (revision 3) @@ -0,0 +1,444 @@ + +`timescale 1ns/1ps + +module uart_agent ( + test_clk, + sin, + dsr_n, + cts_n, + dcd_n, + + sout, + dtr_n, + rts_n, + out1_n, + out2_n); + +input test_clk; +output sin; +output dsr_n; +output cts_n; +output dcd_n; + +input sout; +input dtr_n; +input rts_n; +input out1_n; +input out2_n; + +event uart_read_done, uart_write_done; +event error_detected,uart_parity_error, uart_stop_error1, uart_stop_error2; +event uart_timeout_error; +event abort; + +reg [15:0] rx_count; +reg [15:0] tx_count; +reg [15:0] par_err_count; +reg [15:0] stop_err1_cnt; +reg [15:0] stop_err2_cnt; +reg [15:0] timeout_err_cnt; +reg [15:0] err_cnt; + +reg sin, read, write; +reg dcd_n; +reg dsr_n, cts_n; +wire test_rx_clk; +reg test_tx_clk; +reg stop_err_check; + +integer timeout_count; +integer data_bit_number; +reg [2:0] clk_count; + +reg error_ind; // 1 indicate error + +initial +begin + sin = 1'b1; + dsr_n = 1'b1; + cts_n = 1'b1; + dcd_n = 1'b1; + test_tx_clk = 0; + clk_count = 0; + stop_err_check = 0; + error_ind = 0; +end + +always @(posedge test_clk) +begin + if (clk_count == 3'h0) + test_tx_clk = ~test_tx_clk; + + clk_count = clk_count + 1; +end +assign test_rx_clk = ~test_tx_clk; + +always @(posedge test_clk) +begin + timeout_count = timeout_count + 1; + if (timeout_count == (control_setup.maxtime * 16)) + -> abort; +end + +always @uart_read_done + rx_count = rx_count + 1; + +always @uart_write_done + tx_count = tx_count + 1; + +always @uart_parity_error begin + error_ind = 1; + par_err_count = par_err_count + 1; +end + +always @uart_stop_error1 begin + error_ind = 1; + stop_err1_cnt = stop_err1_cnt + 1; +end + +always @uart_stop_error2 begin + error_ind = 1; + stop_err2_cnt = stop_err2_cnt + 1; +end + +always @uart_timeout_error begin + error_ind = 1; + timeout_err_cnt = timeout_err_cnt + 1; +end + + +always @error_detected begin + error_ind = 1; + err_cnt = err_cnt + 1; +end + + +//////////////////////////////////////////////////////////////////////////////// +task uart_init; +begin + read = 0; + write = 0; + tx_count = 0; + rx_count = 0; + stop_err_check = 0; + par_err_count = 0; + stop_err1_cnt = 0; + stop_err2_cnt = 0; + timeout_err_cnt = 0; + err_cnt = 0; + +end +endtask + + +//////////////////////////////////////////////////////////////////////////////// +task read_char_chk; +input expected_data; + +integer i; +reg [7:0] expected_data; +reg [7:0] data; +reg parity; + +begin + data <= 8'h0; + parity <= 1; + timeout_count = 0; + +fork + begin : loop_1 + @(abort) + $display (">>>>> Exceed time limit, uart no responce.\n"); + ->uart_timeout_error; + disable loop_2; + end + + begin : loop_2 + +// start cycle + @(negedge sout) + disable loop_1; + read <= 1; + +// data cycle + @(posedge test_rx_clk); + for (i = 0; i < data_bit_number; i = i + 1) + begin + @(posedge test_rx_clk) + data[i] <= sout; + parity <= parity ^ sout; + end + +// parity cycle + if(control_setup.parity_en) + begin + @(posedge test_rx_clk); + if ((control_setup.even_odd_parity && (sout == parity)) || + (!control_setup.even_odd_parity && (sout != parity))) + begin + $display (">>>>> Parity Error"); + -> error_detected; + -> uart_parity_error; + end + end + +// stop cycle 1 + @(posedge test_rx_clk); + if (!sout) + begin + $display (">>>>> Stop signal 1 Error"); + -> error_detected; + -> uart_stop_error1; + end + +// stop cycle 2 + if (control_setup.stop_bit_number) + begin + @(posedge test_rx_clk); // stop cycle 2 + if (!sout) + begin + $display (">>>>> Stop signal 2 Error"); + -> error_detected; + -> uart_stop_error2; + end + end + +/* Who Cares +// the stop bits transmitted is one and a half if it is 5-bit + if (data_bit_number == 5) + begin + @(posedge test_rx_clk); // stop cycle for 5-bit/per char + if (!sout) + begin + $display (">>>>> Stop signal 2 Error (5-Bit)"); + -> error_detected; + -> uart_stop_error2; + end + end + else +*/ + +// wait another half cycle for tx_done signal + @(negedge test_rx_clk); + read <= 0; + -> uart_read_done; + + if (expected_data != data) + begin + $display ("Error! Data return is %h, expecting %h", data, expected_data); + -> error_detected; + end + else + $display ("(%m) Data match %h", expected_data); + + $display ("... Read Data from UART done cnt :%d...",rx_count +1); + end +join + +end + +endtask + +//////////////////////////////////////////////////////////////////////////////// +task read_char; +output [7:0] rxd_data; +output timeout; // 1-> timeout +integer i; +reg [7:0] rxd_data; +reg [7:0] data; +reg parity; + +begin + data <= 8'h0; + parity <= 1; + timeout_count = 0; + timeout = 0; + +fork + begin : loop_1 + @(abort) + //$display (">>>>> Exceed time limit, uart no responce.\n"); + //->uart_timeout_error; + timeout = 1; + disable loop_2; + end + + begin : loop_2 + +// start cycle + @(negedge sout) + disable loop_1; + read <= 1; + +// data cycle + @(posedge test_rx_clk); + for (i = 0; i < data_bit_number; i = i + 1) + begin + @(posedge test_rx_clk) + data[i] <= sout; + parity <= parity ^ sout; + end + +// parity cycle + if(control_setup.parity_en) + begin + @(posedge test_rx_clk); + if ((control_setup.even_odd_parity && (sout == parity)) || + (!control_setup.even_odd_parity && (sout != parity))) + begin + $display (">>>>> Parity Error"); + -> error_detected; + -> uart_parity_error; + end + end + +// stop cycle 1 + @(posedge test_rx_clk); + if (!sout) + begin + $display (">>>>> Stop signal 1 Error"); + -> error_detected; + -> uart_stop_error1; + end + +// stop cycle 2 + if (control_setup.stop_bit_number) + begin + @(posedge test_rx_clk); // stop cycle 2 + if (!sout) + begin + $display (">>>>> Stop signal 2 Error"); + -> error_detected; + -> uart_stop_error2; + end + end + +// wait another half cycle for tx_done signal + @(negedge test_rx_clk); + read <= 0; + -> uart_read_done; + +// $display ("(%m) Received Data %c", data); +// $display ("... Read Data from UART done cnt :%d...",rx_count +1); + $write ("%c",data); + rxd_data = data; + end +join + +end + +endtask + +//////////////////////////////////////////////////////////////////////////////// +task write_char; +input [7:0] data; + +integer i; +reg parity; // 0: odd parity, 1: even parity + +begin + parity <= #1 1; + +// start cycle + @(posedge test_tx_clk) + begin + sin <= #1 0; + write <= #1 1; + end + +// data cycle + begin + for (i = 0; i < data_bit_number; i = i + 1) + begin + @(posedge test_tx_clk) + sin <= #1 data[i]; + parity <= parity ^ data[i]; + end + end + +// parity cycle + if (control_setup.parity_en) + begin + @(posedge test_tx_clk) + sin <= #1 + control_setup.even_odd_parity ? !parity : parity; + end + +// stop cycle 1 + @(posedge test_tx_clk) + sin <= #1 stop_err_check ? 0 : 1; + +// stop cycle 2 + @(posedge test_tx_clk); + sin <= #1 1; + if (data_bit_number == 5) + @(negedge test_tx_clk); + else if (control_setup.stop_bit_number) + @(posedge test_tx_clk); + + write <= #1 0; + // $display ("... Write data %h to UART done cnt : %d ...\n", data,tx_count+1); + $write ("%c",data); + -> uart_write_done; +end +endtask + + +//////////////////////////////////////////////////////////////////////////////// +task control_setup; +input [1:0] data_bit_set; +input stop_bit_number; +input parity_en; +input even_odd_parity; +input [15:0] maxtime; +input fifo_enable; + +begin + data_bit_number = data_bit_set + 5; +end +endtask + + +//////////////////////////////////////////////////////////////////////////////// +task report_status; +output [15:0] rx_nu; +output [15:0] tx_nu; +begin + $display ("-------------------- Reporting Configuration --------------------"); + $display (" Data bit number setting is : %0d", data_bit_number); + $display (" Stop bit number setting is : %0d", control_setup.stop_bit_number + 1); + if (control_setup.parity_en) + $display (" Parity is enable"); + else + $display (" Parity is disable"); + + if (control_setup.even_odd_parity) + $display (" Even parity setting"); + else + $display (" Odd parity setting"); + + if (control_setup.fifo_enable) + $display (" FIFO mode is enable"); + else + $display (" FIFO mode is disable"); + + $display ("-----------------------------------------------------------------"); + + $display ("-------------------- Reporting Status --------------------\n"); + $display (" Number of character received is : %d", rx_count); + $display (" Number of character sent is : %d", tx_count); + $display (" Number of parity error rxd is : %d", par_err_count); + $display (" Number of stop1 error rxd is : %d", stop_err1_cnt); + $display (" Number of stop2 error rxd is : %d", stop_err2_cnt); + $display (" Number of timeout error is : %d", timeout_err_cnt); + $display (" Number of error is : %d", err_cnt); + $display ("-----------------------------------------------------------------"); + + rx_nu = rx_count; + tx_nu = tx_count; +end +endtask + + +//////////////////////////////////////////////////////////////////////////////// +endmodule

trunk/verif/tb/uart_agent.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/tb/uart_test.v =================================================================== --- trunk/verif/tb/uart_test.v (nonexistent) +++ trunk/verif/tb/uart_test.v (revision 3) @@ -0,0 +1,54 @@ +task uart_test; + +reg [1:0] data_bit ; +reg stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; +reg parity_en ; // parity enable +reg even_odd_parity ; // 0: odd parity; 1: even parity + +reg [15:0] timeout ;// wait time limit + +reg [15:0] rx_nu; +reg [15:0] tx_nu; +reg [7:0] read_data; +reg [31:0] read_word; +reg [7:0] write_data; +reg flag; +reg fifo_enable ; // fifo mode disable +integer i,j; +begin +tb_uart.uart_init; + +data_bit = 2'b11; +stop_bits = 1'b1; +parity_en = 1'b0; +even_odd_parity = 1'b1; +timeout = 500; +fifo_enable = 0; + + tb_top.tb_uart.control_setup (data_bit, stop_bits, parity_en, even_odd_parity, timeout, fifo_enable); + + + + $write ("\n(%t)Received Character:\n",$time); + flag = 0; + while(flag == 0) + begin + tb_top.tb_uart.read_char(read_data,flag); + //$write ("%c",read_data); + end + + + tb_top.reg_write(16'h0000,32'h11223344); + tb_top.reg_write(16'h0004,32'h55667788); + + + tb_top.reg_read(16'h0000,read_word); + tb_top.reg_read(16'h0004,read_word); + + #100 + tb_top.tb_uart.report_status(rx_nu, tx_nu); + +end +endtask + +

trunk/verif/tb/uart_test.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/verif/tb/spi_test.v =================================================================== --- trunk/verif/tb/spi_test.v (nonexistent) +++ trunk/verif/tb/spi_test.v (revision 3) @@ -0,0 +1,32 @@ +/***************************************************** + Verify the Read/Write in ST Flash +*****************************************************/ + + +task spi_test; +begin + + $display("############################################"); + $display(" Testing ST Flash Read/Write Access "); + $display("############################################"); + + + tb_top.spi_init(); // SPI Tb Init + tb_top.spi_chip_no = 2'b00; // Select the Chip Select to zero + // Write Enable command + tb_top.spi_write_byte(8'h6); // Write Enable instruction + tb_top.spi_sector_errase(24'h00); + tb_top.spi_wait_busy; + + // Page Write + tb_top.spi_write_byte(8'h6); // Write Enable instruction + tb_top.spi_page_write(24'h00); + tb_top.spi_wait_busy; + + // Page Read + tb_top.spi_page_read_verify(24'h00); // Read and verify 256 Bytes + + + tb_top.spi_tb_status; // SPI Tb Init +end +endtask

trunk/verif/tb/spi_test.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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