OpenCores
URL https://opencores.org/ocsvn/uart_block/uart_block/trunk

Subversion Repositories uart_block

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /uart_block
    from Rev 37 to Rev 38
    ↔ Reverse comparison
  •

Rev 37 → Rev 38

/trunk/hdl/iseProject/isim.log
1,5 → 1,5
ISim log file
Running: E:\uart_block\hdl\iseProject\testUart_wishbone_slave_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.wdb
Running: E:\uart_block\hdl\iseProject\testSerial_receiver_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.wdb
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
13,12 → 13,238
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartControl/uDiv/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
at 10 ns(1), Instance /testuart_wishbone_slave/uut/uUartCommunicationBlocks/uBaudGen/ : Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testUart_wishbone_slave.vhd:stim_proc
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 106
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 67
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 29
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 92
# run all
Stopped at time : 36220620100 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 106
# step
Stopped at time : 107415 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
# run all
Stopped at time : 5831395972500 ps : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 37
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 106
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 108
# run all
Stopped at time : 176610 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 112
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:Wrong result... expected 0xC4
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
 
** Failure:Wrong result... expected 0x55
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
# run all
Stopped at time : 7368665202500 ps : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 68
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
# run all
Stopped at time : 45201791145 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 66
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 105787500 ps : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 186
# run all
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 105
# run all
Stopped at time : 12853995542500 ps : File "E:/uart_block/hdl/iseProject/serial_receiver.vhd" Line 33
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 107
ISim O.87xd (signature 0xc3576ebc)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
 
 
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ms
Simulator is doing circuit initialization process.
Finished circuit initialization process.
Stopped at time : 107166 ns : File "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" Line 107
# run all
 
** Failure:NONE. End of simulation.
User(VHDL) Code Called Simulation Stop
In process testSerial_receiver.vhd:stim_proc
INFO: Simulator is stopped.
/trunk/hdl/iseProject/testSerial_receiver.vhd
1,4 → 1,7
--! Test serial_receiver module
--! @file
--! @brief Test serial_receiver module module
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
8,6 → 11,8
ENTITY testSerial_receiver IS
END testSerial_receiver;
--! @brief Test serial_receiver module module
--! @details Receive some simulated byte stream and verify received values
ARCHITECTURE behavior OF testSerial_receiver IS
-- Component Declaration for the Unit Under Test (UUT)
97,7 → 102,9
wait for baudClk_period;
-- Stop bit here
serial_in <= '1';
serial_in <= '1';
---wait until data_ready = '1';
assert data_byte = X"C4" report "Wrong result... expected 0xC4" severity failure;
wait for baudClk_period * 8;
-- Receive 0x55 value (01010101)
125,6 → 132,8
-- Stop bit here
serial_in <= '1';
wait for baudClk_period * 1;
---wait until data_ready = '1';
assert data_byte = X"55" report "Wrong result... expected 0x55" severity failure;
 
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
/trunk/hdl/iseProject/fuseRelaunch.cmd
1,6 → 132,8
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj" "work.testUart_wishbone_slave"
-intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "testSerial_receiver"
/trunk/hdl/iseProject/testDivisor.vhd
1,4 → 1,7
--! Test divisor module
--! @file
--! @brief Test divisor module
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
9,6 → 12,8
ENTITY testDivisor IS
END testDivisor;
--! @brief Test divisor module
--! @details Calculate some divisions and verify if we have the right value
ARCHITECTURE behavior OF testDivisor IS
-- Component Declaration for the Unit Under Test (UUT)
68,19 → 73,21
rst <= '1';
numerator <= conv_std_logic_vector(50000000, 32);
divident <= conv_std_logic_vector(115200, 32);
wait for 20 ns;
wait for clk_period;
rst <= '0';
wait until done = '1';
wait until done = '1';
assert quotient = conv_std_logic_vector(434, 32) report "Wrong result... expected 434." severity failure;
wait for clk_period;
rst <= '1';
numerator <= conv_std_logic_vector(40, 32);
divident <= conv_std_logic_vector(5, 32);
wait for 20 ns;
wait for clk_period;
rst <= '0';
wait until done = '1';
wait until done = '1';
assert quotient = conv_std_logic_vector(8, 32) report "Wrong result... expected 8." severity failure;
wait for clk_period;
 
-- insert stimulus here
/trunk/hdl/iseProject/testSerial_receiver_beh.prj
1,3 → 1,3
vhdl work "pkgDefinitions.vhd"
vhdl work "serial_receiver.vhd"
vhdl work "testSerial_receiver.vhd"
vhdl work "pkgDefinitions.vhd"
vhdl work "serial_receiver.vhd"
vhdl work "testSerial_receiver.vhd"
/trunk/hdl/iseProject/fuse.log
1,37 → 1,21
Running: e:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -o E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe -prj E:/uart_block/hdl/iseProject/testUart_wishbone_slave_beh.prj work.testUart_wishbone_slave
Running: fuse.exe -relaunch -intstyle "ise" -incremental -o "E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe" -prj "E:/uart_block/hdl/iseProject/testSerial_receiver_beh.prj" "testSerial_receiver"
ISim O.87xd (signature 0xc3576ebc)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "E:/uart_block/hdl/iseProject/pkgDefinitions.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_transmitter.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/serial_receiver.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/divisor.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/baud_generator.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_control.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" into library work
WARNING:HDLCompiler:946 - "E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 62: Actual for formal port rst is neither a static name nor a globally static expression
Parsing VHDL file "E:/uart_block/hdl/iseProject/uart_wishbone_slave.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testUart_wishbone_slave.vhd" into library work
Parsing VHDL file "E:/uart_block/hdl/iseProject/testSerial_receiver.vhd" into library work
Starting static elaboration
Completed static elaboration
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling package std_logic_unsigned
Compiling package pkgdefinitions
Compiling architecture behavioral of entity divisor [divisor_default]
Compiling architecture behavioral of entity uart_control [uart_control_default]
Compiling package numeric_std
Compiling architecture behavioral of entity baud_generator [baud_generator_default]
Compiling architecture behavioral of entity serial_transmitter [serial_transmitter_default]
Compiling architecture behavioral of entity serial_receiver [serial_receiver_default]
Compiling architecture behavioral of entity uart_communication_blocks [uart_communication_blocks_defaul...]
Compiling architecture behavioral of entity uart_wishbone_slave [uart_wishbone_slave_default]
Compiling architecture behavior of entity testuart_wishbone_slave
Compiling architecture behavior of entity testserial_receiver
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 21 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testUart_wishbone_slave_isim_beh.exe
Fuse Memory Usage: 37428 KB
Fuse CPU Usage: 420 ms
Compiled 6 VHDL Units
Built simulation executable E:/uart_block/hdl/iseProject/testSerial_receiver_isim_beh.exe
Fuse Memory Usage: 29596 KB
Fuse CPU Usage: 234 ms
/trunk/hdl/iseProject/iseProject.xise
16,7 → 16,7
 
<files>
<file xil_pn:name="serial_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="pkgDefinitions.vhd" xil_pn:type="FILE_VHDL">
30,17 → 30,17
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="serial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="testSerial_receiver.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="divisor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="testDivisor.vhd" xil_pn:type="FILE_VHDL">
50,7 → 50,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="baud_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="testBaud_generator.vhd" xil_pn:type="FILE_VHDL">
60,7 → 60,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="uart_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="testUart_communication_block.vhd" xil_pn:type="FILE_VHDL">
70,7 → 70,7
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="uart_communication_blocks.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="testUart_control.vhd" xil_pn:type="FILE_VHDL">
80,11 → 80,11
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="117"/>
</file>
<file xil_pn:name="uart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="testUart_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="164"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="164"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="164"/>
331,8 → 331,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testUart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
348,7 → 348,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testUart_wishbone_slave" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testSerial_receiver" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
398,7 → 398,7
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testUart_wishbone_slave|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testSerial_receiver|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
/trunk/hdl/iseProject/iseProject.gise
146,11 → 146,12
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="serial_transmitter_xst.xrpt"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testBaud_generator_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testDivisor_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testSerial_receiver_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testSerial_transmitter_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_communication_block_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_control_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testUart_wishbone_slave_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="testUart_wishbone_slave_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="uart_communication_blocks.cmd_log"/>
202,13 → 203,9
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336250815" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1336250815">
<transform xil_pn:end_ts="1336603169" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1336603169">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.vhd"/>
<outfile xil_pn:name="SERIALMASTER.vhd"/>
<outfile xil_pn:name="SYC0001a.vhd"/>
228,11 → 225,11
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1336250968" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5308805702929486166" xil_pn:start_ts="1336250968">
<transform xil_pn:end_ts="1336603169" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-8542187049970039926" xil_pn:start_ts="1336603169">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336250968" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-1238851900205137108" xil_pn:start_ts="1336250968">
<transform xil_pn:end_ts="1336603169" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="8521261985131728908" xil_pn:start_ts="1336603169">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
240,14 → 237,9
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1336250815" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1336250815">
<transform xil_pn:end_ts="1336603169" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1336603169">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="INTERCON_P2P.vhd"/>
<outfile xil_pn:name="SERIALMASTER.vhd"/>
<outfile xil_pn:name="SYC0001a.vhd"/>
267,29 → 259,22
<outfile xil_pn:name="uart_control.vhd"/>
<outfile xil_pn:name="uart_wishbone_slave.vhd"/>
</transform>
<transform xil_pn:end_ts="1336250972" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="8691405173963172662" xil_pn:start_ts="1336250968">
<transform xil_pn:end_ts="1336603171" xil_pn:in_ck="8052531156335828411" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-728369216885656586" xil_pn:start_ts="1336603169">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testUart_wishbone_slave_beh.prj"/>
<outfile xil_pn:name="testUart_wishbone_slave_isim_beh.exe"/>
<outfile xil_pn:name="testSerial_receiver_beh.prj"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1336250972" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="7109246390254422178" xil_pn:start_ts="1336250972">
<transform xil_pn:end_ts="1336603172" xil_pn:in_ck="7043554240611338668" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="1766511671646254562" xil_pn:start_ts="1336603171">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="testSerial_receiver_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1335914570" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1335914570">
<status xil_pn:value="SuccessfullyRun"/>
/trunk/hdl/iseProject/testSerial_receiver_isim_beh.wdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/hdl/iseProject/_xmsgs/pn_parser.xmsgs
8,7 → 8,7
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testBaud_generator.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;E:/uart_block/hdl/iseProject/testSerial_receiver.vhd&quot; into library work</arg>
</msg>
 
</messages>
/trunk/hdl/iseProject/testBaud_generator.vhd
1,4 → 1,7
--! Test baud_generator module
--! @file
--! @brief Test baud_generator module
 
--! Use standard library and import the packages (std_logic_1164,std_logic_unsigned,std_logic_arith)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
7,9 → 10,11
--! Use Global Definitions package
use work.pkgDefinitions.all;
ENTITY testBaud_generator IS
ENTITY testBaud_generator IS
END testBaud_generator;
--! @brief Test baud_generator module
--! @details Exercise the baud generator with 50Mhz clock and dividing by 434, finally checking for period of 8.68 us
ARCHITECTURE behavior OF testBaud_generator IS
COMPONENT baud_generator
31,7 → 36,7
signal baud_oversample : std_logic; --! Signal to connect with UUT
 
-- Clock period definitions (1.8432MHz)
constant clk_period : time := 0.543 us; -- 0.543us (1.8432Mhz) 2ns (50Mhz)
constant clk_period : time := 20 ns; -- 0.543us (1.8432Mhz) 20ns (50Mhz)
BEGIN
56,16 → 61,30
 
-- Stimulus process
stim_proc: process
begin
-- Test the baud generator waiting for 16 clock cycles for 1.8432MHz clock
variable t1 : time;
variable t2 : time;
variable period : time; -- 1/115200 = 8.68 us
begin
-- Test the baud generator waiting for 434 clock cycles from 50MHz clock
rst <= '1';
cycle_wait <= conv_std_logic_vector(16, (nBitsLarge));
wait for 2 ns;
cycle_wait <= conv_std_logic_vector(434, (nBitsLarge)); -- 50000000/115200
wait for clk_period;
rst <= '0';
 
wait for clk_period*300;
 
-- Stop Simulation
wait until baud = '1';
t1 := now; -- Get current simulation time
wait until baud = '0';
wait until baud = '1';
t2 := now; -- Get current simulation time
wait until baud = '0';
wait until baud = '1';
report "Current sim time=" & time'image(now);
period := t2 - t1;
-- Verify if we have the right period 1/115200 = 8.68 us
assert period = 8.68 us report "Wrong period expecter 8.68 us. got: "& time'image(period) severity failure;
-- Stop Simulation
assert false report "NONE. End of simulation." severity failure;
 
wait;
/trunk/hdl/iseProject/fuse.xmsgs
5,8 → 5,5
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="946" delta="unknown" >"E:/uart_block/hdl/iseProject/uart_communication_blocks.vhd" Line 62: Actual for formal port <arg fmt="%s" index="1">rst</arg> is neither a static name nor a globally static expression
</msg>
 
</messages>
 

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