URL
https://opencores.org/ocsvn/udp_ip__core/udp_ip__core/trunk
Subversion Repositories udp_ip__core
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/udp_ip__core
- from Rev 1 to Rev 2
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Rev 1 → Rev 2
/trunk/JAVA_app/setup.sh
0,0 → 1,16
#! /bin/sh |
|
# This script sets up the basic network configuration and a 'fake' ARP table |
# entry for the FPGA. |
# We assume that the FPGA is connected to the ethernet port eth0. |
# The IP adress of the PC is fixed to 192.168.1.2, the IP of the FPGA |
# is fixed to 192.168.1.1. |
# The ARP table entry will cause every packet sent to 192.168.1.1 |
# to be routed to the FPGA. |
|
sudo ifconfig eth0 down |
|
sudo ifconfig eth0 -arp |
sudo ifconfig eth0 192.168.1.2 |
sudo arp -i eth0 -s 192.168.1.1 FF:FF:FF:FF:FF:FF |
sudo ifconfig eth0 mtu 9000 |
trunk/JAVA_app/setup.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/JAVA_app/GigaRxLossy.java
===================================================================
--- trunk/JAVA_app/GigaRxLossy.java (nonexistent)
+++ trunk/JAVA_app/GigaRxLossy.java (revision 2)
@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) 2010 Simon A. Berger
+ *
+ * This program is free software; you may redistribute it and/or modify its
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+
+/*
+ * This is the code used for the evaluation of the FPGA/PC communication using
+ * UDP/IP.
+ * This program can operate in two modes, which correspond to the two evaluations
+ * in the paper:
+ * - one way test: receive packets for 10 seconds. Calculate actual number of
+ * sent packets from the serial numbers.
+ * - two way (duplex) test: send a fixed number of packets and count received
+ * packets.
+ *
+ * The program mode is controlled with the DUPLEX_TEST constant.
+ *
+ * To compile this program use "javac GigaRxLossy.java"
+ * To run the program use "java GigaRxLoss"
+ */
+
+import java.io.IOException;
+import java.net.DatagramPacket;
+import java.net.DatagramSocket;
+import java.net.InetAddress;
+import java.net.InetSocketAddress;
+import java.net.SocketAddress;
+import java.nio.ByteBuffer;
+import java.nio.MappedByteBuffer;
+import java.nio.IntBuffer;
+import java.nio.DoubleBuffer;
+
+import java.nio.channels.ClosedByInterruptException;
+import java.nio.channels.DatagramChannel;
+
+
+public class GigaRxLossy {
+ public static boolean isValid( ByteBuffer b, int size ) {
+ int ref = b.get();
+
+ for( int i = 1; i < size; i++ ) {
+ if( b.get() != ref ) {
+
+ return false;
+ }
+ }
+
+ return true;
+ }
+
+ public static void main(String[] args) throws IOException, InterruptedException {
+ final int MTU = 1500;
+
+ final SocketAddress rxaddr = new InetSocketAddress( 21844 );
+
+ final DatagramChannel rxc = DatagramChannel.open();
+
+ rxc.socket().bind(rxaddr);
+
+ final SocketAddress txsendtoaddr = new InetSocketAddress( "192.168.1.1", 21845 );
+
+
+ // set this constant to:
+ // - false for the one-way test
+ // - true for the duplex test
+
+ boolean DUPLEX_TEST = !true;
+
+
+ boolean haveTx;
+ boolean trigger;
+ if( DUPLEX_TEST ) {
+ haveTx = true;
+ trigger = false;
+
+ } else {
+ haveTx = false;
+ trigger = true;
+ }
+
+
+ final DatagramChannel txc;
+
+ if( haveTx || trigger )
+ {
+ txc = DatagramChannel.open();
+ txc.socket().bind(null);
+ } else {
+ txc = null;
+ }
+
+ final Thread reader = new Thread() {
+ // this is the recaiver thread
+ @Override
+ public void run() {
+
+ java.nio.ByteBuffer rxb = ByteBuffer.allocateDirect(MTU);
+
+ boolean first = true;
+ int firstser = -1;
+ int lastser = -1;
+ int nrec = 0;
+ long time = System.currentTimeMillis();
+
+ long rxbytes = 0;
+ long txn = 0;
+ try {
+ //rxc.connect(rxaddr);
+
+
+ while( !isInterrupted() ) {
+
+ rxb.rewind();
+ rxc.receive(rxb);
+ int rxsize = rxb.position();
+
+ rxb.rewind();
+ //int ser = rxb.asIntBuffer().get(0);
+ IntBuffer ib = rxb.asIntBuffer();
+// DoubleBuffer db = rxb.asDoubleBuffer();
+
+ int ser = ib.get()>>>24;
+
+ // calculate the number of actually sent packets from the serial
+ // number.
+ if( !first ) {
+ if( ser < lastser ) {
+ txn += ser - (lastser - 256 );
+ } else {
+ txn += ser - lastser;
+ }
+ //System.out.printf( "int %d\n", txn );
+ } else {
+ first = false;
+ }
+ lastser = ser;
+
+ if( firstser == -1 ) {
+ firstser = ser;
+ }
+
+
+ // for maximum speed the validity check may be disabled as the current
+ // implementation is fairly inefficient. In our tests we never got any
+ // packet corruption.
+ boolean CHECK_VALID = true;
+ if( CHECK_VALID ) {
+ if( !isValid( rxb, rxsize ) ) {
+ System.out.println( "invalid" );
+ }
+ }
+// lastser = ser;
+ nrec++;
+ rxbytes+=rxsize;
+
+ }
+ } catch( ClosedByInterruptException e ) {
+ System.out.printf( "reader: interrupted. bye ...\n" );
+
+ } catch (IOException e) {
+
+ // TODO Auto-generated catch block
+ e.printStackTrace();
+ throw new RuntimeException( "bailing out." );
+ }
+ long dt = System.currentTimeMillis() - time;
+ System.out.printf( "%d bytes in %d ms: %.2f Mb/s\n", rxbytes, dt, rxbytes / (dt * 1000.0) );
+ int serrange = (lastser - firstser) + 1;
+ System.out.printf( "nrec: %d of %d (%.2f%%)\n", nrec, txn, nrec / (float)txn * 100.0 );
+ }
+ };
+
+ if( !trigger ) {
+ reader.start();
+ }
+
+ if( haveTx ) {
+ Thread writer = new Thread() {
+ // this is the sender thread.
+ @Override
+ public void run() {
+ // TODO Auto-generated method stub
+ //java.nio.ByteBuffer txb = MappedByteBuffer.allocate(MTU);
+ java.nio.ByteBuffer txb = java.nio.ByteBuffer.allocateDirect(MTU);
+ int i = 0;
+ long time = System.currentTimeMillis();
+
+ long txbytes = 0;
+ long nj = 0;
+ while( i < 1000000 ) {
+ txb.rewind();
+
+ txb.asIntBuffer().put(0, i);
+ txb.rewind();
+ try {
+ txbytes += txc.send(txb, txsendtoaddr);
+
+
+
+ } catch (IOException e) {
+ // TODO Auto-generated catch block
+ e.printStackTrace();
+ }
+ i++;
+
+ if( i % 10000 == 0 ) {
+ System.out.printf( "tx -> rx %d\n", i );
+ }
+
+ // if( ack.i != -1 ) {
+ // i = ack.i;
+ // ack.i = -1;
+ // }
+ }
+ long dt = System.currentTimeMillis() - time;
+ System.out.printf( "%d bytes in %d ms: %.2f Mb/s\n", txbytes, dt, txbytes / (dt * 1000.0) );
+ }
+ };
+
+
+
+ writer.start();
+
+ writer.join();
+ reader.interrupt();
+ } else {
+ if( trigger ) {
+ java.nio.ByteBuffer txb = java.nio.ByteBuffer.allocateDirect(MTU);
+ txc.send(txb, txsendtoaddr);
+ Thread.sleep( 1000 );
+ }
+ reader.start();
+ Thread.sleep(10000);
+ reader.interrupt();
+ }
+ }
+}
trunk/JAVA_app/GigaRxLossy.java
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/PAPER/alachiot_berg_stamatak__UDP_IP_core.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/PAPER/alachiot_berg_stamatak__UDP_IP_core.pdf
===================================================================
--- trunk/PAPER/alachiot_berg_stamatak__UDP_IP_core.pdf (nonexistent)
+++ trunk/PAPER/alachiot_berg_stamatak__UDP_IP_core.pdf (revision 2)
trunk/PAPER/alachiot_berg_stamatak__UDP_IP_core.pdf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.xco
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.xco (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.xco (revision 2)
@@ -0,0 +1,59 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Feb 04 10:01:48 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s200
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ft256
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Comparator family Xilinx,_Inc. 9.0
+# END Select
+# BEGIN Parameters
+CSET aclr=false
+CSET ainitval=0
+CSET aset=false
+CSET ce=false
+CSET cepriority=Sync_Overrides_CE
+CSET component_name=comp_11b_equal
+CSET constantbport=false
+CSET constantbportvalue=0000000000000000
+CSET datatype=Unsigned
+CSET nonregisteredoutput=false
+CSET operation=eq
+CSET pipelinestages=0
+CSET radix=2
+CSET registeredoutput=true
+CSET sclr=false
+CSET sset=false
+CSET syncctrlpriority=Reset_Overrides_Set
+CSET width=11
+# END Parameters
+GENERATE
+# CRC: 40267d7f
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.xco
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/PACKET_RECEIVER_FSM.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/PACKET_RECEIVER_FSM.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/PACKET_RECEIVER_FSM.vhd (revision 2)
@@ -0,0 +1,238 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 03:48:34 02/07/2010
+-- Design Name:
+-- Module Name: PACKET_RECEIVER_FSM - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PACKET_RECEIVER_FSM is
+ Port (
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+
+ -- Signals from EMAC
+ rx_sof: in STD_LOGIC; -- active low input
+ rx_eof: in STD_LOGIC; -- active low input
+
+ -- Signals to Counter and Comparator
+ sel_comp_Bval: out STD_LOGIC;
+ comp_Bval: out STD_LOGIC_VECTOR(10 downto 0);
+ rst_count : out STD_LOGIC;
+ en_count : out STD_LOGIC;
+
+ -- Signal from Comparator
+ comp_eq: in STD_LOGIC;
+
+ -- Signals to Length Register
+ wren_MSbyte: out STD_LOGIC;
+ wren_LSbyte: out STD_LOGIC;
+
+ -- Signal to user interface
+ valid_out_usr_data: out STD_LOGIC);
+end PACKET_RECEIVER_FSM;
+
+architecture Behavioral of PACKET_RECEIVER_FSM is
+
+TYPE state is (rst_state,
+ idle_state,
+ detect_n_store_usr_length_MSbyte_state,
+ store_usr_length_LSbyte_state,
+ checksum_gap_state,
+ receive_usr_data_state);
+
+signal current_st,next_st: state;
+
+constant udp_length_match_cycle : std_logic_vector(10 downto 0):="00000100100"; -- UDP length MSbyte - 2
+constant udp_checksum_skip : std_logic_vector(10 downto 0):="00000000001";
+constant gnd_vec : std_logic_vector(10 downto 0):="00000000000";
+begin
+
+process(current_st,rx_sof,rx_eof,comp_eq)
+begin
+case current_st is
+
+
+when rst_state =>
+
+ sel_comp_Bval<='0';
+ comp_Bval<=gnd_vec;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=idle_state;
+
+when idle_state =>
+
+ if rx_sof='0' then -- rx_sof is active low
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_length_match_cycle;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=detect_n_store_usr_length_MSbyte_state;
+
+ else
+ sel_comp_Bval<='0';
+ comp_Bval<=gnd_vec;
+ rst_count<='0';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=idle_state;
+ end if;
+
+when detect_n_store_usr_length_MSbyte_state =>
+
+ if comp_eq='1' then -- comp_eq is active high
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='1';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=store_usr_length_LSbyte_state;
+
+ else
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_length_match_cycle;
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=detect_n_store_usr_length_MSbyte_state;
+ end if;
+
+when store_usr_length_LSbyte_state =>
+
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='1';
+
+ valid_out_usr_data<='0';
+
+ next_st<=checksum_gap_state;
+
+when checksum_gap_state =>
+
+ if comp_eq='1' then -- comp_eq is active high
+ sel_comp_Bval<='1';
+ comp_Bval<=gnd_vec;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=receive_usr_data_state;
+
+ else
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_checksum_skip;
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=checksum_gap_state;
+ end if;
+
+when receive_usr_data_state =>
+
+ if (comp_eq='1' or rx_eof='0') then -- comp_eq is active high rx_eof is active-low
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_length_match_cycle;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='1';
+
+ next_st<=idle_state;
+
+ else
+ sel_comp_Bval<='1';
+ comp_Bval<=gnd_vec;
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='1';
+
+ next_st<=receive_usr_data_state;
+ end if;
+
+
+end case;
+end process;
+
+
+
+
+process(clk)
+begin
+if (rst='1') then
+ current_st<= rst_state;
+elsif (clk'event and clk='1') then
+ current_st <= next_st;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/PACKET_RECEIVER_FSM.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_8b_wren.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_8b_wren.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_8b_wren.vhd (revision 2)
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:40:03 02/07/2010
+-- Design Name:
+-- Module Name: REG_8b_wren - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity REG_8b_wren is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input_val : in STD_LOGIC_VECTOR (7 downto 0);
+ output_val : inout STD_LOGIC_VECTOR(7 downto 0));
+end REG_8b_wren;
+
+architecture Behavioral of REG_8b_wren is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ output_val<="00000000";
+else
+ if clk'event and clk='1' then
+ if wren='1' then
+ output_val<=input_val;
+ end if;
+ end if;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_8b_wren.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_RECEIV.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_RECEIV.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_RECEIV.vhd (revision 2)
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:16:57 11/30/2009
+-- Design Name:
+-- Module Name: COUNTER_11B_EN_RECEIV - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity COUNTER_11B_EN_RECEIV is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end COUNTER_11B_EN_RECEIV;
+
+architecture Behavioral of COUNTER_11B_EN_RECEIV is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ value_O<="00000000000";
+else
+ if clk'event and clk='1' then
+ if count_en='1' then
+ value_O<=value_O+"00000000001";
+ else
+ value_O<=value_O;
+ end if;
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_RECEIV.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd (revision 2)
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02:30:12 11/30/2009
+-- Design Name:
+-- Module Name: COUNTER_6B_LUT_FIFO_MODE - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity COUNTER_6B_LUT_FIFO_MODE is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (5 downto 0));
+end COUNTER_6B_LUT_FIFO_MODE;
+
+architecture Behavioral of COUNTER_6B_LUT_FIFO_MODE is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ if funct_sel='0' then
+ value_O<=(others=>'0');
+ else
+ value_O<="100111";
+ end if;
+else
+ if clk'event and clk='1' then
+ if count_en='1' then
+ value_O<=value_O+"000001";
+ else
+ value_O<=value_O;
+ end if;
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_6B_LUT_FIFO_MODE.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.ngc
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.ngc (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.ngc (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.ngc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.xco
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.xco (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.xco (revision 2)
@@ -0,0 +1,63 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Feb 04 10:02:06 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s200
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ft256
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4
+# END Select
+# BEGIN Parameters
+CSET ce_overrides=ce_overrides_sync_controls
+CSET coefficient_file="C:/PHd_Projects/The_Felsenstein_CoProcessor/ISE_Design/THE_FELSENSTEIN_COPROCESSOR/Copy of definition1_l1_cache.coe"
+CSET common_output_ce=false
+CSET common_output_clk=false
+CSET component_name=dist_mem_64x8
+CSET data_width=8
+CSET default_data=0
+CSET default_data_radix=16
+CSET depth=64
+CSET dual_port_address=non_registered
+CSET dual_port_output_clock_enable=false
+CSET input_clock_enable=false
+CSET input_options=non_registered
+CSET memory_type=rom
+CSET output_options=registered
+CSET pipeline_stages=0
+CSET qualify_we_with_i_ce=false
+CSET reset_qdpo=false
+CSET reset_qspo=false
+CSET single_port_output_clock_enable=false
+CSET sync_reset_qdpo=false
+CSET sync_reset_qspo=false
+# END Parameters
+GENERATE
+# CRC: 86e0277a
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.xco
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/OVERRIDE_LUT_CONTROL.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/OVERRIDE_LUT_CONTROL.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/OVERRIDE_LUT_CONTROL.vhd (revision 2)
@@ -0,0 +1,108 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:09:25 11/30/2009
+-- Design Name:
+-- Module Name: OVERRIDE_LUT_CONTROL - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity OVERRIDE_LUT_CONTROL is
+ Port ( clk : in STD_LOGIC;
+ input_addr : in STD_LOGIC_VECTOR (5 downto 0);
+ sel_total_length_MSBs : out STD_LOGIC;
+ sel_total_length_LSBs : out STD_LOGIC;
+ sel_header_checksum_MSBs : out STD_LOGIC;
+ sel_header_checksum_LSBs : out STD_LOGIC;
+ sel_length_MSBs : out STD_LOGIC;
+ sel_length_LSBs : out STD_LOGIC
+ );
+end OVERRIDE_LUT_CONTROL;
+
+architecture Behavioral of OVERRIDE_LUT_CONTROL is
+
+component comp_6b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+end component;
+
+constant total_length_addr1 : std_logic_vector(5 downto 0):="010000";
+constant total_length_addr2 : std_logic_vector(5 downto 0):="010001";
+
+constant header_checksum_addr1 : std_logic_vector(5 downto 0):="011000";
+constant header_checksum_addr2 : std_logic_vector(5 downto 0):="011001";
+
+constant length_addr1 : std_logic_vector(5 downto 0):="100110";
+constant length_addr2 : std_logic_vector(5 downto 0):="100111";
+
+
+signal sel_header_checksum_MSBs_tmp : std_logic;
+signal sel_total_length_MSBs_tmp : std_logic;
+signal sel_length_MSBs_tmp : std_logic;
+
+begin
+
+TARGET_TOTAL_LENGTH_1 : comp_6b_equal port map (sel_total_length_MSBs_tmp,clk,input_addr,total_length_addr1);
+
+process(clk)
+begin
+if clk'event and clk='1' then
+ sel_total_length_LSBs<=sel_total_length_MSBs_tmp;
+end if;
+end process;
+sel_total_length_MSBs<=sel_total_length_MSBs_tmp;
+
+--TARGET_TOTAL_LENGTH_2 : comp_6b_equal port map (sel_total_length_LSBs,clk,input_addr,total_length_addr2);
+
+TARGET_HEADER_CHECKSUM_1 : comp_6b_equal port map (sel_header_checksum_MSBs_tmp,clk,input_addr,header_checksum_addr1);
+process(clk)
+begin
+if clk'event and clk='1' then
+ sel_header_checksum_LSBs<=sel_header_checksum_MSBs_tmp;
+end if;
+end process;
+
+sel_header_checksum_MSBs<=sel_header_checksum_MSBs_tmp;
+
+
+
+--TARGET_HEADER_CHECKSUM_2 : comp_6b_equal port map (sel_header_checksum_LSBs,clk,input_addr,header_checksum_addr2);
+
+TARGET_LENGTH_1 : comp_6b_equal port map (sel_length_MSBs_tmp,clk,input_addr,length_addr1);
+
+process(clk)
+begin
+if clk'event and clk='1' then
+ sel_length_LSBs<=sel_length_MSBs_tmp;
+end if;
+end process;
+
+sel_length_MSBs<=sel_length_MSBs_tmp;
+--TARGET_LENGTH_2 : comp_6b_equal port map (sel_length_LSBs,clk,input_addr,length_addr2);
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/OVERRIDE_LUT_CONTROL.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_PACKET_TRANSMITTER.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_PACKET_TRANSMITTER.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_PACKET_TRANSMITTER.vhd (revision 2)
@@ -0,0 +1,437 @@
+-----------------------------------------------------------------------------------------
+-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
+-- --
+-- Engineer: Nikolaos Ch. Alachiotis --
+-- --
+-- Contact: alachiot@cs.tum.edu --
+-- n.alachiotis@gmail.com --
+-- --
+-- Create Date: 14:45:39 11/27/2009 --
+-- Module Name: IPV4_PACKET_TRANSMITTER --
+-- Target Devices: Virtex 5 FPGAs --
+-- Tool versions: ISE 10.1 --
+-- Description: This component can be used to send IPv4 Ethernet Packets. --
+-- Additional Comments: The look-up table contains the header fields of the IP packet, --
+-- so please keep in mind that you have to reinitialize this LUT. --
+-- --
+-----------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity IPV4_PACKET_TRANSMITTER is
+ Port ( rst : in STD_LOGIC;
+ clk_125MHz : in STD_LOGIC;
+ transmit_start_enable : in STD_LOGIC;
+ transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
+ usr_data_trans_phase_on : out STD_LOGIC;
+ transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
+ start_of_frame_O : out STD_LOGIC;
+ end_of_frame_O : out STD_LOGIC;
+ source_ready : out STD_LOGIC;
+ transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+end IPV4_PACKET_TRANSMITTER;
+
+architecture Behavioral of IPV4_PACKET_TRANSMITTER is
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------
+-- IPv4 PACKET STRUCTURE : --
+-- Size | Description | Transmission Order | Position --
+-- -----------------------------------------------------------------------------------------------------------
+-- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT --
+-- | X-X-X-X-X-X | | --
+-- | | | --
+-- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT --
+-- | 11111111-11111111-11111111-11111111-... | | --
+-- 2 bytes | Ethernet Type * | 12 13 | LUT --
+-- | (fixed to 00001000-00000000 :=> | | --
+-- | Internet Protocol, Version 4 (IPv4)) | | --
+-- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
+-- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length | 14 | LUT --
+-- | 0100 0101 | | --
+-- 1 byte | Differentiated Services | 15 | LUT --
+-- | 00000000 | | --
+-- 2 bytes | Total Length | 16 17 | REG --
+-- | 00000000-00100100 (base: 20 + 8 + datalength)| | --
+-- 2 bytes | Identification | 18 19 | LUT --
+-- | 00000000-00000000 | | --
+-- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset | 20 21 | LUT --
+-- | 010 - 0000000000000 | | --
+-- 1 byte | Time to Live | 22 | LUT --
+-- | 01000000 | | --
+-- 1 byte | Protocol | 23 | LUT --
+-- | 00010001 | | --
+-- 2 bytes | Header Checksum | 24 25 | REG --
+-- | 10110111 01111101 (base value) | | --
+-- 4 bytes | Source IP Address | 26 27 28 29 | LUT --
+-- | X-X-X-X - FPGA | | --
+-- 4 bytes | Destin IP Address | 30 31 32 33 | LUT --
+-- | X-X-X-X - PC | | --
+-- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
+-- 2 bytes | Source Port | 34 35 | LUT --
+-- | X-X | | --
+-- 2 bytes | Destination Port | 36 37 | LUT --
+-- | X-X | | --
+-- 2 bytes | Length | 38 39 | REG --
+-- | 00000000 - 00010000 (8 + # data bytes) | | --
+-- 2 bytes | Checksum | 40 41 | LUT --
+-- | 00000000 - 00000000 | | --
+-- X bytes | Data | 42 .. X | from input --
+-- | | | --
+-----------------------------------------------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------
+
+-- * More details about the Ethernet Type value you can find here:
+-- http://en.wikipedia.org/wiki/Ethertype
+
+-- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
+-- http://en.wikipedia.org/wiki/IPv4
+
+-- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
+-- http://en.wikipedia.org/wiki/User_Datagram_Protocol
+
+-----------------------------------------------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------
+
+
+
+--------------------------------------------------------------------------------------
+-- COMPONENT DECLARATION
+--------------------------------------------------------------------------------------
+
+component REG_16B_WREN is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input : in STD_LOGIC_VECTOR (15 downto 0);
+ output : out STD_LOGIC_VECTOR (15 downto 0));
+end component;
+
+component IPV4_LUT_INDEXER is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ transmit_enable : in STD_LOGIC;
+ LUT_index : out STD_LOGIC_VECTOR (5 downto 0));
+end component;
+
+component dist_mem_64x8 is
+ port (
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+end component;
+
+component OVERRIDE_LUT_CONTROL is
+ Port ( clk : in STD_LOGIC;
+ input_addr : in STD_LOGIC_VECTOR (5 downto 0);
+ sel_total_length_MSBs : out STD_LOGIC;
+ sel_total_length_LSBs : out STD_LOGIC;
+ sel_header_checksum_MSBs : out STD_LOGIC;
+ sel_header_checksum_LSBs : out STD_LOGIC;
+ sel_length_MSBs : out STD_LOGIC;
+ sel_length_LSBs : out STD_LOGIC
+ );
+end component;
+
+component TARGET_EOF is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start : in STD_LOGIC;
+ total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
+ eof_O : out STD_LOGIC);
+end component;
+
+component ENABLE_USER_DATA_TRANSMISSION is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start_usr_data_trans : in STD_LOGIC;
+ stop_usr_data_trans : in STD_LOGIC;
+ usr_data_sel : out STD_LOGIC);
+end component;
+
+component ALLOW_ZERO_UDP_CHECKSUM is
+ Port ( clk : in STD_LOGIC;
+ input : in STD_LOGIC;
+ output_to_readen : out STD_LOGIC;
+ output_to_datasel : out STD_LOGIC);
+end component;
+
+
+--------------------------------------------------------------------------------------
+-- SIGNAL DECLARATION
+--------------------------------------------------------------------------------------
+
+signal transmit_start_enable_tmp,
+ sel_total_length_MSBs,
+ sel_total_length_LSBs,
+ sel_header_checksum_MSBs,
+ sel_header_checksum_LSBs,
+ sel_length_MSBs,
+ sel_length_LSBs,
+ lut_out_sel,
+ source_ready_previous_value,
+ end_of_frame_O_tmp,
+ transmit_start_enable_reg,
+ usr_data_sel_sig,
+ start_usr_data_read,
+ start_usr_data_trans : STD_LOGIC;
+
+signal LUT_addr : STD_LOGIC_VECTOR(5 downto 0);
+
+signal transmit_data_input_bus_tmp,
+ transmit_data_output_bus_tmp,
+ sel_total_length_MSBs_vec,
+ sel_total_length_LSBs_vec,
+ sel_header_checksum_MSBs_vec,
+ sel_header_checksum_LSBs_vec,
+ sel_length_MSBs_vec,
+ sel_length_LSBs_vec,
+ lut_out_sel_vec,
+ transmit_data_output_bus_no_usr_data,
+ usr_data_not_sel_vec,
+ usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0);
+
+signal transmit_data_length_tmp,
+ data_length_regout,
+ tmp_total_length,
+ tmp_header_checksum,
+ tmp_header_checksum_baseval,
+ tmp_length : STD_LOGIC_VECTOR(15 downto 0);
+
+
+begin
+
+transmit_start_enable_tmp<=transmit_start_enable;
+
+transmit_data_length_tmp<=transmit_data_length;
+
+transmit_data_input_bus_tmp<=transmit_data_input_bus;
+
+----------------------------------------------------------------------------------------------------
+-- start_of_frame_O signal
+----------------------------------------------------------------------------------------------------
+-- Description: start_of_frame_O is active low
+-- We connect it to the delayed for one clock cycle transmit_start_enable input signal
+-- through a NOT gate since transmit_start_enable is active high.
+
+process(clk_125MHz)
+begin
+if clk_125MHz'event and clk_125MHz='1' then
+ transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle.
+end if;
+end process;
+
+start_of_frame_O<=not transmit_start_enable_reg;
+
+----------------------------------------------------------------------------------------------------
+-- end_of_frame_O signal
+----------------------------------------------------------------------------------------------------
+-- Description: end_of_frame_O is active low
+-- The TARGET_EOF module targets the last byte of the packet that is being transmitted
+-- based on a counter that counts the number of transmitted bytes and a comparator that
+-- detects the last byte which is the th byte.
+
+TARGET_EOF_port_map: TARGET_EOF port map
+(
+ rst =>rst,
+ clk =>clk_125MHz,
+ start =>transmit_start_enable_reg,
+ total_length_from_reg =>tmp_total_length,
+ eof_O =>end_of_frame_O_tmp
+);
+
+--* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the
+-- IPv4 packet. (MAC addresses + Ethernet Type)
+
+end_of_frame_O<=end_of_frame_O_tmp;
+
+----------------------------------------------------------------------------------------------------
+-- source_ready signal
+----------------------------------------------------------------------------------------------------
+-- Description: source_ready is active low
+-- This signal is idle(high). (based on rst and end_of_frame_O_tmp).
+-- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp).
+
+process(clk_125MHz)
+begin
+if rst='1' then
+ source_ready<='1';
+ source_ready_previous_value<='1';
+else
+ if clk_125MHz'event and clk_125MHz='1' then
+ if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then
+ source_ready<='0';
+ source_ready_previous_value<='0';
+ else
+ if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then
+ source_ready<='1';
+ source_ready_previous_value<='1';
+ end if;
+ end if;
+ end if;
+end if;
+end process;
+
+----------------------------------------------------------------------------------------------------
+-- transmit_data_output_bus
+----------------------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------
+-- Component Name: REG_16B_WREN
+-- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER
+-- Description: Register that holds the number of bytes of input data
+-- that will be transmitted in the packet.
+----------------------------------------------------------------------------------------------------
+NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map
+(
+ rst =>rst,
+ clk =>clk_125MHz,
+ wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren.
+ input =>transmit_data_length_tmp,
+ output =>data_length_regout
+);
+----------------------------------------------------------------------------------------------------
+
+tmp_total_length<="0000000000011100" + data_length_regout;
+
+tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value!
+tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout;
+
+tmp_length<="0000000000001000" + data_length_regout;
+
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: IPV4_LUT_INDEXER
+-- Instance Name: IPV4_LUT_INDEXER_port_map
+-- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the
+-- addresses to the LUT that contains the header section of the IP packet.
+----------------------------------------------------------------------------------------------------
+IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map
+(
+ rst =>rst,
+ clk =>clk_125MHz,
+ transmit_enable =>transmit_start_enable_tmp,
+ LUT_index =>LUT_addr
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: dist_mem_64x8
+-- Instance Name: LUT_MEM
+-- Description: LUT that contains the header section.
+----------------------------------------------------------------------------------------------------
+LUT_MEM : dist_mem_64x8 port map
+(
+ clk =>clk_125MHz,
+ a =>LUT_addr,
+ qspo =>transmit_data_output_bus_tmp
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: OVERRIDE_LUT_CONTROL
+-- Instance Name: OVERRIDE_LUT_CONTROL_port_map
+-- Description: Decides whether the output byte will come from the LUT or not.
+----------------------------------------------------------------------------------------------------
+OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map
+(
+ clk =>clk_125MHz,
+ input_addr =>LUT_addr,
+ sel_total_length_MSBs =>sel_total_length_MSBs,
+ sel_total_length_LSBs =>sel_total_length_LSBs,
+ sel_header_checksum_MSBs =>sel_header_checksum_MSBs,
+ sel_header_checksum_LSBs =>sel_header_checksum_LSBs,
+ sel_length_MSBs =>sel_length_MSBs,
+ sel_length_LSBs =>sel_length_LSBs
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- MUX 7 to 1
+sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs);
+sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs);
+sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs);
+sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs);
+sel_length_MSBs_vec<=(others=>sel_length_MSBs);
+sel_length_LSBs_vec<=(others=>sel_length_LSBs);
+lut_out_sel_vec <= (others=>lut_out_sel);
+
+lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and
+ (not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and
+ (not sel_length_MSBs) and (not sel_length_LSBs);
+
+-- MUX output
+transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or
+ (tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or
+ (tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or
+ (tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or
+ (tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or
+ (tmp_length(15 downto 8) and sel_length_MSBs_vec) or
+ (tmp_length(7 downto 0) and sel_length_LSBs_vec);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: ALLOW_ZERO_UDP_CHECKSUM
+-- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map
+-- Description: Delays the user data transmition phase in order to transmit two bytes with zero
+-- first.
+----------------------------------------------------------------------------------------------------
+ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map
+(
+ clk =>clk_125MHz,
+ input =>sel_length_LSBs,
+ output_to_readen =>start_usr_data_read,
+ output_to_datasel =>start_usr_data_trans
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: ENABLE_USER_DATA_TRANSMISSION
+-- Instance Name: ENABLE_USER_DATA_READ_port_map
+-- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the
+-- first user byte.
+----------------------------------------------------------------------------------------------------
+ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map
+( rst =>rst,
+ clk =>clk_125MHz,
+ start_usr_data_trans =>start_usr_data_read,
+ stop_usr_data_trans =>end_of_frame_O_tmp,
+ usr_data_sel =>usr_data_trans_phase_on
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: ENABLE_USER_DATA_TRANSMISSION
+-- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map
+-- Description: Sets usr_data_sel_sig signal to select user data for transmittion.
+----------------------------------------------------------------------------------------------------
+ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map
+( rst =>rst,
+ clk =>clk_125MHz,
+ start_usr_data_trans =>start_usr_data_trans,
+ stop_usr_data_trans =>end_of_frame_O_tmp,
+ usr_data_sel =>usr_data_sel_sig
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- MUX 2 to 1
+usr_data_not_sel_vec<=(others=>not usr_data_sel_sig);
+usr_data_sel_vec<=(others=>usr_data_sel_sig);
+
+-- MUX output
+transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or
+ (transmit_data_input_bus and usr_data_sel_vec);
+----------------------------------------------------------------------------------------------------
+
+end Behavioral;
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_PACKET_TRANSMITTER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd (revision 2)
@@ -0,0 +1,60 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:46:33 12/04/2009
+-- Design Name:
+-- Module Name: ALLOW_ZERO_UDP_CHECKSUM - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ALLOW_ZERO_UDP_CHECKSUM is
+ Port ( clk : in STD_LOGIC;
+ input : in STD_LOGIC;
+ output_to_readen : out STD_LOGIC;
+ output_to_datasel : out STD_LOGIC);
+end ALLOW_ZERO_UDP_CHECKSUM;
+
+architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is
+
+signal input_reg : std_logic;
+
+begin
+
+process(clk)
+begin
+ if clk'event and clk='1' then
+ input_reg<=input;
+ end if;
+end process;
+
+output_to_readen<=input_reg;
+
+process(clk)
+begin
+ if clk'event and clk='1' then
+ output_to_datasel<=input_reg;
+ end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ALLOW_ZERO_UDP_CHECKSUM.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_TRANS.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_TRANS.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_TRANS.vhd (revision 2)
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:16:57 11/30/2009
+-- Design Name:
+-- Module Name: COUNTER_11B_EN_TRANS - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity COUNTER_11B_EN_TRANS is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end COUNTER_11B_EN_TRANS;
+
+architecture Behavioral of COUNTER_11B_EN_TRANS is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ value_O<="11111110110";
+else
+ if clk'event and clk='1' then
+ if count_en='1' then
+ value_O<=value_O+"00000000001";
+ else
+ value_O<=value_O;
+ end if;
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/COUNTER_11B_EN_TRANS.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.vhd (revision 2)
@@ -0,0 +1,161 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: K.39
+-- \ \ Application: netgen
+-- / / Filename: comp_6b_equal.vhd
+-- /___/ /\ Timestamp: Thu Feb 04 11:02:26 2010
+-- \ \ / \
+-- \___\/\___\
+--
+-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.vhd
+-- Device : 3s200ft256-4
+-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.ngc
+-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.vhd
+-- # of Entities : 1
+-- Design Name : comp_6b_equal
+-- Xilinx : C:\Xilinx\10.1\ISE
+--
+-- Purpose:
+-- This VHDL netlist is a verification model and uses simulation
+-- primitives which may not represent the true implementation of the
+-- device, however the netlist is functionally correct and should not
+-- be modified. This file cannot be synthesized and should only be used
+-- with supported simulation tools.
+--
+-- Reference:
+-- Development System Reference Guide, Chapter 23
+-- Synthesis and Simulation Design Guide, Chapter 6
+--
+--------------------------------------------------------------------------------
+
+
+-- synthesis translate_off
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+use UNISIM.VPKG.ALL;
+
+entity comp_6b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+end comp_6b_equal;
+
+architecture STRUCTURE of comp_6b_equal is
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;
+ signal BU2_a_ge_b : STD_LOGIC;
+ signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
+ signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
+ signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal b_3 : STD_LOGIC_VECTOR ( 5 downto 0 );
+begin
+ a_2(5) <= a(5);
+ a_2(4) <= a(4);
+ a_2(3) <= a(3);
+ a_2(2) <= a(2);
+ a_2(1) <= a(1);
+ a_2(0) <= a(0);
+ b_3(5) <= b(5);
+ b_3(4) <= b(4);
+ b_3(3) <= b(3);
+ b_3(2) <= b(2);
+ b_3(1) <= b(1);
+ b_3(0) <= b(0);
+ VCC_0 : VCC
+ port map (
+ P => NLW_VCC_P_UNCONNECTED
+ );
+ GND_1 : GND
+ port map (
+ G => NLW_GND_G_UNCONNECTED
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o95 :
+LUT3
+ generic map(
+ INIT => X"80"
+ )
+ port map (
+ I0 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16
+,
+ I1 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17
+,
+ I2 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18
+,
+ O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(1),
+ I1 => b_3(1),
+ I2 => a_2(0),
+ I3 => b_3(0),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o80_18
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(3),
+ I1 => b_3(3),
+ I2 => a_2(2),
+ I3 => b_3(2),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o53_17
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(5),
+ I1 => b_3(5),
+ I2 => a_2(4),
+ I3 => b_3(4),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_16
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,
+ Q => qa_eq_b
+ );
+ BU2_XST_GND : GND
+ port map (
+ G => BU2_a_ge_b
+ );
+
+end STRUCTURE;
+
+-- synthesis translate_on
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.ngc
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.ngc (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.ngc (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
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trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.ngc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/TARGET_EOF.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/TARGET_EOF.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/TARGET_EOF.vhd (revision 2)
@@ -0,0 +1,106 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:22:56 11/30/2009
+-- Design Name:
+-- Module Name: TARGET_EOF - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity TARGET_EOF is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start : in STD_LOGIC;
+ total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
+ eof_O : out STD_LOGIC);
+end TARGET_EOF;
+
+architecture Behavioral of TARGET_EOF is
+
+signal count_end : std_logic:='0';
+signal count_en_sig : std_logic:='0';
+signal rst_counter : std_logic:='0';
+
+component COUNTER_11B_EN_TRANS is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end component;
+
+signal value_O_tmp : std_logic_vector(10 downto 0);
+
+component comp_11b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 10 downto 0 )
+ );
+end component;
+
+signal last_byte,last_byte_reg_in,last_byte_reg_out : std_logic;
+
+begin
+
+process(clk)
+begin
+if (rst='1' or count_end='1') then
+ count_en_sig<='0';
+ rst_counter<='1';
+else
+ rst_counter<='0';
+ if clk'event and clk='1' then
+ if (start='1' and count_en_sig='0') then
+ count_en_sig<='1';
+ end if;
+ end if;
+end if;
+end process;
+
+
+COUNT_TRANFERED_BYTES : COUNTER_11B_EN_TRANS port map
+( rst =>rst_counter,
+ clk =>clk,
+ count_en => count_en_sig,
+ value_O =>value_O_tmp
+);
+
+COMP_TO_TARGET_LAST_BYTE : comp_11b_equal port map
+(
+ qa_eq_b =>last_byte_reg_in,
+ clk =>clk,
+ a =>value_O_tmp,
+ b =>total_length_from_reg(10 downto 0)
+);
+
+process(clk)
+begin
+if clk'event and clk='1' then
+ last_byte_reg_out<=last_byte_reg_in;
+end if;
+end process;
+eof_O<=not last_byte_reg_out;
+count_end<=last_byte_reg_out;
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/TARGET_EOF.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.ngc
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.ngc (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.ngc (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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\ No newline at end of file
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.ngc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_16B_WREN.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_16B_WREN.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_16B_WREN.vhd (revision 2)
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:15:16 11/27/2009
+-- Design Name:
+-- Module Name: REG_16B_WREN - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description: 16bit wide Register with write enable option.
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity REG_16B_WREN is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input : in STD_LOGIC_VECTOR (15 downto 0);
+ output : out STD_LOGIC_VECTOR (15 downto 0));
+end REG_16B_WREN;
+
+architecture Behavioral of REG_16B_WREN is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ output<="0000000000000000";
+else
+if clk'event and clk='1' then
+ if wren='1' then
+ output<=input;
+ end if;
+end if;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/REG_16B_WREN.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.xco
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.xco (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.xco (revision 2)
@@ -0,0 +1,59 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Feb 04 10:02:26 2010
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s200
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ft256
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -4
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Comparator family Xilinx,_Inc. 9.0
+# END Select
+# BEGIN Parameters
+CSET aclr=false
+CSET ainitval=0
+CSET aset=false
+CSET ce=false
+CSET cepriority=Sync_Overrides_CE
+CSET component_name=comp_6b_equal
+CSET constantbport=false
+CSET constantbportvalue=0000000000000000
+CSET datatype=Unsigned
+CSET nonregisteredoutput=false
+CSET operation=eq
+CSET pipelinestages=0
+CSET radix=2
+CSET registeredoutput=true
+CSET sclr=false
+CSET sset=false
+CSET syncctrlpriority=Reset_Overrides_Set
+CSET width=6
+# END Parameters
+GENERATE
+# CRC: dc354663
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_6b_equal.xco
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_LUT_INDEXER.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_LUT_INDEXER.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_LUT_INDEXER.vhd (revision 2)
@@ -0,0 +1,110 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:11:55 11/27/2009
+-- Design Name:
+-- Module Name: IPV4_LUT_INDEXER - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity IPV4_LUT_INDEXER is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ transmit_enable : in STD_LOGIC;
+ LUT_index : out STD_LOGIC_VECTOR (5 downto 0));
+end IPV4_LUT_INDEXER;
+
+architecture Behavioral of IPV4_LUT_INDEXER is
+
+component dist_mem_64x8 is
+ port (
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+end component;
+
+component COUNTER_6B_LUT_FIFO_MODE is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing -- only LUT support is used
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (5 downto 0));
+end component;
+
+component comp_6b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+end component;
+
+signal count_en_sig , count_end , rst_counter: std_logic :='0';
+signal count_val: std_logic_Vector(5 downto 0):=(others=>'0');
+signal count_en_sig_comb : std_logic;
+constant lut_upper_address :std_logic_vector(5 downto 0):="100110"; -- position 38
+
+begin
+
+process(clk)
+begin
+if (rst='1' or count_end='1') then
+ count_en_sig<='0';
+ rst_counter<='1';
+else
+ rst_counter<='0';
+ if clk'event and clk='1' then
+ if (transmit_enable='1' and count_en_sig='0') then
+ count_en_sig<='1';
+ end if;
+ end if;
+end if;
+end process;
+
+LUT_END_CHECK : comp_6b_equal port map (
+qa_eq_b =>count_end,
+ clk =>clk,
+ a =>count_val,
+ b =>lut_upper_address
+
+);
+
+count_en_sig_comb <=count_en_sig or transmit_enable;
+
+
+
+LUT_INDEXER_MODULE : COUNTER_6B_LUT_FIFO_MODE port map (
+ rst => rst_counter,
+ clk => clk,
+ funct_sel =>'0', -- for now only one function is supported
+ count_en =>count_en_sig_comb,
+ value_O =>count_val
+);
+
+LUT_index<=count_val;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPV4_LUT_INDEXER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd (revision 2)
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:05:48 12/04/2009
+-- Design Name:
+-- Module Name: ENABLE_USER_DATA_TRANSMISSION - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ENABLE_USER_DATA_TRANSMISSION is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start_usr_data_trans : in STD_LOGIC;
+ stop_usr_data_trans : in STD_LOGIC;
+ usr_data_sel : out STD_LOGIC);
+end ENABLE_USER_DATA_TRANSMISSION;
+
+architecture Behavioral of ENABLE_USER_DATA_TRANSMISSION is
+
+signal usr_data_sel_prev : std_logic :='0';
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ usr_data_sel<='0';
+ usr_data_sel_prev<='0';
+else
+ if clk'event and clk='1' then
+ if (start_usr_data_trans='1' and usr_data_sel_prev='0') then
+ usr_data_sel<='1';
+ usr_data_sel_prev<='1';
+ end if;
+ if (stop_usr_data_trans='0' and usr_data_sel_prev='1') then -- stop_usr_data_trans is active low
+ usr_data_sel<='0';
+ usr_data_sel_prev<='0';
+ end if;
+ end if;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/ENABLE_USER_DATA_TRANSMISSION.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/UDP_IP_Core.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/UDP_IP_Core.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/UDP_IP_Core.vhd (revision 2)
@@ -0,0 +1,109 @@
+-----------------------------------------------------------------------------------------
+-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
+-- --
+-- Engineer: Nikolaos Ch. Alachiotis --
+-- --
+-- Contact: alachiot@cs.tum.edu --
+-- n.alachiotis@gmail.com --
+-- --
+-- Create Date: 15:29:59 02/07/2010 --
+-- Module Name: UDP_IP_Core --
+-- Target Devices: Virtex 5 FPGAs --
+-- Tool versions: ISE 10.1 --
+-- Description: This component can be used to transmit and receive UDP/IP --
+-- Ethernet Packets (IPv4). --
+-- Additional Comments: The core has been area-optimized and is suitable for direct --
+-- PC-FPGA communication at Gigabit speed. --
+-- --
+-----------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity UDP_IP_Core is
+ Port ( rst : in STD_LOGIC; -- active-high
+ clk_125MHz : in STD_LOGIC;
+
+ -- Transmit signals
+ transmit_start_enable : in STD_LOGIC;
+ transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
+ usr_data_trans_phase_on : out STD_LOGIC;
+ transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
+ start_of_frame_O : out STD_LOGIC;
+ end_of_frame_O : out STD_LOGIC;
+ source_ready : out STD_LOGIC;
+ transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
+
+ --Receive Signals
+ rx_sof : in STD_LOGIC;
+ rx_eof : in STD_LOGIC;
+ input_bus : in STD_LOGIC_VECTOR(7 downto 0);
+ valid_out_usr_data : out STD_LOGIC;
+ usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+end UDP_IP_Core;
+
+architecture Behavioral of UDP_IP_Core is
+
+component IPV4_PACKET_TRANSMITTER is
+ Port ( rst : in STD_LOGIC;
+ clk_125MHz : in STD_LOGIC;
+ transmit_start_enable : in STD_LOGIC;
+ transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
+ usr_data_trans_phase_on : out STD_LOGIC;
+ transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
+ start_of_frame_O : out STD_LOGIC;
+ end_of_frame_O : out STD_LOGIC;
+ source_ready : out STD_LOGIC;
+ transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+end component;
+
+component IPv4_PACKET_RECEIVER is
+ Port ( rst : in STD_LOGIC;
+ clk_125Mhz : in STD_LOGIC;
+ rx_sof : in STD_LOGIC;
+ rx_eof : in STD_LOGIC;
+ input_bus : in STD_LOGIC_VECTOR(7 downto 0);
+ valid_out_usr_data : out STD_LOGIC;
+ usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0));
+end component;
+
+begin
+
+IPV4_PACKET_TRANSMITTER_port_map: IPV4_PACKET_TRANSMITTER
+ Port Map
+ ( rst => rst,
+ clk_125MHz => clk_125MHz,
+ transmit_start_enable => transmit_start_enable,
+ transmit_data_length => transmit_data_length,
+ usr_data_trans_phase_on => usr_data_trans_phase_on,
+ transmit_data_input_bus => transmit_data_input_bus,
+ start_of_frame_O => start_of_frame_O,
+ end_of_frame_O => end_of_frame_O,
+ source_ready => source_ready,
+ transmit_data_output_bus => transmit_data_output_bus
+ );
+
+
+IPv4_PACKET_RECEIVER_port_map: IPv4_PACKET_RECEIVER
+ Port Map
+ ( rst => rst,
+ clk_125Mhz => clk_125Mhz,
+ rx_sof => rx_sof,
+ rx_eof => rx_eof,
+ input_bus => input_bus,
+ valid_out_usr_data => valid_out_usr_data,
+ usr_data_output_bus => usr_data_output_bus
+ );
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/UDP_IP_Core.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.vhd (revision 2)
@@ -0,0 +1,249 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: K.39
+-- \ \ Application: netgen
+-- / / Filename: comp_11b_equal.vhd
+-- /___/ /\ Timestamp: Thu Feb 04 11:01:48 2010
+-- \ \ / \
+-- \___\/\___\
+--
+-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.vhd
+-- Device : 3s200ft256-4
+-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.ngc
+-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.vhd
+-- # of Entities : 1
+-- Design Name : comp_11b_equal
+-- Xilinx : C:\Xilinx\10.1\ISE
+--
+-- Purpose:
+-- This VHDL netlist is a verification model and uses simulation
+-- primitives which may not represent the true implementation of the
+-- device, however the netlist is functionally correct and should not
+-- be modified. This file cannot be synthesized and should only be used
+-- with supported simulation tools.
+--
+-- Reference:
+-- Development System Reference Guide, Chapter 23
+-- Synthesis and Simulation Design Guide, Chapter 6
+--
+--------------------------------------------------------------------------------
+
+
+-- synthesis translate_off
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+use UNISIM.VPKG.ALL;
+
+entity comp_11b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 10 downto 0 )
+ );
+end comp_11b_equal;
+
+architecture STRUCTURE of comp_11b_equal is
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31 : STD_LOGIC;
+
+ signal BU2_N01 : STD_LOGIC;
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;
+ signal BU2_N1 : STD_LOGIC;
+ signal BU2_a_ge_b : STD_LOGIC;
+ signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
+ signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
+ signal a_2 : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal b_3 : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o : STD_LOGIC_VECTOR ( 1 downto 1 );
+begin
+ a_2(10) <= a(10);
+ a_2(9) <= a(9);
+ a_2(8) <= a(8);
+ a_2(7) <= a(7);
+ a_2(6) <= a(6);
+ a_2(5) <= a(5);
+ a_2(4) <= a(4);
+ a_2(3) <= a(3);
+ a_2(2) <= a(2);
+ a_2(1) <= a(1);
+ a_2(0) <= a(0);
+ b_3(10) <= b(10);
+ b_3(9) <= b(9);
+ b_3(8) <= b(8);
+ b_3(7) <= b(7);
+ b_3(6) <= b(6);
+ b_3(5) <= b(5);
+ b_3(4) <= b(4);
+ b_3(3) <= b(3);
+ b_3(2) <= b(2);
+ b_3(1) <= b(1);
+ b_3(0) <= b(0);
+ VCC_0 : VCC
+ port map (
+ P => NLW_VCC_P_UNCONNECTED
+ );
+ GND_1 : GND
+ port map (
+ G => NLW_GND_G_UNCONNECTED
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000136 :
+LUT4
+ generic map(
+ INIT => X"8000"
+ )
+ port map (
+ I0 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31
+,
+ I1 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32
+,
+ I2 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33
+,
+ I3 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34
+,
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0)
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(6),
+ I1 => b_3(6),
+ I2 => a_2(7),
+ I3 => b_3(7),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and0000120_34
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(4),
+ I1 => b_3(4),
+ I2 => a_2(5),
+ I3 => b_3(5),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000093_33
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(2),
+ I1 => b_3(2),
+ I2 => a_2(3),
+ I3 => b_3(3),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000053_32
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(0),
+ I1 => b_3(0),
+ I2 => a_2(1),
+ I3 => b_3(1),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_0_and000026_31
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and0000 :
+LUT3
+ generic map(
+ INIT => X"09"
+ )
+ port map (
+ I0 => b_3(9),
+ I1 => a_2(9),
+ I2 => BU2_N01,
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1)
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o_1_and0000_SW0 :
+LUT4
+ generic map(
+ INIT => X"6FF6"
+ )
+ port map (
+ I0 => a_2(10),
+ I1 => b_3(10),
+ I2 => a_2(8),
+ I3 => b_3(8),
+ O => BU2_N01
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_0_i_mux :
+MUXCY
+ port map (
+ CI =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1)
+,
+ DI => BU2_a_ge_b,
+ S =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(0)
+,
+ O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_opt_carry_tile_and_or_carry_muxs_1_i_mux :
+MUXCY
+ port map (
+ CI => BU2_N1,
+ DI => BU2_a_ge_b,
+ S =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_lut_o(1)
+,
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_async_o(1)
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,
+ Q => qa_eq_b
+ );
+ BU2_XST_VCC : VCC
+ port map (
+ P => BU2_N1
+ );
+ BU2_XST_GND : GND
+ port map (
+ G => BU2_a_ge_b
+ );
+
+end STRUCTURE;
+
+-- synthesis translate_on
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/comp_11b_equal.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.vhd (revision 2)
@@ -0,0 +1,86 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: K.39
+-- \ \ Application: netgen
+-- / / Filename: dist_mem_64x8.vhd
+-- /___/ /\ Timestamp: Thu Feb 04 11:02:06 2010
+-- \ \ / \
+-- \___\/\___\
+--
+-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.vhd
+-- Device : 3s200ft256-4
+-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.ngc
+-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.vhd
+-- # of Entities : 1
+-- Design Name : dist_mem_64x8
+-- Xilinx : C:\Xilinx\10.1\ISE
+--
+-- Purpose:
+-- This VHDL netlist is a verification model and uses simulation
+-- primitives which may not represent the true implementation of the
+-- device, however the netlist is functionally correct and should not
+-- be modified. This file cannot be synthesized and should only be used
+-- with supported simulation tools.
+--
+-- Reference:
+-- Development System Reference Guide, Chapter 23
+-- Synthesis and Simulation Design Guide, Chapter 6
+--
+--------------------------------------------------------------------------------
+
+
+-- synthesis translate_off
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+use UNISIM.VPKG.ALL;
+
+entity dist_mem_64x8 is
+ port (
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+end dist_mem_64x8;
+
+architecture STRUCTURE of dist_mem_64x8 is
+ signal N0 : STD_LOGIC;
+ signal N1 : STD_LOGIC;
+ signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal NlwRenamedSignal_qspo : STD_LOGIC_VECTOR ( 0 downto 0 );
+begin
+ a_2(5) <= a(5);
+ a_2(4) <= a(4);
+ a_2(3) <= a(3);
+ a_2(2) <= a(2);
+ a_2(1) <= a(1);
+ a_2(0) <= a(0);
+ qspo(7) <= NlwRenamedSignal_qspo(0);
+ qspo(6) <= NlwRenamedSignal_qspo(0);
+ qspo(5) <= NlwRenamedSignal_qspo(0);
+ qspo(4) <= NlwRenamedSignal_qspo(0);
+ qspo(3) <= NlwRenamedSignal_qspo(0);
+ qspo(2) <= NlwRenamedSignal_qspo(0);
+ qspo(1) <= NlwRenamedSignal_qspo(0);
+ qspo(0) <= NlwRenamedSignal_qspo(0);
+ VCC_0 : VCC
+ port map (
+ P => N1
+ );
+ GND_1 : GND
+ port map (
+ G => N0
+ );
+ BU2_XST_GND : GND
+ port map (
+ G => NlwRenamedSignal_qspo(0)
+ );
+
+end STRUCTURE;
+
+-- synthesis translate_on
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/dist_mem_64x8.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPv4_PACKET_RECEIVER.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPv4_PACKET_RECEIVER.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPv4_PACKET_RECEIVER.vhd (revision 2)
@@ -0,0 +1,182 @@
+-----------------------------------------------------------------------------------------
+-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
+-- --
+-- Engineer: Nikolaos Ch. Alachiotis --
+-- --
+-- Contact: alachiot@cs.tum.edu --
+-- n.alachiotis@gmail.com --
+-- --
+-- Create Date: 14:32:06 02/07/2010 --
+-- Module Name: IPv4_PACKET_RECEIVER --
+-- Target Devices: Virtex 5 FPGAs --
+-- Tool versions: ISE 10.1 --
+-- Description: This component can be used to receive IPv4 Ethernet Packets. --
+-- Additional Comments: --
+-- --
+-- The receiver does not operate properly for data section of 1 or 2 bytes only. --
+-- --
+-----------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity IPv4_PACKET_RECEIVER is
+ Port ( rst : in STD_LOGIC;
+ clk_125Mhz : in STD_LOGIC;
+ rx_sof : in STD_LOGIC;
+ rx_eof : in STD_LOGIC;
+ input_bus : in STD_LOGIC_VECTOR(7 downto 0);
+ valid_out_usr_data : out STD_LOGIC;
+ usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0));
+end IPv4_PACKET_RECEIVER;
+
+architecture Behavioral of IPv4_PACKET_RECEIVER is
+
+component PACKET_RECEIVER_FSM is
+ Port (
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+
+ -- Signals from EMAC
+ rx_sof: in STD_LOGIC; -- active low input
+ rx_eof: in STD_LOGIC; -- active low input
+
+ -- Signals to Counter and Comparator
+ sel_comp_Bval: out STD_LOGIC;
+ comp_Bval: out STD_LOGIC_VECTOR(10 downto 0);
+ rst_count : out STD_LOGIC;
+ en_count : out STD_LOGIC;
+
+ -- Signal from Comparator
+ comp_eq: in STD_LOGIC;
+
+ -- Signals to Length Register
+ wren_MSbyte: out STD_LOGIC;
+ wren_LSbyte: out STD_LOGIC;
+
+ -- Signal to user interface
+ valid_out_usr_data : out STD_LOGIC);
+end component;
+
+component REG_8b_wren is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input_val : in STD_LOGIC_VECTOR (7 downto 0);
+ output_val : inout STD_LOGIC_VECTOR(7 downto 0));
+end component;
+
+component COUNTER_11B_EN_RECEIV is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end component;
+
+component comp_11b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 10 downto 0 )
+ );
+end component;
+
+signal sel_comp_Bval,
+ rst_count,
+ en_count,
+ comp_eq,
+ wren_MSbyte,
+ wren_LSbyte: STD_LOGIC;
+
+signal MSbyte_reg_val_out,
+ LSbyte_reg_val_out : STD_LOGIC_VECTOR(7 downto 0);
+
+signal counter_val,
+ match_val,
+ comp_Bval,
+ comp_sel_val_vec,
+ comp_n_sel_val_vec,
+ length_val: STD_LOGIC_VECTOR(10 downto 0);
+
+constant length_offest : STD_LOGIC_VECTOR(7 downto 0):="00001010";
+-- This value is formed as 2 (1 clock the latency of comparator and 1 clock fro changing the FSM state) + 8 (number of bytes of UDP header section)
+
+begin
+
+usr_data_output_bus<=input_bus;
+
+PACKET_RECEIVER_FSM_port_map: PACKET_RECEIVER_FSM Port Map
+(
+ rst => rst,
+ clk => clk_125MHz,
+
+ rx_sof => rx_sof,
+ rx_eof => rx_eof,
+
+ sel_comp_Bval => sel_comp_Bval,
+ comp_Bval => comp_Bval,
+ rst_count => rst_count,
+ en_count => en_count,
+
+ comp_eq => comp_eq,
+
+ wren_MSbyte => wren_MSbyte,
+ wren_LSbyte => wren_LSbyte,
+
+ valid_out_usr_data => valid_out_usr_data
+);
+
+MSbyte_REG: REG_8b_wren Port Map
+(
+ rst => rst,
+ clk => clk_125MHz,
+ wren => wren_MSbyte,
+ input_val => input_bus,
+ output_val =>MSbyte_reg_val_out
+);
+
+LSbyte_REG: REG_8b_wren Port Map
+(
+ rst => rst,
+ clk => clk_125MHz,
+ wren => wren_LSbyte,
+ input_val => input_bus,
+ output_val =>LSbyte_reg_val_out
+);
+
+COUNTER_11B_EN_port_map: COUNTER_11B_EN_RECEIV Port Map
+(
+ rst => rst_count,
+ clk => clk_125MHz,
+ count_en => en_count,
+ value_O => counter_val
+);
+
+Comp_11b_equal_port_map: Comp_11b_equal Port Map
+(
+ qa_eq_b => comp_eq,
+ clk => clk_125MHz,
+ a => counter_val,
+ b => match_val
+ );
+
+length_val(7 downto 0)<= LSbyte_reg_val_out-length_offest;
+length_val(10 downto 8)<= MSbyte_reg_val_out (2 downto 0);
+
+comp_sel_val_vec<=(others=> sel_comp_Bval);
+comp_n_sel_val_vec<= (others=> not sel_comp_Bval);
+
+match_val<= (comp_sel_val_vec and length_val) or (comp_n_sel_val_vec and comp_Bval);
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Spartan3/IPv4_PACKET_RECEIVER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/PACKET_RECEIVER_FSM.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/PACKET_RECEIVER_FSM.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/PACKET_RECEIVER_FSM.vhd (revision 2)
@@ -0,0 +1,238 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 03:48:34 02/07/2010
+-- Design Name:
+-- Module Name: PACKET_RECEIVER_FSM - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity PACKET_RECEIVER_FSM is
+ Port (
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+
+ -- Signals from EMAC
+ rx_sof: in STD_LOGIC; -- active low input
+ rx_eof: in STD_LOGIC; -- active low input
+
+ -- Signals to Counter and Comparator
+ sel_comp_Bval: out STD_LOGIC;
+ comp_Bval: out STD_LOGIC_VECTOR(10 downto 0);
+ rst_count : out STD_LOGIC;
+ en_count : out STD_LOGIC;
+
+ -- Signal from Comparator
+ comp_eq: in STD_LOGIC;
+
+ -- Signals to Length Register
+ wren_MSbyte: out STD_LOGIC;
+ wren_LSbyte: out STD_LOGIC;
+
+ -- Signal to user interface
+ valid_out_usr_data: out STD_LOGIC);
+end PACKET_RECEIVER_FSM;
+
+architecture Behavioral of PACKET_RECEIVER_FSM is
+
+TYPE state is (rst_state,
+ idle_state,
+ detect_n_store_usr_length_MSbyte_state,
+ store_usr_length_LSbyte_state,
+ checksum_gap_state,
+ receive_usr_data_state);
+
+signal current_st,next_st: state;
+
+constant udp_length_match_cycle : std_logic_vector(10 downto 0):="00000100100"; -- UDP length MSbyte - 2
+constant udp_checksum_skip : std_logic_vector(10 downto 0):="00000000001";
+constant gnd_vec : std_logic_vector(10 downto 0):="00000000000";
+begin
+
+process(current_st,rx_sof,rx_eof,comp_eq)
+begin
+case current_st is
+
+
+when rst_state =>
+
+ sel_comp_Bval<='0';
+ comp_Bval<=gnd_vec;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=idle_state;
+
+when idle_state =>
+
+ if rx_sof='0' then -- rx_sof is active low
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_length_match_cycle;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=detect_n_store_usr_length_MSbyte_state;
+
+ else
+ sel_comp_Bval<='0';
+ comp_Bval<=gnd_vec;
+ rst_count<='0';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=idle_state;
+ end if;
+
+when detect_n_store_usr_length_MSbyte_state =>
+
+ if comp_eq='1' then -- comp_eq is active high
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='1';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=store_usr_length_LSbyte_state;
+
+ else
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_length_match_cycle;
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=detect_n_store_usr_length_MSbyte_state;
+ end if;
+
+when store_usr_length_LSbyte_state =>
+
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_checksum_skip; -- Just to skip the UDP checksum field
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='1';
+
+ valid_out_usr_data<='0';
+
+ next_st<=checksum_gap_state;
+
+when checksum_gap_state =>
+
+ if comp_eq='1' then -- comp_eq is active high
+ sel_comp_Bval<='1';
+ comp_Bval<=gnd_vec;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=receive_usr_data_state;
+
+ else
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_checksum_skip;
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='0';
+
+ next_st<=checksum_gap_state;
+ end if;
+
+when receive_usr_data_state =>
+
+ if (comp_eq='1' or rx_eof='0') then -- comp_eq is active high rx_eof is active-low
+ sel_comp_Bval<='0';
+ comp_Bval<=udp_length_match_cycle;
+ rst_count<='1';
+ en_count<='0';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='1';
+
+ next_st<=idle_state;
+
+ else
+ sel_comp_Bval<='1';
+ comp_Bval<=gnd_vec;
+ rst_count<='0';
+ en_count<='1';
+
+ wren_MSbyte<='0';
+ wren_LSbyte<='0';
+
+ valid_out_usr_data<='1';
+
+ next_st<=receive_usr_data_state;
+ end if;
+
+
+end case;
+end process;
+
+
+
+
+process(clk)
+begin
+if (rst='1') then
+ current_st<= rst_state;
+elsif (clk'event and clk='1') then
+ current_st <= next_st;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/PACKET_RECEIVER_FSM.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.xco
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.xco (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.xco (revision 2)
@@ -0,0 +1,59 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Mon Nov 30 15:37:25 2009
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc5vsx95t
+SET devicefamily = virtex5
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff1136
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -1
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Comparator family Xilinx,_Inc. 9.0
+# END Select
+# BEGIN Parameters
+CSET aclr=false
+CSET ainitval=0
+CSET aset=false
+CSET ce=false
+CSET cepriority=Sync_Overrides_CE
+CSET component_name=comp_11b_equal
+CSET constantbport=false
+CSET constantbportvalue=0000000000000000
+CSET datatype=Unsigned
+CSET nonregisteredoutput=false
+CSET operation=eq
+CSET pipelinestages=0
+CSET radix=2
+CSET registeredoutput=true
+CSET sclr=false
+CSET sset=false
+CSET syncctrlpriority=Reset_Overrides_Set
+CSET width=11
+# END Parameters
+GENERATE
+# CRC: 6f28c282
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.xco
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_RECEIV.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_RECEIV.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_RECEIV.vhd (revision 2)
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:16:57 11/30/2009
+-- Design Name:
+-- Module Name: COUNTER_11B_EN_RECEIV - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity COUNTER_11B_EN_RECEIV is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end COUNTER_11B_EN_RECEIV;
+
+architecture Behavioral of COUNTER_11B_EN_RECEIV is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ value_O<="00000000000";
+else
+ if clk'event and clk='1' then
+ if count_en='1' then
+ value_O<=value_O+"00000000001";
+ else
+ value_O<=value_O;
+ end if;
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_RECEIV.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd (revision 2)
@@ -0,0 +1,63 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02:30:12 11/30/2009
+-- Design Name:
+-- Module Name: COUNTER_6B_LUT_FIFO_MODE - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity COUNTER_6B_LUT_FIFO_MODE is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (5 downto 0));
+end COUNTER_6B_LUT_FIFO_MODE;
+
+architecture Behavioral of COUNTER_6B_LUT_FIFO_MODE is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ if funct_sel='0' then
+ value_O<=(others=>'0');
+ else
+ value_O<="100111";
+ end if;
+else
+ if clk'event and clk='1' then
+ if count_en='1' then
+ value_O<=value_O+"000001";
+ else
+ value_O<=value_O;
+ end if;
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_6B_LUT_FIFO_MODE.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_8b_wren.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_8b_wren.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_8b_wren.vhd (revision 2)
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:40:03 02/07/2010
+-- Design Name:
+-- Module Name: REG_8b_wren - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity REG_8b_wren is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input_val : in STD_LOGIC_VECTOR (7 downto 0);
+ output_val : inout STD_LOGIC_VECTOR(7 downto 0));
+end REG_8b_wren;
+
+architecture Behavioral of REG_8b_wren is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ output_val<="00000000";
+else
+ if clk'event and clk='1' then
+ if wren='1' then
+ output_val<=input_val;
+ end if;
+ end if;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_8b_wren.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.xco
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.xco (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.xco (revision 2)
@@ -0,0 +1,63 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Tue Dec 01 14:45:04 2009
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc5vsx95t
+SET devicefamily = virtex5
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff1136
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -1
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Distributed_Memory_Generator family Xilinx,_Inc. 3.4
+# END Select
+# BEGIN Parameters
+CSET ce_overrides=ce_overrides_sync_controls
+CSET coefficient_file=C:/PHd_Projects/The_Felsenstein_CoProcessor/definition2_ipv4_lut.coe
+CSET common_output_ce=false
+CSET common_output_clk=false
+CSET component_name=dist_mem_64x8
+CSET data_width=8
+CSET default_data=0
+CSET default_data_radix=16
+CSET depth=64
+CSET dual_port_address=non_registered
+CSET dual_port_output_clock_enable=false
+CSET input_clock_enable=false
+CSET input_options=non_registered
+CSET memory_type=rom
+CSET output_options=registered
+CSET pipeline_stages=0
+CSET qualify_we_with_i_ce=false
+CSET reset_qdpo=false
+CSET reset_qspo=false
+CSET single_port_output_clock_enable=false
+CSET sync_reset_qdpo=false
+CSET sync_reset_qspo=false
+# END Parameters
+GENERATE
+# CRC: 87a11b99
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.xco
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.ngc
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.ngc (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.ngc (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.ngc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/OVERRIDE_LUT_CONTROL.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/OVERRIDE_LUT_CONTROL.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/OVERRIDE_LUT_CONTROL.vhd (revision 2)
@@ -0,0 +1,108 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 15:09:25 11/30/2009
+-- Design Name:
+-- Module Name: OVERRIDE_LUT_CONTROL - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity OVERRIDE_LUT_CONTROL is
+ Port ( clk : in STD_LOGIC;
+ input_addr : in STD_LOGIC_VECTOR (5 downto 0);
+ sel_total_length_MSBs : out STD_LOGIC;
+ sel_total_length_LSBs : out STD_LOGIC;
+ sel_header_checksum_MSBs : out STD_LOGIC;
+ sel_header_checksum_LSBs : out STD_LOGIC;
+ sel_length_MSBs : out STD_LOGIC;
+ sel_length_LSBs : out STD_LOGIC
+ );
+end OVERRIDE_LUT_CONTROL;
+
+architecture Behavioral of OVERRIDE_LUT_CONTROL is
+
+component comp_6b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+end component;
+
+constant total_length_addr1 : std_logic_vector(5 downto 0):="010000";
+constant total_length_addr2 : std_logic_vector(5 downto 0):="010001";
+
+constant header_checksum_addr1 : std_logic_vector(5 downto 0):="011000";
+constant header_checksum_addr2 : std_logic_vector(5 downto 0):="011001";
+
+constant length_addr1 : std_logic_vector(5 downto 0):="100110";
+constant length_addr2 : std_logic_vector(5 downto 0):="100111";
+
+
+signal sel_header_checksum_MSBs_tmp : std_logic;
+signal sel_total_length_MSBs_tmp : std_logic;
+signal sel_length_MSBs_tmp : std_logic;
+
+begin
+
+TARGET_TOTAL_LENGTH_1 : comp_6b_equal port map (sel_total_length_MSBs_tmp,clk,input_addr,total_length_addr1);
+
+process(clk)
+begin
+if clk'event and clk='1' then
+ sel_total_length_LSBs<=sel_total_length_MSBs_tmp;
+end if;
+end process;
+sel_total_length_MSBs<=sel_total_length_MSBs_tmp;
+
+--TARGET_TOTAL_LENGTH_2 : comp_6b_equal port map (sel_total_length_LSBs,clk,input_addr,total_length_addr2);
+
+TARGET_HEADER_CHECKSUM_1 : comp_6b_equal port map (sel_header_checksum_MSBs_tmp,clk,input_addr,header_checksum_addr1);
+process(clk)
+begin
+if clk'event and clk='1' then
+ sel_header_checksum_LSBs<=sel_header_checksum_MSBs_tmp;
+end if;
+end process;
+
+sel_header_checksum_MSBs<=sel_header_checksum_MSBs_tmp;
+
+
+
+--TARGET_HEADER_CHECKSUM_2 : comp_6b_equal port map (sel_header_checksum_LSBs,clk,input_addr,header_checksum_addr2);
+
+TARGET_LENGTH_1 : comp_6b_equal port map (sel_length_MSBs_tmp,clk,input_addr,length_addr1);
+
+process(clk)
+begin
+if clk'event and clk='1' then
+ sel_length_LSBs<=sel_length_MSBs_tmp;
+end if;
+end process;
+
+sel_length_MSBs<=sel_length_MSBs_tmp;
+--TARGET_LENGTH_2 : comp_6b_equal port map (sel_length_LSBs,clk,input_addr,length_addr2);
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/OVERRIDE_LUT_CONTROL.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_PACKET_TRANSMITTER.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_PACKET_TRANSMITTER.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_PACKET_TRANSMITTER.vhd (revision 2)
@@ -0,0 +1,437 @@
+-----------------------------------------------------------------------------------------
+-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
+-- --
+-- Engineer: Nikolaos Ch. Alachiotis --
+-- --
+-- Contact: alachiot@cs.tum.edu --
+-- n.alachiotis@gmail.com --
+-- --
+-- Create Date: 14:45:39 11/27/2009 --
+-- Module Name: IPV4_PACKET_TRANSMITTER --
+-- Target Devices: Virtex 5 FPGAs --
+-- Tool versions: ISE 10.1 --
+-- Description: This component can be used to send IPv4 Ethernet Packets. --
+-- Additional Comments: The look-up table contains the header fields of the IP packet, --
+-- so please keep in mind that you have to reinitialize this LUT. --
+-- --
+-----------------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity IPV4_PACKET_TRANSMITTER is
+ Port ( rst : in STD_LOGIC;
+ clk_125MHz : in STD_LOGIC;
+ transmit_start_enable : in STD_LOGIC;
+ transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
+ usr_data_trans_phase_on : out STD_LOGIC;
+ transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
+ start_of_frame_O : out STD_LOGIC;
+ end_of_frame_O : out STD_LOGIC;
+ source_ready : out STD_LOGIC;
+ transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+end IPV4_PACKET_TRANSMITTER;
+
+architecture Behavioral of IPV4_PACKET_TRANSMITTER is
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------
+-- IPv4 PACKET STRUCTURE : --
+-- Size | Description | Transmission Order | Position --
+-- -----------------------------------------------------------------------------------------------------------
+-- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT --
+-- | X-X-X-X-X-X | | --
+-- | | | --
+-- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT --
+-- | 11111111-11111111-11111111-11111111-... | | --
+-- 2 bytes | Ethernet Type * | 12 13 | LUT --
+-- | (fixed to 00001000-00000000 :=> | | --
+-- | Internet Protocol, Version 4 (IPv4)) | | --
+-- -- Start of IPv4 Packet ** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
+-- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length | 14 | LUT --
+-- | 0100 0101 | | --
+-- 1 byte | Differentiated Services | 15 | LUT --
+-- | 00000000 | | --
+-- 2 bytes | Total Length | 16 17 | REG --
+-- | 00000000-00100100 (base: 20 + 8 + datalength)| | --
+-- 2 bytes | Identification | 18 19 | LUT --
+-- | 00000000-00000000 | | --
+-- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset | 20 21 | LUT --
+-- | 010 - 0000000000000 | | --
+-- 1 byte | Time to Live | 22 | LUT --
+-- | 01000000 | | --
+-- 1 byte | Protocol | 23 | LUT --
+-- | 00010001 | | --
+-- 2 bytes | Header Checksum | 24 25 | REG --
+-- | 10110111 01111101 (base value) | | --
+-- 4 bytes | Source IP Address | 26 27 28 29 | LUT --
+-- | X-X-X-X - FPGA | | --
+-- 4 bytes | Destin IP Address | 30 31 32 33 | LUT --
+-- | X-X-X-X - PC | | --
+-- -- Start of UDP Packet *** - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- | --
+-- 2 bytes | Source Port | 34 35 | LUT --
+-- | X-X | | --
+-- 2 bytes | Destination Port | 36 37 | LUT --
+-- | X-X | | --
+-- 2 bytes | Length | 38 39 | REG --
+-- | 00000000 - 00010000 (8 + # data bytes) | | --
+-- 2 bytes | Checksum | 40 41 | LUT --
+-- | 00000000 - 00000000 | | --
+-- X bytes | Data | 42 .. X | from input --
+-- | | | --
+-----------------------------------------------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------
+
+-- * More details about the Ethernet Type value you can find here:
+-- http://en.wikipedia.org/wiki/Ethertype
+
+-- ** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
+-- http://en.wikipedia.org/wiki/IPv4
+
+-- *** More details about the Internet Protocol, Version 4 (IPv4) you can find here:
+-- http://en.wikipedia.org/wiki/User_Datagram_Protocol
+
+-----------------------------------------------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------------------------------------------------
+
+
+
+--------------------------------------------------------------------------------------
+-- COMPONENT DECLARATION
+--------------------------------------------------------------------------------------
+
+component REG_16B_WREN is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input : in STD_LOGIC_VECTOR (15 downto 0);
+ output : out STD_LOGIC_VECTOR (15 downto 0));
+end component;
+
+component IPV4_LUT_INDEXER is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ transmit_enable : in STD_LOGIC;
+ LUT_index : out STD_LOGIC_VECTOR (5 downto 0));
+end component;
+
+component dist_mem_64x8 is
+ port (
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+end component;
+
+component OVERRIDE_LUT_CONTROL is
+ Port ( clk : in STD_LOGIC;
+ input_addr : in STD_LOGIC_VECTOR (5 downto 0);
+ sel_total_length_MSBs : out STD_LOGIC;
+ sel_total_length_LSBs : out STD_LOGIC;
+ sel_header_checksum_MSBs : out STD_LOGIC;
+ sel_header_checksum_LSBs : out STD_LOGIC;
+ sel_length_MSBs : out STD_LOGIC;
+ sel_length_LSBs : out STD_LOGIC
+ );
+end component;
+
+component TARGET_EOF is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start : in STD_LOGIC;
+ total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
+ eof_O : out STD_LOGIC);
+end component;
+
+component ENABLE_USER_DATA_TRANSMISSION is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start_usr_data_trans : in STD_LOGIC;
+ stop_usr_data_trans : in STD_LOGIC;
+ usr_data_sel : out STD_LOGIC);
+end component;
+
+component ALLOW_ZERO_UDP_CHECKSUM is
+ Port ( clk : in STD_LOGIC;
+ input : in STD_LOGIC;
+ output_to_readen : out STD_LOGIC;
+ output_to_datasel : out STD_LOGIC);
+end component;
+
+
+--------------------------------------------------------------------------------------
+-- SIGNAL DECLARATION
+--------------------------------------------------------------------------------------
+
+signal transmit_start_enable_tmp,
+ sel_total_length_MSBs,
+ sel_total_length_LSBs,
+ sel_header_checksum_MSBs,
+ sel_header_checksum_LSBs,
+ sel_length_MSBs,
+ sel_length_LSBs,
+ lut_out_sel,
+ source_ready_previous_value,
+ end_of_frame_O_tmp,
+ transmit_start_enable_reg,
+ usr_data_sel_sig,
+ start_usr_data_read,
+ start_usr_data_trans : STD_LOGIC;
+
+signal LUT_addr : STD_LOGIC_VECTOR(5 downto 0);
+
+signal transmit_data_input_bus_tmp,
+ transmit_data_output_bus_tmp,
+ sel_total_length_MSBs_vec,
+ sel_total_length_LSBs_vec,
+ sel_header_checksum_MSBs_vec,
+ sel_header_checksum_LSBs_vec,
+ sel_length_MSBs_vec,
+ sel_length_LSBs_vec,
+ lut_out_sel_vec,
+ transmit_data_output_bus_no_usr_data,
+ usr_data_not_sel_vec,
+ usr_data_sel_vec : STD_LOGIC_VECTOR(7 downto 0);
+
+signal transmit_data_length_tmp,
+ data_length_regout,
+ tmp_total_length,
+ tmp_header_checksum,
+ tmp_header_checksum_baseval,
+ tmp_length : STD_LOGIC_VECTOR(15 downto 0);
+
+
+begin
+
+transmit_start_enable_tmp<=transmit_start_enable;
+
+transmit_data_length_tmp<=transmit_data_length;
+
+transmit_data_input_bus_tmp<=transmit_data_input_bus;
+
+----------------------------------------------------------------------------------------------------
+-- start_of_frame_O signal
+----------------------------------------------------------------------------------------------------
+-- Description: start_of_frame_O is active low
+-- We connect it to the delayed for one clock cycle transmit_start_enable input signal
+-- through a NOT gate since transmit_start_enable is active high.
+
+process(clk_125MHz)
+begin
+if clk_125MHz'event and clk_125MHz='1' then
+ transmit_start_enable_reg<=transmit_start_enable_tmp; -- Delay transmit_start_enable one cycle.
+end if;
+end process;
+
+start_of_frame_O<=not transmit_start_enable_reg;
+
+----------------------------------------------------------------------------------------------------
+-- end_of_frame_O signal
+----------------------------------------------------------------------------------------------------
+-- Description: end_of_frame_O is active low
+-- The TARGET_EOF module targets the last byte of the packet that is being transmitted
+-- based on a counter that counts the number of transmitted bytes and a comparator that
+-- detects the last byte which is the th byte.
+
+TARGET_EOF_port_map: TARGET_EOF port map
+(
+ rst =>rst,
+ clk =>clk_125MHz,
+ start =>transmit_start_enable_reg,
+ total_length_from_reg =>tmp_total_length,
+ eof_O =>end_of_frame_O_tmp
+);
+
+--* The counter in TARGET_EOF starts from -X, where X is the number of bytes transmitted before the
+-- IPv4 packet. (MAC addresses + Ethernet Type)
+
+end_of_frame_O<=end_of_frame_O_tmp;
+
+----------------------------------------------------------------------------------------------------
+-- source_ready signal
+----------------------------------------------------------------------------------------------------
+-- Description: source_ready is active low
+-- This signal is idle(high). (based on rst and end_of_frame_O_tmp).
+-- This signal is active(low). (based on transmit_start_enable and end_of_frame_O_tmp).
+
+process(clk_125MHz)
+begin
+if rst='1' then
+ source_ready<='1';
+ source_ready_previous_value<='1';
+else
+ if clk_125MHz'event and clk_125MHz='1' then
+ if (transmit_start_enable_tmp='1' and source_ready_previous_value='1') then
+ source_ready<='0';
+ source_ready_previous_value<='0';
+ else
+ if (end_of_frame_O_tmp='0' and source_ready_previous_value='0') then
+ source_ready<='1';
+ source_ready_previous_value<='1';
+ end if;
+ end if;
+ end if;
+end if;
+end process;
+
+----------------------------------------------------------------------------------------------------
+-- transmit_data_output_bus
+----------------------------------------------------------------------------------------------------
+----------------------------------------------------------------------------------------------------
+-- Component Name: REG_16B_WREN
+-- Instance Name: NUMBER_OR_DATA_IN_BYTES_REGISTER
+-- Description: Register that holds the number of bytes of input data
+-- that will be transmitted in the packet.
+----------------------------------------------------------------------------------------------------
+NUMBER_OR_DATA_IN_BYTES_REGISTER : REG_16B_WREN port map
+(
+ rst =>rst,
+ clk =>clk_125MHz,
+ wren =>transmit_start_enable_tmp, -- The transmit_start_enable input signal can be used as wren.
+ input =>transmit_data_length_tmp,
+ output =>data_length_regout
+);
+----------------------------------------------------------------------------------------------------
+
+tmp_total_length<="0000000000011100" + data_length_regout;
+
+tmp_header_checksum_baseval<="1011011101111101"; -- CHANGE VALUE! : You have to change this value!
+tmp_header_checksum<=tmp_header_checksum_baseval - data_length_regout;
+
+tmp_length<="0000000000001000" + data_length_regout;
+
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: IPV4_LUT_INDEXER
+-- Instance Name: IPV4_LUT_INDEXER_port_map
+-- Description: When transmit_enable is high for one cycle IPV4_LUT_INDEXER generates the
+-- addresses to the LUT that contains the header section of the IP packet.
+----------------------------------------------------------------------------------------------------
+IPV4_LUT_INDEXER_port_map : IPV4_LUT_INDEXER port map
+(
+ rst =>rst,
+ clk =>clk_125MHz,
+ transmit_enable =>transmit_start_enable_tmp,
+ LUT_index =>LUT_addr
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: dist_mem_64x8
+-- Instance Name: LUT_MEM
+-- Description: LUT that contains the header section.
+----------------------------------------------------------------------------------------------------
+LUT_MEM : dist_mem_64x8 port map
+(
+ clk =>clk_125MHz,
+ a =>LUT_addr,
+ qspo =>transmit_data_output_bus_tmp
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: OVERRIDE_LUT_CONTROL
+-- Instance Name: OVERRIDE_LUT_CONTROL_port_map
+-- Description: Decides whether the output byte will come from the LUT or not.
+----------------------------------------------------------------------------------------------------
+OVERRIDE_LUT_CONTROL_port_map : OVERRIDE_LUT_CONTROL port map
+(
+ clk =>clk_125MHz,
+ input_addr =>LUT_addr,
+ sel_total_length_MSBs =>sel_total_length_MSBs,
+ sel_total_length_LSBs =>sel_total_length_LSBs,
+ sel_header_checksum_MSBs =>sel_header_checksum_MSBs,
+ sel_header_checksum_LSBs =>sel_header_checksum_LSBs,
+ sel_length_MSBs =>sel_length_MSBs,
+ sel_length_LSBs =>sel_length_LSBs
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- MUX 7 to 1
+sel_total_length_MSBs_vec<=(others=>sel_total_length_MSBs);
+sel_total_length_LSBs_vec<=(others=>sel_total_length_LSBs);
+sel_header_checksum_MSBs_vec<=(others=>sel_header_checksum_MSBs);
+sel_header_checksum_LSBs_vec<=(others=>sel_header_checksum_LSBs);
+sel_length_MSBs_vec<=(others=>sel_length_MSBs);
+sel_length_LSBs_vec<=(others=>sel_length_LSBs);
+lut_out_sel_vec <= (others=>lut_out_sel);
+
+lut_out_sel<=(not sel_total_length_MSBs) and (not sel_total_length_LSBs) and
+ (not sel_header_checksum_MSBs) and (not sel_header_checksum_LSBs) and
+ (not sel_length_MSBs) and (not sel_length_LSBs);
+
+-- MUX output
+transmit_data_output_bus_no_usr_data<= (transmit_data_output_bus_tmp and lut_out_sel_vec) or
+ (tmp_total_length(15 downto 8) and sel_total_length_MSBs_vec) or
+ (tmp_total_length(7 downto 0) and sel_total_length_LSBs_vec) or
+ (tmp_header_checksum(15 downto 8) and sel_header_checksum_MSBs_vec) or
+ (tmp_header_checksum(7 downto 0) and sel_header_checksum_LSBs_vec) or
+ (tmp_length(15 downto 8) and sel_length_MSBs_vec) or
+ (tmp_length(7 downto 0) and sel_length_LSBs_vec);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: ALLOW_ZERO_UDP_CHECKSUM
+-- Instance Name: ALLOW_ZERO_UDP_CHECKSUM_port_map
+-- Description: Delays the user data transmition phase in order to transmit two bytes with zero
+-- first.
+----------------------------------------------------------------------------------------------------
+ALLOW_ZERO_UDP_CHECKSUM_port_map: ALLOW_ZERO_UDP_CHECKSUM port map
+(
+ clk =>clk_125MHz,
+ input =>sel_length_LSBs,
+ output_to_readen =>start_usr_data_read,
+ output_to_datasel =>start_usr_data_trans
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: ENABLE_USER_DATA_TRANSMISSION
+-- Instance Name: ENABLE_USER_DATA_READ_port_map
+-- Description: Sets usr_data_trans_phase_on signal one cycle before the transmittion of the
+-- first user byte.
+----------------------------------------------------------------------------------------------------
+ENABLE_USER_DATA_READ_port_map: ENABLE_USER_DATA_TRANSMISSION port map
+( rst =>rst,
+ clk =>clk_125MHz,
+ start_usr_data_trans =>start_usr_data_read,
+ stop_usr_data_trans =>end_of_frame_O_tmp,
+ usr_data_sel =>usr_data_trans_phase_on
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- Component Name: ENABLE_USER_DATA_TRANSMISSION
+-- Instance Name: ENABLE_USER_DATA_TRANSMISSION_port_map
+-- Description: Sets usr_data_sel_sig signal to select user data for transmittion.
+----------------------------------------------------------------------------------------------------
+ENABLE_USER_DATA_TRANSMISSION_port_map: ENABLE_USER_DATA_TRANSMISSION port map
+( rst =>rst,
+ clk =>clk_125MHz,
+ start_usr_data_trans =>start_usr_data_trans,
+ stop_usr_data_trans =>end_of_frame_O_tmp,
+ usr_data_sel =>usr_data_sel_sig
+);
+----------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------
+-- MUX 2 to 1
+usr_data_not_sel_vec<=(others=>not usr_data_sel_sig);
+usr_data_sel_vec<=(others=>usr_data_sel_sig);
+
+-- MUX output
+transmit_data_output_bus<=(transmit_data_output_bus_no_usr_data and usr_data_not_sel_vec) or
+ (transmit_data_input_bus and usr_data_sel_vec);
+----------------------------------------------------------------------------------------------------
+
+end Behavioral;
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_PACKET_TRANSMITTER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd (revision 2)
@@ -0,0 +1,60 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 14:46:33 12/04/2009
+-- Design Name:
+-- Module Name: ALLOW_ZERO_UDP_CHECKSUM - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ALLOW_ZERO_UDP_CHECKSUM is
+ Port ( clk : in STD_LOGIC;
+ input : in STD_LOGIC;
+ output_to_readen : out STD_LOGIC;
+ output_to_datasel : out STD_LOGIC);
+end ALLOW_ZERO_UDP_CHECKSUM;
+
+architecture Behavioral of ALLOW_ZERO_UDP_CHECKSUM is
+
+signal input_reg : std_logic;
+
+begin
+
+process(clk)
+begin
+ if clk'event and clk='1' then
+ input_reg<=input;
+ end if;
+end process;
+
+output_to_readen<=input_reg;
+
+process(clk)
+begin
+ if clk'event and clk='1' then
+ output_to_datasel<=input_reg;
+ end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ALLOW_ZERO_UDP_CHECKSUM.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_TRANS.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_TRANS.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_TRANS.vhd (revision 2)
@@ -0,0 +1,58 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:16:57 11/30/2009
+-- Design Name:
+-- Module Name: COUNTER_11B_EN_TRANS - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity COUNTER_11B_EN_TRANS is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end COUNTER_11B_EN_TRANS;
+
+architecture Behavioral of COUNTER_11B_EN_TRANS is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ value_O<="11111110110";
+else
+ if clk'event and clk='1' then
+ if count_en='1' then
+ value_O<=value_O+"00000000001";
+ else
+ value_O<=value_O;
+ end if;
+ end if;
+end if;
+end process;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/COUNTER_11B_EN_TRANS.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.vhd (revision 2)
@@ -0,0 +1,141 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: K.39
+-- \ \ Application: netgen
+-- / / Filename: comp_6b_equal.vhd
+-- /___/ /\ Timestamp: Mon Nov 30 14:23:03 2009
+-- \ \ / \
+-- \___\/\___\
+--
+-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_6b_equal.vhd
+-- Device : 5vsx95tff1136-1
+-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.ngc
+-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_6b_equal.vhd
+-- # of Entities : 1
+-- Design Name : comp_6b_equal
+-- Xilinx : C:\Xilinx\10.1\ISE
+--
+-- Purpose:
+-- This VHDL netlist is a verification model and uses simulation
+-- primitives which may not represent the true implementation of the
+-- device, however the netlist is functionally correct and should not
+-- be modified. This file cannot be synthesized and should only be used
+-- with supported simulation tools.
+--
+-- Reference:
+-- Development System Reference Guide, Chapter 23
+-- Synthesis and Simulation Design Guide, Chapter 6
+--
+--------------------------------------------------------------------------------
+
+
+-- synthesis translate_off
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+use UNISIM.VPKG.ALL;
+
+entity comp_6b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+end comp_6b_equal;
+
+architecture STRUCTURE of comp_6b_equal is
+ signal BU2_N01 : STD_LOGIC;
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;
+ signal BU2_a_ge_b : STD_LOGIC;
+ signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
+ signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
+ signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal b_3 : STD_LOGIC_VECTOR ( 5 downto 0 );
+begin
+ a_2(5) <= a(5);
+ a_2(4) <= a(4);
+ a_2(3) <= a(3);
+ a_2(2) <= a(2);
+ a_2(1) <= a(1);
+ a_2(0) <= a(0);
+ b_3(5) <= b(5);
+ b_3(4) <= b(4);
+ b_3(3) <= b(3);
+ b_3(2) <= b(2);
+ b_3(1) <= b(1);
+ b_3(0) <= b(0);
+ VCC_0 : VCC
+ port map (
+ P => NLW_VCC_P_UNCONNECTED
+ );
+ GND_1 : GND
+ port map (
+ G => NLW_GND_G_UNCONNECTED
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o107 :
+LUT6
+ generic map(
+ INIT => X"0000000080200802"
+ )
+ port map (
+ I0 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16
+,
+ I1 => b_3(5),
+ I2 => b_3(4),
+ I3 => a_2(5),
+ I4 => a_2(4),
+ I5 => BU2_N01,
+ O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o107_SW0 :
+LUT4
+ generic map(
+ INIT => X"6FF6"
+ )
+ port map (
+ I0 => a_2(0),
+ I1 => b_3(0),
+ I2 => a_2(3),
+ I3 => b_3(3),
+ O => BU2_N01
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(1),
+ I1 => b_3(1),
+ I2 => a_2(2),
+ I3 => b_3(2),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o85_16
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,
+ Q => qa_eq_b
+ );
+ BU2_XST_GND : GND
+ port map (
+ G => BU2_a_ge_b
+ );
+
+end STRUCTURE;
+
+-- synthesis translate_on
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.ngc
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.ngc (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.ngc (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.ngc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/TARGET_EOF.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/TARGET_EOF.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/TARGET_EOF.vhd (revision 2)
@@ -0,0 +1,106 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:22:56 11/30/2009
+-- Design Name:
+-- Module Name: TARGET_EOF - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity TARGET_EOF is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start : in STD_LOGIC;
+ total_length_from_reg : in STD_LOGIC_VECTOR(15 downto 0);
+ eof_O : out STD_LOGIC);
+end TARGET_EOF;
+
+architecture Behavioral of TARGET_EOF is
+
+signal count_end : std_logic:='0';
+signal count_en_sig : std_logic:='0';
+signal rst_counter : std_logic:='0';
+
+component COUNTER_11B_EN_TRANS is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end component;
+
+signal value_O_tmp : std_logic_vector(10 downto 0);
+
+component comp_11b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 10 downto 0 )
+ );
+end component;
+
+signal last_byte,last_byte_reg_in,last_byte_reg_out : std_logic;
+
+begin
+
+process(clk)
+begin
+if (rst='1' or count_end='1') then
+ count_en_sig<='0';
+ rst_counter<='1';
+else
+ rst_counter<='0';
+ if clk'event and clk='1' then
+ if (start='1' and count_en_sig='0') then
+ count_en_sig<='1';
+ end if;
+ end if;
+end if;
+end process;
+
+
+COUNT_TRANFERED_BYTES : COUNTER_11B_EN_TRANS port map
+( rst =>rst_counter,
+ clk =>clk,
+ count_en => count_en_sig,
+ value_O =>value_O_tmp
+);
+
+COMP_TO_TARGET_LAST_BYTE : comp_11b_equal port map
+(
+ qa_eq_b =>last_byte_reg_in,
+ clk =>clk,
+ a =>value_O_tmp,
+ b =>total_length_from_reg(10 downto 0)
+);
+
+process(clk)
+begin
+if clk'event and clk='1' then
+ last_byte_reg_out<=last_byte_reg_in;
+end if;
+end process;
+eof_O<=not last_byte_reg_out;
+count_end<=last_byte_reg_out;
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/TARGET_EOF.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.ngc
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.ngc (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.ngc (revision 2)
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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\ No newline at end of file
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.ngc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_16B_WREN.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_16B_WREN.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_16B_WREN.vhd (revision 2)
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 21:15:16 11/27/2009
+-- Design Name:
+-- Module Name: REG_16B_WREN - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description: 16bit wide Register with write enable option.
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity REG_16B_WREN is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input : in STD_LOGIC_VECTOR (15 downto 0);
+ output : out STD_LOGIC_VECTOR (15 downto 0));
+end REG_16B_WREN;
+
+architecture Behavioral of REG_16B_WREN is
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ output<="0000000000000000";
+else
+if clk'event and clk='1' then
+ if wren='1' then
+ output<=input;
+ end if;
+end if;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/REG_16B_WREN.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_LUT_INDEXER.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_LUT_INDEXER.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_LUT_INDEXER.vhd (revision 2)
@@ -0,0 +1,110 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:11:55 11/27/2009
+-- Design Name:
+-- Module Name: IPV4_LUT_INDEXER - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity IPV4_LUT_INDEXER is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ transmit_enable : in STD_LOGIC;
+ LUT_index : out STD_LOGIC_VECTOR (5 downto 0));
+end IPV4_LUT_INDEXER;
+
+architecture Behavioral of IPV4_LUT_INDEXER is
+
+component dist_mem_64x8 is
+ port (
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+end component;
+
+component COUNTER_6B_LUT_FIFO_MODE is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ funct_sel : in STD_LOGIC; -- 0 for lut addressing, 1 for fifo addressing -- only LUT support is used
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (5 downto 0));
+end component;
+
+component comp_6b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 5 downto 0 )
+ );
+end component;
+
+signal count_en_sig , count_end , rst_counter: std_logic :='0';
+signal count_val: std_logic_Vector(5 downto 0):=(others=>'0');
+signal count_en_sig_comb : std_logic;
+constant lut_upper_address :std_logic_vector(5 downto 0):="100110"; -- position 38
+
+begin
+
+process(clk)
+begin
+if (rst='1' or count_end='1') then
+ count_en_sig<='0';
+ rst_counter<='1';
+else
+ rst_counter<='0';
+ if clk'event and clk='1' then
+ if (transmit_enable='1' and count_en_sig='0') then
+ count_en_sig<='1';
+ end if;
+ end if;
+end if;
+end process;
+
+LUT_END_CHECK : comp_6b_equal port map (
+qa_eq_b =>count_end,
+ clk =>clk,
+ a =>count_val,
+ b =>lut_upper_address
+
+);
+
+count_en_sig_comb <=count_en_sig or transmit_enable;
+
+
+
+LUT_INDEXER_MODULE : COUNTER_6B_LUT_FIFO_MODE port map (
+ rst => rst_counter,
+ clk => clk,
+ funct_sel =>'0', -- for now only one function is supported
+ count_en =>count_en_sig_comb,
+ value_O =>count_val
+);
+
+LUT_index<=count_val;
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPV4_LUT_INDEXER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.xco
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.xco (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.xco (revision 2)
@@ -0,0 +1,59 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Mon Nov 30 13:23:03 2009
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc5vsx95t
+SET devicefamily = virtex5
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = ff1136
+SET removerpms = False
+SET simulationfiles = Structural
+SET speedgrade = -1
+SET verilogsim = False
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Comparator family Xilinx,_Inc. 9.0
+# END Select
+# BEGIN Parameters
+CSET aclr=false
+CSET ainitval=0
+CSET aset=false
+CSET ce=false
+CSET cepriority=Sync_Overrides_CE
+CSET component_name=comp_6b_equal
+CSET constantbport=false
+CSET constantbportvalue=0000000000000000
+CSET datatype=Unsigned
+CSET nonregisteredoutput=false
+CSET operation=eq
+CSET pipelinestages=0
+CSET radix=2
+CSET registeredoutput=true
+CSET sclr=false
+CSET sset=false
+CSET syncctrlpriority=Reset_Overrides_Set
+CSET width=6
+# END Parameters
+GENERATE
+# CRC: 74b0a9bd
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_6b_equal.xco
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd (revision 2)
@@ -0,0 +1,64 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 12:05:48 12/04/2009
+-- Design Name:
+-- Module Name: ENABLE_USER_DATA_TRANSMISSION - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ENABLE_USER_DATA_TRANSMISSION is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ start_usr_data_trans : in STD_LOGIC;
+ stop_usr_data_trans : in STD_LOGIC;
+ usr_data_sel : out STD_LOGIC);
+end ENABLE_USER_DATA_TRANSMISSION;
+
+architecture Behavioral of ENABLE_USER_DATA_TRANSMISSION is
+
+signal usr_data_sel_prev : std_logic :='0';
+
+begin
+
+process(clk)
+begin
+if rst='1' then
+ usr_data_sel<='0';
+ usr_data_sel_prev<='0';
+else
+ if clk'event and clk='1' then
+ if (start_usr_data_trans='1' and usr_data_sel_prev='0') then
+ usr_data_sel<='1';
+ usr_data_sel_prev<='1';
+ end if;
+ if (stop_usr_data_trans='0' and usr_data_sel_prev='1') then -- stop_usr_data_trans is active low
+ usr_data_sel<='0';
+ usr_data_sel_prev<='0';
+ end if;
+ end if;
+end if;
+end process;
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/ENABLE_USER_DATA_TRANSMISSION.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/UDP_IP_Core.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/UDP_IP_Core.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/UDP_IP_Core.vhd (revision 2)
@@ -0,0 +1,109 @@
+-----------------------------------------------------------------------------------------
+-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
+-- --
+-- Engineer: Nikolaos Ch. Alachiotis --
+-- --
+-- Contact: alachiot@cs.tum.edu --
+-- n.alachiotis@gmail.com --
+-- --
+-- Create Date: 15:29:59 02/07/2010 --
+-- Module Name: UDP_IP_Core --
+-- Target Devices: Virtex 5 FPGAs --
+-- Tool versions: ISE 10.1 --
+-- Description: This component can be used to transmit and receive UDP/IP --
+-- Ethernet Packets (IPv4). --
+-- Additional Comments: The core has been area-optimized and is suitable for direct --
+-- PC-FPGA communication at Gigabit speed. --
+-- --
+-----------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity UDP_IP_Core is
+ Port ( rst : in STD_LOGIC; -- active-high
+ clk_125MHz : in STD_LOGIC;
+
+ -- Transmit signals
+ transmit_start_enable : in STD_LOGIC;
+ transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
+ usr_data_trans_phase_on : out STD_LOGIC;
+ transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
+ start_of_frame_O : out STD_LOGIC;
+ end_of_frame_O : out STD_LOGIC;
+ source_ready : out STD_LOGIC;
+ transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
+
+ --Receive Signals
+ rx_sof : in STD_LOGIC;
+ rx_eof : in STD_LOGIC;
+ input_bus : in STD_LOGIC_VECTOR(7 downto 0);
+ valid_out_usr_data : out STD_LOGIC;
+ usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+end UDP_IP_Core;
+
+architecture Behavioral of UDP_IP_Core is
+
+component IPV4_PACKET_TRANSMITTER is
+ Port ( rst : in STD_LOGIC;
+ clk_125MHz : in STD_LOGIC;
+ transmit_start_enable : in STD_LOGIC;
+ transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
+ usr_data_trans_phase_on : out STD_LOGIC;
+ transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
+ start_of_frame_O : out STD_LOGIC;
+ end_of_frame_O : out STD_LOGIC;
+ source_ready : out STD_LOGIC;
+ transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
+ );
+end component;
+
+component IPv4_PACKET_RECEIVER is
+ Port ( rst : in STD_LOGIC;
+ clk_125Mhz : in STD_LOGIC;
+ rx_sof : in STD_LOGIC;
+ rx_eof : in STD_LOGIC;
+ input_bus : in STD_LOGIC_VECTOR(7 downto 0);
+ valid_out_usr_data : out STD_LOGIC;
+ usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0));
+end component;
+
+begin
+
+IPV4_PACKET_TRANSMITTER_port_map: IPV4_PACKET_TRANSMITTER
+ Port Map
+ ( rst => rst,
+ clk_125MHz => clk_125MHz,
+ transmit_start_enable => transmit_start_enable,
+ transmit_data_length => transmit_data_length,
+ usr_data_trans_phase_on => usr_data_trans_phase_on,
+ transmit_data_input_bus => transmit_data_input_bus,
+ start_of_frame_O => start_of_frame_O,
+ end_of_frame_O => end_of_frame_O,
+ source_ready => source_ready,
+ transmit_data_output_bus => transmit_data_output_bus
+ );
+
+
+IPv4_PACKET_RECEIVER_port_map: IPv4_PACKET_RECEIVER
+ Port Map
+ ( rst => rst,
+ clk_125Mhz => clk_125Mhz,
+ rx_sof => rx_sof,
+ rx_eof => rx_eof,
+ input_bus => input_bus,
+ valid_out_usr_data => valid_out_usr_data,
+ usr_data_output_bus => usr_data_output_bus
+ );
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/UDP_IP_Core.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.vhd (revision 2)
@@ -0,0 +1,196 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: K.39
+-- \ \ Application: netgen
+-- / / Filename: comp_11b_equal.vhd
+-- /___/ /\ Timestamp: Mon Nov 30 16:37:25 2009
+-- \ \ / \
+-- \___\/\___\
+--
+-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\comp_11b_equal.vhd
+-- Device : 5vsx95tff1136-1
+-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.ngc
+-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/comp_11b_equal.vhd
+-- # of Entities : 1
+-- Design Name : comp_11b_equal
+-- Xilinx : C:\Xilinx\10.1\ISE
+--
+-- Purpose:
+-- This VHDL netlist is a verification model and uses simulation
+-- primitives which may not represent the true implementation of the
+-- device, however the netlist is functionally correct and should not
+-- be modified. This file cannot be synthesized and should only be used
+-- with supported simulation tools.
+--
+-- Reference:
+-- Development System Reference Guide, Chapter 23
+-- Synthesis and Simulation Design Guide, Chapter 6
+--
+--------------------------------------------------------------------------------
+
+
+-- synthesis translate_off
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+use UNISIM.VPKG.ALL;
+
+entity comp_11b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 10 downto 0 )
+ );
+end comp_11b_equal;
+
+architecture STRUCTURE of comp_11b_equal is
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26 : STD_LOGIC;
+
+ signal BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result : STD_LOGIC;
+ signal BU2_a_ge_b : STD_LOGIC;
+ signal NLW_VCC_P_UNCONNECTED : STD_LOGIC;
+ signal NLW_GND_G_UNCONNECTED : STD_LOGIC;
+ signal a_2 : STD_LOGIC_VECTOR ( 10 downto 0 );
+ signal b_3 : STD_LOGIC_VECTOR ( 10 downto 0 );
+begin
+ a_2(10) <= a(10);
+ a_2(9) <= a(9);
+ a_2(8) <= a(8);
+ a_2(7) <= a(7);
+ a_2(6) <= a(6);
+ a_2(5) <= a(5);
+ a_2(4) <= a(4);
+ a_2(3) <= a(3);
+ a_2(2) <= a(2);
+ a_2(1) <= a(1);
+ a_2(0) <= a(0);
+ b_3(10) <= b(10);
+ b_3(9) <= b(9);
+ b_3(8) <= b(8);
+ b_3(7) <= b(7);
+ b_3(6) <= b(6);
+ b_3(5) <= b(5);
+ b_3(4) <= b(4);
+ b_3(3) <= b(3);
+ b_3(2) <= b(2);
+ b_3(1) <= b(1);
+ b_3(0) <= b(0);
+ VCC_0 : VCC
+ port map (
+ P => NLW_VCC_P_UNCONNECTED
+ );
+ GND_1 : GND
+ port map (
+ G => NLW_GND_G_UNCONNECTED
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o206 :
+LUT6
+ generic map(
+ INIT => X"9000000000000000"
+ )
+ port map (
+ I0 => a_2(2),
+ I1 => b_3(2),
+ I2 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26
+,
+ I3 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27
+,
+ I4 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28
+,
+ I5 =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29
+,
+ O => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189 :
+LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => a_2(5),
+ I1 => b_3(5),
+ I2 => a_2(6),
+ I3 => b_3(6),
+ I4 => a_2(7),
+ I5 => b_3(7),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o189_29
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139 :
+LUT6
+ generic map(
+ INIT => X"9009000000009009"
+ )
+ port map (
+ I0 => a_2(8),
+ I1 => b_3(8),
+ I2 => a_2(9),
+ I3 => b_3(9),
+ I4 => a_2(10),
+ I5 => b_3(10),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o139_28
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(3),
+ I1 => b_3(3),
+ I2 => a_2(4),
+ I3 => b_3(4),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o62_27
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26 :
+LUT4
+ generic map(
+ INIT => X"9009"
+ )
+ port map (
+ I0 => a_2(0),
+ I1 => b_3(0),
+ I2 => a_2(1),
+ I3 => b_3(1),
+ O =>
+BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_i_use_carry_plus_luts_lut_and_i_gate_bit_tier_gen_1_i_tier_loop_tiles_0_i_tile_o26_26
+
+ );
+ BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_gen_output_reg_output_reg_fd_output_1 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_structure_logic_gen_nonpipelined_a_equal_notequal_b_i_a_eq_ne_b_temp_result,
+ Q => qa_eq_b
+ );
+ BU2_XST_GND : GND
+ port map (
+ G => BU2_a_ge_b
+ );
+
+end STRUCTURE;
+
+-- synthesis translate_on
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/comp_11b_equal.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.vhd (revision 2)
@@ -0,0 +1,264 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: K.39
+-- \ \ Application: netgen
+-- / / Filename: dist_mem_64x8.vhd
+-- /___/ /\ Timestamp: Tue Dec 01 15:45:04 2009
+-- \ \ / \
+-- \___\/\___\
+--
+-- Command : -intstyle ise -w -sim -ofmt vhdl C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.ngc C:\PHd_Projects\The_Felsenstein_CoProcessor\COREGEN_Design\tmp\_cg\dist_mem_64x8.vhd
+-- Device : 5vsx95tff1136-1
+-- Input file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.ngc
+-- Output file : C:/PHd_Projects/The_Felsenstein_CoProcessor/COREGEN_Design/tmp/_cg/dist_mem_64x8.vhd
+-- # of Entities : 1
+-- Design Name : dist_mem_64x8
+-- Xilinx : C:\Xilinx\10.1\ISE
+--
+-- Purpose:
+-- This VHDL netlist is a verification model and uses simulation
+-- primitives which may not represent the true implementation of the
+-- device, however the netlist is functionally correct and should not
+-- be modified. This file cannot be synthesized and should only be used
+-- with supported simulation tools.
+--
+-- Reference:
+-- Development System Reference Guide, Chapter 23
+-- Synthesis and Simulation Design Guide, Chapter 6
+--
+--------------------------------------------------------------------------------
+
+
+-- synthesis translate_off
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+use UNISIM.VPKG.ALL;
+
+entity dist_mem_64x8 is
+ port (
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 5 downto 0 );
+ qspo : out STD_LOGIC_VECTOR ( 7 downto 0 )
+ );
+end dist_mem_64x8;
+
+architecture STRUCTURE of dist_mem_64x8 is
+ signal N0 : STD_LOGIC;
+ signal N1 : STD_LOGIC;
+ signal a_2 : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal qspo_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal BU2_U0_gen_rom_rom_inst_spo_int : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal BU2_qdpo : STD_LOGIC_VECTOR ( 0 downto 0 );
+begin
+ a_2(5) <= a(5);
+ a_2(4) <= a(4);
+ a_2(3) <= a(3);
+ a_2(2) <= a(2);
+ a_2(1) <= a(1);
+ a_2(0) <= a(0);
+ qspo(7) <= qspo_3(7);
+ qspo(6) <= qspo_3(6);
+ qspo(5) <= qspo_3(5);
+ qspo(4) <= qspo_3(4);
+ qspo(3) <= qspo_3(3);
+ qspo(2) <= qspo_3(2);
+ qspo(1) <= qspo_3(1);
+ qspo(0) <= qspo_3(0);
+ VCC_0 : VCC
+ port map (
+ P => N1
+ );
+ GND_1 : GND
+ port map (
+ G => N0
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom0000111 : LUT6
+ generic map(
+ INIT => X"0000061400040604"
+ )
+ port map (
+ I0 => a_2(2),
+ I1 => a_2(3),
+ I2 => a_2(5),
+ I3 => a_2(1),
+ I4 => a_2(4),
+ I5 => a_2(0),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(1)
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000071 : LUT6
+ generic map(
+ INIT => X"2100210023022222"
+ )
+ port map (
+ I0 => a_2(3),
+ I1 => a_2(5),
+ I2 => a_2(4),
+ I3 => a_2(1),
+ I4 => a_2(0),
+ I5 => a_2(2),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(7)
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000041 : LUT6
+ generic map(
+ INIT => X"0204162600041726"
+ )
+ port map (
+ I0 => a_2(2),
+ I1 => a_2(3),
+ I2 => a_2(5),
+ I3 => a_2(1),
+ I4 => a_2(4),
+ I5 => a_2(0),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(4)
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000051 : LUT6
+ generic map(
+ INIT => X"2301030311110112"
+ )
+ port map (
+ I0 => a_2(4),
+ I1 => a_2(5),
+ I2 => a_2(2),
+ I3 => a_2(0),
+ I4 => a_2(1),
+ I5 => a_2(3),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(5)
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000021 : LUT6
+ generic map(
+ INIT => X"0100057801014578"
+ )
+ port map (
+ I0 => a_2(5),
+ I1 => a_2(1),
+ I2 => a_2(2),
+ I3 => a_2(3),
+ I4 => a_2(4),
+ I5 => a_2(0),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(2)
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000031 : LUT6
+ generic map(
+ INIT => X"090101020B0A0202"
+ )
+ port map (
+ I0 => a_2(3),
+ I1 => a_2(4),
+ I2 => a_2(5),
+ I3 => a_2(1),
+ I4 => a_2(0),
+ I5 => a_2(2),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(3)
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000061 : LUT6
+ generic map(
+ INIT => X"010701EF02460224"
+ )
+ port map (
+ I0 => a_2(2),
+ I1 => a_2(3),
+ I2 => a_2(4),
+ I3 => a_2(5),
+ I4 => a_2(0),
+ I5 => a_2(1),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(6)
+ );
+ BU2_U0_gen_rom_rom_inst_Mrom_spo_int_rom000011 : LUT6
+ generic map(
+ INIT => X"1202020210347366"
+ )
+ port map (
+ I0 => a_2(3),
+ I1 => a_2(5),
+ I2 => a_2(1),
+ I3 => a_2(0),
+ I4 => a_2(2),
+ I5 => a_2(4),
+ O => BU2_U0_gen_rom_rom_inst_spo_int(0)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_7 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(7),
+ Q => qspo_3(7)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_6 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(6),
+ Q => qspo_3(6)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_5 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(5),
+ Q => qspo_3(5)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_4 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(4),
+ Q => qspo_3(4)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_3 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(3),
+ Q => qspo_3(3)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_2 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(2),
+ Q => qspo_3(2)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_1 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(1),
+ Q => qspo_3(1)
+ );
+ BU2_U0_gen_rom_rom_inst_qspo_int_0 : FD
+ generic map(
+ INIT => '0'
+ )
+ port map (
+ C => clk,
+ D => BU2_U0_gen_rom_rom_inst_spo_int(0),
+ Q => qspo_3(0)
+ );
+ BU2_XST_GND : GND
+ port map (
+ G => BU2_qdpo(0)
+ );
+
+end STRUCTURE;
+
+-- synthesis translate_on
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/dist_mem_64x8.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPv4_PACKET_RECEIVER.vhd
===================================================================
--- trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPv4_PACKET_RECEIVER.vhd (nonexistent)
+++ trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPv4_PACKET_RECEIVER.vhd (revision 2)
@@ -0,0 +1,182 @@
+-----------------------------------------------------------------------------------------
+-- Copyright (C) 2010 Nikolaos Ch. Alachiotis --
+-- --
+-- Engineer: Nikolaos Ch. Alachiotis --
+-- --
+-- Contact: alachiot@cs.tum.edu --
+-- n.alachiotis@gmail.com --
+-- --
+-- Create Date: 14:32:06 02/07/2010 --
+-- Module Name: IPv4_PACKET_RECEIVER --
+-- Target Devices: Virtex 5 FPGAs --
+-- Tool versions: ISE 10.1 --
+-- Description: This component can be used to receive IPv4 Ethernet Packets. --
+-- Additional Comments: --
+-- --
+-- The receiver does not operate properly for data section of 1 or 2 bytes only. --
+-- --
+-----------------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity IPv4_PACKET_RECEIVER is
+ Port ( rst : in STD_LOGIC;
+ clk_125Mhz : in STD_LOGIC;
+ rx_sof : in STD_LOGIC;
+ rx_eof : in STD_LOGIC;
+ input_bus : in STD_LOGIC_VECTOR(7 downto 0);
+ valid_out_usr_data : out STD_LOGIC;
+ usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0));
+end IPv4_PACKET_RECEIVER;
+
+architecture Behavioral of IPv4_PACKET_RECEIVER is
+
+component PACKET_RECEIVER_FSM is
+ Port (
+ rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+
+ -- Signals from EMAC
+ rx_sof: in STD_LOGIC; -- active low input
+ rx_eof: in STD_LOGIC; -- active low input
+
+ -- Signals to Counter and Comparator
+ sel_comp_Bval: out STD_LOGIC;
+ comp_Bval: out STD_LOGIC_VECTOR(10 downto 0);
+ rst_count : out STD_LOGIC;
+ en_count : out STD_LOGIC;
+
+ -- Signal from Comparator
+ comp_eq: in STD_LOGIC;
+
+ -- Signals to Length Register
+ wren_MSbyte: out STD_LOGIC;
+ wren_LSbyte: out STD_LOGIC;
+
+ -- Signal to user interface
+ valid_out_usr_data : out STD_LOGIC);
+end component;
+
+component REG_8b_wren is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ wren : in STD_LOGIC;
+ input_val : in STD_LOGIC_VECTOR (7 downto 0);
+ output_val : inout STD_LOGIC_VECTOR(7 downto 0));
+end component;
+
+component COUNTER_11B_EN_RECEIV is
+ Port ( rst : in STD_LOGIC;
+ clk : in STD_LOGIC;
+ count_en : in STD_LOGIC;
+ value_O : inout STD_LOGIC_VECTOR (10 downto 0));
+end component;
+
+component comp_11b_equal is
+ port (
+ qa_eq_b : out STD_LOGIC;
+ clk : in STD_LOGIC := 'X';
+ a : in STD_LOGIC_VECTOR ( 10 downto 0 );
+ b : in STD_LOGIC_VECTOR ( 10 downto 0 )
+ );
+end component;
+
+signal sel_comp_Bval,
+ rst_count,
+ en_count,
+ comp_eq,
+ wren_MSbyte,
+ wren_LSbyte: STD_LOGIC;
+
+signal MSbyte_reg_val_out,
+ LSbyte_reg_val_out : STD_LOGIC_VECTOR(7 downto 0);
+
+signal counter_val,
+ match_val,
+ comp_Bval,
+ comp_sel_val_vec,
+ comp_n_sel_val_vec,
+ length_val: STD_LOGIC_VECTOR(10 downto 0);
+
+constant length_offest : STD_LOGIC_VECTOR(7 downto 0):="00001010";
+-- This value is formed as 2 (1 clock the latency of comparator and 1 clock fro changing the FSM state) + 8 (number of bytes of UDP header section)
+
+begin
+
+usr_data_output_bus<=input_bus;
+
+PACKET_RECEIVER_FSM_port_map: PACKET_RECEIVER_FSM Port Map
+(
+ rst => rst,
+ clk => clk_125MHz,
+
+ rx_sof => rx_sof,
+ rx_eof => rx_eof,
+
+ sel_comp_Bval => sel_comp_Bval,
+ comp_Bval => comp_Bval,
+ rst_count => rst_count,
+ en_count => en_count,
+
+ comp_eq => comp_eq,
+
+ wren_MSbyte => wren_MSbyte,
+ wren_LSbyte => wren_LSbyte,
+
+ valid_out_usr_data => valid_out_usr_data
+);
+
+MSbyte_REG: REG_8b_wren Port Map
+(
+ rst => rst,
+ clk => clk_125MHz,
+ wren => wren_MSbyte,
+ input_val => input_bus,
+ output_val =>MSbyte_reg_val_out
+);
+
+LSbyte_REG: REG_8b_wren Port Map
+(
+ rst => rst,
+ clk => clk_125MHz,
+ wren => wren_LSbyte,
+ input_val => input_bus,
+ output_val =>LSbyte_reg_val_out
+);
+
+COUNTER_11B_EN_port_map: COUNTER_11B_EN_RECEIV Port Map
+(
+ rst => rst_count,
+ clk => clk_125MHz,
+ count_en => en_count,
+ value_O => counter_val
+);
+
+Comp_11b_equal_port_map: Comp_11b_equal Port Map
+(
+ qa_eq_b => comp_eq,
+ clk => clk_125MHz,
+ a => counter_val,
+ b => match_val
+ );
+
+length_val(7 downto 0)<= LSbyte_reg_val_out-length_offest;
+length_val(10 downto 8)<= MSbyte_reg_val_out (2 downto 0);
+
+comp_sel_val_vec<=(others=> sel_comp_Bval);
+comp_n_sel_val_vec<= (others=> not sel_comp_Bval);
+
+match_val<= (comp_sel_val_vec and length_val) or (comp_n_sel_val_vec and comp_Bval);
+
+
+end Behavioral;
+
trunk/UDP_IP_CORE/UDP_IP_CORE__Virtex5/IPv4_PACKET_RECEIVER.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/LUT_COE_file/definition2_ipv4_lut.coe
===================================================================
--- trunk/LUT_COE_file/definition2_ipv4_lut.coe (nonexistent)
+++ trunk/LUT_COE_file/definition2_ipv4_lut.coe (revision 2)
@@ -0,0 +1,66 @@
+MEMORY_INITIALIZATION_RADIX=2;
+MEMORY_INITIALIZATION_VECTOR=
+00000000,
+00100001,
+01110000,
+11101001,
+00110100,
+01011100,
+11111111,
+11111111,
+11111111,
+11111111,
+11111111,
+11111111,
+00001000,
+00000000,
+01000101,
+00000000,
+00100100,
+00000000,
+00000000,
+00000000,
+01000000,
+00000000,
+01000000,
+00010001,
+10110111,
+01111101,
+11000000,
+10101000,
+00000001,
+00000001,
+11000000,
+10101000,
+00000001,
+00000010,
+01010101,
+01010101,
+01010101,
+01010100,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000,
+00000000;
trunk/LUT_COE_file/definition2_ipv4_lut.coe
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/README.txt
===================================================================
--- trunk/README.txt (nonexistent)
+++ trunk/README.txt (revision 2)
@@ -0,0 +1,264 @@
+======================================================================================================
+UDP/IP Core for FPGAs (in VHDL)
+======================================================================================================
+
+Update date: February 9th, 2010
+Build date: December 15th, 2009
+
+
+Description
+-----------
+
+
+This is a VHDL implementation of a UDP/IP core that can be connected to the input and output ports of the
+Virtex-5 Ethernet MAC Local Link Wrapper and enable communication betweena a PC and a FPGA.
+
+It has been area-optimized, it is suitable for direct PC-FPGA communication and can operate at Gigabit speed.
+
+
+Example placement on a Virtex 5:
+
+
+-- -----------------------------------------------------------------------
+-- | EXAMPLE DESIGN WRAPPER |
+-- | --------------------------------------------------------|
+-- | |LOCAL LINK WRAPPER |
+-- | | -----------------------------------------|
+-- | UDP/IP core | |BLOCK LEVEL WRAPPER |
+-- | ----------- | | --------------------- |
+-- | |-------- | | ---------- | | ETHERNET MAC | |
+-- | || IPv4 | | | | | | | WRAPPER | --------- |
+-- |->| pack |-> |->| |--|--->| Tx Tx |--| |--->|
+-- | || trans| | | | | | | client PHY | | | |
+-- | |-------- | | | LOCAL | | | I/F I/F | | | |
+-- | | | | | LINK | | | | | PHY | |
+-- | | | | | FIFO | | | | | I/F | |
+-- | | | | | | | | | | | |
+-- | |-------- | | | | | | Rx Rx | | | |
+-- | || IPv4 | | | | | | | client PHY | | | |
+-- | || pack |<- |<-| |<-|----| I/F I/F |<-| |<---|
+-- | ||receiv| | | | | | | | --------- |
+-- | |-------- | | ---------- | --------------------- |
+-- | ----------- | -----------------------------------------|
+-- | --------------------------------------------------------|
+-- -----------------------------------------------------------------------
+
+
+
+Package Structure
+-----------------
+
+This package contains the following files and folder:
+
+-README : This file
+
+-UDP_IP_CORE : This folder contains VHDL, XCO and NGC files both for Virtex 5 as well as Spartan 3 FPGAs.
+
+-LUT COE file : This folder contains a COE file for the LUT that contains the IP packet header field.
+
+-JAVA app : This folder contains the JAVA application used on the PC side for transmitting and receiving packets.
+
+-PAPER : This folder contains a paper that describes in detail the design and implementation of the core.
+
+
+
+Usage of the UDP/IP core
+------------------------
+
+
+Before integrating the core into your design you have to reinitialize the LUT of the transmitter.
+This LUT contains the header section of the IP packet.One must change the X fields that appear in the following table.
+
+The field that should be changed are:
+Destination MAC Address : (LUT)
+Source MAC Address : (LUT)
+Source IP Address : (LUT)
+Destination IP Address : (LUT)
+Source Port : (LUT)
+Destination Port : (LUT)
+Header Checksum : VHDL file
+
+The Addresses are read from the LUT, thats why a reinitialization is required.
+The Header Checksum base value is not read from the LUT. It can be found in the VHDL file.
+The Header Checksum base value depends on the IP Addresses and it is the Header Checksum value of a packet with no user data.
+
+If you choose to use the JAVA application provided in this packet only the Destination MAC Address needs to change.
+
+
+------------------------------------------------------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------------------------------------------------------
+-- IPv4 PACKET STRUCTURE : -- --
+-- size | Description | Transmission Order | Position --
+------------------------------------------------------------------------------------------------------------------------------------------
+-- 6 bytes | Destin MAC Address (PC) | 0 1 2 3 4 5 | LUT --
+-- | X-X-X-X-X-X | | --
+-- | | | --
+-- 6 bytes | Source MAC Address (FPGA) | 6 7 8 9 10 11 | LUT --
+-- | 11111111-11111111-11111111-11111111-... | | --
+-- 2 bytes | Ethernet Type | 12 13 | LUT --
+-- | (fixed to 00001000-00000000 :=> | | --
+-- | Internet Protocol, Version 4 (IPv4)) | | --
+-- -- Start of IPv4 Packet - - - - - - - - - - - - - -- --
+-- 1 byte | 4 MSBs = Version , 4 LSBs = Header Length| 14 | LUT --
+-- | 0100 0101 | | --
+-- 1 byte | Differentiated Services | 15 | LUT --
+-- | 00000000 | | --
+-- 2 bytes | Total Length | 16 17 | REG --
+-- | 00000000-00100100 (base: 20 + 8 + datalength)| | --
+-- 2 bytes | Identification | 18 19 | LUT --
+-- | 00000000-00000000 | | --
+-- 2 bytes | 3 MSBs = Flags , 13 LSBs = Fragment Offset| 20 21 | LUT --
+-- | 010 - 0000000000000 | | --
+-- 1 byte | Time to Live | 22 | LUT --
+-- | 01000000 | | --
+-- 1 byte | Protocol | 23 | LUT --
+-- | 00010001 | | --
+-- 2 bytes | Header Checksum | 24 25 | REG --
+-- | X X (base value) | | --
+-- 4 bytes | Source IP Address | 26 27 28 29 | LUT --
+-- | X-X-X-X - FPGA | | --
+-- 4 bytes | Destin IP Address | 30 31 32 33 | LUT --
+-- | X-X-X-X - PC | | --
+-- -- Start of UDP Packet - - - - - - - - - - - - - - -- --
+-- 2 bytes | Source Port | 34 35 | LUT --
+-- | X-X | | --
+-- 2 bytes | Destination Port | 36 37 | LUT --
+-- | X-X | | --
+-- 2 bytes | Length | 38 39 | REG --
+-- | 00000000 - 00010000 (8 + # data bytes)| | --
+-- 2 bytes | Checksum | 40 41 | LUT --
+-- | 00000000 - 00000000 | | --
+-- X bytes | Data | 42 .. X | from input --
+-- | | | -- --
+------------------------------------------------------------------------------------------------------------------------------------------
+------------------------------------------------------------------------------------------------------------------------------------------
+
+
+
+Interface of the UDP/IP core
+----------------------------
+
+
+The interface of the unit is defined as follows:
+
+entity UDP_IP_Core is
+ Port ( rst : in STD_LOGIC; -- active-high
+ clk_125MHz : in STD_LOGIC;
+
+ -- Transmit signals
+ transmit_start_enable : in STD_LOGIC;
+ transmit_data_length : in STD_LOGIC_VECTOR (15 downto 0);
+ usr_data_trans_phase_on : out STD_LOGIC;
+ transmit_data_input_bus : in STD_LOGIC_VECTOR (7 downto 0);
+ start_of_frame_O : out STD_LOGIC;
+ end_of_frame_O : out STD_LOGIC;
+ source_ready : out STD_LOGIC;
+ transmit_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0);
+
+ --Receive Signals
+ rx_sof : in STD_LOGIC;
+ rx_eof : in STD_LOGIC;
+ input_bus : in STD_LOGIC_VECTOR(7 downto 0);
+ valid_out_usr_data : out STD_LOGIC;
+ usr_data_output_bus : out STD_LOGIC_VECTOR (7 downto 0)
+);
+end UDP_IP_Core;
+
+
+The UDP/IP core and the LOCAL LINK WRAPPER must have the same rst and clk signals.
+
+Signal transmit_start_enable : active high , It must be high for one clock cycle only.
+
+Signal transmit_data_length : number of user data to be transmitted (number of bytes)
+
+Signal usr_data_trans_phase_on: is high one clock cycle before the transmittion of user data and remains high while transmitting user data.
+
+Signal transmit_data_input_bus : input data to be transmitted. Starts transmitting one clock cycle after the usr_data_trans_phase_on is set.
+
+Signals start_of_frame_O,end_of_frame_O,source_ready,transmit_data_output_bus should be connected to the local link wrapper's input ports.
+
+Signals rx_sof, rx_eof : active low, inputs from the local link wrapper
+
+Signal input_bus : input from the local link wrapper
+
+Signal valid_out_usr_data : output to user, when set it indicates that the usr_data_output_bus contains the user data section of the incoming packet
+
+Signal usr_data_output_bus : user data output bus output to the user
+
+
+
+Implementation Details
+----------------------
+
+The VHDL unit have been designed using the Xilinx 10.1 Design Suite.
+
+ISE 10.1 was used to create the unit.
+
+
+
+Verification Details
+--------------------
+
+Modelsim 6.3f was used for extensive post place and route simulations.
+
+The development board HTG-V5-PCIE by HiTech Global populated with a V5SX95T-1 FPGA was used to verify the correct behavior of the core.
+
+The Spartan3 configuration has not been hardware-verified!
+
+
+Citation
+--------
+
+By using this component in any architecture design and associated publication, you agree to cite it as:
+"Efficient PC-FPGA Communication over Gigabit Ethernet", by Nikolaos Alachiotis, Simon A. Berger and Alexandros Stamatakis,
+The Exelixis Lab, Exelixis-RRDR-2010-4, TU Munich, February 2010.
+
+
+Authors and Contact Details
+---------------------------
+
+Nikos Alachiotis alachiot@in.tum.de , n.alachiotis@gmail.com
+Simon A. Berger bergers@in.tum.de
+Alexandros Stamatakis stamatak@in.tum.de
+
+Technichal University of Munich
+Department of Computer Science / I 12
+The Exelixis Lab
+Boltzmannstr. 3
+D-85748 Garching b. Muenchen
+
+
+Copyright
+---------
+
+This component is free. In case you use it for any purpose, particularly
+when publishing work relying on this component you must cite it as:
+
+IPv4 PACKET TRANSMITTER by Nikolas Alachiotis and Alexandros Stamatakis, The Exelixis Lab, TU Munich, distributed by the authors via
+http://wwwkramer.in.tum.de/exelixis/
+
+You can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This component is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+
+
+Release Notes
+------------
+
+Update date: February 9th, 2010
+
+Build date : December 15th, 2009
+
+
+
+
+
+
+
trunk/README.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
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