URL
https://opencores.org/ocsvn/usb11_sim_model/usb11_sim_model/trunk
Subversion Repositories usb11_sim_model
Compare Revisions
- This comparison shows the changes necessary to convert path
/usb11_sim_model
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/USB_tb.vhd
7,8 → 7,8
-- is not removed from the file and that any derivative work contains the original copyright notice and -- |
-- the associated disclaimer. -- |
-- -- |
-- This software is provided ''as is'' and without any express or implied warranties, including, but not -- |
-- limited to, the implied warranties of merchantability and fitness for a particular purpose. in no event -- |
-- This software is provided ''as is'' and without any expressed or implied warranties, including, but not -- |
-- limited to, the implied warranties of merchantability and fitness for a particular purpose. In no event -- |
-- shall the author or contributors be liable for any direct, indirect, incidental, special, exemplary, or -- |
-- consequential damages (including, but not limited to, procurement of substitute goods or services; loss -- |
-- of use, data, or profits; or business interruption) however caused and on any theory of liability, -- |
19,7 → 19,7
-- -- |
-- File name : USB_tb.vhd -- |
-- Author : Martin Neumann martin@neumanns-mail.de -- |
-- Description : USB test bench used with usb_mster.vhd, usb_Stimuli.vhd and usb_fs_monitor.vhd. -- |
-- Description : USB test bench - an example how to use the usb_master files together an US application. -- |
-- -- |
--==========================================================================================================-- |
-- -- |
28,6 → 28,7
-- Version / date Description -- |
-- -- |
-- 01 05 Mar 2011 MN Initial version -- |
-- 02 15 Apr 2013 MN Simplified -- |
-- -- |
-- End change history -- |
--==========================================================================================================-- |
41,26 → 42,27
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ARCHITECTURE sim OF usb_tb IS |
|
CONSTANT BUFSIZE_BITS : POSITIVE := 8; |
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SIGNAL FPGA_ready : STD_LOGIC; |
SIGNAL RXdat : STD_LOGIC_VECTOR(7 DOWNTO 0); |
SIGNAL RXlen : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0); |
SIGNAL RXrdy : STD_LOGIC; |
SIGNAL RXval : STD_LOGIC; |
SIGNAL TXcork : STD_LOGIC; |
SIGNAL TXdat : STD_LOGIC_VECTOR(7 DOWNTO 0); |
SIGNAL TXrdy : STD_LOGIC; |
SIGNAL TXroom : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0); |
SIGNAL TXval : STD_LOGIC; |
SIGNAL USB_rst : STD_LOGIC; |
CONSTANT BUFSIZE_BITS : Integer := 8; |
TYPE outp_mode IS(RECV, SEND); |
SIGNAL clk_60mhz : STD_LOGIC; |
SIGNAL fpga_ready : STD_LOGIC; |
SIGNAL online : STD_LOGIC; |
SIGNAL clk_12MHz : STD_LOGIC; |
SIGNAL clk_60MHz : STD_LOGIC; |
SIGNAL outp_cntl : outp_mode; |
SIGNAL outp_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); |
SIGNAL rst_neg_ext : STD_LOGIC; |
SIGNAL rst_neg_syc : STD_LOGIC; |
SIGNAL usb_Dn : STD_LOGIC := 'L'; |
SIGNAL usb_Dp : STD_LOGIC := 'Z'; -- allow forcing 'H', avoid 'X' |
SIGNAL reset_sync : STD_LOGIC; |
SIGNAL rxdat : STD_LOGIC_VECTOR(7 DOWNTO 0); |
SIGNAL rxlen : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0); |
SIGNAL rxrdy : STD_LOGIC; |
SIGNAL rxval : STD_LOGIC; |
SIGNAL txcork : STD_LOGIC; |
SIGNAL txdat : STD_LOGIC_VECTOR(7 DOWNTO 0); |
SIGNAL txrdy : STD_LOGIC; |
SIGNAL txroom : STD_LOGIC_VECTOR(BUFSIZE_BITS-1 DOWNTO 0); |
SIGNAL txval : STD_LOGIC; |
SIGNAL usb_dn : STD_LOGIC := 'L'; |
SIGNAL usb_dp : STD_LOGIC := 'Z'; -- allow forcing 'H', avoid 'X' |
SIGNAL usb_rst : STD_LOGIC; |
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BEGIN |
|
72,52 → 74,23
clk_60MHz <= '0'; |
WAIT FOR 8000 ps; |
clk_60MHz <= '1'; |
-- WAIT FOR 8667 ps; -- 60 MHz |
WAIT FOR 8393 ps; -- 61 MHz |
WAIT FOR 8667 ps; -- 60 MHz |
-- WAIT FOR 8393 ps; -- 61 MHz |
-- WAIT FOR 8949 ps; -- 59 MHz |
end loop; |
END PROCESS; |
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p_clk_12MHz : PROCESS |
BEGIN |
clk_12MHz <= '0'; |
WAIT FOR 20866 ps; |
clk_12MHz <= '1'; |
WAIT FOR 41600 ps; |
clk_12MHz <= '0'; |
WAIT FOR 20867 ps; |
END PROCESS; |
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p_rst_neg_ext : PROCESS |
BEGIN |
rst_neg_ext <= '0'; |
WAIT FOR 301 ns; |
rst_neg_ext <= '1'; |
WAIT; |
END PROCESS; |
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usb_fs_master : ENTITY work.usb_fs_master |
port map ( |
usb_clk => clk_12MHz, |
int_clk => clk_60MHz, |
PORT MAP ( |
rst_neg_ext => rst_neg_ext, |
usb_Dp => usb_dp, |
usb_Dn => usb_dn, |
RXval => RXval, |
RXdat => RXdat, |
RXrdy => RXrdy, |
RXlen => RXlen, |
TXval => TXval, |
TXdat => TXdat, |
TXrdy => TXrdy, |
TXroom => TXroom, |
TXcork => TXcork |
usb_Dn => usb_dn |
); |
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usb_dp <= 'H' WHEN FPGA_ready ='1' ELSE 'L'; -- connect FPGA_ready to the pullup resistor logic, .... |
usb_dn <= 'L'; -- ... keeping usb_dp='L' during FPGA initialization. |
usb_dp <= 'L' WHEN reset_sync ='1' OR FPGA_ready ='0' ELSE 'H' after 10 ns; |
usb_dn <= 'L'; |
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usb_fs_slave_1 : ENTITY work.usb_fs_slave |
usb_fs_slave_1 : ENTITY work.usb_fs_port |
GENERIC MAP( |
VENDORID => X"FB9A", |
PRODUCTID => X"FB9A", |
127,9 → 100,10
PORT MAP( |
clk => clk_60MHz, -- i |
rst_neg_ext => rst_neg_ext, -- i |
rst_neg_syc => rst_neg_syc, -- o RST_NEG_EXT streched to next clock |
reset_syc => reset_sync, -- o positive active, streched to the next clock |
d_pos => usb_dp, -- io Pos USB data line |
d_neg => usb_dn, -- io Neg USB data line |
d_oe => OPEN, |
USB_rst => USB_rst, -- o USB reset detected (SE0 > 2.5 us) |
online => online, -- o High when the device is in Config state. |
RXval => RXval, -- o High if a received byte available on RXDAT. |
144,5 → 118,42
FPGA_ready => FPGA_ready -- o Connect FPGA_ready to the pullup resistor logic |
); |
|
TXcork <= '0'; -- Don't hold TX transmission |
TXdat <= outp_reg; |
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simple_application : process (clk_60MHz, reset_sync) |
-- returns received bytes with twisted high - and low order nibbles -- |
begin |
if reset_sync ='1' then |
outp_cntl <= RECV; |
outp_reg <= (OTHERS => '0'); |
TXval <= '0'; |
RXrdy <= '0'; |
elsif rising_edge(clk_60MHz) then |
if outp_cntl = RECV then |
TXval <= '0'; |
if RXval = '1' then |
RXrdy <= '0'; |
outp_reg <= RXdat(3 DOWNTO 0) & RXdat(7 DOWNTO 4); |
outp_cntl <= SEND; |
else |
-- RXrdy <= online; |
RXrdy <= '1'; |
outp_cntl <= RECV; |
end if; |
else -- outp_cntl = SEND |
if TXrdy = '1' then |
TXval <= '1'; |
RXrdy <= '1'; |
outp_cntl <= RECV; |
else |
TXval <= '0'; |
RXrdy <= '0'; |
outp_cntl <= SEND; |
end if; |
end if; |
end if; |
end process; |
|
END sim; |
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