URL
https://opencores.org/ocsvn/usb_fpga_1_15/usb_fpga_1_15/trunk
Subversion Repositories usb_fpga_1_15
Compare Revisions
- This comparison shows the changes necessary to convert path
/usb_fpga_1_15/trunk/constraints
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/usb-fpga-2.xdc
0,0 → 1,6
# bitstream settings for all ZTEX Series 2 FPGA Boards |
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] |
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design] |
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 2 [current_design] |
set_property BITSTREAM.GENERAL.COMPRESS true [current_design] |
|
/convert.repl
0,0 → 1,71
PB0/FD0 PB[0] |
PB1/FD1 PB[1] |
PB2/FD2 PB[2] |
PB3/FD3 PB[3] |
PB4/FD4 PB[4] |
PB5/FD5 PB[5] |
PB6/FD6 PB[6] |
PB7/FD7 PB[7] |
|
PD0/FD8 PD[0] |
PD1/FD9 PD[1] |
PD2/FD10 PD[2] |
PD3/FD11 PD[3] |
PD4/FD12 PD[4] |
PD5/FD13 PD[5] |
PD6/FD14 PD[6] |
PD7/FD15 PD[7] |
|
PA0/INT0# PA[0] |
PA1/INT1# PA[1] |
PA2/SLOE PA[2] |
PA3/WU2 PA[3] |
PA4/FIFOADR0 PA[4] |
PA5/FIFOADR1 PA[5] |
PA6/PKTEND PA[6] |
PA7/FLAGD/SLCS# PA[7] |
|
PC0/GPIFADR0 PC[0] |
PC1/GPIFADR1 PC[1] |
PC2/GPIFADR2 PC[2] |
PC3/GPIFADR3 PC[3] |
PC4/GPIFADR4 PC[4] |
PC5/GPIFADR5 PC[5] |
PC6/GPIFADR6 PC[6] |
PC7/GPIFADR7 PC[7] |
|
PE0/T0OUT PE[0] |
PE1/T1OUT PE[1] |
PE2/T2OUT PE[2] |
PE3/RXD0OUT PE[3] |
PE4/RXD1OUT PE[4] |
PE5/INT6 PE[5] |
PE6/T2EX PE[6] |
PE7/GPIFADR8 PE[7] |
|
RDY0/SLRD SLRD |
RDY1/SLWR SLWR |
RDY2 RDY2 |
RDY3 RDY3 |
RDY4 RDY4 |
RDY5 RDY5 |
|
CTL0/FLAGA FLAGA |
CTL1/FLAGB FLAGB |
CTL2/FLAGC FLAGC |
CTL3 CTL3 |
CTL4 CTL4 |
CTL5 CTL5 |
|
INT4 INT4 |
INT5# INT5_N |
|
T0 T0 |
|
SCL SCL |
SDA SDA |
|
RxD0 RxD0 |
TxD0 TxD0 |
RxD1 RxD1 |
TxD1 TxD1 |
/usb-fpga-2.13.repl
0,0 → 1,4
PC4/GPIFADR4 FLASH_DO |
PC5/GPIFADR5 FLASH_CS |
PC6/GPIFADR6 FLASH_CLK |
PC7/GPIFADR7 FLASH_DI |
/convert.sh
0,0 → 1,107
#!/bin/bash |
|
for txt in *.txt; do |
ucf=${txt%*.txt}.ucf |
xdc=${txt%*.txt}.xdc |
tf=${txt%*.txt}.tmp |
|
rm -f $tf |
[ -f "${txt%*.txt}.repl" ] && cp ${txt%*.txt}.repl $tf |
cat convert.repl >> $tf |
|
echo "# !!! Constraint files are application specific !!!" > $ucf |
echo "# !!! This is a template only !!!" >> $ucf |
echo -e "\n# on-board signals\n" >> $ucf |
|
echo "# !!! Constraint files are application specific !!!" > $xdc |
echo "# !!! This is a template only !!!" >> $xdc |
echo -e "\n# on-board signals\n" >> $xdc |
|
|
pa="" |
while read a b c; do |
if [ "$pa" != "" -a "$a" = "" ]; then |
echo >> $ucf |
echo >> $xdc |
fi |
if [ "$a" = "-" ]; then |
if [ "$c" != "" ]; then |
case "$b" in |
"CLKOUT/FXCLK") |
echo "# CLKOUT/FXCLK " >> $ucf |
echo "NET \"fxclk_in\" TNM_NET = \"fxclk_in\";" >> $ucf |
echo "TIMESPEC \"ts_fxclk_in\" = PERIOD \"fxclk_in\" 48 MHz HIGH 50 %;" >> $ucf |
echo "NET \"fxclk_in\" LOC = \"$c\" | IOSTANDARD = LVCMOS33 ;" >> $ucf |
|
echo "# CLKOUT/FXCLK " >> $xdc |
echo "create_clock -name fxclk_in -period 20.833 [get_ports fxclk_in]" >> $xdc |
echo "set_property PACKAGE_PIN $c [get_ports fxclk_in]" >> $xdc |
echo "set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]" >> $xdc |
;; |
"IFCLK") |
echo "# IFCLK " >> $ucf |
echo "NET \"ifclk_in\" TNM_NET = \"ifclk_in\";" >> $ucf |
echo "TIMESPEC \"ts_ifclk_in\" = PERIOD \"ifclk_in\" 48 MHz HIGH 50 %;" >> $ucf |
echo "NET \"ifclk_in\" LOC = \"$c\" | IOSTANDARD = LVCMOS33 ;" >> $ucf |
|
echo "# IFCLK " >> $xdc |
echo "create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in]" >> $xdc |
echo "set_property PACKAGE_PIN $c [get_ports ifclk_in]" >> $xdc |
echo "set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]" >> $xdc |
;; |
*) |
b2=`echo "$b" | tr -d "*" ` |
c2=`grep -i -m 1 -x "$b2.*" $tf | ( read a b c; echo $b )` |
if [ "$c2" != "" ]; then |
echo "NET \"$c2\" LOC = \"$c\" | IOSTANDARD = LVCMOS33 ; # $b2" | tr "[]" "<>" >> $ucf |
|
# echo -e "\n# $b2" >> $xdc |
# echo "set_property PACKAGE_PIN $c [get_ports {$c2}]" >> $xdc |
echo -e "\nset_property PACKAGE_PIN $c [get_ports {$c2}] ;# $b2" >> $xdc |
echo "set_property IOSTANDARD LVCMOS33 [get_ports {$c2}]" >> $xdc |
else |
echo "Unknown signal: $b" >&2 |
echo "$b" >> convert.unknown |
fi |
;; |
esac |
fi |
pa=$a |
else |
pa="" |
fi |
done < $txt |
|
echo -e "\n# external I/O\n" >> $ucf |
echo -e "\n\n# external I/O" >> $xdc |
|
rm -f $tf |
pa="" |
while read a b c; do |
if [ "$a" != "-" -a "$c" != "" ]; then |
echo "$a $c $a / $b" >> $tf |
fi |
done < $txt |
|
pa="A" |
cnt=0 |
sort -V $tf | while read a b c; do |
a0=${a:0:1} |
if [ "$a0" != "$pa" ]; then |
cnt=0 |
echo >> $ucf |
echo >> $xdc |
fi |
echo "NET \"IO_$a0<$cnt>\" LOC = \"$b\" | IOSTANDARD = LVCMOS33 ; # $c" >> $ucf |
|
# echo -e "\n# $c" >> $xdc |
# echo "set_property PACKAGE_PIN $b [get_ports {IO_$a0[$cnt]}]" >> $xdc |
echo -e "\nset_property PACKAGE_PIN $b [get_ports {IO_$a0[$cnt]}] ;# $c" >> $xdc |
echo "set_property IOSTANDARD LVCMOS33 [get_ports {IO_$a0[$cnt]}]" >> $xdc |
|
let "cnt+=1" |
pa=$a0 |
done |
|
rm -f $tf |
done |
convert.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: usb-fpga-2.16.repl
===================================================================
--- usb-fpga-2.16.repl (nonexistent)
+++ usb-fpga-2.16.repl (revision 4)
@@ -0,0 +1,4 @@
+PC4/GPIFADR4 FLASH_DO
+PC5/GPIFADR5 FLASH_CS
+PC6/GPIFADR6 FLASH_CLK
+PC7/GPIFADR7 FLASH_DI
Index: usb-fpga-2.01.ucf
===================================================================
--- usb-fpga-2.01.ucf (nonexistent)
+++ usb-fpga-2.01.ucf (revision 4)
@@ -0,0 +1,182 @@
+# !!! Constraint files are application specific !!!
+# !!! This is a template only !!!
+
+# on-board signals
+
+# CLKOUT/FXCLK
+NET "fxclk_in" TNM_NET = "fxclk_in";
+TIMESPEC "ts_fxclk_in" = PERIOD "fxclk_in" 48 MHz HIGH 50 %;
+NET "fxclk_in" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
+
+# IFCLK
+NET "ifclk_in" TNM_NET = "ifclk_in";
+TIMESPEC "ts_ifclk_in" = PERIOD "ifclk_in" 48 MHz HIGH 50 %;
+NET "ifclk_in" LOC = "T8" | IOSTANDARD = LVCMOS33 ;
+
+NET "PB<0>" LOC = "T9" | IOSTANDARD = LVCMOS33 ; # PB0/FD0
+NET "PB<1>" LOC = "R9" | IOSTANDARD = LVCMOS33 ; # PB1/FD1
+NET "PB<2>" LOC = "P9" | IOSTANDARD = LVCMOS33 ; # PB2/FD2
+NET "PB<3>" LOC = "N9" | IOSTANDARD = LVCMOS33 ; # PB3/FD3
+NET "PB<4>" LOC = "M10" | IOSTANDARD = LVCMOS33 ; # PB4/FD4
+NET "PB<5>" LOC = "P11" | IOSTANDARD = LVCMOS33 ; # PB5/FD5
+NET "PB<6>" LOC = "M11" | IOSTANDARD = LVCMOS33 ; # PB6/FD6
+NET "PB<7>" LOC = "M12" | IOSTANDARD = LVCMOS33 ; # PB7/FD7
+
+NET "PD<0>" LOC = "P8" | IOSTANDARD = LVCMOS33 ; # PD0/FD8
+NET "PD<1>" LOC = "M7" | IOSTANDARD = LVCMOS33 ; # PD1/FD9
+NET "PD<2>" LOC = "P7" | IOSTANDARD = LVCMOS33 ; # PD2/FD10
+NET "PD<3>" LOC = "R7" | IOSTANDARD = LVCMOS33 ; # PD3/FD11
+NET "PD<4>" LOC = "M6" | IOSTANDARD = LVCMOS33 ; # PD4/FD12
+NET "PD<5>" LOC = "N6" | IOSTANDARD = LVCMOS33 ; # PD5/FD13
+NET "PD<6>" LOC = "P6" | IOSTANDARD = LVCMOS33 ; # PD6/FD14
+NET "PD<7>" LOC = "T6" | IOSTANDARD = LVCMOS33 ; # PD7/FD15
+
+NET "PA<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 ; # PA0/INT0#
+NET "PA<1>" LOC = "T10" | IOSTANDARD = LVCMOS33 ; # PA1/INT1#
+NET "PA<2>" LOC = "B10" | IOSTANDARD = LVCMOS33 ; # PA2/SLOE
+NET "PA<3>" LOC = "T3" | IOSTANDARD = LVCMOS33 ; # PA3/WU2
+NET "PA<4>" LOC = "T11" | IOSTANDARD = LVCMOS33 ; # PA4/FIFOADR0
+NET "PA<5>" LOC = "N11" | IOSTANDARD = LVCMOS33 ; # PA5/FIFOADR1
+NET "PA<6>" LOC = "T5" | IOSTANDARD = LVCMOS33 ; # PA6/PKTEND
+NET "PA<7>" LOC = "R3" | IOSTANDARD = LVCMOS33 ; # PA7/FLAGD/SLCS#
+
+NET "PC<0>" LOC = "P10" | IOSTANDARD = LVCMOS33 ; # PC0/GPIFADR0
+NET "PC<1>" LOC = "N12" | IOSTANDARD = LVCMOS33 ; # PC1/GPIFADR1
+NET "PC<2>" LOC = "P12" | IOSTANDARD = LVCMOS33 ; # PC2/GPIFADR2
+NET "PC<3>" LOC = "N5" | IOSTANDARD = LVCMOS33 ; # PC3/GPIFADR3
+NET "PC<4>" LOC = "P5" | IOSTANDARD = LVCMOS33 ; # PC4/GPIFADR4
+NET "PC<5>" LOC = "L8" | IOSTANDARD = LVCMOS33 ; # PC5/GPIFADR5
+NET "PC<6>" LOC = "L7" | IOSTANDARD = LVCMOS33 ; # PC6/GPIFADR6
+NET "PC<7>" LOC = "R5" | IOSTANDARD = LVCMOS33 ; # PC7/GPIFADR7
+
+NET "PE<0>" LOC = "A8" | IOSTANDARD = LVCMOS33 ; # PE0/T0OUT
+NET "PE<1>" LOC = "B8" | IOSTANDARD = LVCMOS33 ; # PE1/T1OUT
+NET "PE<2>" LOC = "A7" | IOSTANDARD = LVCMOS33 ; # PE2/T2OUT
+NET "PE<3>" LOC = "A6" | IOSTANDARD = LVCMOS33 ; # PE3/RXD0OUT
+NET "PE<4>" LOC = "B6" | IOSTANDARD = LVCMOS33 ; # PE4/RXD1OUT
+NET "PE<5>" LOC = "A5" | IOSTANDARD = LVCMOS33 ; # PE5/INT6
+
+NET "SLRD" LOC = "T4" | IOSTANDARD = LVCMOS33 ; # RDY0/SLRD
+NET "SLWR" LOC = "P4" | IOSTANDARD = LVCMOS33 ; # RDY1/SLWR
+NET "RDY2" LOC = "A4" | IOSTANDARD = LVCMOS33 ; # RDY2
+
+NET "FLAGA" LOC = "L10" | IOSTANDARD = LVCMOS33 ; # CTL0/FLAGA
+NET "FLAGB" LOC = "M9" | IOSTANDARD = LVCMOS33 ; # CTL1/FLAGB
+NET "FLAGC" LOC = "N8" | IOSTANDARD = LVCMOS33 ; # CTL2/FLAGC
+NET "CTL3" LOC = "A10" | IOSTANDARD = LVCMOS33 ; # CTL3
+
+NET "INT4" LOC = "A11" | IOSTANDARD = LVCMOS33 ; # INT4
+NET "INT5_N" LOC = "A9" | IOSTANDARD = LVCMOS33 ; # INT5#
+NET "T0" LOC = "B12" | IOSTANDARD = LVCMOS33 ; # T0
+
+NET "SCL" LOC = "A12" | IOSTANDARD = LVCMOS33 ; # SCL
+NET "SDA" LOC = "A13" | IOSTANDARD = LVCMOS33 ; # SDA
+
+NET "RxD0" LOC = "A14" | IOSTANDARD = LVCMOS33 ; # RxD0
+NET "TxD0" LOC = "B14" | IOSTANDARD = LVCMOS33 ; # TxD0
+
+# external I/O
+
+NET "IO_A<0>" LOC = "T12" | IOSTANDARD = LVCMOS33 ; # A3 / T12~IO_L52N_M1DQ15_1
+NET "IO_A<1>" LOC = "T14" | IOSTANDARD = LVCMOS33 ; # A4 / T14~IO_L51P_M1DQ12_1
+NET "IO_A<2>" LOC = "T15" | IOSTANDARD = LVCMOS33 ; # A5 / T15~IO_L50N_M1UDQSN_1
+NET "IO_A<3>" LOC = "R16" | IOSTANDARD = LVCMOS33 ; # A6 / R16~IO_L49N_M1DQ11_1
+NET "IO_A<4>" LOC = "P16" | IOSTANDARD = LVCMOS33 ; # A7 / P16~IO_L48N_M1DQ9_1
+NET "IO_A<5>" LOC = "N16" | IOSTANDARD = LVCMOS33 ; # A8 / N16~IO_L45N_A0_M1LDQSN_1
+NET "IO_A<6>" LOC = "M16" | IOSTANDARD = LVCMOS33 ; # A9 / M16~IO_L46N_FOE_B_M1DQ3_1
+NET "IO_A<7>" LOC = "L13" | IOSTANDARD = LVCMOS33 ; # A10 / L13~IO_L53N_VREF_1
+NET "IO_A<8>" LOC = "L16" | IOSTANDARD = LVCMOS33 ; # A11 / L16~IO_L47N_LDC_M1DQ1_1
+NET "IO_A<9>" LOC = "M13" | IOSTANDARD = LVCMOS33 ; # A12 / M13~IO_L74P_AWAKE_1
+NET "IO_A<10>" LOC = "K16" | IOSTANDARD = LVCMOS33 ; # A13 / K16~IO_L44N_A2_M1DQ7_1
+NET "IO_A<11>" LOC = "K14" | IOSTANDARD = LVCMOS33 ; # A14 / K14~IO_L41N_GCLK8_M1CASN_1
+NET "IO_A<12>" LOC = "J16" | IOSTANDARD = LVCMOS33 ; # A18 / J16~IO_L43N_GCLK4_M1DQ5_1
+NET "IO_A<13>" LOC = "H16" | IOSTANDARD = LVCMOS33 ; # A19 / H16~IO_L37N_A6_M1A1_1
+NET "IO_A<14>" LOC = "J12" | IOSTANDARD = LVCMOS33 ; # A20 / J12~IO_L40N_GCLK10_M1A6_1
+NET "IO_A<15>" LOC = "H14" | IOSTANDARD = LVCMOS33 ; # A21 / H14~IO_L39N_M1ODT_1
+NET "IO_A<16>" LOC = "G16" | IOSTANDARD = LVCMOS33 ; # A22 / G16~IO_L36N_A8_M1BA1_1
+NET "IO_A<17>" LOC = "F12" | IOSTANDARD = LVCMOS33 ; # A23 / F12~IO_L30P_A21_M1RESET_1
+NET "IO_A<18>" LOC = "F16" | IOSTANDARD = LVCMOS33 ; # A24 / F16~IO_L35N_A10_M1A2_1
+NET "IO_A<19>" LOC = "F14" | IOSTANDARD = LVCMOS33 ; # A25 / F14~IO_L32N_A16_M1A9_1
+NET "IO_A<20>" LOC = "E16" | IOSTANDARD = LVCMOS33 ; # A26 / E16~IO_L34N_A12_M1BA2_1
+NET "IO_A<21>" LOC = "E13" | IOSTANDARD = LVCMOS33 ; # A27 / E13~IO_L1P_A25_1
+NET "IO_A<22>" LOC = "D16" | IOSTANDARD = LVCMOS33 ; # A28 / D16~IO_L31N_A18_M1A12_1
+NET "IO_A<23>" LOC = "C16" | IOSTANDARD = LVCMOS33 ; # A29 / C16~IO_L33N_A14_M1A4_1
+NET "IO_A<24>" LOC = "B16" | IOSTANDARD = LVCMOS33 ; # A30 / B16~IO_L29N_A22_M1A14_1
+
+NET "IO_B<0>" LOC = "R12" | IOSTANDARD = LVCMOS33 ; # B3 / R12~IO_L52P_M1DQ14_1
+NET "IO_B<1>" LOC = "T13" | IOSTANDARD = LVCMOS33 ; # B4 / T13~IO_L51N_M1DQ13_1
+NET "IO_B<2>" LOC = "R14" | IOSTANDARD = LVCMOS33 ; # B5 / R14~IO_L50P_M1UDQS_1
+NET "IO_B<3>" LOC = "R15" | IOSTANDARD = LVCMOS33 ; # B6 / R15~IO_L49P_M1DQ10_1
+NET "IO_B<4>" LOC = "P15" | IOSTANDARD = LVCMOS33 ; # B7 / P15~IO_L48P_HDC_M1DQ8_1
+NET "IO_B<5>" LOC = "N14" | IOSTANDARD = LVCMOS33 ; # B8 / N14~IO_L45P_A1_M1LDQS_1
+NET "IO_B<6>" LOC = "M15" | IOSTANDARD = LVCMOS33 ; # B9 / M15~IO_L46P_FCS_B_M1DQ2_1
+NET "IO_B<7>" LOC = "L12" | IOSTANDARD = LVCMOS33 ; # B10 / L12~IO_L53P_1
+NET "IO_B<8>" LOC = "L14" | IOSTANDARD = LVCMOS33 ; # B11 / L14~IO_L47P_FWE_B_M1DQ0_1
+NET "IO_B<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 ; # B12 / K12~IO_L42P_GCLK7_M1UDM_1
+NET "IO_B<10>" LOC = "K15" | IOSTANDARD = LVCMOS33 ; # B13 / K15~IO_L44P_A3_M1DQ6_1
+NET "IO_B<11>" LOC = "J13" | IOSTANDARD = LVCMOS33 ; # B14 / J13~IO_L41P_GCLK9_IRDY1_M1RASN_1
+NET "IO_B<12>" LOC = "J14" | IOSTANDARD = LVCMOS33 ; # B18 / J14~IO_L43P_GCLK5_M1DQ4_1
+NET "IO_B<13>" LOC = "H15" | IOSTANDARD = LVCMOS33 ; # B19 / H15~IO_L37P_A7_M1A0_1
+NET "IO_B<14>" LOC = "G12" | IOSTANDARD = LVCMOS33 ; # B20 / G12~IO_L38P_A5_M1CLK_1
+NET "IO_B<15>" LOC = "H13" | IOSTANDARD = LVCMOS33 ; # B21 / H13~IO_L39P_M1A3_1
+NET "IO_B<16>" LOC = "G14" | IOSTANDARD = LVCMOS33 ; # B22 / G14~IO_L36P_A9_M1BA0_1
+NET "IO_B<17>" LOC = "G11" | IOSTANDARD = LVCMOS33 ; # B23 / G11~IO_L30N_A20_M1A11_1
+NET "IO_B<18>" LOC = "F15" | IOSTANDARD = LVCMOS33 ; # B24 / F15~IO_L35P_A11_M1A7_1
+NET "IO_B<19>" LOC = "F13" | IOSTANDARD = LVCMOS33 ; # B25 / F13~IO_L32P_A17_M1A8_1
+NET "IO_B<20>" LOC = "E15" | IOSTANDARD = LVCMOS33 ; # B26 / E15~IO_L34P_A13_M1WE_1
+NET "IO_B<21>" LOC = "E12" | IOSTANDARD = LVCMOS33 ; # B27 / E12~IO_L1N_A24_VREF_1
+NET "IO_B<22>" LOC = "D14" | IOSTANDARD = LVCMOS33 ; # B28 / D14~IO_L31P_A19_M1CKE_1
+NET "IO_B<23>" LOC = "C15" | IOSTANDARD = LVCMOS33 ; # B29 / C15~IO_L33P_A15_M1A10_1
+NET "IO_B<24>" LOC = "B15" | IOSTANDARD = LVCMOS33 ; # B30 / B15~IO_L29P_A23_M1A13_1
+
+NET "IO_C<0>" LOC = "R2" | IOSTANDARD = LVCMOS33 ; # C3 / R2~IO_L32P_M3DQ14_3
+NET "IO_C<1>" LOC = "P2" | IOSTANDARD = LVCMOS33 ; # C4 / P2~IO_L33P_M3DQ12_3
+NET "IO_C<2>" LOC = "N3" | IOSTANDARD = LVCMOS33 ; # C5 / N3~IO_L34P_M3UDQS_3
+NET "IO_C<3>" LOC = "M5" | IOSTANDARD = LVCMOS33 ; # C6 / M5~IO_L2P_3
+NET "IO_C<4>" LOC = "M4" | IOSTANDARD = LVCMOS33 ; # C7 / M4~IO_L1P_3
+NET "IO_C<5>" LOC = "M2" | IOSTANDARD = LVCMOS33 ; # C8 / M2~IO_L35P_M3DQ10_3
+NET "IO_C<6>" LOC = "L5" | IOSTANDARD = LVCMOS33 ; # C9 / L5~IO_L45N_M3ODT_3
+NET "IO_C<7>" LOC = "L3" | IOSTANDARD = LVCMOS33 ; # C10 / L3~IO_L36P_M3DQ8_3
+NET "IO_C<8>" LOC = "K2" | IOSTANDARD = LVCMOS33 ; # C11 / K2~IO_L37P_M3DQ0_3
+NET "IO_C<9>" LOC = "J4" | IOSTANDARD = LVCMOS33 ; # C12 / J4~IO_L42N_GCLK24_M3LDM_3
+NET "IO_C<10>" LOC = "J3" | IOSTANDARD = LVCMOS33 ; # C13 / J3~IO_L38P_M3DQ2_3
+NET "IO_C<11>" LOC = "H5" | IOSTANDARD = LVCMOS33 ; # C14 / H5~IO_L43N_GCLK22_IRDY2_M3CASN_3
+NET "IO_C<12>" LOC = "H4" | IOSTANDARD = LVCMOS33 ; # C15 / H4~IO_L44P_GCLK21_M3A5_3
+NET "IO_C<13>" LOC = "H2" | IOSTANDARD = LVCMOS33 ; # C19 / H2~IO_L39P_M3LDQS_3
+NET "IO_C<14>" LOC = "G3" | IOSTANDARD = LVCMOS33 ; # C20 / G3~IO_L40P_M3DQ6_3
+NET "IO_C<15>" LOC = "F5" | IOSTANDARD = LVCMOS33 ; # C21 / F5~IO_L55N_M3A14_3
+NET "IO_C<16>" LOC = "F2" | IOSTANDARD = LVCMOS33 ; # C22 / F2~IO_L41P_GCLK27_M3DQ4_3
+NET "IO_C<17>" LOC = "F4" | IOSTANDARD = LVCMOS33 ; # C23 / F4~IO_L53P_M3CKE_3
+NET "IO_C<18>" LOC = "E2" | IOSTANDARD = LVCMOS33 ; # C24 / E2~IO_L46P_M3CLK_3
+NET "IO_C<19>" LOC = "E4" | IOSTANDARD = LVCMOS33 ; # C25 / E4~IO_L54P_M3RESET_3
+NET "IO_C<20>" LOC = "D3" | IOSTANDARD = LVCMOS33 ; # C26 / D3~IO_L49P_M3A7_3
+NET "IO_C<21>" LOC = "C3" | IOSTANDARD = LVCMOS33 ; # C27 / C3~IO_L48P_M3BA0_3
+NET "IO_C<22>" LOC = "C1" | IOSTANDARD = LVCMOS33 ; # C28 / C1~IO_L50P_M3WE_3
+NET "IO_C<23>" LOC = "B3" | IOSTANDARD = LVCMOS33 ; # C29 / B3~IO_L83P_3
+NET "IO_C<24>" LOC = "A3" | IOSTANDARD = LVCMOS33 ; # C30 / A3~IO_L83N_VREF_3
+
+NET "IO_D<0>" LOC = "R1" | IOSTANDARD = LVCMOS33 ; # D3 / R1~IO_L32N_M3DQ15_3
+NET "IO_D<1>" LOC = "P1" | IOSTANDARD = LVCMOS33 ; # D4 / P1~IO_L33N_M3DQ13_3
+NET "IO_D<2>" LOC = "N1" | IOSTANDARD = LVCMOS33 ; # D5 / N1~IO_L34N_M3UDQSN_3
+NET "IO_D<3>" LOC = "N4" | IOSTANDARD = LVCMOS33 ; # D6 / N4~IO_L2N_3
+NET "IO_D<4>" LOC = "M3" | IOSTANDARD = LVCMOS33 ; # D7 / M3~IO_L1N_VREF_3
+NET "IO_D<5>" LOC = "M1" | IOSTANDARD = LVCMOS33 ; # D8 / M1~IO_L35N_M3DQ11_3
+NET "IO_D<6>" LOC = "L4" | IOSTANDARD = LVCMOS33 ; # D9 / L4~IO_L45P_M3A3_3
+NET "IO_D<7>" LOC = "L1" | IOSTANDARD = LVCMOS33 ; # D10 / L1~IO_L36N_M3DQ9_3
+NET "IO_D<8>" LOC = "K1" | IOSTANDARD = LVCMOS33 ; # D11 / K1~IO_L37N_M3DQ1_3
+NET "IO_D<9>" LOC = "K3" | IOSTANDARD = LVCMOS33 ; # D12 / K3~IO_L42P_GCLK25_TRDY2_M3UDM_3
+NET "IO_D<10>" LOC = "J1" | IOSTANDARD = LVCMOS33 ; # D13 / J1~IO_L38N_M3DQ3_3
+NET "IO_D<11>" LOC = "K5" | IOSTANDARD = LVCMOS33 ; # D14 / K5~IO_L47P_M3A0_3
+NET "IO_D<12>" LOC = "H3" | IOSTANDARD = LVCMOS33 ; # D15 / H3~IO_L44N_GCLK20_M3A6_3
+NET "IO_D<13>" LOC = "H1" | IOSTANDARD = LVCMOS33 ; # D19 / H1~IO_L39N_M3LDQSN_3
+NET "IO_D<14>" LOC = "G1" | IOSTANDARD = LVCMOS33 ; # D20 / G1~IO_L40N_M3DQ7_3
+NET "IO_D<15>" LOC = "G5" | IOSTANDARD = LVCMOS33 ; # D21 / G5~IO_L51N_M3A4_3
+NET "IO_D<16>" LOC = "F1" | IOSTANDARD = LVCMOS33 ; # D22 / F1~IO_L41N_GCLK26_M3DQ5_3
+NET "IO_D<17>" LOC = "F3" | IOSTANDARD = LVCMOS33 ; # D23 / F3~IO_L53N_M3A12_3
+NET "IO_D<18>" LOC = "E1" | IOSTANDARD = LVCMOS33 ; # D24 / E1~IO_L46N_M3CLKN_3
+NET "IO_D<19>" LOC = "E3" | IOSTANDARD = LVCMOS33 ; # D25 / E3~IO_L54N_M3A11_3
+NET "IO_D<20>" LOC = "D1" | IOSTANDARD = LVCMOS33 ; # D26 / D1~IO_L49N_M3A2_3
+NET "IO_D<21>" LOC = "C2" | IOSTANDARD = LVCMOS33 ; # D27 / C2~IO_L48N_M3BA1_3
+NET "IO_D<22>" LOC = "B1" | IOSTANDARD = LVCMOS33 ; # D28 / B1~IO_L50N_M3BA2_3
+NET "IO_D<23>" LOC = "B2" | IOSTANDARD = LVCMOS33 ; # D29 / B2~IO_L52P_M3A8_3
+NET "IO_D<24>" LOC = "A2" | IOSTANDARD = LVCMOS33 ; # D30 / A2~IO_L52N_M3A9_3
Index: usb-fpga-2.01.xdc
===================================================================
--- usb-fpga-2.01.xdc (nonexistent)
+++ usb-fpga-2.01.xdc (revision 4)
@@ -0,0 +1,486 @@
+# !!! Constraint files are application specific !!!
+# !!! This is a template only !!!
+
+# on-board signals
+
+# CLKOUT/FXCLK
+create_clock -name fxclk_in -period 20.833 [get_ports fxclk_in]
+set_property PACKAGE_PIN T7 [get_ports fxclk_in]
+set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in]
+
+# IFCLK
+create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in]
+set_property PACKAGE_PIN T8 [get_ports ifclk_in]
+set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]
+
+
+set_property PACKAGE_PIN T9 [get_ports {PB[0]}] ;# PB0/FD0
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[0]}]
+
+set_property PACKAGE_PIN R9 [get_ports {PB[1]}] ;# PB1/FD1
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[1]}]
+
+set_property PACKAGE_PIN P9 [get_ports {PB[2]}] ;# PB2/FD2
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[2]}]
+
+set_property PACKAGE_PIN N9 [get_ports {PB[3]}] ;# PB3/FD3
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[3]}]
+
+set_property PACKAGE_PIN M10 [get_ports {PB[4]}] ;# PB4/FD4
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[4]}]
+
+set_property PACKAGE_PIN P11 [get_ports {PB[5]}] ;# PB5/FD5
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[5]}]
+
+set_property PACKAGE_PIN M11 [get_ports {PB[6]}] ;# PB6/FD6
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[6]}]
+
+set_property PACKAGE_PIN M12 [get_ports {PB[7]}] ;# PB7/FD7
+set_property IOSTANDARD LVCMOS33 [get_ports {PB[7]}]
+
+
+set_property PACKAGE_PIN P8 [get_ports {PD[0]}] ;# PD0/FD8
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[0]}]
+
+set_property PACKAGE_PIN M7 [get_ports {PD[1]}] ;# PD1/FD9
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[1]}]
+
+set_property PACKAGE_PIN P7 [get_ports {PD[2]}] ;# PD2/FD10
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[2]}]
+
+set_property PACKAGE_PIN R7 [get_ports {PD[3]}] ;# PD3/FD11
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[3]}]
+
+set_property PACKAGE_PIN M6 [get_ports {PD[4]}] ;# PD4/FD12
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[4]}]
+
+set_property PACKAGE_PIN N6 [get_ports {PD[5]}] ;# PD5/FD13
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[5]}]
+
+set_property PACKAGE_PIN P6 [get_ports {PD[6]}] ;# PD6/FD14
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[6]}]
+
+set_property PACKAGE_PIN T6 [get_ports {PD[7]}] ;# PD7/FD15
+set_property IOSTANDARD LVCMOS33 [get_ports {PD[7]}]
+
+
+set_property PACKAGE_PIN R11 [get_ports {PA[0]}] ;# PA0/INT0#
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}]
+
+set_property PACKAGE_PIN T10 [get_ports {PA[1]}] ;# PA1/INT1#
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}]
+
+set_property PACKAGE_PIN B10 [get_ports {PA[2]}] ;# PA2/SLOE
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}]
+
+set_property PACKAGE_PIN T3 [get_ports {PA[3]}] ;# PA3/WU2
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}]
+
+set_property PACKAGE_PIN T11 [get_ports {PA[4]}] ;# PA4/FIFOADR0
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}]
+
+set_property PACKAGE_PIN N11 [get_ports {PA[5]}] ;# PA5/FIFOADR1
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}]
+
+set_property PACKAGE_PIN T5 [get_ports {PA[6]}] ;# PA6/PKTEND
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}]
+
+set_property PACKAGE_PIN R3 [get_ports {PA[7]}] ;# PA7/FLAGD/SLCS#
+set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}]
+
+
+set_property PACKAGE_PIN P10 [get_ports {PC[0]}] ;# PC0/GPIFADR0
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
+
+set_property PACKAGE_PIN N12 [get_ports {PC[1]}] ;# PC1/GPIFADR1
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
+
+set_property PACKAGE_PIN P12 [get_ports {PC[2]}] ;# PC2/GPIFADR2
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[2]}]
+
+set_property PACKAGE_PIN N5 [get_ports {PC[3]}] ;# PC3/GPIFADR3
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[3]}]
+
+set_property PACKAGE_PIN P5 [get_ports {PC[4]}] ;# PC4/GPIFADR4
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[4]}]
+
+set_property PACKAGE_PIN L8 [get_ports {PC[5]}] ;# PC5/GPIFADR5
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[5]}]
+
+set_property PACKAGE_PIN L7 [get_ports {PC[6]}] ;# PC6/GPIFADR6
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[6]}]
+
+set_property PACKAGE_PIN R5 [get_ports {PC[7]}] ;# PC7/GPIFADR7
+set_property IOSTANDARD LVCMOS33 [get_ports {PC[7]}]
+
+
+set_property PACKAGE_PIN A8 [get_ports {PE[0]}] ;# PE0/T0OUT
+set_property IOSTANDARD LVCMOS33 [get_ports {PE[0]}]
+
+set_property PACKAGE_PIN B8 [get_ports {PE[1]}] ;# PE1/T1OUT
+set_property IOSTANDARD LVCMOS33 [get_ports {PE[1]}]
+
+set_property PACKAGE_PIN A7 [get_ports {PE[2]}] ;# PE2/T2OUT
+set_property IOSTANDARD LVCMOS33 [get_ports {PE[2]}]
+
+set_property PACKAGE_PIN A6 [get_ports {PE[3]}] ;# PE3/RXD0OUT
+set_property IOSTANDARD LVCMOS33 [get_ports {PE[3]}]
+
+set_property PACKAGE_PIN B6 [get_ports {PE[4]}] ;# PE4/RXD1OUT
+set_property IOSTANDARD LVCMOS33 [get_ports {PE[4]}]
+
+set_property PACKAGE_PIN A5 [get_ports {PE[5]}] ;# PE5/INT6
+set_property IOSTANDARD LVCMOS33 [get_ports {PE[5]}]
+
+
+set_property PACKAGE_PIN T4 [get_ports {SLRD}] ;# RDY0/SLRD
+set_property IOSTANDARD LVCMOS33 [get_ports {SLRD}]
+
+set_property PACKAGE_PIN P4 [get_ports {SLWR}] ;# RDY1/SLWR
+set_property IOSTANDARD LVCMOS33 [get_ports {SLWR}]
+
+set_property PACKAGE_PIN A4 [get_ports {RDY2}] ;# RDY2
+set_property IOSTANDARD LVCMOS33 [get_ports {RDY2}]
+
+
+set_property PACKAGE_PIN L10 [get_ports {FLAGA}] ;# CTL0/FLAGA
+set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}]
+
+set_property PACKAGE_PIN M9 [get_ports {FLAGB}] ;# CTL1/FLAGB
+set_property IOSTANDARD LVCMOS33 [get_ports {FLAGB}]
+
+set_property PACKAGE_PIN N8 [get_ports {FLAGC}] ;# CTL2/FLAGC
+set_property IOSTANDARD LVCMOS33 [get_ports {FLAGC}]
+
+set_property PACKAGE_PIN A10 [get_ports {CTL3}] ;# CTL3
+set_property IOSTANDARD LVCMOS33 [get_ports {CTL3}]
+
+
+set_property PACKAGE_PIN A11 [get_ports {INT4}] ;# INT4
+set_property IOSTANDARD LVCMOS33 [get_ports {INT4}]
+
+set_property PACKAGE_PIN A9 [get_ports {INT5_N}] ;# INT5#
+set_property IOSTANDARD LVCMOS33 [get_ports {INT5_N}]
+
+set_property PACKAGE_PIN B12 [get_ports {T0}] ;# T0
+set_property IOSTANDARD LVCMOS33 [get_ports {T0}]
+
+
+set_property PACKAGE_PIN A12 [get_ports {SCL}] ;# SCL
+set_property IOSTANDARD LVCMOS33 [get_ports {SCL}]
+
+set_property PACKAGE_PIN A13 [get_ports {SDA}] ;# SDA
+set_property IOSTANDARD LVCMOS33 [get_ports {SDA}]
+
+
+set_property PACKAGE_PIN A14 [get_ports {RxD0}] ;# RxD0
+set_property IOSTANDARD LVCMOS33 [get_ports {RxD0}]
+
+set_property PACKAGE_PIN B14 [get_ports {TxD0}] ;# TxD0
+set_property IOSTANDARD LVCMOS33 [get_ports {TxD0}]
+
+
+# external I/O
+
+set_property PACKAGE_PIN T12 [get_ports {IO_A[0]}] ;# A3 / T12~IO_L52N_M1DQ15_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[0]}]
+
+set_property PACKAGE_PIN T14 [get_ports {IO_A[1]}] ;# A4 / T14~IO_L51P_M1DQ12_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[1]}]
+
+set_property PACKAGE_PIN T15 [get_ports {IO_A[2]}] ;# A5 / T15~IO_L50N_M1UDQSN_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[2]}]
+
+set_property PACKAGE_PIN R16 [get_ports {IO_A[3]}] ;# A6 / R16~IO_L49N_M1DQ11_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[3]}]
+
+set_property PACKAGE_PIN P16 [get_ports {IO_A[4]}] ;# A7 / P16~IO_L48N_M1DQ9_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[4]}]
+
+set_property PACKAGE_PIN N16 [get_ports {IO_A[5]}] ;# A8 / N16~IO_L45N_A0_M1LDQSN_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[5]}]
+
+set_property PACKAGE_PIN M16 [get_ports {IO_A[6]}] ;# A9 / M16~IO_L46N_FOE_B_M1DQ3_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[6]}]
+
+set_property PACKAGE_PIN L13 [get_ports {IO_A[7]}] ;# A10 / L13~IO_L53N_VREF_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[7]}]
+
+set_property PACKAGE_PIN L16 [get_ports {IO_A[8]}] ;# A11 / L16~IO_L47N_LDC_M1DQ1_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[8]}]
+
+set_property PACKAGE_PIN M13 [get_ports {IO_A[9]}] ;# A12 / M13~IO_L74P_AWAKE_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[9]}]
+
+set_property PACKAGE_PIN K16 [get_ports {IO_A[10]}] ;# A13 / K16~IO_L44N_A2_M1DQ7_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[10]}]
+
+set_property PACKAGE_PIN K14 [get_ports {IO_A[11]}] ;# A14 / K14~IO_L41N_GCLK8_M1CASN_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[11]}]
+
+set_property PACKAGE_PIN J16 [get_ports {IO_A[12]}] ;# A18 / J16~IO_L43N_GCLK4_M1DQ5_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[12]}]
+
+set_property PACKAGE_PIN H16 [get_ports {IO_A[13]}] ;# A19 / H16~IO_L37N_A6_M1A1_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[13]}]
+
+set_property PACKAGE_PIN J12 [get_ports {IO_A[14]}] ;# A20 / J12~IO_L40N_GCLK10_M1A6_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[14]}]
+
+set_property PACKAGE_PIN H14 [get_ports {IO_A[15]}] ;# A21 / H14~IO_L39N_M1ODT_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[15]}]
+
+set_property PACKAGE_PIN G16 [get_ports {IO_A[16]}] ;# A22 / G16~IO_L36N_A8_M1BA1_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[16]}]
+
+set_property PACKAGE_PIN F12 [get_ports {IO_A[17]}] ;# A23 / F12~IO_L30P_A21_M1RESET_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[17]}]
+
+set_property PACKAGE_PIN F16 [get_ports {IO_A[18]}] ;# A24 / F16~IO_L35N_A10_M1A2_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[18]}]
+
+set_property PACKAGE_PIN F14 [get_ports {IO_A[19]}] ;# A25 / F14~IO_L32N_A16_M1A9_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[19]}]
+
+set_property PACKAGE_PIN E16 [get_ports {IO_A[20]}] ;# A26 / E16~IO_L34N_A12_M1BA2_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[20]}]
+
+set_property PACKAGE_PIN E13 [get_ports {IO_A[21]}] ;# A27 / E13~IO_L1P_A25_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[21]}]
+
+set_property PACKAGE_PIN D16 [get_ports {IO_A[22]}] ;# A28 / D16~IO_L31N_A18_M1A12_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[22]}]
+
+set_property PACKAGE_PIN C16 [get_ports {IO_A[23]}] ;# A29 / C16~IO_L33N_A14_M1A4_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[23]}]
+
+set_property PACKAGE_PIN B16 [get_ports {IO_A[24]}] ;# A30 / B16~IO_L29N_A22_M1A14_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[24]}]
+
+
+set_property PACKAGE_PIN R12 [get_ports {IO_B[0]}] ;# B3 / R12~IO_L52P_M1DQ14_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[0]}]
+
+set_property PACKAGE_PIN T13 [get_ports {IO_B[1]}] ;# B4 / T13~IO_L51N_M1DQ13_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[1]}]
+
+set_property PACKAGE_PIN R14 [get_ports {IO_B[2]}] ;# B5 / R14~IO_L50P_M1UDQS_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[2]}]
+
+set_property PACKAGE_PIN R15 [get_ports {IO_B[3]}] ;# B6 / R15~IO_L49P_M1DQ10_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[3]}]
+
+set_property PACKAGE_PIN P15 [get_ports {IO_B[4]}] ;# B7 / P15~IO_L48P_HDC_M1DQ8_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[4]}]
+
+set_property PACKAGE_PIN N14 [get_ports {IO_B[5]}] ;# B8 / N14~IO_L45P_A1_M1LDQS_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[5]}]
+
+set_property PACKAGE_PIN M15 [get_ports {IO_B[6]}] ;# B9 / M15~IO_L46P_FCS_B_M1DQ2_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[6]}]
+
+set_property PACKAGE_PIN L12 [get_ports {IO_B[7]}] ;# B10 / L12~IO_L53P_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[7]}]
+
+set_property PACKAGE_PIN L14 [get_ports {IO_B[8]}] ;# B11 / L14~IO_L47P_FWE_B_M1DQ0_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[8]}]
+
+set_property PACKAGE_PIN K12 [get_ports {IO_B[9]}] ;# B12 / K12~IO_L42P_GCLK7_M1UDM_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[9]}]
+
+set_property PACKAGE_PIN K15 [get_ports {IO_B[10]}] ;# B13 / K15~IO_L44P_A3_M1DQ6_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[10]}]
+
+set_property PACKAGE_PIN J13 [get_ports {IO_B[11]}] ;# B14 / J13~IO_L41P_GCLK9_IRDY1_M1RASN_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[11]}]
+
+set_property PACKAGE_PIN J14 [get_ports {IO_B[12]}] ;# B18 / J14~IO_L43P_GCLK5_M1DQ4_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[12]}]
+
+set_property PACKAGE_PIN H15 [get_ports {IO_B[13]}] ;# B19 / H15~IO_L37P_A7_M1A0_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[13]}]
+
+set_property PACKAGE_PIN G12 [get_ports {IO_B[14]}] ;# B20 / G12~IO_L38P_A5_M1CLK_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[14]}]
+
+set_property PACKAGE_PIN H13 [get_ports {IO_B[15]}] ;# B21 / H13~IO_L39P_M1A3_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[15]}]
+
+set_property PACKAGE_PIN G14 [get_ports {IO_B[16]}] ;# B22 / G14~IO_L36P_A9_M1BA0_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[16]}]
+
+set_property PACKAGE_PIN G11 [get_ports {IO_B[17]}] ;# B23 / G11~IO_L30N_A20_M1A11_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[17]}]
+
+set_property PACKAGE_PIN F15 [get_ports {IO_B[18]}] ;# B24 / F15~IO_L35P_A11_M1A7_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[18]}]
+
+set_property PACKAGE_PIN F13 [get_ports {IO_B[19]}] ;# B25 / F13~IO_L32P_A17_M1A8_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[19]}]
+
+set_property PACKAGE_PIN E15 [get_ports {IO_B[20]}] ;# B26 / E15~IO_L34P_A13_M1WE_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[20]}]
+
+set_property PACKAGE_PIN E12 [get_ports {IO_B[21]}] ;# B27 / E12~IO_L1N_A24_VREF_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[21]}]
+
+set_property PACKAGE_PIN D14 [get_ports {IO_B[22]}] ;# B28 / D14~IO_L31P_A19_M1CKE_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[22]}]
+
+set_property PACKAGE_PIN C15 [get_ports {IO_B[23]}] ;# B29 / C15~IO_L33P_A15_M1A10_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[23]}]
+
+set_property PACKAGE_PIN B15 [get_ports {IO_B[24]}] ;# B30 / B15~IO_L29P_A23_M1A13_1
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[24]}]
+
+
+set_property PACKAGE_PIN R2 [get_ports {IO_C[0]}] ;# C3 / R2~IO_L32P_M3DQ14_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[0]}]
+
+set_property PACKAGE_PIN P2 [get_ports {IO_C[1]}] ;# C4 / P2~IO_L33P_M3DQ12_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[1]}]
+
+set_property PACKAGE_PIN N3 [get_ports {IO_C[2]}] ;# C5 / N3~IO_L34P_M3UDQS_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[2]}]
+
+set_property PACKAGE_PIN M5 [get_ports {IO_C[3]}] ;# C6 / M5~IO_L2P_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[3]}]
+
+set_property PACKAGE_PIN M4 [get_ports {IO_C[4]}] ;# C7 / M4~IO_L1P_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[4]}]
+
+set_property PACKAGE_PIN M2 [get_ports {IO_C[5]}] ;# C8 / M2~IO_L35P_M3DQ10_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[5]}]
+
+set_property PACKAGE_PIN L5 [get_ports {IO_C[6]}] ;# C9 / L5~IO_L45N_M3ODT_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[6]}]
+
+set_property PACKAGE_PIN L3 [get_ports {IO_C[7]}] ;# C10 / L3~IO_L36P_M3DQ8_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[7]}]
+
+set_property PACKAGE_PIN K2 [get_ports {IO_C[8]}] ;# C11 / K2~IO_L37P_M3DQ0_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[8]}]
+
+set_property PACKAGE_PIN J4 [get_ports {IO_C[9]}] ;# C12 / J4~IO_L42N_GCLK24_M3LDM_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[9]}]
+
+set_property PACKAGE_PIN J3 [get_ports {IO_C[10]}] ;# C13 / J3~IO_L38P_M3DQ2_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[10]}]
+
+set_property PACKAGE_PIN H5 [get_ports {IO_C[11]}] ;# C14 / H5~IO_L43N_GCLK22_IRDY2_M3CASN_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[11]}]
+
+set_property PACKAGE_PIN H4 [get_ports {IO_C[12]}] ;# C15 / H4~IO_L44P_GCLK21_M3A5_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[12]}]
+
+set_property PACKAGE_PIN H2 [get_ports {IO_C[13]}] ;# C19 / H2~IO_L39P_M3LDQS_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[13]}]
+
+set_property PACKAGE_PIN G3 [get_ports {IO_C[14]}] ;# C20 / G3~IO_L40P_M3DQ6_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[14]}]
+
+set_property PACKAGE_PIN F5 [get_ports {IO_C[15]}] ;# C21 / F5~IO_L55N_M3A14_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[15]}]
+
+set_property PACKAGE_PIN F2 [get_ports {IO_C[16]}] ;# C22 / F2~IO_L41P_GCLK27_M3DQ4_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[16]}]
+
+set_property PACKAGE_PIN F4 [get_ports {IO_C[17]}] ;# C23 / F4~IO_L53P_M3CKE_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[17]}]
+
+set_property PACKAGE_PIN E2 [get_ports {IO_C[18]}] ;# C24 / E2~IO_L46P_M3CLK_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[18]}]
+
+set_property PACKAGE_PIN E4 [get_ports {IO_C[19]}] ;# C25 / E4~IO_L54P_M3RESET_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[19]}]
+
+set_property PACKAGE_PIN D3 [get_ports {IO_C[20]}] ;# C26 / D3~IO_L49P_M3A7_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[20]}]
+
+set_property PACKAGE_PIN C3 [get_ports {IO_C[21]}] ;# C27 / C3~IO_L48P_M3BA0_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[21]}]
+
+set_property PACKAGE_PIN C1 [get_ports {IO_C[22]}] ;# C28 / C1~IO_L50P_M3WE_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[22]}]
+
+set_property PACKAGE_PIN B3 [get_ports {IO_C[23]}] ;# C29 / B3~IO_L83P_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[23]}]
+
+set_property PACKAGE_PIN A3 [get_ports {IO_C[24]}] ;# C30 / A3~IO_L83N_VREF_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[24]}]
+
+
+set_property PACKAGE_PIN R1 [get_ports {IO_D[0]}] ;# D3 / R1~IO_L32N_M3DQ15_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[0]}]
+
+set_property PACKAGE_PIN P1 [get_ports {IO_D[1]}] ;# D4 / P1~IO_L33N_M3DQ13_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[1]}]
+
+set_property PACKAGE_PIN N1 [get_ports {IO_D[2]}] ;# D5 / N1~IO_L34N_M3UDQSN_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[2]}]
+
+set_property PACKAGE_PIN N4 [get_ports {IO_D[3]}] ;# D6 / N4~IO_L2N_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[3]}]
+
+set_property PACKAGE_PIN M3 [get_ports {IO_D[4]}] ;# D7 / M3~IO_L1N_VREF_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[4]}]
+
+set_property PACKAGE_PIN M1 [get_ports {IO_D[5]}] ;# D8 / M1~IO_L35N_M3DQ11_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[5]}]
+
+set_property PACKAGE_PIN L4 [get_ports {IO_D[6]}] ;# D9 / L4~IO_L45P_M3A3_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[6]}]
+
+set_property PACKAGE_PIN L1 [get_ports {IO_D[7]}] ;# D10 / L1~IO_L36N_M3DQ9_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[7]}]
+
+set_property PACKAGE_PIN K1 [get_ports {IO_D[8]}] ;# D11 / K1~IO_L37N_M3DQ1_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[8]}]
+
+set_property PACKAGE_PIN K3 [get_ports {IO_D[9]}] ;# D12 / K3~IO_L42P_GCLK25_TRDY2_M3UDM_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[9]}]
+
+set_property PACKAGE_PIN J1 [get_ports {IO_D[10]}] ;# D13 / J1~IO_L38N_M3DQ3_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[10]}]
+
+set_property PACKAGE_PIN K5 [get_ports {IO_D[11]}] ;# D14 / K5~IO_L47P_M3A0_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[11]}]
+
+set_property PACKAGE_PIN H3 [get_ports {IO_D[12]}] ;# D15 / H3~IO_L44N_GCLK20_M3A6_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[12]}]
+
+set_property PACKAGE_PIN H1 [get_ports {IO_D[13]}] ;# D19 / H1~IO_L39N_M3LDQSN_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[13]}]
+
+set_property PACKAGE_PIN G1 [get_ports {IO_D[14]}] ;# D20 / G1~IO_L40N_M3DQ7_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[14]}]
+
+set_property PACKAGE_PIN G5 [get_ports {IO_D[15]}] ;# D21 / G5~IO_L51N_M3A4_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[15]}]
+
+set_property PACKAGE_PIN F1 [get_ports {IO_D[16]}] ;# D22 / F1~IO_L41N_GCLK26_M3DQ5_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[16]}]
+
+set_property PACKAGE_PIN F3 [get_ports {IO_D[17]}] ;# D23 / F3~IO_L53N_M3A12_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[17]}]
+
+set_property PACKAGE_PIN E1 [get_ports {IO_D[18]}] ;# D24 / E1~IO_L46N_M3CLKN_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[18]}]
+
+set_property PACKAGE_PIN E3 [get_ports {IO_D[19]}] ;# D25 / E3~IO_L54N_M3A11_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[19]}]
+
+set_property PACKAGE_PIN D1 [get_ports {IO_D[20]}] ;# D26 / D1~IO_L49N_M3A2_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[20]}]
+
+set_property PACKAGE_PIN C2 [get_ports {IO_D[21]}] ;# D27 / C2~IO_L48N_M3BA1_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[21]}]
+
+set_property PACKAGE_PIN B1 [get_ports {IO_D[22]}] ;# D28 / B1~IO_L50N_M3BA2_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[22]}]
+
+set_property PACKAGE_PIN B2 [get_ports {IO_D[23]}] ;# D29 / B2~IO_L52P_M3A8_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[23]}]
+
+set_property PACKAGE_PIN A2 [get_ports {IO_D[24]}] ;# D30 / A2~IO_L52N_M3A9_3
+set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[24]}]
Index: usb-fpga-2.01.txt
===================================================================
--- usb-fpga-2.01.txt (nonexistent)
+++ usb-fpga-2.01.txt (revision 4)
@@ -0,0 +1,167 @@
+A3 T12~IO_L52N_M1DQ15_1 T12
+B3 R12~IO_L52P_M1DQ14_1 R12
+A4 T14~IO_L51P_M1DQ12_1 T14
+B4 T13~IO_L51N_M1DQ13_1 T13
+A5 T15~IO_L50N_M1UDQSN_1 T15
+B5 R14~IO_L50P_M1UDQS_1 R14
+A6 R16~IO_L49N_M1DQ11_1 R16
+B6 R15~IO_L49P_M1DQ10_1 R15
+A7 P16~IO_L48N_M1DQ9_1 P16
+B7 P15~IO_L48P_HDC_M1DQ8_1 P15
+A8 N16~IO_L45N_A0_M1LDQSN_1 N16
+B8 N14~IO_L45P_A1_M1LDQS_1 N14
+A9 M16~IO_L46N_FOE_B_M1DQ3_1 M16
+B9 M15~IO_L46P_FCS_B_M1DQ2_1 M15
+A10 L13~IO_L53N_VREF_1 L13
+B10 L12~IO_L53P_1 L12
+A11 L16~IO_L47N_LDC_M1DQ1_1 L16
+B11 L14~IO_L47P_FWE_B_M1DQ0_1 L14
+A12 M13~IO_L74P_AWAKE_1 M13
+B12 K12~IO_L42P_GCLK7_M1UDM_1 K12
+A13 K16~IO_L44N_A2_M1DQ7_1 K16
+B13 K15~IO_L44P_A3_M1DQ6_1 K15
+A14 K14~IO_L41N_GCLK8_M1CASN_1 K14
+B14 J13~IO_L41P_GCLK9_IRDY1_M1RASN_1 J13
+A18 J16~IO_L43N_GCLK4_M1DQ5_1 J16
+B18 J14~IO_L43P_GCLK5_M1DQ4_1 J14
+A19 H16~IO_L37N_A6_M1A1_1 H16
+B19 H15~IO_L37P_A7_M1A0_1 H15
+A20 J12~IO_L40N_GCLK10_M1A6_1 J12
+B20 G12~IO_L38P_A5_M1CLK_1 G12
+A21 H14~IO_L39N_M1ODT_1 H14
+B21 H13~IO_L39P_M1A3_1 H13
+A22 G16~IO_L36N_A8_M1BA1_1 G16
+B22 G14~IO_L36P_A9_M1BA0_1 G14
+A23 F12~IO_L30P_A21_M1RESET_1 F12
+B23 G11~IO_L30N_A20_M1A11_1 G11
+A24 F16~IO_L35N_A10_M1A2_1 F16
+B24 F15~IO_L35P_A11_M1A7_1 F15
+A25 F14~IO_L32N_A16_M1A9_1 F14
+B25 F13~IO_L32P_A17_M1A8_1 F13
+A26 E16~IO_L34N_A12_M1BA2_1 E16
+B26 E15~IO_L34P_A13_M1WE_1 E15
+A27 E13~IO_L1P_A25_1 E13
+B27 E12~IO_L1N_A24_VREF_1 E12
+A28 D16~IO_L31N_A18_M1A12_1 D16
+B28 D14~IO_L31P_A19_M1CKE_1 D14
+A29 C16~IO_L33N_A14_M1A4_1 C16
+B29 C15~IO_L33P_A15_M1A10_1 C15
+A30 B16~IO_L29N_A22_M1A14_1 B16
+B30 B15~IO_L29P_A23_M1A13_1 B15
+
+C3 R2~IO_L32P_M3DQ14_3 R2
+D3 R1~IO_L32N_M3DQ15_3 R1
+C4 P2~IO_L33P_M3DQ12_3 P2
+D4 P1~IO_L33N_M3DQ13_3 P1
+C5 N3~IO_L34P_M3UDQS_3 N3
+D5 N1~IO_L34N_M3UDQSN_3 N1
+C6 M5~IO_L2P_3 M5
+D6 N4~IO_L2N_3 N4
+C7 M4~IO_L1P_3 M4
+D7 M3~IO_L1N_VREF_3 M3
+C8 M2~IO_L35P_M3DQ10_3 M2
+D8 M1~IO_L35N_M3DQ11_3 M1
+C9 L5~IO_L45N_M3ODT_3 L5
+D9 L4~IO_L45P_M3A3_3 L4
+C10 L3~IO_L36P_M3DQ8_3 L3
+D10 L1~IO_L36N_M3DQ9_3 L1
+C11 K2~IO_L37P_M3DQ0_3 K2
+D11 K1~IO_L37N_M3DQ1_3 K1
+C12 J4~IO_L42N_GCLK24_M3LDM_3 J4
+D12 K3~IO_L42P_GCLK25_TRDY2_M3UDM_3 K3
+C13 J3~IO_L38P_M3DQ2_3 J3
+D13 J1~IO_L38N_M3DQ3_3 J1
+C14 H5~IO_L43N_GCLK22_IRDY2_M3CASN_3 H5
+D14 K5~IO_L47P_M3A0_3 K5
+C15 H4~IO_L44P_GCLK21_M3A5_3 H4
+D15 H3~IO_L44N_GCLK20_M3A6_3 H3
+C19 H2~IO_L39P_M3LDQS_3 H2
+D19 H1~IO_L39N_M3LDQSN_3 H1
+C20 G3~IO_L40P_M3DQ6_3 G3
+D20 G1~IO_L40N_M3DQ7_3 G1
+C21 F5~IO_L55N_M3A14_3 F5
+D21 G5~IO_L51N_M3A4_3 G5
+C22 F2~IO_L41P_GCLK27_M3DQ4_3 F2
+D22 F1~IO_L41N_GCLK26_M3DQ5_3 F1
+C23 F4~IO_L53P_M3CKE_3 F4
+D23 F3~IO_L53N_M3A12_3 F3
+C24 E2~IO_L46P_M3CLK_3 E2
+D24 E1~IO_L46N_M3CLKN_3 E1
+C25 E4~IO_L54P_M3RESET_3 E4
+D25 E3~IO_L54N_M3A11_3 E3
+C26 D3~IO_L49P_M3A7_3 D3
+D26 D1~IO_L49N_M3A2_3 D1
+C27 C3~IO_L48P_M3BA0_3 C3
+D27 C2~IO_L48N_M3BA1_3 C2
+C28 C1~IO_L50P_M3WE_3 C1
+D28 B1~IO_L50N_M3BA2_3 B1
+C29 B3~IO_L83P_3 B3
+D29 B2~IO_L52P_M3A8_3 B2
+C30 A3~IO_L83N_VREF_3 A3
+D30 A2~IO_L52N_M3A9_3 A2
+
+- CLKOUT/FXCLK T7
+
+- IFCLK T8
+
+- PB0/FD0 T9
+- PB1/FD1 R9
+- PB2/FD2 P9
+- PB3/FD3 N9
+- PB4/FD4 M10
+- PB5/FD5 P11
+- PB6/FD6 M11
+- PB7/FD7 M12
+
+- PD0/FD8 P8
+- PD1/FD9 M7
+- PD2/FD10 P7
+- PD3/FD11 R7
+- PD4/FD12 M6
+- PD5/FD13 N6
+- PD6/FD14 P6
+- PD7/FD15 T6
+
+- PA0/INT0# R11
+- PA1/INT1# T10
+- PA2/*SLOE B10
+- PA3/*WU2 T3
+- PA4/FIFOADR0 T11
+- PA5/FIFOADR1 N11
+- PA6/*PKTEND T5
+- PA7/*FLAGD/SLCS# R3
+
+- PC0/GPIFADR0 P10
+- PC1/GPIFADR1 N12
+- PC2/GPIFADR2 P12
+- PC3/GPIFADR3 N5
+- PC4/GPIFADR4 P5
+- PC5/GPIFADR5 L8
+- PC6/GPIFADR6 L7
+- PC7/GPIFADR7 R5
+
+- PE0/T0OUT A8
+- PE1/T1OUT B8
+- PE2/T2OUT A7
+- PE3/RXD0OUT A6
+- PE4/RXD1OUT B6
+- PE5/INT6 A5
+
+- RDY0/*SLRD T4
+- RDY1/*SLWR P4
+- RDY2 A4
+
+- CTL0/*FLAGA L10
+- CTL1/*FLAGB M9
+- CTL2/*FLAGC N8
+- CTL3 A10
+
+- INT4 A11
+- INT5# A9
+- T0 B12
+
+- SCL A12
+- SDA A13
+
+- RxD0 A14
+- TxD0 B14
Index: usb-fpga-2.04.ucf
===================================================================
--- usb-fpga-2.04.ucf (nonexistent)
+++ usb-fpga-2.04.ucf (revision 4)
@@ -0,0 +1,158 @@
+# !!! Constraint files are application specific !!!
+# !!! This is a template only !!!
+
+# on-board signals
+
+# CLKOUT/FXCLK
+NET "fxclk_in" TNM_NET = "fxclk_in";
+TIMESPEC "ts_fxclk_in" = PERIOD "fxclk_in" 48 MHz HIGH 50 %;
+NET "fxclk_in" LOC = "J16" | IOSTANDARD = LVCMOS33 ;
+
+# IFCLK
+NET "ifclk_in" TNM_NET = "ifclk_in";
+TIMESPEC "ts_ifclk_in" = PERIOD "ifclk_in" 48 MHz HIGH 50 %;
+NET "ifclk_in" LOC = "J14" | IOSTANDARD = LVCMOS33 ;
+
+NET "PB<0>" LOC = "D16" | IOSTANDARD = LVCMOS33 ; # PB0/FD0
+NET "PB<1>" LOC = "F15" | IOSTANDARD = LVCMOS33 ; # PB1/FD1
+NET "PB<2>" LOC = "E15" | IOSTANDARD = LVCMOS33 ; # PB2/FD2
+NET "PB<3>" LOC = "D14" | IOSTANDARD = LVCMOS33 ; # PB3/FD3
+NET "PB<4>" LOC = "F13" | IOSTANDARD = LVCMOS33 ; # PB4/FD4
+NET "PB<5>" LOC = "E12" | IOSTANDARD = LVCMOS33 ; # PB5/FD5
+NET "PB<6>" LOC = "F12" | IOSTANDARD = LVCMOS33 ; # PB6/FD6
+NET "PB<7>" LOC = "G12" | IOSTANDARD = LVCMOS33 ; # PB7/FD7
+
+NET "PD<0>" LOC = "H14" | IOSTANDARD = LVCMOS33 ; # PD0/FD8
+NET "PD<1>" LOC = "J11" | IOSTANDARD = LVCMOS33 ; # PD1/FD9
+NET "PD<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 ; # PD2/FD10
+NET "PD<3>" LOC = "J13" | IOSTANDARD = LVCMOS33 ; # PD3/FD11
+NET "PD<4>" LOC = "K12" | IOSTANDARD = LVCMOS33 ; # PD4/FD12
+NET "PD<5>" LOC = "K15" | IOSTANDARD = LVCMOS33 ; # PD5/FD13
+NET "PD<6>" LOC = "K16" | IOSTANDARD = LVCMOS33 ; # PD6/FD14
+NET "PD<7>" LOC = "M14" | IOSTANDARD = LVCMOS33 ; # PD7/FD15
+
+NET "PA<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 ; # PA0/INT0#
+NET "PA<1>" LOC = "T10" | IOSTANDARD = LVCMOS33 ; # PA1/INT1#
+NET "PA<2>" LOC = "H13" | IOSTANDARD = LVCMOS33 ; # PA2/SLOE
+NET "PA<3>" LOC = "T3" | IOSTANDARD = LVCMOS33 ; # PA3/WU2
+NET "PA<4>" LOC = "T11" | IOSTANDARD = LVCMOS33 ; # PA4/FIFOADR0
+NET "PA<5>" LOC = "N11" | IOSTANDARD = LVCMOS33 ; # PA5/FIFOADR1
+NET "PA<6>" LOC = "T5" | IOSTANDARD = LVCMOS33 ; # PA6/PKTEND
+NET "PA<7>" LOC = "R3" | IOSTANDARD = LVCMOS33 ; # PA7/FLAGD/SLCS#
+
+NET "PC<0>" LOC = "P10" | IOSTANDARD = LVCMOS33 ; # PC0/GPIFADR0
+NET "PC<1>" LOC = "N12" | IOSTANDARD = LVCMOS33 ; # PC1/GPIFADR1
+NET "PC<2>" LOC = "P12" | IOSTANDARD = LVCMOS33 ; # PC2/GPIFADR2
+NET "PC<3>" LOC = "N5" | IOSTANDARD = LVCMOS33 ; # PC3/GPIFADR3
+NET "PC<4>" LOC = "P5" | IOSTANDARD = LVCMOS33 ; # PC4/GPIFADR4
+NET "PC<5>" LOC = "L8" | IOSTANDARD = LVCMOS33 ; # PC5/GPIFADR5
+NET "PC<6>" LOC = "L7" | IOSTANDARD = LVCMOS33 ; # PC6/GPIFADR6
+NET "PC<7>" LOC = "R5" | IOSTANDARD = LVCMOS33 ; # PC7/GPIFADR7
+
+NET "SLRD" LOC = "H16" | IOSTANDARD = LVCMOS33 ; # RDY0/SLRD
+NET "SLWR" LOC = "H15" | IOSTANDARD = LVCMOS33 ; # RDY1/SLWR
+
+NET "FLAGA" LOC = "G14" | IOSTANDARD = LVCMOS33 ; # CTL0/FLAGA
+NET "FLAGB" LOC = "G16" | IOSTANDARD = LVCMOS33 ; # CTL1/FLAGB
+NET "FLAGC" LOC = "H11" | IOSTANDARD = LVCMOS33 ; # CTL2/FLAGC
+NET "CTL3" LOC = "G11" | IOSTANDARD = LVCMOS33 ; # CTL3
+
+NET "SCL" LOC = "F15" | IOSTANDARD = LVCMOS33 ; # SCL
+NET "SDA" LOC = "E16" | IOSTANDARD = LVCMOS33 ; # SDA
+
+NET "RxD1" LOC = "E13" | IOSTANDARD = LVCMOS33 ; # RxD1
+NET "TxD1" LOC = "F14" | IOSTANDARD = LVCMOS33 ; # TxD1
+
+# external I/O
+
+NET "IO_A<0>" LOC = "B16" | IOSTANDARD = LVCMOS33 ; # A6 / B16~IO_L29N_A22_M1A14_1
+NET "IO_A<1>" LOC = "B15" | IOSTANDARD = LVCMOS33 ; # A7 / B15~IO_L29P_A23_M1A13_1
+NET "IO_A<2>" LOC = "A14" | IOSTANDARD = LVCMOS33 ; # A8 / A14~IO_L65N_SCP2_0
+NET "IO_A<3>" LOC = "A13" | IOSTANDARD = LVCMOS33 ; # A9 / A13~IO_L63N_SCP6_0
+NET "IO_A<4>" LOC = "A12" | IOSTANDARD = LVCMOS33 ; # A10 / A12~IO_L62N_VREF_0
+NET "IO_A<5>" LOC = "D12" | IOSTANDARD = LVCMOS33 ; # A11 / D12~IO_L66N_SCP0_0
+NET "IO_A<6>" LOC = "D11" | IOSTANDARD = LVCMOS33 ; # A12 / D11~IO_L66P_SCP1_0
+NET "IO_A<7>" LOC = "A11" | IOSTANDARD = LVCMOS33 ; # A13 / A11~IO_L39N_0
+NET "IO_A<8>" LOC = "A10" | IOSTANDARD = LVCMOS33 ; # A14 / A10~IO_L35N_GCLK16_0
+NET "IO_A<9>" LOC = "C10" | IOSTANDARD = LVCMOS33 ; # A18 / C10~IO_L37N_GCLK12_0
+NET "IO_A<10>" LOC = "D9" | IOSTANDARD = LVCMOS33 ; # A19 / D9~IO_L40N_0
+NET "IO_A<11>" LOC = "A9" | IOSTANDARD = LVCMOS33 ; # A20 / A9~IO_L34N_GCLK18_0
+NET "IO_A<12>" LOC = "C8" | IOSTANDARD = LVCMOS33 ; # A21 / C8~IO_L38N_VREF_0
+NET "IO_A<13>" LOC = "A8" | IOSTANDARD = LVCMOS33 ; # A22 / A8~IO_L33N_0
+NET "IO_A<14>" LOC = "E8" | IOSTANDARD = LVCMOS33 ; # A23 / E8~IO_L36N_GCLK14_0
+NET "IO_A<15>" LOC = "E7" | IOSTANDARD = LVCMOS33 ; # A24 / E7~IO_L36P_GCLK15_0
+NET "IO_A<16>" LOC = "A7" | IOSTANDARD = LVCMOS33 ; # A25 / A7~IO_L6N_0
+NET "IO_A<17>" LOC = "C6" | IOSTANDARD = LVCMOS33 ; # A26 / C6~IO_L7N_0
+NET "IO_A<18>" LOC = "A6" | IOSTANDARD = LVCMOS33 ; # A27 / A6~IO_L4N_0
+NET "IO_A<19>" LOC = "A5" | IOSTANDARD = LVCMOS33 ; # A28 / A5~IO_L2N_0
+NET "IO_A<20>" LOC = "C5" | IOSTANDARD = LVCMOS33 ; # A29 / C5~IO_L3N_0
+NET "IO_A<21>" LOC = "A4" | IOSTANDARD = LVCMOS33 ; # A30 / A4~IO_L1N_VREF_0
+
+NET "IO_B<0>" LOC = "C16" | IOSTANDARD = LVCMOS33 ; # B6 / C16~IO_L33N_A14_M1A4_1
+NET "IO_B<1>" LOC = "C15" | IOSTANDARD = LVCMOS33 ; # B7 / C15~IO_L33P_A15_M1A10_1
+NET "IO_B<2>" LOC = "B14" | IOSTANDARD = LVCMOS33 ; # B8 / B14~IO_L65P_SCP3_0
+NET "IO_B<3>" LOC = "C13" | IOSTANDARD = LVCMOS33 ; # B9 / C13~IO_L63P_SCP7_0
+NET "IO_B<4>" LOC = "B12" | IOSTANDARD = LVCMOS33 ; # B10 / B12~IO_L62P_0
+NET "IO_B<5>" LOC = "E11" | IOSTANDARD = LVCMOS33 ; # B11 / E11~IO_L64N_SCP4_0
+NET "IO_B<6>" LOC = "F10" | IOSTANDARD = LVCMOS33 ; # B12 / F10~IO_L64P_SCP5_0
+NET "IO_B<7>" LOC = "C11" | IOSTANDARD = LVCMOS33 ; # B13 / C11~IO_L39P_0
+NET "IO_B<8>" LOC = "B10" | IOSTANDARD = LVCMOS33 ; # B14 / B10~IO_L35P_GCLK17_0
+NET "IO_B<9>" LOC = "E10" | IOSTANDARD = LVCMOS33 ; # B18 / E10~IO_L37P_GCLK13_0
+NET "IO_B<10>" LOC = "F9" | IOSTANDARD = LVCMOS33 ; # B19 / F9~IO_L40P_0
+NET "IO_B<11>" LOC = "C9" | IOSTANDARD = LVCMOS33 ; # B20 / C9~IO_L34P_GCLK19_0
+NET "IO_B<12>" LOC = "D8" | IOSTANDARD = LVCMOS33 ; # B21 / D8~IO_L38P_0
+NET "IO_B<13>" LOC = "B8" | IOSTANDARD = LVCMOS33 ; # B22 / B8~IO_L33P_0
+NET "IO_B<14>" LOC = "F7" | IOSTANDARD = LVCMOS33 ; # B23 / F7~IO_L5P_0
+NET "IO_B<15>" LOC = "E6" | IOSTANDARD = LVCMOS33 ; # B24 / E6~IO_L5N_0
+NET "IO_B<16>" LOC = "C7" | IOSTANDARD = LVCMOS33 ; # B25 / C7~IO_L6P_0
+NET "IO_B<17>" LOC = "D6" | IOSTANDARD = LVCMOS33 ; # B26 / D6~IO_L7P_0
+NET "IO_B<18>" LOC = "B6" | IOSTANDARD = LVCMOS33 ; # B27 / B6~IO_L4P_0
+NET "IO_B<19>" LOC = "B5" | IOSTANDARD = LVCMOS33 ; # B28 / B5~IO_L2P_0
+NET "IO_B<20>" LOC = "D5" | IOSTANDARD = LVCMOS33 ; # B29 / D5~IO_L3P_0
+NET "IO_B<21>" LOC = "C4" | IOSTANDARD = LVCMOS33 ; # B30 / C4~IO_L1P_HSWAPEN_0
+
+NET "IO_C<0>" LOC = "R15" | IOSTANDARD = LVCMOS33 ; # C6 / R15~IO_L49P_M1DQ10_1
+NET "IO_C<1>" LOC = "N16" | IOSTANDARD = LVCMOS33 ; # C7 / N16~IO_L45N_A0_M1LDQSN_1
+NET "IO_C<2>" LOC = "N14" | IOSTANDARD = LVCMOS33 ; # C8 / N14~IO_L45P_A1_M1LDQS_1
+NET "IO_C<3>" LOC = "T15" | IOSTANDARD = LVCMOS33 ; # C9 / T15~IO_L50N_M1UDQSN_1
+NET "IO_C<4>" LOC = "R14" | IOSTANDARD = LVCMOS33 ; # C10 / R14~IO_L50P_M1UDQS_1
+NET "IO_C<5>" LOC = "R12" | IOSTANDARD = LVCMOS33 ; # C11 / R12~IO_L52P_M1DQ14_1
+NET "IO_C<6>" LOC = "L16" | IOSTANDARD = LVCMOS33 ; # C12 / L16~IO_L47N_LDC_M1DQ1_1
+NET "IO_C<7>" LOC = "L14" | IOSTANDARD = LVCMOS33 ; # C13 / L14~IO_L47P_FWE_B_M1DQ0_1
+NET "IO_C<8>" LOC = "L13" | IOSTANDARD = LVCMOS33 ; # C14 / L13~IO_L53N_VREF_1
+NET "IO_C<9>" LOC = "L12" | IOSTANDARD = LVCMOS33 ; # C15 / L12~IO_L53P_1
+NET "IO_C<10>" LOC = "M11" | IOSTANDARD = LVCMOS33 ; # C19 / M11~IO_L2N_CMPMOSI_2
+NET "IO_C<11>" LOC = "K11" | IOSTANDARD = LVCMOS33 ; # C20 / K11~IO_L42N_GCLK6_TRDY1_M1LDM_1
+NET "IO_C<12>" LOC = "L10" | IOSTANDARD = LVCMOS33 ; # C21 / L10~IO_L16P_2
+NET "IO_C<13>" LOC = "P9" | IOSTANDARD = LVCMOS33 ; # C22 / P9~IO_L14N_D12_2
+NET "IO_C<14>" LOC = "N9" | IOSTANDARD = LVCMOS33 ; # C23 / N9~IO_L14P_D11_2
+NET "IO_C<15>" LOC = "M9" | IOSTANDARD = LVCMOS33 ; # C24 / M9~IO_L29P_GCLK3_2
+NET "IO_C<16>" LOC = "N8" | IOSTANDARD = LVCMOS33 ; # C25 / N8~IO_L29N_GCLK2_2
+NET "IO_C<17>" LOC = "R7" | IOSTANDARD = LVCMOS33 ; # C26 / R7~IO_L32P_GCLK29_2
+NET "IO_C<18>" LOC = "M7" | IOSTANDARD = LVCMOS33 ; # C27 / M7~IO_L31N_GCLK30_D15_2
+NET "IO_C<19>" LOC = "P6" | IOSTANDARD = LVCMOS33 ; # C28 / P6~IO_L47P_2
+NET "IO_C<20>" LOC = "M6" | IOSTANDARD = LVCMOS33 ; # C29 / M6~IO_L64P_D8_2
+NET "IO_C<21>" LOC = "P4" | IOSTANDARD = LVCMOS33 ; # C30 / P4~IO_L63P_2
+
+NET "IO_D<0>" LOC = "R16" | IOSTANDARD = LVCMOS33 ; # D6 / R16~IO_L49N_M1DQ11_1
+NET "IO_D<1>" LOC = "P16" | IOSTANDARD = LVCMOS33 ; # D7 / P16~IO_L48N_M1DQ9_1
+NET "IO_D<2>" LOC = "P15" | IOSTANDARD = LVCMOS33 ; # D8 / P15~IO_L48P_HDC_M1DQ8_1
+NET "IO_D<3>" LOC = "T14" | IOSTANDARD = LVCMOS33 ; # D9 / T14~IO_L51P_M1DQ12_1
+NET "IO_D<4>" LOC = "T13" | IOSTANDARD = LVCMOS33 ; # D10 / T13~IO_L51N_M1DQ13_1
+NET "IO_D<5>" LOC = "T12" | IOSTANDARD = LVCMOS33 ; # D11 / T12~IO_L52N_M1DQ15_1
+NET "IO_D<6>" LOC = "M16" | IOSTANDARD = LVCMOS33 ; # D12 / M16~IO_L46N_FOE_B_M1DQ3_1
+NET "IO_D<7>" LOC = "M15" | IOSTANDARD = LVCMOS33 ; # D13 / M15~IO_L46P_FCS_B_M1DQ2_1
+NET "IO_D<8>" LOC = "K14" | IOSTANDARD = LVCMOS33 ; # D14 / K14~IO_L41N_GCLK8_M1CASN_1
+NET "IO_D<9>" LOC = "M13" | IOSTANDARD = LVCMOS33 ; # D15 / M13~IO_L74P_AWAKE_1
+NET "IO_D<10>" LOC = "M12" | IOSTANDARD = LVCMOS33 ; # D19 / M12~IO_L2P_CMPCLK_2
+NET "IO_D<11>" LOC = "P11" | IOSTANDARD = LVCMOS33 ; # D20 / P11~IO_L13N_D10_2
+NET "IO_D<12>" LOC = "M10" | IOSTANDARD = LVCMOS33 ; # D21 / M10~IO_L16N_VREF_2
+NET "IO_D<13>" LOC = "T9" | IOSTANDARD = LVCMOS33 ; # D22 / T9~IO_L23N_2
+NET "IO_D<14>" LOC = "R9" | IOSTANDARD = LVCMOS33 ; # D23 / R9~IO_L23P_2
+NET "IO_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 ; # D24 / T8~IO_L30N_GCLK0_USERCCLK_2
+NET "IO_D<16>" LOC = "P8" | IOSTANDARD = LVCMOS33 ; # D25 / P8~IO_L30P_GCLK1_D13_2
+NET "IO_D<17>" LOC = "T7" | IOSTANDARD = LVCMOS33 ; # D26 / T7~IO_L32N_GCLK28_2
+NET "IO_D<18>" LOC = "P7" | IOSTANDARD = LVCMOS33 ; # D27 / P7~IO_L31P_GCLK31_D14_2
+NET "IO_D<19>" LOC = "T6" | IOSTANDARD = LVCMOS33 ; # D28 / T6~IO_L47N_2
+NET "IO_D<20>" LOC = "N6" | IOSTANDARD = LVCMOS33 ; # D29 / N6~IO_L64N_D9_2
+NET "IO_D<21>" LOC = "T4" | IOSTANDARD = LVCMOS33 ; # D30 / T4~IO_L63N_2
Index: usb-fpga-2.13.xdc
===================================================================
--- usb-fpga-2.13.xdc (revision 3)
+++ usb-fpga-2.13.xdc (revision 4)
@@ -14,638 +14,482 @@
set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in]
-# PB0/FD0
-set_property PACKAGE_PIN M16 [get_ports {PB[0]}]
+set_property PACKAGE_PIN M16 [get_ports {PB[0]}] ;# PB0/FD0
set_property IOSTANDARD LVCMOS33 [get_ports {PB[0]}]
-# PB1/FD1
-set_property PACKAGE_PIN L16 [get_ports {PB[1]}]
+set_property PACKAGE_PIN L16 [get_ports {PB[1]}] ;# PB1/FD1
set_property IOSTANDARD LVCMOS33 [get_ports {PB[1]}]
-# PB2/FD2
-set_property PACKAGE_PIN L14 [get_ports {PB[2]}]
+set_property PACKAGE_PIN L14 [get_ports {PB[2]}] ;# PB2/FD2
set_property IOSTANDARD LVCMOS33 [get_ports {PB[2]}]
-# PB3/FD3
-set_property PACKAGE_PIN M14 [get_ports {PB[3]}]
+set_property PACKAGE_PIN M14 [get_ports {PB[3]}] ;# PB3/FD3
set_property IOSTANDARD LVCMOS33 [get_ports {PB[3]}]
-# PB4/FD4
-set_property PACKAGE_PIN L18 [get_ports {PB[4]}]
+set_property PACKAGE_PIN L18 [get_ports {PB[4]}] ;# PB4/FD4
set_property IOSTANDARD LVCMOS33 [get_ports {PB[4]}]
-# PB5/FD5
-set_property PACKAGE_PIN M18 [get_ports {PB[5]}]
+set_property PACKAGE_PIN M18 [get_ports {PB[5]}] ;# PB5/FD5
set_property IOSTANDARD LVCMOS33 [get_ports {PB[5]}]
-# PB6/FD6
-set_property PACKAGE_PIN R12 [get_ports {PB[6]}]
+set_property PACKAGE_PIN R12 [get_ports {PB[6]}] ;# PB6/FD6
set_property IOSTANDARD LVCMOS33 [get_ports {PB[6]}]
-# PB7/FD7
-set_property PACKAGE_PIN R13 [get_ports {PB[7]}]
+set_property PACKAGE_PIN R13 [get_ports {PB[7]}] ;# PB7/FD7
set_property IOSTANDARD LVCMOS33 [get_ports {PB[7]}]
-# PD0/FD8
-set_property PACKAGE_PIN T9 [get_ports {PD[0]}]
+set_property PACKAGE_PIN T9 [get_ports {PD[0]}] ;# PD0/FD8
set_property IOSTANDARD LVCMOS33 [get_ports {PD[0]}]
-# PD1/FD9
-set_property PACKAGE_PIN V10 [get_ports {PD[1]}]
+set_property PACKAGE_PIN V10 [get_ports {PD[1]}] ;# PD1/FD9
set_property IOSTANDARD LVCMOS33 [get_ports {PD[1]}]
-# PD2/FD10
-set_property PACKAGE_PIN U11 [get_ports {PD[2]}]
+set_property PACKAGE_PIN U11 [get_ports {PD[2]}] ;# PD2/FD10
set_property IOSTANDARD LVCMOS33 [get_ports {PD[2]}]
-# PD3/FD11
-set_property PACKAGE_PIN V11 [get_ports {PD[3]}]
+set_property PACKAGE_PIN V11 [get_ports {PD[3]}] ;# PD3/FD11
set_property IOSTANDARD LVCMOS33 [get_ports {PD[3]}]
-# PD4/FD12
-set_property PACKAGE_PIN V12 [get_ports {PD[4]}]
+set_property PACKAGE_PIN V12 [get_ports {PD[4]}] ;# PD4/FD12
set_property IOSTANDARD LVCMOS33 [get_ports {PD[4]}]
-# PD5/FD13
-set_property PACKAGE_PIN U13 [get_ports {PD[5]}]
+set_property PACKAGE_PIN U13 [get_ports {PD[5]}] ;# PD5/FD13
set_property IOSTANDARD LVCMOS33 [get_ports {PD[5]}]
-# PD6/FD14
-set_property PACKAGE_PIN U14 [get_ports {PD[6]}]
+set_property PACKAGE_PIN U14 [get_ports {PD[6]}] ;# PD6/FD14
set_property IOSTANDARD LVCMOS33 [get_ports {PD[6]}]
-# PD7/FD15
-set_property PACKAGE_PIN V14 [get_ports {PD[7]}]
+set_property PACKAGE_PIN V14 [get_ports {PD[7]}] ;# PD7/FD15
set_property IOSTANDARD LVCMOS33 [get_ports {PD[7]}]
-# PA0/INT0#
-set_property PACKAGE_PIN R15 [get_ports {PA[0]}]
+set_property PACKAGE_PIN R15 [get_ports {PA[0]}] ;# PA0/INT0#
set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}]
-# PA1/INT1#
-set_property PACKAGE_PIN T15 [get_ports {PA[1]}]
+set_property PACKAGE_PIN T15 [get_ports {PA[1]}] ;# PA1/INT1#
set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}]
-# PA2/SLOE
-set_property PACKAGE_PIN T14 [get_ports {PA[2]}]
+set_property PACKAGE_PIN T14 [get_ports {PA[2]}] ;# PA2/SLOE
set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}]
-# PA3/WU2
-set_property PACKAGE_PIN T13 [get_ports {PA[3]}]
+set_property PACKAGE_PIN T13 [get_ports {PA[3]}] ;# PA3/WU2
set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}]
-# PA4/FIFOADR0
-set_property PACKAGE_PIN R11 [get_ports {PA[4]}]
+set_property PACKAGE_PIN R11 [get_ports {PA[4]}] ;# PA4/FIFOADR0
set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}]
-# PA5/FIFOADR1
-set_property PACKAGE_PIN T11 [get_ports {PA[5]}]
+set_property PACKAGE_PIN T11 [get_ports {PA[5]}] ;# PA5/FIFOADR1
set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}]
-# PA6/PKTEND
-set_property PACKAGE_PIN R10 [get_ports {PA[6]}]
+set_property PACKAGE_PIN R10 [get_ports {PA[6]}] ;# PA6/PKTEND
set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}]
-# PA7/FLAGD/SLCS#
-set_property PACKAGE_PIN T10 [get_ports {PA[7]}]
+set_property PACKAGE_PIN T10 [get_ports {PA[7]}] ;# PA7/FLAGD/SLCS#
set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}]
-# PC0/GPIFADR0
-set_property PACKAGE_PIN R17 [get_ports {PC[0]}]
+set_property PACKAGE_PIN R17 [get_ports {PC[0]}] ;# PC0/GPIFADR0
set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}]
-# PC1/GPIFADR1
-set_property PACKAGE_PIN R18 [get_ports {PC[1]}]
+set_property PACKAGE_PIN R18 [get_ports {PC[1]}] ;# PC1/GPIFADR1
set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}]
-# PC2/GPIFADR2
-set_property PACKAGE_PIN P18 [get_ports {PC[2]}]
+set_property PACKAGE_PIN P18 [get_ports {PC[2]}] ;# PC2/GPIFADR2
set_property IOSTANDARD LVCMOS33 [get_ports {PC[2]}]
-# PC3/GPIFADR3
-set_property PACKAGE_PIN P14 [get_ports {PC[3]}]
+set_property PACKAGE_PIN P14 [get_ports {PC[3]}] ;# PC3/GPIFADR3
set_property IOSTANDARD LVCMOS33 [get_ports {PC[3]}]
-# PC4/GPIFADR4
-set_property PACKAGE_PIN K18 [get_ports {FLASH_DO}]
+set_property PACKAGE_PIN K18 [get_ports {FLASH_DO}] ;# PC4/GPIFADR4
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DO}]
-# PC5/GPIFADR5
-set_property PACKAGE_PIN L13 [get_ports {FLASH_CS}]
+set_property PACKAGE_PIN L13 [get_ports {FLASH_CS}] ;# PC5/GPIFADR5
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CS}]
-# PC6/GPIFADR6
-set_property PACKAGE_PIN E9 [get_ports {FLASH_CLK}]
+set_property PACKAGE_PIN E9 [get_ports {FLASH_CLK}] ;# PC6/GPIFADR6
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CLK}]
-# PC7/GPIFADR7
-set_property PACKAGE_PIN K17 [get_ports {FLASH_DI}]
+set_property PACKAGE_PIN K17 [get_ports {FLASH_DI}] ;# PC7/GPIFADR7
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DI}]
-# PE0/T0OUT
-set_property PACKAGE_PIN P10 [get_ports {PE[0]}]
+set_property PACKAGE_PIN P10 [get_ports {PE[0]}] ;# PE0/T0OUT
set_property IOSTANDARD LVCMOS33 [get_ports {PE[0]}]
-# PE1/T1OUT
-set_property PACKAGE_PIN P7 [get_ports {PE[1]}]
+set_property PACKAGE_PIN P7 [get_ports {PE[1]}] ;# PE1/T1OUT
set_property IOSTANDARD LVCMOS33 [get_ports {PE[1]}]
-# PE2/T2OUT
-set_property PACKAGE_PIN V15 [get_ports {PE[2]}]
+set_property PACKAGE_PIN V15 [get_ports {PE[2]}] ;# PE2/T2OUT
set_property IOSTANDARD LVCMOS33 [get_ports {PE[2]}]
-# PE5/INT6
-set_property PACKAGE_PIN R16 [get_ports {PE[5]}]
+set_property PACKAGE_PIN R16 [get_ports {PE[5]}] ;# PE5/INT6
set_property IOSTANDARD LVCMOS33 [get_ports {PE[5]}]
-# PE6/T2EX
-set_property PACKAGE_PIN T16 [get_ports {PE[6]}]
+set_property PACKAGE_PIN T16 [get_ports {PE[6]}] ;# PE6/T2EX
set_property IOSTANDARD LVCMOS33 [get_ports {PE[6]}]
-# RDY0/SLRD
-set_property PACKAGE_PIN V16 [get_ports {SLRD}]
+set_property PACKAGE_PIN V16 [get_ports {SLRD}] ;# RDY0/SLRD
set_property IOSTANDARD LVCMOS33 [get_ports {SLRD}]
-# RDY1/SLWR
-set_property PACKAGE_PIN U16 [get_ports {SLWR}]
+set_property PACKAGE_PIN U16 [get_ports {SLWR}] ;# RDY1/SLWR
set_property IOSTANDARD LVCMOS33 [get_ports {SLWR}]
-# RDY2
-set_property PACKAGE_PIN V17 [get_ports {RDY2}]
+set_property PACKAGE_PIN V17 [get_ports {RDY2}] ;# RDY2
set_property IOSTANDARD LVCMOS33 [get_ports {RDY2}]
-# RDY3
-set_property PACKAGE_PIN U17 [get_ports {RDY3}]
+set_property PACKAGE_PIN U17 [get_ports {RDY3}] ;# RDY3
set_property IOSTANDARD LVCMOS33 [get_ports {RDY3}]
-# RDY4
-set_property PACKAGE_PIN U18 [get_ports {RDY4}]
+set_property PACKAGE_PIN U18 [get_ports {RDY4}] ;# RDY4
set_property IOSTANDARD LVCMOS33 [get_ports {RDY4}]
-# RDY5
-set_property PACKAGE_PIN T18 [get_ports {RDY5}]
+set_property PACKAGE_PIN T18 [get_ports {RDY5}] ;# RDY5
set_property IOSTANDARD LVCMOS33 [get_ports {RDY5}]
-# CTL0/FLAGA
-set_property PACKAGE_PIN N16 [get_ports {FLAGA}]
+set_property PACKAGE_PIN N16 [get_ports {FLAGA}] ;# CTL0/FLAGA
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}]
-# CTL1/FLAGB
-set_property PACKAGE_PIN N15 [get_ports {FLAGB}]
+set_property PACKAGE_PIN N15 [get_ports {FLAGB}] ;# CTL1/FLAGB
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGB}]
-# CTL2/FLAGC
-set_property PACKAGE_PIN N14 [get_ports {FLAGC}]
+set_property PACKAGE_PIN N14 [get_ports {FLAGC}] ;# CTL2/FLAGC
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGC}]
-# CTL3
-set_property PACKAGE_PIN N17 [get_ports {CTL3}]
+set_property PACKAGE_PIN N17 [get_ports {CTL3}] ;# CTL3
set_property IOSTANDARD LVCMOS33 [get_ports {CTL3}]
-# CTL4
-set_property PACKAGE_PIN M13 [get_ports {CTL4}]
+set_property PACKAGE_PIN M13 [get_ports {CTL4}] ;# CTL4
set_property IOSTANDARD LVCMOS33 [get_ports {CTL4}]
-# INT4
-set_property PACKAGE_PIN D10 [get_ports {INT4}]
+set_property PACKAGE_PIN D10 [get_ports {INT4}] ;# INT4
set_property IOSTANDARD LVCMOS33 [get_ports {INT4}]
-# INT5#
-set_property PACKAGE_PIN U12 [get_ports {INT5_N}]
+set_property PACKAGE_PIN U12 [get_ports {INT5_N}] ;# INT5#
set_property IOSTANDARD LVCMOS33 [get_ports {INT5_N}]
-# T0
-set_property PACKAGE_PIN M17 [get_ports {T0}]
+set_property PACKAGE_PIN M17 [get_ports {T0}] ;# T0
set_property IOSTANDARD LVCMOS33 [get_ports {T0}]
-# SCL
-set_property PACKAGE_PIN B8 [get_ports {SCL}]
+set_property PACKAGE_PIN B8 [get_ports {SCL}] ;# SCL
set_property IOSTANDARD LVCMOS33 [get_ports {SCL}]
-# SDA
-set_property PACKAGE_PIN A10 [get_ports {SDA}]
+set_property PACKAGE_PIN A10 [get_ports {SDA}] ;# SDA
set_property IOSTANDARD LVCMOS33 [get_ports {SDA}]
-# RxD0
-set_property PACKAGE_PIN A8 [get_ports {RxD0}]
+set_property PACKAGE_PIN A8 [get_ports {RxD0}] ;# RxD0
set_property IOSTANDARD LVCMOS33 [get_ports {RxD0}]
-# TxD0
-set_property PACKAGE_PIN A9 [get_ports {TxD0}]
+set_property PACKAGE_PIN A9 [get_ports {TxD0}] ;# TxD0
set_property IOSTANDARD LVCMOS33 [get_ports {TxD0}]
# external I/O
-
-# A3 / E22~IO_L22P_T3_16
-set_property PACKAGE_PIN K16 [get_ports {IO_A[0]}]
+set_property PACKAGE_PIN K16 [get_ports {IO_A[0]}] ;# A3 / E22~IO_L22P_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[0]}]
-# A4 / C22~IO_L20P_T3_16
-set_property PACKAGE_PIN K15 [get_ports {IO_A[1]}]
+set_property PACKAGE_PIN K15 [get_ports {IO_A[1]}] ;# A4 / C22~IO_L20P_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[1]}]
-# A5 / E21~IO_L23P_T3_16
-set_property PACKAGE_PIN J15 [get_ports {IO_A[2]}]
+set_property PACKAGE_PIN J15 [get_ports {IO_A[2]}] ;# A5 / E21~IO_L23P_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[2]}]
-# A6 / B21~IO_L21P_T3_DQS_16
-set_property PACKAGE_PIN H15 [get_ports {IO_A[3]}]
+set_property PACKAGE_PIN H15 [get_ports {IO_A[3]}] ;# A6 / B21~IO_L21P_T3_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[3]}]
-# A7 / D20~IO_L19P_T3_16
-set_property PACKAGE_PIN J14 [get_ports {IO_A[4]}]
+set_property PACKAGE_PIN J14 [get_ports {IO_A[4]}] ;# A7 / D20~IO_L19P_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[4]}]
-# A8 / B20~IO_L16P_T2_16
-set_property PACKAGE_PIN H17 [get_ports {IO_A[5]}]
+set_property PACKAGE_PIN H17 [get_ports {IO_A[5]}] ;# A8 / B20~IO_L16P_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[5]}]
-# A9 / C19~IO_L13N_T2_MRCC_16
-set_property PACKAGE_PIN G17 [get_ports {IO_A[6]}]
+set_property PACKAGE_PIN G17 [get_ports {IO_A[6]}] ;# A9 / C19~IO_L13N_T2_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[6]}]
-# A10 / C18~IO_L13P_T2_MRCC_16
-set_property PACKAGE_PIN G18 [get_ports {IO_A[7]}]
+set_property PACKAGE_PIN G18 [get_ports {IO_A[7]}] ;# A10 / C18~IO_L13P_T2_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[7]}]
-# A11 / B18~IO_L11N_T1_SRCC_16
-set_property PACKAGE_PIN F18 [get_ports {IO_A[8]}]
+set_property PACKAGE_PIN F18 [get_ports {IO_A[8]}] ;# A11 / B18~IO_L11N_T1_SRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[8]}]
-# A12 / B17~IO_L11P_T1_SRCC_16
-set_property PACKAGE_PIN E18 [get_ports {IO_A[9]}]
+set_property PACKAGE_PIN E18 [get_ports {IO_A[9]}] ;# A12 / B17~IO_L11P_T1_SRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[9]}]
-# A13 / B16~IO_L7N_T1_16
-set_property PACKAGE_PIN D18 [get_ports {IO_A[10]}]
+set_property PACKAGE_PIN D18 [get_ports {IO_A[10]}] ;# A13 / B16~IO_L7N_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[10]}]
-# A14 / A16~IO_L9N_T1_DQS_16
-set_property PACKAGE_PIN G13 [get_ports {IO_A[11]}]
+set_property PACKAGE_PIN G13 [get_ports {IO_A[11]}] ;# A14 / A16~IO_L9N_T1_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[11]}]
-# A18 / A14~IO_L10N_T1_16
-set_property PACKAGE_PIN F13 [get_ports {IO_A[12]}]
+set_property PACKAGE_PIN F13 [get_ports {IO_A[12]}] ;# A18 / A14~IO_L10N_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[12]}]
-# A19 / D15~IO_L6N_T0_VREF_16
-set_property PACKAGE_PIN E16 [get_ports {IO_A[13]}]
+set_property PACKAGE_PIN E16 [get_ports {IO_A[13]}] ;# A19 / D15~IO_L6N_T0_VREF_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[13]}]
-# A20 / B13~IO_L8N_T1_16
-set_property PACKAGE_PIN C17 [get_ports {IO_A[14]}]
+set_property PACKAGE_PIN C17 [get_ports {IO_A[14]}] ;# A20 / B13~IO_L8N_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[14]}]
-# A21 / N3~IO_L19N_T3_VREF_35
-set_property PACKAGE_PIN A18 [get_ports {IO_A[15]}]
+set_property PACKAGE_PIN A18 [get_ports {IO_A[15]}] ;# A21 / N3~IO_L19N_T3_VREF_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[15]}]
-# A22 / H4~IO_L12P_T1_MRCC_35
-set_property PACKAGE_PIN C15 [get_ports {IO_A[16]}]
+set_property PACKAGE_PIN C15 [get_ports {IO_A[16]}] ;# A22 / H4~IO_L12P_T1_MRCC_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[16]}]
-# A23 / G4~IO_L12N_T1_MRCC_35
-set_property PACKAGE_PIN B17 [get_ports {IO_A[17]}]
+set_property PACKAGE_PIN B17 [get_ports {IO_A[17]}] ;# A23 / G4~IO_L12N_T1_MRCC_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[17]}]
-# A24 / E3~IO_L6N_T0_VREF_35
-set_property PACKAGE_PIN C14 [get_ports {IO_A[18]}]
+set_property PACKAGE_PIN C14 [get_ports {IO_A[18]}] ;# A24 / E3~IO_L6N_T0_VREF_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[18]}]
-# A25 / B2~IO_L2N_T0_AD12N_35
-set_property PACKAGE_PIN D13 [get_ports {IO_A[19]}]
+set_property PACKAGE_PIN D13 [get_ports {IO_A[19]}] ;# A25 / B2~IO_L2N_T0_AD12N_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[19]}]
-# A26 / D2~IO_L4N_T0_35
-set_property PACKAGE_PIN A16 [get_ports {IO_A[20]}]
+set_property PACKAGE_PIN A16 [get_ports {IO_A[20]}] ;# A26 / D2~IO_L4N_T0_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[20]}]
-# A27 / G2~IO_L8N_T1_AD14N_35
-set_property PACKAGE_PIN B14 [get_ports {IO_A[21]}]
+set_property PACKAGE_PIN B14 [get_ports {IO_A[21]}] ;# A27 / G2~IO_L8N_T1_AD14N_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[21]}]
-# A28 / A1~IO_L1N_T0_AD4N_35
-set_property PACKAGE_PIN B12 [get_ports {IO_A[22]}]
+set_property PACKAGE_PIN B12 [get_ports {IO_A[22]}] ;# A28 / A1~IO_L1N_T0_AD4N_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[22]}]
-# A29 / D1~IO_L3N_T0_DQS_AD5N_35
-set_property PACKAGE_PIN A14 [get_ports {IO_A[23]}]
+set_property PACKAGE_PIN A14 [get_ports {IO_A[23]}] ;# A29 / D1~IO_L3N_T0_DQS_AD5N_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[23]}]
-# A30 / G1~IO_L5P_T0_AD13P_35
-set_property PACKAGE_PIN B11 [get_ports {IO_A[24]}]
+set_property PACKAGE_PIN B11 [get_ports {IO_A[24]}] ;# A30 / G1~IO_L5P_T0_AD13P_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[24]}]
-# B3 / D22~IO_L22N_T3_16
-set_property PACKAGE_PIN J18 [get_ports {IO_B[0]}]
+set_property PACKAGE_PIN J18 [get_ports {IO_B[0]}] ;# B3 / D22~IO_L22N_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[0]}]
-# B4 / B22~IO_L20N_T3_16
-set_property PACKAGE_PIN J17 [get_ports {IO_B[1]}]
+set_property PACKAGE_PIN J17 [get_ports {IO_B[1]}] ;# B4 / B22~IO_L20N_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[1]}]
-# B5 / D21~IO_L23N_T3_16
-set_property PACKAGE_PIN K13 [get_ports {IO_B[2]}]
+set_property PACKAGE_PIN K13 [get_ports {IO_B[2]}] ;# B5 / D21~IO_L23N_T3_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[2]}]
-# B6 / A21~IO_L21N_T3_DQS_16
-set_property PACKAGE_PIN J13 [get_ports {IO_B[3]}]
+set_property PACKAGE_PIN J13 [get_ports {IO_B[3]}] ;# B6 / A21~IO_L21N_T3_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[3]}]
-# B7 / C20~IO_L19N_T3_VREF_16
-set_property PACKAGE_PIN H14 [get_ports {IO_B[4]}]
+set_property PACKAGE_PIN H14 [get_ports {IO_B[4]}] ;# B7 / C20~IO_L19N_T3_VREF_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[4]}]
-# B8 / A20~IO_L16N_T2_16
-set_property PACKAGE_PIN G14 [get_ports {IO_B[5]}]
+set_property PACKAGE_PIN G14 [get_ports {IO_B[5]}] ;# B8 / A20~IO_L16N_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[5]}]
-# B9 / A19~IO_L17N_T2_16
-set_property PACKAGE_PIN G16 [get_ports {IO_B[6]}]
+set_property PACKAGE_PIN G16 [get_ports {IO_B[6]}] ;# B9 / A19~IO_L17N_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[6]}]
-# B10 / A18~IO_L17P_T2_16
-set_property PACKAGE_PIN H16 [get_ports {IO_B[7]}]
+set_property PACKAGE_PIN H16 [get_ports {IO_B[7]}] ;# B10 / A18~IO_L17P_T2_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[7]}]
-# B11 / D17~IO_L12P_T1_MRCC_16
-set_property PACKAGE_PIN F16 [get_ports {IO_B[8]}]
+set_property PACKAGE_PIN F16 [get_ports {IO_B[8]}] ;# B11 / D17~IO_L12P_T1_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[8]}]
-# B12 / C17~IO_L12N_T1_MRCC_16
-set_property PACKAGE_PIN F15 [get_ports {IO_B[9]}]
+set_property PACKAGE_PIN F15 [get_ports {IO_B[9]}] ;# B12 / C17~IO_L12N_T1_MRCC_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[9]}]
-# B13 / B15~IO_L7P_T1_16
-set_property PACKAGE_PIN E17 [get_ports {IO_B[10]}]
+set_property PACKAGE_PIN E17 [get_ports {IO_B[10]}] ;# B13 / B15~IO_L7P_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[10]}]
-# B14 / A15~IO_L9P_T1_DQS_16
-set_property PACKAGE_PIN D17 [get_ports {IO_B[11]}]
+set_property PACKAGE_PIN D17 [get_ports {IO_B[11]}] ;# B14 / A15~IO_L9P_T1_DQS_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[11]}]
-# B18 / A13~IO_L10P_T1_16
-set_property PACKAGE_PIN F14 [get_ports {IO_B[12]}]
+set_property PACKAGE_PIN F14 [get_ports {IO_B[12]}] ;# B18 / A13~IO_L10P_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[12]}]
-# B19 / D14~IO_L6P_T0_16
-set_property PACKAGE_PIN E15 [get_ports {IO_B[13]}]
+set_property PACKAGE_PIN E15 [get_ports {IO_B[13]}] ;# B19 / D14~IO_L6P_T0_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[13]}]
-# B20 / C13~IO_L8P_T1_16
-set_property PACKAGE_PIN C16 [get_ports {IO_B[14]}]
+set_property PACKAGE_PIN C16 [get_ports {IO_B[14]}] ;# B20 / C13~IO_L8P_T1_16
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[14]}]
-# B21 / H3~IO_L11P_T1_SRCC_35
-set_property PACKAGE_PIN B18 [get_ports {IO_B[15]}]
+set_property PACKAGE_PIN B18 [get_ports {IO_B[15]}] ;# B21 / H3~IO_L11P_T1_SRCC_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[15]}]
-# B22 / G3~IO_L11N_T1_SRCC_35
-set_property PACKAGE_PIN D15 [get_ports {IO_B[16]}]
+set_property PACKAGE_PIN D15 [get_ports {IO_B[16]}] ;# B22 / G3~IO_L11N_T1_SRCC_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[16]}]
-# B23 / F4~IO_0_35
-set_property PACKAGE_PIN B16 [get_ports {IO_B[17]}]
+set_property PACKAGE_PIN B16 [get_ports {IO_B[17]}] ;# B23 / F4~IO_0_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[17]}]
-# B24 / F3~IO_L6P_T0_35
-set_property PACKAGE_PIN D14 [get_ports {IO_B[18]}]
+set_property PACKAGE_PIN D14 [get_ports {IO_B[18]}] ;# B24 / F3~IO_L6P_T0_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[18]}]
-# B25 / C2~IO_L2P_T0_AD12P_35
-set_property PACKAGE_PIN D12 [get_ports {IO_B[19]}]
+set_property PACKAGE_PIN D12 [get_ports {IO_B[19]}] ;# B25 / C2~IO_L2P_T0_AD12P_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[19]}]
-# B26 / E2~IO_L4P_T0_35
-set_property PACKAGE_PIN A15 [get_ports {IO_B[20]}]
+set_property PACKAGE_PIN A15 [get_ports {IO_B[20]}] ;# B26 / E2~IO_L4P_T0_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[20]}]
-# B27 / H2~IO_L8P_T1_AD14P_35
-set_property PACKAGE_PIN B13 [get_ports {IO_B[21]}]
+set_property PACKAGE_PIN B13 [get_ports {IO_B[21]}] ;# B27 / H2~IO_L8P_T1_AD14P_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[21]}]
-# B28 / B1~IO_L1P_T0_AD4P_35
-set_property PACKAGE_PIN C12 [get_ports {IO_B[22]}]
+set_property PACKAGE_PIN C12 [get_ports {IO_B[22]}] ;# B28 / B1~IO_L1P_T0_AD4P_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[22]}]
-# B29 / E1~IO_L3P_T0_DQS_AD5P_35
-set_property PACKAGE_PIN A13 [get_ports {IO_B[23]}]
+set_property PACKAGE_PIN A13 [get_ports {IO_B[23]}] ;# B29 / E1~IO_L3P_T0_DQS_AD5P_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[23]}]
-# B30 / F1~IO_L5N_T0_AD13N_35
-set_property PACKAGE_PIN A11 [get_ports {IO_B[24]}]
+set_property PACKAGE_PIN A11 [get_ports {IO_B[24]}] ;# B30 / F1~IO_L5N_T0_AD13N_35
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[24]}]
-# C3 / AB17~IO_L2N_T0_13
-set_property PACKAGE_PIN U9 [get_ports {IO_C[0]}]
+set_property PACKAGE_PIN U9 [get_ports {IO_C[0]}] ;# C3 / AB17~IO_L2N_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[0]}]
-# C4 / Y16~IO_L1P_T0_13
-set_property PACKAGE_PIN U8 [get_ports {IO_C[1]}]
+set_property PACKAGE_PIN U8 [get_ports {IO_C[1]}] ;# C4 / Y16~IO_L1P_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[1]}]
-# C5 / AA15~IO_L4P_T0_13
-set_property PACKAGE_PIN U7 [get_ports {IO_C[2]}]
+set_property PACKAGE_PIN U7 [get_ports {IO_C[2]}] ;# C5 / AA15~IO_L4P_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[2]}]
-# C6 / Y13~IO_L5P_T0_13
-set_property PACKAGE_PIN U6 [get_ports {IO_C[3]}]
+set_property PACKAGE_PIN U6 [get_ports {IO_C[3]}] ;# C6 / Y13~IO_L5P_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[3]}]
-# C7 / W14~IO_L6P_T0_13
-set_property PACKAGE_PIN T8 [get_ports {IO_C[4]}]
+set_property PACKAGE_PIN T8 [get_ports {IO_C[4]}] ;# C7 / W14~IO_L6P_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[4]}]
-# C8 / AA13~IO_L3P_T0_DQS_13
-set_property PACKAGE_PIN R8 [get_ports {IO_C[5]}]
+set_property PACKAGE_PIN R8 [get_ports {IO_C[5]}] ;# C8 / AA13~IO_L3P_T0_DQS_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[5]}]
-# C9 / AB12~IO_L7N_T1_13
-set_property PACKAGE_PIN R7 [get_ports {IO_C[6]}]
+set_property PACKAGE_PIN R7 [get_ports {IO_C[6]}] ;# C9 / AB12~IO_L7N_T1_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[6]}]
-# C10 / W12~IO_L12N_T1_MRCC_13
-set_property PACKAGE_PIN T6 [get_ports {IO_C[7]}]
+set_property PACKAGE_PIN T6 [get_ports {IO_C[7]}] ;# C10 / W12~IO_L12N_T1_MRCC_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[7]}]
-# C11 / AA11~IO_L9N_T1_DQS_13
-set_property PACKAGE_PIN R6 [get_ports {IO_C[8]}]
+set_property PACKAGE_PIN R6 [get_ports {IO_C[8]}] ;# C11 / AA11~IO_L9N_T1_DQS_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[8]}]
-# C12 / AA9~IO_L8P_T1_13
-set_property PACKAGE_PIN R5 [get_ports {IO_C[9]}]
+set_property PACKAGE_PIN R5 [get_ports {IO_C[9]}] ;# C12 / AA9~IO_L8P_T1_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[9]}]
-# C13 / W9~IO_L24P_T3_34
-set_property PACKAGE_PIN V2 [get_ports {IO_C[10]}]
+set_property PACKAGE_PIN V2 [get_ports {IO_C[10]}] ;# C13 / W9~IO_L24P_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[10]}]
-# C14 / AA8~IO_L22P_T3_34
-set_property PACKAGE_PIN U2 [get_ports {IO_C[11]}]
+set_property PACKAGE_PIN U2 [get_ports {IO_C[11]}] ;# C14 / AA8~IO_L22P_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[11]}]
-# C15 / V7~IO_L19P_T3_34
-set_property PACKAGE_PIN K6 [get_ports {IO_C[12]}]
+set_property PACKAGE_PIN K6 [get_ports {IO_C[12]}] ;# C15 / V7~IO_L19P_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[12]}]
-# C19 / AB6~IO_L20N_T3_34
-set_property PACKAGE_PIN N6 [get_ports {IO_C[13]}]
+set_property PACKAGE_PIN N6 [get_ports {IO_C[13]}] ;# C19 / AB6~IO_L20N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[13]}]
-# C20 / AA5~IO_L10P_T1_34
-set_property PACKAGE_PIN M6 [get_ports {IO_C[14]}]
+set_property PACKAGE_PIN M6 [get_ports {IO_C[14]}] ;# C20 / AA5~IO_L10P_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[14]}]
-# C21 / Y4~IO_L11P_T1_SRCC_34
-set_property PACKAGE_PIN L6 [get_ports {IO_C[15]}]
+set_property PACKAGE_PIN L6 [get_ports {IO_C[15]}] ;# C21 / Y4~IO_L11P_T1_SRCC_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[15]}]
-# C22 / V4~IO_L12P_T1_MRCC_34
-set_property PACKAGE_PIN L5 [get_ports {IO_C[16]}]
+set_property PACKAGE_PIN L5 [get_ports {IO_C[16]}] ;# C22 / V4~IO_L12P_T1_MRCC_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[16]}]
-# C23 / Y3~IO_L9P_T1_DQS_34
-set_property PACKAGE_PIN N4 [get_ports {IO_C[17]}]
+set_property PACKAGE_PIN N4 [get_ports {IO_C[17]}] ;# C23 / Y3~IO_L9P_T1_DQS_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[17]}]
-# C24 / U3~IO_L6P_T0_34
-set_property PACKAGE_PIN M4 [get_ports {IO_C[18]}]
+set_property PACKAGE_PIN M4 [get_ports {IO_C[18]}] ;# C24 / U3~IO_L6P_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[18]}]
-# C25 / AB3~IO_L8P_T1_34
-set_property PACKAGE_PIN M3 [get_ports {IO_C[19]}]
+set_property PACKAGE_PIN M3 [get_ports {IO_C[19]}] ;# C25 / AB3~IO_L8P_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[19]}]
-# C26 / W2~IO_L4P_T0_34
-set_property PACKAGE_PIN M2 [get_ports {IO_C[20]}]
+set_property PACKAGE_PIN M2 [get_ports {IO_C[20]}] ;# C26 / W2~IO_L4P_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[20]}]
-# C27 / U2~IO_L2P_T0_34
-set_property PACKAGE_PIN K5 [get_ports {IO_C[21]}]
+set_property PACKAGE_PIN K5 [get_ports {IO_C[21]}] ;# C27 / U2~IO_L2P_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[21]}]
-# C28 / AA1~IO_L7P_T1_34
-set_property PACKAGE_PIN L4 [get_ports {IO_C[22]}]
+set_property PACKAGE_PIN L4 [get_ports {IO_C[22]}] ;# C28 / AA1~IO_L7P_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[22]}]
-# C29 / W1~IO_L5P_T0_34
-set_property PACKAGE_PIN L3 [get_ports {IO_C[23]}]
+set_property PACKAGE_PIN L3 [get_ports {IO_C[23]}] ;# C29 / W1~IO_L5P_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[23]}]
-# C30 / T1~IO_L1P_T0_34
-set_property PACKAGE_PIN K3 [get_ports {IO_C[24]}]
+set_property PACKAGE_PIN K3 [get_ports {IO_C[24]}] ;# C30 / T1~IO_L1P_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[24]}]
-# D3 / AB16~IO_L2P_T0_13
-set_property PACKAGE_PIN V9 [get_ports {IO_D[0]}]
+set_property PACKAGE_PIN V9 [get_ports {IO_D[0]}] ;# D3 / AB16~IO_L2P_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[0]}]
-# D4 / AA16~IO_L1N_T0_13
-set_property PACKAGE_PIN V7 [get_ports {IO_D[1]}]
+set_property PACKAGE_PIN V7 [get_ports {IO_D[1]}] ;# D4 / AA16~IO_L1N_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[1]}]
-# D5 / AB15~IO_L4N_T0_13
-set_property PACKAGE_PIN V6 [get_ports {IO_D[2]}]
+set_property PACKAGE_PIN V6 [get_ports {IO_D[2]}] ;# D5 / AB15~IO_L4N_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[2]}]
-# D6 / AA14~IO_L5N_T0_13
-set_property PACKAGE_PIN V5 [get_ports {IO_D[3]}]
+set_property PACKAGE_PIN V5 [get_ports {IO_D[3]}] ;# D6 / AA14~IO_L5N_T0_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[3]}]
-# D7 / Y14~IO_L6N_T0_VREF_13
-set_property PACKAGE_PIN V4 [get_ports {IO_D[4]}]
+set_property PACKAGE_PIN V4 [get_ports {IO_D[4]}] ;# D7 / Y14~IO_L6N_T0_VREF_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[4]}]
-# D8 / AB13~IO_L3N_T0_DQS_13
-set_property PACKAGE_PIN T5 [get_ports {IO_D[5]}]
+set_property PACKAGE_PIN T5 [get_ports {IO_D[5]}] ;# D8 / AB13~IO_L3N_T0_DQS_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[5]}]
-# D9 / AB11~IO_L7P_T1_13
-set_property PACKAGE_PIN T4 [get_ports {IO_D[6]}]
+set_property PACKAGE_PIN T4 [get_ports {IO_D[6]}] ;# D9 / AB11~IO_L7P_T1_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[6]}]
-# D10 / W11~IO_L12P_T1_MRCC_13
-set_property PACKAGE_PIN U4 [get_ports {IO_D[7]}]
+set_property PACKAGE_PIN U4 [get_ports {IO_D[7]}] ;# D10 / W11~IO_L12P_T1_MRCC_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[7]}]
-# D11 / AA10~IO_L9P_T1_DQS_13
-set_property PACKAGE_PIN U3 [get_ports {IO_D[8]}]
+set_property PACKAGE_PIN U3 [get_ports {IO_D[8]}] ;# D11 / AA10~IO_L9P_T1_DQS_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[8]}]
-# D12 / AB10~IO_L8N_T1_13
-set_property PACKAGE_PIN V1 [get_ports {IO_D[9]}]
+set_property PACKAGE_PIN V1 [get_ports {IO_D[9]}] ;# D12 / AB10~IO_L8N_T1_13
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[9]}]
-# D13 / Y9~IO_L24N_T3_34
-set_property PACKAGE_PIN U1 [get_ports {IO_D[10]}]
+set_property PACKAGE_PIN U1 [get_ports {IO_D[10]}] ;# D13 / Y9~IO_L24N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[10]}]
-# D14 / AB8~IO_L22N_T3_34
-set_property PACKAGE_PIN T3 [get_ports {IO_D[11]}]
+set_property PACKAGE_PIN T3 [get_ports {IO_D[11]}] ;# D14 / AB8~IO_L22N_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[11]}]
-# D15 / W7~IO_L19N_T3_VREF_34
-set_property PACKAGE_PIN R3 [get_ports {IO_D[12]}]
+set_property PACKAGE_PIN R3 [get_ports {IO_D[12]}] ;# D15 / W7~IO_L19N_T3_VREF_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[12]}]
-# D19 / AB7~IO_L20P_T3_34
-set_property PACKAGE_PIN P5 [get_ports {IO_D[13]}]
+set_property PACKAGE_PIN P5 [get_ports {IO_D[13]}] ;# D19 / AB7~IO_L20P_T3_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[13]}]
-# D20 / AB5~IO_L10N_T1_34
-set_property PACKAGE_PIN N5 [get_ports {IO_D[14]}]
+set_property PACKAGE_PIN N5 [get_ports {IO_D[14]}] ;# D20 / AB5~IO_L10N_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[14]}]
-# D21 / AA4~IO_L11N_T1_SRCC_34
-set_property PACKAGE_PIN P4 [get_ports {IO_D[15]}]
+set_property PACKAGE_PIN P4 [get_ports {IO_D[15]}] ;# D21 / AA4~IO_L11N_T1_SRCC_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[15]}]
-# D22 / W4~IO_L12N_T1_MRCC_34
-set_property PACKAGE_PIN P3 [get_ports {IO_D[16]}]
+set_property PACKAGE_PIN P3 [get_ports {IO_D[16]}] ;# D22 / W4~IO_L12N_T1_MRCC_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[16]}]
-# D23 / AA3~IO_L9N_T1_DQS_34
-set_property PACKAGE_PIN T1 [get_ports {IO_D[17]}]
+set_property PACKAGE_PIN T1 [get_ports {IO_D[17]}] ;# D23 / AA3~IO_L9N_T1_DQS_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[17]}]
-# D24 / V3~IO_L6N_T0_VREF_34
-set_property PACKAGE_PIN R1 [get_ports {IO_D[18]}]
+set_property PACKAGE_PIN R1 [get_ports {IO_D[18]}] ;# D24 / V3~IO_L6N_T0_VREF_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[18]}]
-# D25 / AB2~IO_L8N_T1_34
-set_property PACKAGE_PIN R2 [get_ports {IO_D[19]}]
+set_property PACKAGE_PIN R2 [get_ports {IO_D[19]}] ;# D25 / AB2~IO_L8N_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[19]}]
-# D26 / Y2~IO_L4N_T0_34
-set_property PACKAGE_PIN P2 [get_ports {IO_D[20]}]
+set_property PACKAGE_PIN P2 [get_ports {IO_D[20]}] ;# D26 / Y2~IO_L4N_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[20]}]
-# D27 / V2~IO_L2N_T0_34
-set_property PACKAGE_PIN N2 [get_ports {IO_D[21]}]
+set_property PACKAGE_PIN N2 [get_ports {IO_D[21]}] ;# D27 / V2~IO_L2N_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[21]}]
-# D28 / AB1~IO_L7N_T1_34
-set_property PACKAGE_PIN N1 [get_ports {IO_D[22]}]
+set_property PACKAGE_PIN N1 [get_ports {IO_D[22]}] ;# D28 / AB1~IO_L7N_T1_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[22]}]
-# D29 / Y1~IO_L5N_T0_34
-set_property PACKAGE_PIN M1 [get_ports {IO_D[23]}]
+set_property PACKAGE_PIN M1 [get_ports {IO_D[23]}] ;# D29 / Y1~IO_L5N_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[23]}]
-# D30 / U1~IO_L1N_T0_34
-set_property PACKAGE_PIN L1 [get_ports {IO_D[24]}]
+set_property PACKAGE_PIN L1 [get_ports {IO_D[24]}] ;# D30 / U1~IO_L1N_T0_34
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[24]}]
/usb-fpga-2.04.xdc
0,0 → 1,418
# !!! Constraint files are application specific !!! |
# !!! This is a template only !!! |
|
# on-board signals |
|
# CLKOUT/FXCLK |
create_clock -name fxclk_in -period 20.833 [get_ports fxclk_in] |
set_property PACKAGE_PIN J16 [get_ports fxclk_in] |
set_property IOSTANDARD LVCMOS33 [get_ports fxclk_in] |
|
# IFCLK |
create_clock -name ifclk_in -period 20.833 [get_ports ifclk_in] |
set_property PACKAGE_PIN J14 [get_ports ifclk_in] |
set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in] |
|
|
set_property PACKAGE_PIN D16 [get_ports {PB[0]}] ;# PB0/FD0 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[0]}] |
|
set_property PACKAGE_PIN F15 [get_ports {PB[1]}] ;# PB1/FD1 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[1]}] |
|
set_property PACKAGE_PIN E15 [get_ports {PB[2]}] ;# PB2/FD2 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[2]}] |
|
set_property PACKAGE_PIN D14 [get_ports {PB[3]}] ;# PB3/FD3 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[3]}] |
|
set_property PACKAGE_PIN F13 [get_ports {PB[4]}] ;# PB4/FD4 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[4]}] |
|
set_property PACKAGE_PIN E12 [get_ports {PB[5]}] ;# PB5/FD5 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[5]}] |
|
set_property PACKAGE_PIN F12 [get_ports {PB[6]}] ;# PB6/FD6 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[6]}] |
|
set_property PACKAGE_PIN G12 [get_ports {PB[7]}] ;# PB7/FD7 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[7]}] |
|
|
set_property PACKAGE_PIN H14 [get_ports {PD[0]}] ;# PD0/FD8 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[0]}] |
|
set_property PACKAGE_PIN J11 [get_ports {PD[1]}] ;# PD1/FD9 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[1]}] |
|
set_property PACKAGE_PIN J12 [get_ports {PD[2]}] ;# PD2/FD10 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[2]}] |
|
set_property PACKAGE_PIN J13 [get_ports {PD[3]}] ;# PD3/FD11 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[3]}] |
|
set_property PACKAGE_PIN K12 [get_ports {PD[4]}] ;# PD4/FD12 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[4]}] |
|
set_property PACKAGE_PIN K15 [get_ports {PD[5]}] ;# PD5/FD13 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[5]}] |
|
set_property PACKAGE_PIN K16 [get_ports {PD[6]}] ;# PD6/FD14 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[6]}] |
|
set_property PACKAGE_PIN M14 [get_ports {PD[7]}] ;# PD7/FD15 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[7]}] |
|
|
set_property PACKAGE_PIN R11 [get_ports {PA[0]}] ;# PA0/INT0# |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}] |
|
set_property PACKAGE_PIN T10 [get_ports {PA[1]}] ;# PA1/INT1# |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}] |
|
set_property PACKAGE_PIN H13 [get_ports {PA[2]}] ;# PA2/SLOE |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}] |
|
set_property PACKAGE_PIN T3 [get_ports {PA[3]}] ;# PA3/WU2 |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}] |
|
set_property PACKAGE_PIN T11 [get_ports {PA[4]}] ;# PA4/FIFOADR0 |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}] |
|
set_property PACKAGE_PIN N11 [get_ports {PA[5]}] ;# PA5/FIFOADR1 |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}] |
|
set_property PACKAGE_PIN T5 [get_ports {PA[6]}] ;# PA6/PKTEND |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}] |
|
set_property PACKAGE_PIN R3 [get_ports {PA[7]}] ;# PA7/FLAGD/SLCS# |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}] |
|
|
set_property PACKAGE_PIN P10 [get_ports {PC[0]}] ;# PC0/GPIFADR0 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}] |
|
set_property PACKAGE_PIN N12 [get_ports {PC[1]}] ;# PC1/GPIFADR1 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}] |
|
set_property PACKAGE_PIN P12 [get_ports {PC[2]}] ;# PC2/GPIFADR2 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[2]}] |
|
set_property PACKAGE_PIN N5 [get_ports {PC[3]}] ;# PC3/GPIFADR3 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[3]}] |
|
set_property PACKAGE_PIN P5 [get_ports {PC[4]}] ;# PC4/GPIFADR4 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[4]}] |
|
set_property PACKAGE_PIN L8 [get_ports {PC[5]}] ;# PC5/GPIFADR5 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[5]}] |
|
set_property PACKAGE_PIN L7 [get_ports {PC[6]}] ;# PC6/GPIFADR6 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[6]}] |
|
set_property PACKAGE_PIN R5 [get_ports {PC[7]}] ;# PC7/GPIFADR7 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[7]}] |
|
|
set_property PACKAGE_PIN H16 [get_ports {SLRD}] ;# RDY0/SLRD |
set_property IOSTANDARD LVCMOS33 [get_ports {SLRD}] |
|
set_property PACKAGE_PIN H15 [get_ports {SLWR}] ;# RDY1/SLWR |
set_property IOSTANDARD LVCMOS33 [get_ports {SLWR}] |
|
|
set_property PACKAGE_PIN G14 [get_ports {FLAGA}] ;# CTL0/FLAGA |
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}] |
|
set_property PACKAGE_PIN G16 [get_ports {FLAGB}] ;# CTL1/FLAGB |
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGB}] |
|
set_property PACKAGE_PIN H11 [get_ports {FLAGC}] ;# CTL2/FLAGC |
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGC}] |
|
set_property PACKAGE_PIN G11 [get_ports {CTL3}] ;# CTL3 |
set_property IOSTANDARD LVCMOS33 [get_ports {CTL3}] |
|
|
set_property PACKAGE_PIN F15 [get_ports {SCL}] ;# SCL |
set_property IOSTANDARD LVCMOS33 [get_ports {SCL}] |
|
set_property PACKAGE_PIN E16 [get_ports {SDA}] ;# SDA |
set_property IOSTANDARD LVCMOS33 [get_ports {SDA}] |
|
|
set_property PACKAGE_PIN E13 [get_ports {RxD1}] ;# RxD1 |
set_property IOSTANDARD LVCMOS33 [get_ports {RxD1}] |
|
set_property PACKAGE_PIN F14 [get_ports {TxD1}] ;# TxD1 |
set_property IOSTANDARD LVCMOS33 [get_ports {TxD1}] |
|
|
# external I/O |
|
set_property PACKAGE_PIN B16 [get_ports {IO_A[0]}] ;# A6 / B16~IO_L29N_A22_M1A14_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[0]}] |
|
set_property PACKAGE_PIN B15 [get_ports {IO_A[1]}] ;# A7 / B15~IO_L29P_A23_M1A13_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[1]}] |
|
set_property PACKAGE_PIN A14 [get_ports {IO_A[2]}] ;# A8 / A14~IO_L65N_SCP2_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[2]}] |
|
set_property PACKAGE_PIN A13 [get_ports {IO_A[3]}] ;# A9 / A13~IO_L63N_SCP6_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[3]}] |
|
set_property PACKAGE_PIN A12 [get_ports {IO_A[4]}] ;# A10 / A12~IO_L62N_VREF_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[4]}] |
|
set_property PACKAGE_PIN D12 [get_ports {IO_A[5]}] ;# A11 / D12~IO_L66N_SCP0_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[5]}] |
|
set_property PACKAGE_PIN D11 [get_ports {IO_A[6]}] ;# A12 / D11~IO_L66P_SCP1_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[6]}] |
|
set_property PACKAGE_PIN A11 [get_ports {IO_A[7]}] ;# A13 / A11~IO_L39N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[7]}] |
|
set_property PACKAGE_PIN A10 [get_ports {IO_A[8]}] ;# A14 / A10~IO_L35N_GCLK16_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[8]}] |
|
set_property PACKAGE_PIN C10 [get_ports {IO_A[9]}] ;# A18 / C10~IO_L37N_GCLK12_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[9]}] |
|
set_property PACKAGE_PIN D9 [get_ports {IO_A[10]}] ;# A19 / D9~IO_L40N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[10]}] |
|
set_property PACKAGE_PIN A9 [get_ports {IO_A[11]}] ;# A20 / A9~IO_L34N_GCLK18_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[11]}] |
|
set_property PACKAGE_PIN C8 [get_ports {IO_A[12]}] ;# A21 / C8~IO_L38N_VREF_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[12]}] |
|
set_property PACKAGE_PIN A8 [get_ports {IO_A[13]}] ;# A22 / A8~IO_L33N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[13]}] |
|
set_property PACKAGE_PIN E8 [get_ports {IO_A[14]}] ;# A23 / E8~IO_L36N_GCLK14_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[14]}] |
|
set_property PACKAGE_PIN E7 [get_ports {IO_A[15]}] ;# A24 / E7~IO_L36P_GCLK15_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[15]}] |
|
set_property PACKAGE_PIN A7 [get_ports {IO_A[16]}] ;# A25 / A7~IO_L6N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[16]}] |
|
set_property PACKAGE_PIN C6 [get_ports {IO_A[17]}] ;# A26 / C6~IO_L7N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[17]}] |
|
set_property PACKAGE_PIN A6 [get_ports {IO_A[18]}] ;# A27 / A6~IO_L4N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[18]}] |
|
set_property PACKAGE_PIN A5 [get_ports {IO_A[19]}] ;# A28 / A5~IO_L2N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[19]}] |
|
set_property PACKAGE_PIN C5 [get_ports {IO_A[20]}] ;# A29 / C5~IO_L3N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[20]}] |
|
set_property PACKAGE_PIN A4 [get_ports {IO_A[21]}] ;# A30 / A4~IO_L1N_VREF_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[21]}] |
|
|
set_property PACKAGE_PIN C16 [get_ports {IO_B[0]}] ;# B6 / C16~IO_L33N_A14_M1A4_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[0]}] |
|
set_property PACKAGE_PIN C15 [get_ports {IO_B[1]}] ;# B7 / C15~IO_L33P_A15_M1A10_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[1]}] |
|
set_property PACKAGE_PIN B14 [get_ports {IO_B[2]}] ;# B8 / B14~IO_L65P_SCP3_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[2]}] |
|
set_property PACKAGE_PIN C13 [get_ports {IO_B[3]}] ;# B9 / C13~IO_L63P_SCP7_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[3]}] |
|
set_property PACKAGE_PIN B12 [get_ports {IO_B[4]}] ;# B10 / B12~IO_L62P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[4]}] |
|
set_property PACKAGE_PIN E11 [get_ports {IO_B[5]}] ;# B11 / E11~IO_L64N_SCP4_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[5]}] |
|
set_property PACKAGE_PIN F10 [get_ports {IO_B[6]}] ;# B12 / F10~IO_L64P_SCP5_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[6]}] |
|
set_property PACKAGE_PIN C11 [get_ports {IO_B[7]}] ;# B13 / C11~IO_L39P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[7]}] |
|
set_property PACKAGE_PIN B10 [get_ports {IO_B[8]}] ;# B14 / B10~IO_L35P_GCLK17_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[8]}] |
|
set_property PACKAGE_PIN E10 [get_ports {IO_B[9]}] ;# B18 / E10~IO_L37P_GCLK13_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[9]}] |
|
set_property PACKAGE_PIN F9 [get_ports {IO_B[10]}] ;# B19 / F9~IO_L40P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[10]}] |
|
set_property PACKAGE_PIN C9 [get_ports {IO_B[11]}] ;# B20 / C9~IO_L34P_GCLK19_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[11]}] |
|
set_property PACKAGE_PIN D8 [get_ports {IO_B[12]}] ;# B21 / D8~IO_L38P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[12]}] |
|
set_property PACKAGE_PIN B8 [get_ports {IO_B[13]}] ;# B22 / B8~IO_L33P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[13]}] |
|
set_property PACKAGE_PIN F7 [get_ports {IO_B[14]}] ;# B23 / F7~IO_L5P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[14]}] |
|
set_property PACKAGE_PIN E6 [get_ports {IO_B[15]}] ;# B24 / E6~IO_L5N_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[15]}] |
|
set_property PACKAGE_PIN C7 [get_ports {IO_B[16]}] ;# B25 / C7~IO_L6P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[16]}] |
|
set_property PACKAGE_PIN D6 [get_ports {IO_B[17]}] ;# B26 / D6~IO_L7P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[17]}] |
|
set_property PACKAGE_PIN B6 [get_ports {IO_B[18]}] ;# B27 / B6~IO_L4P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[18]}] |
|
set_property PACKAGE_PIN B5 [get_ports {IO_B[19]}] ;# B28 / B5~IO_L2P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[19]}] |
|
set_property PACKAGE_PIN D5 [get_ports {IO_B[20]}] ;# B29 / D5~IO_L3P_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[20]}] |
|
set_property PACKAGE_PIN C4 [get_ports {IO_B[21]}] ;# B30 / C4~IO_L1P_HSWAPEN_0 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[21]}] |
|
|
set_property PACKAGE_PIN R15 [get_ports {IO_C[0]}] ;# C6 / R15~IO_L49P_M1DQ10_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[0]}] |
|
set_property PACKAGE_PIN N16 [get_ports {IO_C[1]}] ;# C7 / N16~IO_L45N_A0_M1LDQSN_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[1]}] |
|
set_property PACKAGE_PIN N14 [get_ports {IO_C[2]}] ;# C8 / N14~IO_L45P_A1_M1LDQS_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[2]}] |
|
set_property PACKAGE_PIN T15 [get_ports {IO_C[3]}] ;# C9 / T15~IO_L50N_M1UDQSN_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[3]}] |
|
set_property PACKAGE_PIN R14 [get_ports {IO_C[4]}] ;# C10 / R14~IO_L50P_M1UDQS_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[4]}] |
|
set_property PACKAGE_PIN R12 [get_ports {IO_C[5]}] ;# C11 / R12~IO_L52P_M1DQ14_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[5]}] |
|
set_property PACKAGE_PIN L16 [get_ports {IO_C[6]}] ;# C12 / L16~IO_L47N_LDC_M1DQ1_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[6]}] |
|
set_property PACKAGE_PIN L14 [get_ports {IO_C[7]}] ;# C13 / L14~IO_L47P_FWE_B_M1DQ0_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[7]}] |
|
set_property PACKAGE_PIN L13 [get_ports {IO_C[8]}] ;# C14 / L13~IO_L53N_VREF_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[8]}] |
|
set_property PACKAGE_PIN L12 [get_ports {IO_C[9]}] ;# C15 / L12~IO_L53P_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[9]}] |
|
set_property PACKAGE_PIN M11 [get_ports {IO_C[10]}] ;# C19 / M11~IO_L2N_CMPMOSI_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[10]}] |
|
set_property PACKAGE_PIN K11 [get_ports {IO_C[11]}] ;# C20 / K11~IO_L42N_GCLK6_TRDY1_M1LDM_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[11]}] |
|
set_property PACKAGE_PIN L10 [get_ports {IO_C[12]}] ;# C21 / L10~IO_L16P_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[12]}] |
|
set_property PACKAGE_PIN P9 [get_ports {IO_C[13]}] ;# C22 / P9~IO_L14N_D12_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[13]}] |
|
set_property PACKAGE_PIN N9 [get_ports {IO_C[14]}] ;# C23 / N9~IO_L14P_D11_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[14]}] |
|
set_property PACKAGE_PIN M9 [get_ports {IO_C[15]}] ;# C24 / M9~IO_L29P_GCLK3_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[15]}] |
|
set_property PACKAGE_PIN N8 [get_ports {IO_C[16]}] ;# C25 / N8~IO_L29N_GCLK2_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[16]}] |
|
set_property PACKAGE_PIN R7 [get_ports {IO_C[17]}] ;# C26 / R7~IO_L32P_GCLK29_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[17]}] |
|
set_property PACKAGE_PIN M7 [get_ports {IO_C[18]}] ;# C27 / M7~IO_L31N_GCLK30_D15_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[18]}] |
|
set_property PACKAGE_PIN P6 [get_ports {IO_C[19]}] ;# C28 / P6~IO_L47P_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[19]}] |
|
set_property PACKAGE_PIN M6 [get_ports {IO_C[20]}] ;# C29 / M6~IO_L64P_D8_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[20]}] |
|
set_property PACKAGE_PIN P4 [get_ports {IO_C[21]}] ;# C30 / P4~IO_L63P_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[21]}] |
|
|
set_property PACKAGE_PIN R16 [get_ports {IO_D[0]}] ;# D6 / R16~IO_L49N_M1DQ11_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[0]}] |
|
set_property PACKAGE_PIN P16 [get_ports {IO_D[1]}] ;# D7 / P16~IO_L48N_M1DQ9_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[1]}] |
|
set_property PACKAGE_PIN P15 [get_ports {IO_D[2]}] ;# D8 / P15~IO_L48P_HDC_M1DQ8_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[2]}] |
|
set_property PACKAGE_PIN T14 [get_ports {IO_D[3]}] ;# D9 / T14~IO_L51P_M1DQ12_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[3]}] |
|
set_property PACKAGE_PIN T13 [get_ports {IO_D[4]}] ;# D10 / T13~IO_L51N_M1DQ13_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[4]}] |
|
set_property PACKAGE_PIN T12 [get_ports {IO_D[5]}] ;# D11 / T12~IO_L52N_M1DQ15_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[5]}] |
|
set_property PACKAGE_PIN M16 [get_ports {IO_D[6]}] ;# D12 / M16~IO_L46N_FOE_B_M1DQ3_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[6]}] |
|
set_property PACKAGE_PIN M15 [get_ports {IO_D[7]}] ;# D13 / M15~IO_L46P_FCS_B_M1DQ2_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[7]}] |
|
set_property PACKAGE_PIN K14 [get_ports {IO_D[8]}] ;# D14 / K14~IO_L41N_GCLK8_M1CASN_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[8]}] |
|
set_property PACKAGE_PIN M13 [get_ports {IO_D[9]}] ;# D15 / M13~IO_L74P_AWAKE_1 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[9]}] |
|
set_property PACKAGE_PIN M12 [get_ports {IO_D[10]}] ;# D19 / M12~IO_L2P_CMPCLK_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[10]}] |
|
set_property PACKAGE_PIN P11 [get_ports {IO_D[11]}] ;# D20 / P11~IO_L13N_D10_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[11]}] |
|
set_property PACKAGE_PIN M10 [get_ports {IO_D[12]}] ;# D21 / M10~IO_L16N_VREF_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[12]}] |
|
set_property PACKAGE_PIN T9 [get_ports {IO_D[13]}] ;# D22 / T9~IO_L23N_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[13]}] |
|
set_property PACKAGE_PIN R9 [get_ports {IO_D[14]}] ;# D23 / R9~IO_L23P_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[14]}] |
|
set_property PACKAGE_PIN T8 [get_ports {IO_D[15]}] ;# D24 / T8~IO_L30N_GCLK0_USERCCLK_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[15]}] |
|
set_property PACKAGE_PIN P8 [get_ports {IO_D[16]}] ;# D25 / P8~IO_L30P_GCLK1_D13_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[16]}] |
|
set_property PACKAGE_PIN T7 [get_ports {IO_D[17]}] ;# D26 / T7~IO_L32N_GCLK28_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[17]}] |
|
set_property PACKAGE_PIN P7 [get_ports {IO_D[18]}] ;# D27 / P7~IO_L31P_GCLK31_D14_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[18]}] |
|
set_property PACKAGE_PIN T6 [get_ports {IO_D[19]}] ;# D28 / T6~IO_L47N_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[19]}] |
|
set_property PACKAGE_PIN N6 [get_ports {IO_D[20]}] ;# D29 / N6~IO_L64N_D9_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[20]}] |
|
set_property PACKAGE_PIN T4 [get_ports {IO_D[21]}] ;# D30 / T4~IO_L63N_2 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[21]}] |
/usb-fpga-2.04.txt
0,0 → 1,143
A6 B16~IO_L29N_A22_M1A14_1 B16 |
B6 C16~IO_L33N_A14_M1A4_1 C16 |
A7 B15~IO_L29P_A23_M1A13_1 B15 |
B7 C15~IO_L33P_A15_M1A10_1 C15 |
A8 A14~IO_L65N_SCP2_0 A14 |
B8 B14~IO_L65P_SCP3_0 B14 |
A9 A13~IO_L63N_SCP6_0 A13 |
B9 C13~IO_L63P_SCP7_0 C13 |
A10 A12~IO_L62N_VREF_0 A12 |
B10 B12~IO_L62P_0 B12 |
A11 D12~IO_L66N_SCP0_0 D12 |
B11 E11~IO_L64N_SCP4_0 E11 |
A12 D11~IO_L66P_SCP1_0 D11 |
B12 F10~IO_L64P_SCP5_0 F10 |
A13 A11~IO_L39N_0 A11 |
B13 C11~IO_L39P_0 C11 |
A14 A10~IO_L35N_GCLK16_0 A10 |
B14 B10~IO_L35P_GCLK17_0 B10 |
A18 C10~IO_L37N_GCLK12_0 C10 |
B18 E10~IO_L37P_GCLK13_0 E10 |
A19 D9~IO_L40N_0 D9 |
B19 F9~IO_L40P_0 F9 |
A20 A9~IO_L34N_GCLK18_0 A9 |
B20 C9~IO_L34P_GCLK19_0 C9 |
A21 C8~IO_L38N_VREF_0 C8 |
B21 D8~IO_L38P_0 D8 |
A22 A8~IO_L33N_0 A8 |
B22 B8~IO_L33P_0 B8 |
A23 E8~IO_L36N_GCLK14_0 E8 |
B23 F7~IO_L5P_0 F7 |
A24 E7~IO_L36P_GCLK15_0 E7 |
B24 E6~IO_L5N_0 E6 |
A25 A7~IO_L6N_0 A7 |
B25 C7~IO_L6P_0 C7 |
A26 C6~IO_L7N_0 C6 |
B26 D6~IO_L7P_0 D6 |
A27 A6~IO_L4N_0 A6 |
B27 B6~IO_L4P_0 B6 |
A28 A5~IO_L2N_0 A5 |
B28 B5~IO_L2P_0 B5 |
A29 C5~IO_L3N_0 C5 |
B29 D5~IO_L3P_0 D5 |
A30 A4~IO_L1N_VREF_0 A4 |
B30 C4~IO_L1P_HSWAPEN_0 C4 |
|
C6 R15~IO_L49P_M1DQ10_1 R15 |
D6 R16~IO_L49N_M1DQ11_1 R16 |
C7 N16~IO_L45N_A0_M1LDQSN_1 N16 |
D7 P16~IO_L48N_M1DQ9_1 P16 |
C8 N14~IO_L45P_A1_M1LDQS_1 N14 |
D8 P15~IO_L48P_HDC_M1DQ8_1 P15 |
C9 T15~IO_L50N_M1UDQSN_1 T15 |
D9 T14~IO_L51P_M1DQ12_1 T14 |
C10 R14~IO_L50P_M1UDQS_1 R14 |
D10 T13~IO_L51N_M1DQ13_1 T13 |
C11 R12~IO_L52P_M1DQ14_1 R12 |
D11 T12~IO_L52N_M1DQ15_1 T12 |
C12 L16~IO_L47N_LDC_M1DQ1_1 L16 |
D12 M16~IO_L46N_FOE_B_M1DQ3_1 M16 |
C13 L14~IO_L47P_FWE_B_M1DQ0_1 L14 |
D13 M15~IO_L46P_FCS_B_M1DQ2_1 M15 |
C14 L13~IO_L53N_VREF_1 L13 |
D14 K14~IO_L41N_GCLK8_M1CASN_1 K14 |
C15 L12~IO_L53P_1 L12 |
D15 M13~IO_L74P_AWAKE_1 M13 |
C19 M11~IO_L2N_CMPMOSI_2 M11 |
D19 M12~IO_L2P_CMPCLK_2 M12 |
C20 K11~IO_L42N_GCLK6_TRDY1_M1LDM_1 K11 |
D20 P11~IO_L13N_D10_2 P11 |
C21 L10~IO_L16P_2 L10 |
D21 M10~IO_L16N_VREF_2 M10 |
C22 P9~IO_L14N_D12_2 P9 |
D22 T9~IO_L23N_2 T9 |
C23 N9~IO_L14P_D11_2 N9 |
D23 R9~IO_L23P_2 R9 |
C24 M9~IO_L29P_GCLK3_2 M9 |
D24 T8~IO_L30N_GCLK0_USERCCLK_2 T8 |
C25 N8~IO_L29N_GCLK2_2 N8 |
D25 P8~IO_L30P_GCLK1_D13_2 P8 |
C26 R7~IO_L32P_GCLK29_2 R7 |
D26 T7~IO_L32N_GCLK28_2 T7 |
C27 M7~IO_L31N_GCLK30_D15_2 M7 |
D27 P7~IO_L31P_GCLK31_D14_2 P7 |
C28 P6~IO_L47P_2 P6 |
D28 T6~IO_L47N_2 T6 |
C29 M6~IO_L64P_D8_2 M6 |
D29 N6~IO_L64N_D9_2 N6 |
C30 P4~IO_L63P_2 P4 |
D30 T4~IO_L63N_2 T4 |
|
- CLKOUT/FXCLK J16 |
|
- IFCLK J14 |
|
- PB0/FD0 D16 |
- PB1/FD1 F15 |
- PB2/FD2 E15 |
- PB3/FD3 D14 |
- PB4/FD4 F13 |
- PB5/FD5 E12 |
- PB6/FD6 F12 |
- PB7/FD7 G12 |
|
- PD0/FD8 H14 |
- PD1/FD9 J11 |
- PD2/FD10 J12 |
- PD3/FD11 J13 |
- PD4/FD12 K12 |
- PD5/FD13 K15 |
- PD6/FD14 K16 |
- PD7/FD15 M14 |
|
- PA0/INT0# R11 |
- PA1/INT1# T10 |
- PA2/*SLOE H13 |
- PA3/*WU2 T3 |
- PA4/FIFOADR0 T11 |
- PA5/FIFOADR1 N11 |
- PA6/*PKTEND T5 |
- PA7/*FLAGD/SLCS# R3 |
|
- PC0/GPIFADR0 P10 |
- PC1/GPIFADR1 N12 |
- PC2/GPIFADR2 P12 |
- PC3/GPIFADR3 N5 |
- PC4/GPIFADR4 P5 |
- PC5/GPIFADR5 L8 |
- PC6/GPIFADR6 L7 |
- PC7/GPIFADR7 R5 |
|
- RDY0/*SLRD H16 |
- RDY1/*SLWR H15 |
|
- CTL0/*FLAGA G14 |
- CTL1/*FLAGB G16 |
- CTL2/*FLAGC H11 |
- CTL3 G11 |
|
- SCL F15 |
- SDA E16 |
|
- RxD1 E13 |
- TxD1 F14 |
/usb-fpga-2.13.txt
0,0 → 1,180
A3 E22~IO_L22P_T3_16 K16 |
B3 D22~IO_L22N_T3_16 J18 |
A4 C22~IO_L20P_T3_16 K15 |
B4 B22~IO_L20N_T3_16 J17 |
A5 E21~IO_L23P_T3_16 J15 |
B5 D21~IO_L23N_T3_16 K13 |
A6 B21~IO_L21P_T3_DQS_16 H15 |
B6 A21~IO_L21N_T3_DQS_16 J13 |
A7 D20~IO_L19P_T3_16 J14 |
B7 C20~IO_L19N_T3_VREF_16 H14 |
A8 B20~IO_L16P_T2_16 H17 |
B8 A20~IO_L16N_T2_16 G14 |
A9 C19~IO_L13N_T2_MRCC_16 G17 |
B9 A19~IO_L17N_T2_16 G16 |
A10 C18~IO_L13P_T2_MRCC_16 G18 |
B10 A18~IO_L17P_T2_16 H16 |
A11 B18~IO_L11N_T1_SRCC_16 F18 |
B11 D17~IO_L12P_T1_MRCC_16 F16 |
A12 B17~IO_L11P_T1_SRCC_16 E18 |
B12 C17~IO_L12N_T1_MRCC_16 F15 |
A13 B16~IO_L7N_T1_16 D18 |
B13 B15~IO_L7P_T1_16 E17 |
A14 A16~IO_L9N_T1_DQS_16 G13 |
B14 A15~IO_L9P_T1_DQS_16 D17 |
A18 A14~IO_L10N_T1_16 F13 |
B18 A13~IO_L10P_T1_16 F14 |
A19 D15~IO_L6N_T0_VREF_16 E16 |
B19 D14~IO_L6P_T0_16 E15 |
A20 B13~IO_L8N_T1_16 C17 |
B20 C13~IO_L8P_T1_16 C16 |
A21 N3~IO_L19N_T3_VREF_35 A18 |
B21 H3~IO_L11P_T1_SRCC_35 B18 |
A22 H4~IO_L12P_T1_MRCC_35 C15 |
B22 G3~IO_L11N_T1_SRCC_35 D15 |
A23 G4~IO_L12N_T1_MRCC_35 B17 |
B23 F4~IO_0_35 B16 |
A24 E3~IO_L6N_T0_VREF_35 C14 |
B24 F3~IO_L6P_T0_35 D14 |
A25 B2~IO_L2N_T0_AD12N_35 D13 |
B25 C2~IO_L2P_T0_AD12P_35 D12 |
A26 D2~IO_L4N_T0_35 A16 |
B26 E2~IO_L4P_T0_35 A15 |
A27 G2~IO_L8N_T1_AD14N_35 B14 |
B27 H2~IO_L8P_T1_AD14P_35 B13 |
A28 A1~IO_L1N_T0_AD4N_35 B12 |
B28 B1~IO_L1P_T0_AD4P_35 C12 |
A29 D1~IO_L3N_T0_DQS_AD5N_35 A14 |
B29 E1~IO_L3P_T0_DQS_AD5P_35 A13 |
A30 G1~IO_L5P_T0_AD13P_35 B11 |
B30 F1~IO_L5N_T0_AD13N_35 A11 |
|
C3 AB17~IO_L2N_T0_13 U9 |
D3 AB16~IO_L2P_T0_13 V9 |
C4 Y16~IO_L1P_T0_13 U8 |
D4 AA16~IO_L1N_T0_13 V7 |
C5 AA15~IO_L4P_T0_13 U7 |
D5 AB15~IO_L4N_T0_13 V6 |
C6 Y13~IO_L5P_T0_13 U6 |
D6 AA14~IO_L5N_T0_13 V5 |
C7 W14~IO_L6P_T0_13 T8 |
D7 Y14~IO_L6N_T0_VREF_13 V4 |
C8 AA13~IO_L3P_T0_DQS_13 R8 |
D8 AB13~IO_L3N_T0_DQS_13 T5 |
C9 AB12~IO_L7N_T1_13 R7 |
D9 AB11~IO_L7P_T1_13 T4 |
C10 W12~IO_L12N_T1_MRCC_13 T6 |
D10 W11~IO_L12P_T1_MRCC_13 U4 |
C11 AA11~IO_L9N_T1_DQS_13 R6 |
D11 AA10~IO_L9P_T1_DQS_13 U3 |
C12 AA9~IO_L8P_T1_13 R5 |
D12 AB10~IO_L8N_T1_13 V1 |
C13 W9~IO_L24P_T3_34 V2 |
D13 Y9~IO_L24N_T3_34 U1 |
C14 AA8~IO_L22P_T3_34 U2 |
D14 AB8~IO_L22N_T3_34 T3 |
C15 V7~IO_L19P_T3_34 K6 |
D15 W7~IO_L19N_T3_VREF_34 R3 |
C16 VCCO_CD |
D16 VCCO_CD |
C17 GND |
D17 GND |
C18 3.3V |
D18 3.3V |
C19 AB6~IO_L20N_T3_34 N6 |
D19 AB7~IO_L20P_T3_34 P5 |
C20 AA5~IO_L10P_T1_34 M6 |
D20 AB5~IO_L10N_T1_34 N5 |
C21 Y4~IO_L11P_T1_SRCC_34 L6 |
D21 AA4~IO_L11N_T1_SRCC_34 P4 |
C22 V4~IO_L12P_T1_MRCC_34 L5 |
D22 W4~IO_L12N_T1_MRCC_34 P3 |
C23 Y3~IO_L9P_T1_DQS_34 N4 |
D23 AA3~IO_L9N_T1_DQS_34 T1 |
C24 U3~IO_L6P_T0_34 M4 |
D24 V3~IO_L6N_T0_VREF_34 R1 |
C25 AB3~IO_L8P_T1_34 M3 |
D25 AB2~IO_L8N_T1_34 R2 |
C26 W2~IO_L4P_T0_34 M2 |
D26 Y2~IO_L4N_T0_34 P2 |
C27 U2~IO_L2P_T0_34 K5 |
D27 V2~IO_L2N_T0_34 N2 |
C28 AA1~IO_L7P_T1_34 L4 |
D28 AB1~IO_L7N_T1_34 N1 |
C29 W1~IO_L5P_T0_34 L3 |
D29 Y1~IO_L5N_T0_34 M1 |
C30 T1~IO_L1P_T0_34 K3 |
D30 U1~IO_L1N_T0_34 L1 |
|
- CLKOUT/FXCLK P15 |
|
- IFCLK P17 |
|
- PB0/FD0 M16 |
- PB1/FD1 L16 |
- PB2/FD2 L14 |
- PB3/FD3 M14 |
- PB4/FD4 L18 |
- PB5/FD5 M18 |
- PB6/FD6 R12 |
- PB7/FD7 R13 |
|
- PD0/FD8 T9 |
- PD1/FD9 V10 |
- PD2/FD10 U11 |
- PD3/FD11 V11 |
- PD4/FD12 V12 |
- PD5/FD13 U13 |
- PD6/FD14 U14 |
- PD7/FD15 V14 |
|
- PA0/INT0# R15 |
- PA1/INT1# T15 |
- PA2/*SLOE T14 |
- PA3/*WU2 T13 |
- PA4/FIFOADR0 R11 |
- PA5/FIFOADR1 T11 |
- PA6/*PKTEND R10 |
- PA7/*FLAGD/SLCS# T10 |
|
- PC0/GPIFADR0 R17 |
- PC1/GPIFADR1 R18 |
- PC2/GPIFADR2 P18 |
- PC3/GPIFADR3 P14 |
- PC4/GPIFADR4 K18 |
- PC5/GPIFADR5 L13 |
- PC6/GPIFADR6 E9 |
- PC7/GPIFADR7 K17 |
|
- PE0/T0OUT P10 |
- PE1/T1OUT P7 |
- PE2/T2OUT V15 |
- PE3/RXD0OUT |
- PE4/RXD1OUT |
- PE5/INT6 R16 |
- PE6/T2EX T16 |
- PE7/GPIFADR8 |
|
- RDY0/*SLRD V16 |
- RDY1/*SLWR U16 |
- RDY2 V17 |
- RDY3 U17 |
- RDY4 U18 |
- RDY5 T18 |
|
- CTL0/*FLAGA N16 |
- CTL1/*FLAGB N15 |
- CTL2/*FLAGC N14 |
- CTL3 N17 |
- CTL4 M13 |
- CTL5 |
|
- INT4 D10 |
- INT5# U12 |
- T0 M17 |
|
- SCL B8 |
- SDA A10 |
|
- RxD0 A8 |
- TxD0 A9 |
/usb-fpga-2.16.xdc
14,638 → 14,482
set_property IOSTANDARD LVCMOS33 [get_ports ifclk_in] |
|
|
# PB0/FD0 |
set_property PACKAGE_PIN P20 [get_ports {PB[0]}] |
set_property PACKAGE_PIN P20 [get_ports {PB[0]}] ;# PB0/FD0 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[0]}] |
|
# PB1/FD1 |
set_property PACKAGE_PIN N17 [get_ports {PB[1]}] |
set_property PACKAGE_PIN N17 [get_ports {PB[1]}] ;# PB1/FD1 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[1]}] |
|
# PB2/FD2 |
set_property PACKAGE_PIN P21 [get_ports {PB[2]}] |
set_property PACKAGE_PIN P21 [get_ports {PB[2]}] ;# PB2/FD2 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[2]}] |
|
# PB3/FD3 |
set_property PACKAGE_PIN R21 [get_ports {PB[3]}] |
set_property PACKAGE_PIN R21 [get_ports {PB[3]}] ;# PB3/FD3 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[3]}] |
|
# PB4/FD4 |
set_property PACKAGE_PIN T21 [get_ports {PB[4]}] |
set_property PACKAGE_PIN T21 [get_ports {PB[4]}] ;# PB4/FD4 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[4]}] |
|
# PB5/FD5 |
set_property PACKAGE_PIN U21 [get_ports {PB[5]}] |
set_property PACKAGE_PIN U21 [get_ports {PB[5]}] ;# PB5/FD5 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[5]}] |
|
# PB6/FD6 |
set_property PACKAGE_PIN P19 [get_ports {PB[6]}] |
set_property PACKAGE_PIN P19 [get_ports {PB[6]}] ;# PB6/FD6 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[6]}] |
|
# PB7/FD7 |
set_property PACKAGE_PIN R19 [get_ports {PB[7]}] |
set_property PACKAGE_PIN R19 [get_ports {PB[7]}] ;# PB7/FD7 |
set_property IOSTANDARD LVCMOS33 [get_ports {PB[7]}] |
|
|
# PD0/FD8 |
set_property PACKAGE_PIN T20 [get_ports {PD[0]}] |
set_property PACKAGE_PIN T20 [get_ports {PD[0]}] ;# PD0/FD8 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[0]}] |
|
# PD1/FD9 |
set_property PACKAGE_PIN U20 [get_ports {PD[1]}] |
set_property PACKAGE_PIN U20 [get_ports {PD[1]}] ;# PD1/FD9 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[1]}] |
|
# PD2/FD10 |
set_property PACKAGE_PIN U18 [get_ports {PD[2]}] |
set_property PACKAGE_PIN U18 [get_ports {PD[2]}] ;# PD2/FD10 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[2]}] |
|
# PD3/FD11 |
set_property PACKAGE_PIN U17 [get_ports {PD[3]}] |
set_property PACKAGE_PIN U17 [get_ports {PD[3]}] ;# PD3/FD11 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[3]}] |
|
# PD4/FD12 |
set_property PACKAGE_PIN W19 [get_ports {PD[4]}] |
set_property PACKAGE_PIN W19 [get_ports {PD[4]}] ;# PD4/FD12 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[4]}] |
|
# PD5/FD13 |
set_property PACKAGE_PIN W20 [get_ports {PD[5]}] |
set_property PACKAGE_PIN W20 [get_ports {PD[5]}] ;# PD5/FD13 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[5]}] |
|
# PD6/FD14 |
set_property PACKAGE_PIN W21 [get_ports {PD[6]}] |
set_property PACKAGE_PIN W21 [get_ports {PD[6]}] ;# PD6/FD14 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[6]}] |
|
# PD7/FD15 |
set_property PACKAGE_PIN W22 [get_ports {PD[7]}] |
set_property PACKAGE_PIN W22 [get_ports {PD[7]}] ;# PD7/FD15 |
set_property IOSTANDARD LVCMOS33 [get_ports {PD[7]}] |
|
|
# PA0/INT0# |
set_property PACKAGE_PIN M22 [get_ports {PA[0]}] |
set_property PACKAGE_PIN M22 [get_ports {PA[0]}] ;# PA0/INT0# |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}] |
|
# PA1/INT1# |
set_property PACKAGE_PIN M21 [get_ports {PA[1]}] |
set_property PACKAGE_PIN M21 [get_ports {PA[1]}] ;# PA1/INT1# |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}] |
|
# PA2/SLOE |
set_property PACKAGE_PIN M20 [get_ports {PA[2]}] |
set_property PACKAGE_PIN M20 [get_ports {PA[2]}] ;# PA2/SLOE |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}] |
|
# PA3/WU2 |
set_property PACKAGE_PIN M18 [get_ports {PA[3]}] |
set_property PACKAGE_PIN M18 [get_ports {PA[3]}] ;# PA3/WU2 |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}] |
|
# PA4/FIFOADR0 |
set_property PACKAGE_PIN N19 [get_ports {PA[4]}] |
set_property PACKAGE_PIN N19 [get_ports {PA[4]}] ;# PA4/FIFOADR0 |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}] |
|
# PA5/FIFOADR1 |
set_property PACKAGE_PIN N18 [get_ports {PA[5]}] |
set_property PACKAGE_PIN N18 [get_ports {PA[5]}] ;# PA5/FIFOADR1 |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}] |
|
# PA6/PKTEND |
set_property PACKAGE_PIN P17 [get_ports {PA[6]}] |
set_property PACKAGE_PIN P17 [get_ports {PA[6]}] ;# PA6/PKTEND |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}] |
|
# PA7/FLAGD/SLCS# |
set_property PACKAGE_PIN R18 [get_ports {PA[7]}] |
set_property PACKAGE_PIN R18 [get_ports {PA[7]}] ;# PA7/FLAGD/SLCS# |
set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}] |
|
|
# PC0/GPIFADR0 |
set_property PACKAGE_PIN L20 [get_ports {PC[0]}] |
set_property PACKAGE_PIN L20 [get_ports {PC[0]}] ;# PC0/GPIFADR0 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[0]}] |
|
# PC1/GPIFADR1 |
set_property PACKAGE_PIN L19 [get_ports {PC[1]}] |
set_property PACKAGE_PIN L19 [get_ports {PC[1]}] ;# PC1/GPIFADR1 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[1]}] |
|
# PC2/GPIFADR2 |
set_property PACKAGE_PIN L18 [get_ports {PC[2]}] |
set_property PACKAGE_PIN L18 [get_ports {PC[2]}] ;# PC2/GPIFADR2 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[2]}] |
|
# PC3/GPIFADR3 |
set_property PACKAGE_PIN L16 [get_ports {PC[3]}] |
set_property PACKAGE_PIN L16 [get_ports {PC[3]}] ;# PC3/GPIFADR3 |
set_property IOSTANDARD LVCMOS33 [get_ports {PC[3]}] |
|
# PC4/GPIFADR4 |
set_property PACKAGE_PIN R22 [get_ports {FLASH_DO}] |
set_property PACKAGE_PIN R22 [get_ports {FLASH_DO}] ;# PC4/GPIFADR4 |
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DO}] |
|
# PC5/GPIFADR5 |
set_property PACKAGE_PIN T19 [get_ports {FLASH_CS}] |
set_property PACKAGE_PIN T19 [get_ports {FLASH_CS}] ;# PC5/GPIFADR5 |
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CS}] |
|
# PC6/GPIFADR6 |
set_property PACKAGE_PIN L12 [get_ports {FLASH_CLK}] |
set_property PACKAGE_PIN L12 [get_ports {FLASH_CLK}] ;# PC6/GPIFADR6 |
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_CLK}] |
|
# PC7/GPIFADR7 |
set_property PACKAGE_PIN P22 [get_ports {FLASH_DI}] |
set_property PACKAGE_PIN P22 [get_ports {FLASH_DI}] ;# PC7/GPIFADR7 |
set_property IOSTANDARD LVCMOS33 [get_ports {FLASH_DI}] |
|
|
# PE0/T0OUT |
set_property PACKAGE_PIN G11 [get_ports {PE[0]}] |
set_property PACKAGE_PIN G11 [get_ports {PE[0]}] ;# PE0/T0OUT |
set_property IOSTANDARD LVCMOS33 [get_ports {PE[0]}] |
|
# PE1/T1OUT |
set_property PACKAGE_PIN U12 [get_ports {PE[1]}] |
set_property PACKAGE_PIN U12 [get_ports {PE[1]}] ;# PE1/T1OUT |
set_property IOSTANDARD LVCMOS33 [get_ports {PE[1]}] |
|
# PE2/T2OUT |
set_property PACKAGE_PIN V17 [get_ports {PE[2]}] |
set_property PACKAGE_PIN V17 [get_ports {PE[2]}] ;# PE2/T2OUT |
set_property IOSTANDARD LVCMOS33 [get_ports {PE[2]}] |
|
# PE5/INT6 |
set_property PACKAGE_PIN AA19 [get_ports {PE[5]}] |
set_property PACKAGE_PIN AA19 [get_ports {PE[5]}] ;# PE5/INT6 |
set_property IOSTANDARD LVCMOS33 [get_ports {PE[5]}] |
|
# PE6/T2EX |
set_property PACKAGE_PIN AB20 [get_ports {PE[6]}] |
set_property PACKAGE_PIN AB20 [get_ports {PE[6]}] ;# PE6/T2EX |
set_property IOSTANDARD LVCMOS33 [get_ports {PE[6]}] |
|
|
# RDY0/SLRD |
set_property PACKAGE_PIN AB22 [get_ports {SLRD}] |
set_property PACKAGE_PIN AB22 [get_ports {SLRD}] ;# RDY0/SLRD |
set_property IOSTANDARD LVCMOS33 [get_ports {SLRD}] |
|
# RDY1/SLWR |
set_property PACKAGE_PIN AB21 [get_ports {SLWR}] |
set_property PACKAGE_PIN AB21 [get_ports {SLWR}] ;# RDY1/SLWR |
set_property IOSTANDARD LVCMOS33 [get_ports {SLWR}] |
|
# RDY2 |
set_property PACKAGE_PIN AB18 [get_ports {RDY2}] |
set_property PACKAGE_PIN AB18 [get_ports {RDY2}] ;# RDY2 |
set_property IOSTANDARD LVCMOS33 [get_ports {RDY2}] |
|
# RDY3 |
set_property PACKAGE_PIN AA21 [get_ports {RDY3}] |
set_property PACKAGE_PIN AA21 [get_ports {RDY3}] ;# RDY3 |
set_property IOSTANDARD LVCMOS33 [get_ports {RDY3}] |
|
# RDY4 |
set_property PACKAGE_PIN AA20 [get_ports {RDY4}] |
set_property PACKAGE_PIN AA20 [get_ports {RDY4}] ;# RDY4 |
set_property IOSTANDARD LVCMOS33 [get_ports {RDY4}] |
|
# RDY5 |
set_property PACKAGE_PIN AA18 [get_ports {RDY5}] |
set_property PACKAGE_PIN AA18 [get_ports {RDY5}] ;# RDY5 |
set_property IOSTANDARD LVCMOS33 [get_ports {RDY5}] |
|
|
# CTL0/FLAGA |
set_property PACKAGE_PIN K19 [get_ports {FLAGA}] |
set_property PACKAGE_PIN K19 [get_ports {FLAGA}] ;# CTL0/FLAGA |
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGA}] |
|
# CTL1/FLAGB |
set_property PACKAGE_PIN K18 [get_ports {FLAGB}] |
set_property PACKAGE_PIN K18 [get_ports {FLAGB}] ;# CTL1/FLAGB |
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGB}] |
|
# CTL2/FLAGC |
set_property PACKAGE_PIN L21 [get_ports {FLAGC}] |
set_property PACKAGE_PIN L21 [get_ports {FLAGC}] ;# CTL2/FLAGC |
set_property IOSTANDARD LVCMOS33 [get_ports {FLAGC}] |
|
# CTL3 |
set_property PACKAGE_PIN K22 [get_ports {CTL3}] |
set_property PACKAGE_PIN K22 [get_ports {CTL3}] ;# CTL3 |
set_property IOSTANDARD LVCMOS33 [get_ports {CTL3}] |
|
# CTL4 |
set_property PACKAGE_PIN K21 [get_ports {CTL4}] |
set_property PACKAGE_PIN K21 [get_ports {CTL4}] ;# CTL4 |
set_property IOSTANDARD LVCMOS33 [get_ports {CTL4}] |
|
|
# INT4 |
set_property PACKAGE_PIN G13 [get_ports {INT4}] |
set_property PACKAGE_PIN G13 [get_ports {INT4}] ;# INT4 |
set_property IOSTANDARD LVCMOS33 [get_ports {INT4}] |
|
# INT5# |
set_property PACKAGE_PIN V18 [get_ports {INT5_N}] |
set_property PACKAGE_PIN V18 [get_ports {INT5_N}] ;# INT5# |
set_property IOSTANDARD LVCMOS33 [get_ports {INT5_N}] |
|
# T0 |
set_property PACKAGE_PIN H22 [get_ports {T0}] |
set_property PACKAGE_PIN H22 [get_ports {T0}] ;# T0 |
set_property IOSTANDARD LVCMOS33 [get_ports {T0}] |
|
|
# SCL |
set_property PACKAGE_PIN H19 [get_ports {SCL}] |
set_property PACKAGE_PIN H19 [get_ports {SCL}] ;# SCL |
set_property IOSTANDARD LVCMOS33 [get_ports {SCL}] |
|
# SDA |
set_property PACKAGE_PIN H20 [get_ports {SDA}] |
set_property PACKAGE_PIN H20 [get_ports {SDA}] ;# SDA |
set_property IOSTANDARD LVCMOS33 [get_ports {SDA}] |
|
|
# RxD0 |
set_property PACKAGE_PIN J16 [get_ports {RxD0}] |
set_property PACKAGE_PIN J16 [get_ports {RxD0}] ;# RxD0 |
set_property IOSTANDARD LVCMOS33 [get_ports {RxD0}] |
|
# TxD0 |
set_property PACKAGE_PIN H15 [get_ports {TxD0}] |
set_property PACKAGE_PIN H15 [get_ports {TxD0}] ;# TxD0 |
set_property IOSTANDARD LVCMOS33 [get_ports {TxD0}] |
|
|
# external I/O |
|
|
# A3 / E22~IO_L22P_T3_16 |
set_property PACKAGE_PIN E22 [get_ports {IO_A[0]}] |
set_property PACKAGE_PIN E22 [get_ports {IO_A[0]}] ;# A3 / E22~IO_L22P_T3_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[0]}] |
|
# A4 / C22~IO_L20P_T3_16 |
set_property PACKAGE_PIN C22 [get_ports {IO_A[1]}] |
set_property PACKAGE_PIN C22 [get_ports {IO_A[1]}] ;# A4 / C22~IO_L20P_T3_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[1]}] |
|
# A5 / E21~IO_L23P_T3_16 |
set_property PACKAGE_PIN E21 [get_ports {IO_A[2]}] |
set_property PACKAGE_PIN E21 [get_ports {IO_A[2]}] ;# A5 / E21~IO_L23P_T3_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[2]}] |
|
# A6 / B21~IO_L21P_T3_DQS_16 |
set_property PACKAGE_PIN B21 [get_ports {IO_A[3]}] |
set_property PACKAGE_PIN B21 [get_ports {IO_A[3]}] ;# A6 / B21~IO_L21P_T3_DQS_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[3]}] |
|
# A7 / D20~IO_L19P_T3_16 |
set_property PACKAGE_PIN D20 [get_ports {IO_A[4]}] |
set_property PACKAGE_PIN D20 [get_ports {IO_A[4]}] ;# A7 / D20~IO_L19P_T3_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[4]}] |
|
# A8 / B20~IO_L16P_T2_16 |
set_property PACKAGE_PIN B20 [get_ports {IO_A[5]}] |
set_property PACKAGE_PIN B20 [get_ports {IO_A[5]}] ;# A8 / B20~IO_L16P_T2_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[5]}] |
|
# A9 / C19~IO_L13N_T2_MRCC_16 |
set_property PACKAGE_PIN C19 [get_ports {IO_A[6]}] |
set_property PACKAGE_PIN C19 [get_ports {IO_A[6]}] ;# A9 / C19~IO_L13N_T2_MRCC_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[6]}] |
|
# A10 / C18~IO_L13P_T2_MRCC_16 |
set_property PACKAGE_PIN C18 [get_ports {IO_A[7]}] |
set_property PACKAGE_PIN C18 [get_ports {IO_A[7]}] ;# A10 / C18~IO_L13P_T2_MRCC_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[7]}] |
|
# A11 / B18~IO_L11N_T1_SRCC_16 |
set_property PACKAGE_PIN B18 [get_ports {IO_A[8]}] |
set_property PACKAGE_PIN B18 [get_ports {IO_A[8]}] ;# A11 / B18~IO_L11N_T1_SRCC_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[8]}] |
|
# A12 / B17~IO_L11P_T1_SRCC_16 |
set_property PACKAGE_PIN B17 [get_ports {IO_A[9]}] |
set_property PACKAGE_PIN B17 [get_ports {IO_A[9]}] ;# A12 / B17~IO_L11P_T1_SRCC_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[9]}] |
|
# A13 / B16~IO_L7N_T1_16 |
set_property PACKAGE_PIN B16 [get_ports {IO_A[10]}] |
set_property PACKAGE_PIN B16 [get_ports {IO_A[10]}] ;# A13 / B16~IO_L7N_T1_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[10]}] |
|
# A14 / A16~IO_L9N_T1_DQS_16 |
set_property PACKAGE_PIN A16 [get_ports {IO_A[11]}] |
set_property PACKAGE_PIN A16 [get_ports {IO_A[11]}] ;# A14 / A16~IO_L9N_T1_DQS_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[11]}] |
|
# A18 / A14~IO_L10N_T1_16 |
set_property PACKAGE_PIN A14 [get_ports {IO_A[12]}] |
set_property PACKAGE_PIN A14 [get_ports {IO_A[12]}] ;# A18 / A14~IO_L10N_T1_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[12]}] |
|
# A19 / D15~IO_L6N_T0_VREF_16 |
set_property PACKAGE_PIN D15 [get_ports {IO_A[13]}] |
set_property PACKAGE_PIN D15 [get_ports {IO_A[13]}] ;# A19 / D15~IO_L6N_T0_VREF_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[13]}] |
|
# A20 / B13~IO_L8N_T1_16 |
set_property PACKAGE_PIN B13 [get_ports {IO_A[14]}] |
set_property PACKAGE_PIN B13 [get_ports {IO_A[14]}] ;# A20 / B13~IO_L8N_T1_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[14]}] |
|
# A21 / N3~IO_L19N_T3_VREF_35 |
set_property PACKAGE_PIN N3 [get_ports {IO_A[15]}] |
set_property PACKAGE_PIN N3 [get_ports {IO_A[15]}] ;# A21 / N3~IO_L19N_T3_VREF_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[15]}] |
|
# A22 / H4~IO_L12P_T1_MRCC_35 |
set_property PACKAGE_PIN H4 [get_ports {IO_A[16]}] |
set_property PACKAGE_PIN H4 [get_ports {IO_A[16]}] ;# A22 / H4~IO_L12P_T1_MRCC_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[16]}] |
|
# A23 / G4~IO_L12N_T1_MRCC_35 |
set_property PACKAGE_PIN G4 [get_ports {IO_A[17]}] |
set_property PACKAGE_PIN G4 [get_ports {IO_A[17]}] ;# A23 / G4~IO_L12N_T1_MRCC_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[17]}] |
|
# A24 / E3~IO_L6N_T0_VREF_35 |
set_property PACKAGE_PIN E3 [get_ports {IO_A[18]}] |
set_property PACKAGE_PIN E3 [get_ports {IO_A[18]}] ;# A24 / E3~IO_L6N_T0_VREF_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[18]}] |
|
# A25 / B2~IO_L2N_T0_AD12N_35 |
set_property PACKAGE_PIN B2 [get_ports {IO_A[19]}] |
set_property PACKAGE_PIN B2 [get_ports {IO_A[19]}] ;# A25 / B2~IO_L2N_T0_AD12N_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[19]}] |
|
# A26 / D2~IO_L4N_T0_35 |
set_property PACKAGE_PIN D2 [get_ports {IO_A[20]}] |
set_property PACKAGE_PIN D2 [get_ports {IO_A[20]}] ;# A26 / D2~IO_L4N_T0_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[20]}] |
|
# A27 / G2~IO_L8N_T1_AD14N_35 |
set_property PACKAGE_PIN G2 [get_ports {IO_A[21]}] |
set_property PACKAGE_PIN G2 [get_ports {IO_A[21]}] ;# A27 / G2~IO_L8N_T1_AD14N_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[21]}] |
|
# A28 / A1~IO_L1N_T0_AD4N_35 |
set_property PACKAGE_PIN A1 [get_ports {IO_A[22]}] |
set_property PACKAGE_PIN A1 [get_ports {IO_A[22]}] ;# A28 / A1~IO_L1N_T0_AD4N_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[22]}] |
|
# A29 / D1~IO_L3N_T0_DQS_AD5N_35 |
set_property PACKAGE_PIN D1 [get_ports {IO_A[23]}] |
set_property PACKAGE_PIN D1 [get_ports {IO_A[23]}] ;# A29 / D1~IO_L3N_T0_DQS_AD5N_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[23]}] |
|
# A30 / G1~IO_L5P_T0_AD13P_35 |
set_property PACKAGE_PIN G1 [get_ports {IO_A[24]}] |
set_property PACKAGE_PIN G1 [get_ports {IO_A[24]}] ;# A30 / G1~IO_L5P_T0_AD13P_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_A[24]}] |
|
|
# B3 / D22~IO_L22N_T3_16 |
set_property PACKAGE_PIN D22 [get_ports {IO_B[0]}] |
set_property PACKAGE_PIN D22 [get_ports {IO_B[0]}] ;# B3 / D22~IO_L22N_T3_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[0]}] |
|
# B4 / B22~IO_L20N_T3_16 |
set_property PACKAGE_PIN B22 [get_ports {IO_B[1]}] |
set_property PACKAGE_PIN B22 [get_ports {IO_B[1]}] ;# B4 / B22~IO_L20N_T3_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[1]}] |
|
# B5 / D21~IO_L23N_T3_16 |
set_property PACKAGE_PIN D21 [get_ports {IO_B[2]}] |
set_property PACKAGE_PIN D21 [get_ports {IO_B[2]}] ;# B5 / D21~IO_L23N_T3_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[2]}] |
|
# B6 / A21~IO_L21N_T3_DQS_16 |
set_property PACKAGE_PIN A21 [get_ports {IO_B[3]}] |
set_property PACKAGE_PIN A21 [get_ports {IO_B[3]}] ;# B6 / A21~IO_L21N_T3_DQS_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[3]}] |
|
# B7 / C20~IO_L19N_T3_VREF_16 |
set_property PACKAGE_PIN C20 [get_ports {IO_B[4]}] |
set_property PACKAGE_PIN C20 [get_ports {IO_B[4]}] ;# B7 / C20~IO_L19N_T3_VREF_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[4]}] |
|
# B8 / A20~IO_L16N_T2_16 |
set_property PACKAGE_PIN A20 [get_ports {IO_B[5]}] |
set_property PACKAGE_PIN A20 [get_ports {IO_B[5]}] ;# B8 / A20~IO_L16N_T2_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[5]}] |
|
# B9 / A19~IO_L17N_T2_16 |
set_property PACKAGE_PIN A19 [get_ports {IO_B[6]}] |
set_property PACKAGE_PIN A19 [get_ports {IO_B[6]}] ;# B9 / A19~IO_L17N_T2_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[6]}] |
|
# B10 / A18~IO_L17P_T2_16 |
set_property PACKAGE_PIN A18 [get_ports {IO_B[7]}] |
set_property PACKAGE_PIN A18 [get_ports {IO_B[7]}] ;# B10 / A18~IO_L17P_T2_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[7]}] |
|
# B11 / D17~IO_L12P_T1_MRCC_16 |
set_property PACKAGE_PIN D17 [get_ports {IO_B[8]}] |
set_property PACKAGE_PIN D17 [get_ports {IO_B[8]}] ;# B11 / D17~IO_L12P_T1_MRCC_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[8]}] |
|
# B12 / C17~IO_L12N_T1_MRCC_16 |
set_property PACKAGE_PIN C17 [get_ports {IO_B[9]}] |
set_property PACKAGE_PIN C17 [get_ports {IO_B[9]}] ;# B12 / C17~IO_L12N_T1_MRCC_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[9]}] |
|
# B13 / B15~IO_L7P_T1_16 |
set_property PACKAGE_PIN B15 [get_ports {IO_B[10]}] |
set_property PACKAGE_PIN B15 [get_ports {IO_B[10]}] ;# B13 / B15~IO_L7P_T1_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[10]}] |
|
# B14 / A15~IO_L9P_T1_DQS_16 |
set_property PACKAGE_PIN A15 [get_ports {IO_B[11]}] |
set_property PACKAGE_PIN A15 [get_ports {IO_B[11]}] ;# B14 / A15~IO_L9P_T1_DQS_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[11]}] |
|
# B18 / A13~IO_L10P_T1_16 |
set_property PACKAGE_PIN A13 [get_ports {IO_B[12]}] |
set_property PACKAGE_PIN A13 [get_ports {IO_B[12]}] ;# B18 / A13~IO_L10P_T1_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[12]}] |
|
# B19 / D14~IO_L6P_T0_16 |
set_property PACKAGE_PIN D14 [get_ports {IO_B[13]}] |
set_property PACKAGE_PIN D14 [get_ports {IO_B[13]}] ;# B19 / D14~IO_L6P_T0_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[13]}] |
|
# B20 / C13~IO_L8P_T1_16 |
set_property PACKAGE_PIN C13 [get_ports {IO_B[14]}] |
set_property PACKAGE_PIN C13 [get_ports {IO_B[14]}] ;# B20 / C13~IO_L8P_T1_16 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[14]}] |
|
# B21 / H3~IO_L11P_T1_SRCC_35 |
set_property PACKAGE_PIN H3 [get_ports {IO_B[15]}] |
set_property PACKAGE_PIN H3 [get_ports {IO_B[15]}] ;# B21 / H3~IO_L11P_T1_SRCC_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[15]}] |
|
# B22 / G3~IO_L11N_T1_SRCC_35 |
set_property PACKAGE_PIN G3 [get_ports {IO_B[16]}] |
set_property PACKAGE_PIN G3 [get_ports {IO_B[16]}] ;# B22 / G3~IO_L11N_T1_SRCC_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[16]}] |
|
# B23 / F4~IO_0_35 |
set_property PACKAGE_PIN F4 [get_ports {IO_B[17]}] |
set_property PACKAGE_PIN F4 [get_ports {IO_B[17]}] ;# B23 / F4~IO_0_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[17]}] |
|
# B24 / F3~IO_L6P_T0_35 |
set_property PACKAGE_PIN F3 [get_ports {IO_B[18]}] |
set_property PACKAGE_PIN F3 [get_ports {IO_B[18]}] ;# B24 / F3~IO_L6P_T0_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[18]}] |
|
# B25 / C2~IO_L2P_T0_AD12P_35 |
set_property PACKAGE_PIN C2 [get_ports {IO_B[19]}] |
set_property PACKAGE_PIN C2 [get_ports {IO_B[19]}] ;# B25 / C2~IO_L2P_T0_AD12P_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[19]}] |
|
# B26 / E2~IO_L4P_T0_35 |
set_property PACKAGE_PIN E2 [get_ports {IO_B[20]}] |
set_property PACKAGE_PIN E2 [get_ports {IO_B[20]}] ;# B26 / E2~IO_L4P_T0_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[20]}] |
|
# B27 / H2~IO_L8P_T1_AD14P_35 |
set_property PACKAGE_PIN H2 [get_ports {IO_B[21]}] |
set_property PACKAGE_PIN H2 [get_ports {IO_B[21]}] ;# B27 / H2~IO_L8P_T1_AD14P_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[21]}] |
|
# B28 / B1~IO_L1P_T0_AD4P_35 |
set_property PACKAGE_PIN B1 [get_ports {IO_B[22]}] |
set_property PACKAGE_PIN B1 [get_ports {IO_B[22]}] ;# B28 / B1~IO_L1P_T0_AD4P_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[22]}] |
|
# B29 / E1~IO_L3P_T0_DQS_AD5P_35 |
set_property PACKAGE_PIN E1 [get_ports {IO_B[23]}] |
set_property PACKAGE_PIN E1 [get_ports {IO_B[23]}] ;# B29 / E1~IO_L3P_T0_DQS_AD5P_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[23]}] |
|
# B30 / F1~IO_L5N_T0_AD13N_35 |
set_property PACKAGE_PIN F1 [get_ports {IO_B[24]}] |
set_property PACKAGE_PIN F1 [get_ports {IO_B[24]}] ;# B30 / F1~IO_L5N_T0_AD13N_35 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_B[24]}] |
|
|
# C3 / AB17~IO_L2N_T0_13 |
set_property PACKAGE_PIN AB17 [get_ports {IO_C[0]}] |
set_property PACKAGE_PIN AB17 [get_ports {IO_C[0]}] ;# C3 / AB17~IO_L2N_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[0]}] |
|
# C4 / Y16~IO_L1P_T0_13 |
set_property PACKAGE_PIN Y16 [get_ports {IO_C[1]}] |
set_property PACKAGE_PIN Y16 [get_ports {IO_C[1]}] ;# C4 / Y16~IO_L1P_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[1]}] |
|
# C5 / AA15~IO_L4P_T0_13 |
set_property PACKAGE_PIN AA15 [get_ports {IO_C[2]}] |
set_property PACKAGE_PIN AA15 [get_ports {IO_C[2]}] ;# C5 / AA15~IO_L4P_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[2]}] |
|
# C6 / Y13~IO_L5P_T0_13 |
set_property PACKAGE_PIN Y13 [get_ports {IO_C[3]}] |
set_property PACKAGE_PIN Y13 [get_ports {IO_C[3]}] ;# C6 / Y13~IO_L5P_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[3]}] |
|
# C7 / W14~IO_L6P_T0_13 |
set_property PACKAGE_PIN W14 [get_ports {IO_C[4]}] |
set_property PACKAGE_PIN W14 [get_ports {IO_C[4]}] ;# C7 / W14~IO_L6P_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[4]}] |
|
# C8 / AA13~IO_L3P_T0_DQS_13 |
set_property PACKAGE_PIN AA13 [get_ports {IO_C[5]}] |
set_property PACKAGE_PIN AA13 [get_ports {IO_C[5]}] ;# C8 / AA13~IO_L3P_T0_DQS_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[5]}] |
|
# C9 / AB12~IO_L7N_T1_13 |
set_property PACKAGE_PIN AB12 [get_ports {IO_C[6]}] |
set_property PACKAGE_PIN AB12 [get_ports {IO_C[6]}] ;# C9 / AB12~IO_L7N_T1_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[6]}] |
|
# C10 / W12~IO_L12N_T1_MRCC_13 |
set_property PACKAGE_PIN W12 [get_ports {IO_C[7]}] |
set_property PACKAGE_PIN W12 [get_ports {IO_C[7]}] ;# C10 / W12~IO_L12N_T1_MRCC_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[7]}] |
|
# C11 / AA11~IO_L9N_T1_DQS_13 |
set_property PACKAGE_PIN AA11 [get_ports {IO_C[8]}] |
set_property PACKAGE_PIN AA11 [get_ports {IO_C[8]}] ;# C11 / AA11~IO_L9N_T1_DQS_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[8]}] |
|
# C12 / AA9~IO_L8P_T1_13 |
set_property PACKAGE_PIN AA9 [get_ports {IO_C[9]}] |
set_property PACKAGE_PIN AA9 [get_ports {IO_C[9]}] ;# C12 / AA9~IO_L8P_T1_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[9]}] |
|
# C13 / W9~IO_L24P_T3_34 |
set_property PACKAGE_PIN W9 [get_ports {IO_C[10]}] |
set_property PACKAGE_PIN W9 [get_ports {IO_C[10]}] ;# C13 / W9~IO_L24P_T3_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[10]}] |
|
# C14 / AA8~IO_L22P_T3_34 |
set_property PACKAGE_PIN AA8 [get_ports {IO_C[11]}] |
set_property PACKAGE_PIN AA8 [get_ports {IO_C[11]}] ;# C14 / AA8~IO_L22P_T3_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[11]}] |
|
# C15 / V7~IO_L19P_T3_34 |
set_property PACKAGE_PIN V7 [get_ports {IO_C[12]}] |
set_property PACKAGE_PIN V7 [get_ports {IO_C[12]}] ;# C15 / V7~IO_L19P_T3_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[12]}] |
|
# C19 / AB6~IO_L20N_T3_34 |
set_property PACKAGE_PIN AB6 [get_ports {IO_C[13]}] |
set_property PACKAGE_PIN AB6 [get_ports {IO_C[13]}] ;# C19 / AB6~IO_L20N_T3_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[13]}] |
|
# C20 / AA5~IO_L10P_T1_34 |
set_property PACKAGE_PIN AA5 [get_ports {IO_C[14]}] |
set_property PACKAGE_PIN AA5 [get_ports {IO_C[14]}] ;# C20 / AA5~IO_L10P_T1_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[14]}] |
|
# C21 / Y4~IO_L11P_T1_SRCC_34 |
set_property PACKAGE_PIN Y4 [get_ports {IO_C[15]}] |
set_property PACKAGE_PIN Y4 [get_ports {IO_C[15]}] ;# C21 / Y4~IO_L11P_T1_SRCC_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[15]}] |
|
# C22 / V4~IO_L12P_T1_MRCC_34 |
set_property PACKAGE_PIN V4 [get_ports {IO_C[16]}] |
set_property PACKAGE_PIN V4 [get_ports {IO_C[16]}] ;# C22 / V4~IO_L12P_T1_MRCC_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[16]}] |
|
# C23 / Y3~IO_L9P_T1_DQS_34 |
set_property PACKAGE_PIN Y3 [get_ports {IO_C[17]}] |
set_property PACKAGE_PIN Y3 [get_ports {IO_C[17]}] ;# C23 / Y3~IO_L9P_T1_DQS_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[17]}] |
|
# C24 / U3~IO_L6P_T0_34 |
set_property PACKAGE_PIN U3 [get_ports {IO_C[18]}] |
set_property PACKAGE_PIN U3 [get_ports {IO_C[18]}] ;# C24 / U3~IO_L6P_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[18]}] |
|
# C25 / AB3~IO_L8P_T1_34 |
set_property PACKAGE_PIN AB3 [get_ports {IO_C[19]}] |
set_property PACKAGE_PIN AB3 [get_ports {IO_C[19]}] ;# C25 / AB3~IO_L8P_T1_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[19]}] |
|
# C26 / W2~IO_L4P_T0_34 |
set_property PACKAGE_PIN W2 [get_ports {IO_C[20]}] |
set_property PACKAGE_PIN W2 [get_ports {IO_C[20]}] ;# C26 / W2~IO_L4P_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[20]}] |
|
# C27 / U2~IO_L2P_T0_34 |
set_property PACKAGE_PIN U2 [get_ports {IO_C[21]}] |
set_property PACKAGE_PIN U2 [get_ports {IO_C[21]}] ;# C27 / U2~IO_L2P_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[21]}] |
|
# C28 / AA1~IO_L7P_T1_34 |
set_property PACKAGE_PIN AA1 [get_ports {IO_C[22]}] |
set_property PACKAGE_PIN AA1 [get_ports {IO_C[22]}] ;# C28 / AA1~IO_L7P_T1_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[22]}] |
|
# C29 / W1~IO_L5P_T0_34 |
set_property PACKAGE_PIN W1 [get_ports {IO_C[23]}] |
set_property PACKAGE_PIN W1 [get_ports {IO_C[23]}] ;# C29 / W1~IO_L5P_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[23]}] |
|
# C30 / T1~IO_L1P_T0_34 |
set_property PACKAGE_PIN T1 [get_ports {IO_C[24]}] |
set_property PACKAGE_PIN T1 [get_ports {IO_C[24]}] ;# C30 / T1~IO_L1P_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_C[24]}] |
|
|
# D3 / AB16~IO_L2P_T0_13 |
set_property PACKAGE_PIN AB16 [get_ports {IO_D[0]}] |
set_property PACKAGE_PIN AB16 [get_ports {IO_D[0]}] ;# D3 / AB16~IO_L2P_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[0]}] |
|
# D4 / AA16~IO_L1N_T0_13 |
set_property PACKAGE_PIN AA16 [get_ports {IO_D[1]}] |
set_property PACKAGE_PIN AA16 [get_ports {IO_D[1]}] ;# D4 / AA16~IO_L1N_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[1]}] |
|
# D5 / AB15~IO_L4N_T0_13 |
set_property PACKAGE_PIN AB15 [get_ports {IO_D[2]}] |
set_property PACKAGE_PIN AB15 [get_ports {IO_D[2]}] ;# D5 / AB15~IO_L4N_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[2]}] |
|
# D6 / AA14~IO_L5N_T0_13 |
set_property PACKAGE_PIN AA14 [get_ports {IO_D[3]}] |
set_property PACKAGE_PIN AA14 [get_ports {IO_D[3]}] ;# D6 / AA14~IO_L5N_T0_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[3]}] |
|
# D7 / Y14~IO_L6N_T0_VREF_13 |
set_property PACKAGE_PIN Y14 [get_ports {IO_D[4]}] |
set_property PACKAGE_PIN Y14 [get_ports {IO_D[4]}] ;# D7 / Y14~IO_L6N_T0_VREF_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[4]}] |
|
# D8 / AB13~IO_L3N_T0_DQS_13 |
set_property PACKAGE_PIN AB13 [get_ports {IO_D[5]}] |
set_property PACKAGE_PIN AB13 [get_ports {IO_D[5]}] ;# D8 / AB13~IO_L3N_T0_DQS_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[5]}] |
|
# D9 / AB11~IO_L7P_T1_13 |
set_property PACKAGE_PIN AB11 [get_ports {IO_D[6]}] |
set_property PACKAGE_PIN AB11 [get_ports {IO_D[6]}] ;# D9 / AB11~IO_L7P_T1_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[6]}] |
|
# D10 / W11~IO_L12P_T1_MRCC_13 |
set_property PACKAGE_PIN W11 [get_ports {IO_D[7]}] |
set_property PACKAGE_PIN W11 [get_ports {IO_D[7]}] ;# D10 / W11~IO_L12P_T1_MRCC_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[7]}] |
|
# D11 / AA10~IO_L9P_T1_DQS_13 |
set_property PACKAGE_PIN AA10 [get_ports {IO_D[8]}] |
set_property PACKAGE_PIN AA10 [get_ports {IO_D[8]}] ;# D11 / AA10~IO_L9P_T1_DQS_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[8]}] |
|
# D12 / AB10~IO_L8N_T1_13 |
set_property PACKAGE_PIN AB10 [get_ports {IO_D[9]}] |
set_property PACKAGE_PIN AB10 [get_ports {IO_D[9]}] ;# D12 / AB10~IO_L8N_T1_13 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[9]}] |
|
# D13 / Y9~IO_L24N_T3_34 |
set_property PACKAGE_PIN Y9 [get_ports {IO_D[10]}] |
set_property PACKAGE_PIN Y9 [get_ports {IO_D[10]}] ;# D13 / Y9~IO_L24N_T3_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[10]}] |
|
# D14 / AB8~IO_L22N_T3_34 |
set_property PACKAGE_PIN AB8 [get_ports {IO_D[11]}] |
set_property PACKAGE_PIN AB8 [get_ports {IO_D[11]}] ;# D14 / AB8~IO_L22N_T3_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[11]}] |
|
# D15 / W7~IO_L19N_T3_VREF_34 |
set_property PACKAGE_PIN W7 [get_ports {IO_D[12]}] |
set_property PACKAGE_PIN W7 [get_ports {IO_D[12]}] ;# D15 / W7~IO_L19N_T3_VREF_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[12]}] |
|
# D19 / AB7~IO_L20P_T3_34 |
set_property PACKAGE_PIN AB7 [get_ports {IO_D[13]}] |
set_property PACKAGE_PIN AB7 [get_ports {IO_D[13]}] ;# D19 / AB7~IO_L20P_T3_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[13]}] |
|
# D20 / AB5~IO_L10N_T1_34 |
set_property PACKAGE_PIN AB5 [get_ports {IO_D[14]}] |
set_property PACKAGE_PIN AB5 [get_ports {IO_D[14]}] ;# D20 / AB5~IO_L10N_T1_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[14]}] |
|
# D21 / AA4~IO_L11N_T1_SRCC_34 |
set_property PACKAGE_PIN AA4 [get_ports {IO_D[15]}] |
set_property PACKAGE_PIN AA4 [get_ports {IO_D[15]}] ;# D21 / AA4~IO_L11N_T1_SRCC_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[15]}] |
|
# D22 / W4~IO_L12N_T1_MRCC_34 |
set_property PACKAGE_PIN W4 [get_ports {IO_D[16]}] |
set_property PACKAGE_PIN W4 [get_ports {IO_D[16]}] ;# D22 / W4~IO_L12N_T1_MRCC_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[16]}] |
|
# D23 / AA3~IO_L9N_T1_DQS_34 |
set_property PACKAGE_PIN AA3 [get_ports {IO_D[17]}] |
set_property PACKAGE_PIN AA3 [get_ports {IO_D[17]}] ;# D23 / AA3~IO_L9N_T1_DQS_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[17]}] |
|
# D24 / V3~IO_L6N_T0_VREF_34 |
set_property PACKAGE_PIN V3 [get_ports {IO_D[18]}] |
set_property PACKAGE_PIN V3 [get_ports {IO_D[18]}] ;# D24 / V3~IO_L6N_T0_VREF_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[18]}] |
|
# D25 / AB2~IO_L8N_T1_34 |
set_property PACKAGE_PIN AB2 [get_ports {IO_D[19]}] |
set_property PACKAGE_PIN AB2 [get_ports {IO_D[19]}] ;# D25 / AB2~IO_L8N_T1_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[19]}] |
|
# D26 / Y2~IO_L4N_T0_34 |
set_property PACKAGE_PIN Y2 [get_ports {IO_D[20]}] |
set_property PACKAGE_PIN Y2 [get_ports {IO_D[20]}] ;# D26 / Y2~IO_L4N_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[20]}] |
|
# D27 / V2~IO_L2N_T0_34 |
set_property PACKAGE_PIN V2 [get_ports {IO_D[21]}] |
set_property PACKAGE_PIN V2 [get_ports {IO_D[21]}] ;# D27 / V2~IO_L2N_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[21]}] |
|
# D28 / AB1~IO_L7N_T1_34 |
set_property PACKAGE_PIN AB1 [get_ports {IO_D[22]}] |
set_property PACKAGE_PIN AB1 [get_ports {IO_D[22]}] ;# D28 / AB1~IO_L7N_T1_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[22]}] |
|
# D29 / Y1~IO_L5N_T0_34 |
set_property PACKAGE_PIN Y1 [get_ports {IO_D[23]}] |
set_property PACKAGE_PIN Y1 [get_ports {IO_D[23]}] ;# D29 / Y1~IO_L5N_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[23]}] |
|
# D30 / U1~IO_L1N_T0_34 |
set_property PACKAGE_PIN U1 [get_ports {IO_D[24]}] |
set_property PACKAGE_PIN U1 [get_ports {IO_D[24]}] ;# D30 / U1~IO_L1N_T0_34 |
set_property IOSTANDARD LVCMOS33 [get_ports {IO_D[24]}] |
/usb-fpga-2.16.txt
0,0 → 1,180
A3 E22~IO_L22P_T3_16 E22 |
B3 D22~IO_L22N_T3_16 D22 |
A4 C22~IO_L20P_T3_16 C22 |
B4 B22~IO_L20N_T3_16 B22 |
A5 E21~IO_L23P_T3_16 E21 |
B5 D21~IO_L23N_T3_16 D21 |
A6 B21~IO_L21P_T3_DQS_16 B21 |
B6 A21~IO_L21N_T3_DQS_16 A21 |
A7 D20~IO_L19P_T3_16 D20 |
B7 C20~IO_L19N_T3_VREF_16 C20 |
A8 B20~IO_L16P_T2_16 B20 |
B8 A20~IO_L16N_T2_16 A20 |
A9 C19~IO_L13N_T2_MRCC_16 C19 |
B9 A19~IO_L17N_T2_16 A19 |
A10 C18~IO_L13P_T2_MRCC_16 C18 |
B10 A18~IO_L17P_T2_16 A18 |
A11 B18~IO_L11N_T1_SRCC_16 B18 |
B11 D17~IO_L12P_T1_MRCC_16 D17 |
A12 B17~IO_L11P_T1_SRCC_16 B17 |
B12 C17~IO_L12N_T1_MRCC_16 C17 |
A13 B16~IO_L7N_T1_16 B16 |
B13 B15~IO_L7P_T1_16 B15 |
A14 A16~IO_L9N_T1_DQS_16 A16 |
B14 A15~IO_L9P_T1_DQS_16 A15 |
A18 A14~IO_L10N_T1_16 A14 |
B18 A13~IO_L10P_T1_16 A13 |
A19 D15~IO_L6N_T0_VREF_16 D15 |
B19 D14~IO_L6P_T0_16 D14 |
A20 B13~IO_L8N_T1_16 B13 |
B20 C13~IO_L8P_T1_16 C13 |
A21 N3~IO_L19N_T3_VREF_35 N3 |
B21 H3~IO_L11P_T1_SRCC_35 H3 |
A22 H4~IO_L12P_T1_MRCC_35 H4 |
B22 G3~IO_L11N_T1_SRCC_35 G3 |
A23 G4~IO_L12N_T1_MRCC_35 G4 |
B23 F4~IO_0_35 F4 |
A24 E3~IO_L6N_T0_VREF_35 E3 |
B24 F3~IO_L6P_T0_35 F3 |
A25 B2~IO_L2N_T0_AD12N_35 B2 |
B25 C2~IO_L2P_T0_AD12P_35 C2 |
A26 D2~IO_L4N_T0_35 D2 |
B26 E2~IO_L4P_T0_35 E2 |
A27 G2~IO_L8N_T1_AD14N_35 G2 |
B27 H2~IO_L8P_T1_AD14P_35 H2 |
A28 A1~IO_L1N_T0_AD4N_35 A1 |
B28 B1~IO_L1P_T0_AD4P_35 B1 |
A29 D1~IO_L3N_T0_DQS_AD5N_35 D1 |
B29 E1~IO_L3P_T0_DQS_AD5P_35 E1 |
A30 G1~IO_L5P_T0_AD13P_35 G1 |
B30 F1~IO_L5N_T0_AD13N_35 F1 |
|
C3 AB17~IO_L2N_T0_13 AB17 |
D3 AB16~IO_L2P_T0_13 AB16 |
C4 Y16~IO_L1P_T0_13 Y16 |
D4 AA16~IO_L1N_T0_13 AA16 |
C5 AA15~IO_L4P_T0_13 AA15 |
D5 AB15~IO_L4N_T0_13 AB15 |
C6 Y13~IO_L5P_T0_13 Y13 |
D6 AA14~IO_L5N_T0_13 AA14 |
C7 W14~IO_L6P_T0_13 W14 |
D7 Y14~IO_L6N_T0_VREF_13 Y14 |
C8 AA13~IO_L3P_T0_DQS_13 AA13 |
D8 AB13~IO_L3N_T0_DQS_13 AB13 |
C9 AB12~IO_L7N_T1_13 AB12 |
D9 AB11~IO_L7P_T1_13 AB11 |
C10 W12~IO_L12N_T1_MRCC_13 W12 |
D10 W11~IO_L12P_T1_MRCC_13 W11 |
C11 AA11~IO_L9N_T1_DQS_13 AA11 |
D11 AA10~IO_L9P_T1_DQS_13 AA10 |
C12 AA9~IO_L8P_T1_13 AA9 |
D12 AB10~IO_L8N_T1_13 AB10 |
C13 W9~IO_L24P_T3_34 W9 |
D13 Y9~IO_L24N_T3_34 Y9 |
C14 AA8~IO_L22P_T3_34 AA8 |
D14 AB8~IO_L22N_T3_34 AB8 |
C15 V7~IO_L19P_T3_34 V7 |
D15 W7~IO_L19N_T3_VREF_34 W7 |
C16 VCCO_CD |
D16 VCCO_CD |
C17 GND |
D17 GND |
C18 3.3V |
D18 3.3V |
C19 AB6~IO_L20N_T3_34 AB6 |
D19 AB7~IO_L20P_T3_34 AB7 |
C20 AA5~IO_L10P_T1_34 AA5 |
D20 AB5~IO_L10N_T1_34 AB5 |
C21 Y4~IO_L11P_T1_SRCC_34 Y4 |
D21 AA4~IO_L11N_T1_SRCC_34 AA4 |
C22 V4~IO_L12P_T1_MRCC_34 V4 |
D22 W4~IO_L12N_T1_MRCC_34 W4 |
C23 Y3~IO_L9P_T1_DQS_34 Y3 |
D23 AA3~IO_L9N_T1_DQS_34 AA3 |
C24 U3~IO_L6P_T0_34 U3 |
D24 V3~IO_L6N_T0_VREF_34 V3 |
C25 AB3~IO_L8P_T1_34 AB3 |
D25 AB2~IO_L8N_T1_34 AB2 |
C26 W2~IO_L4P_T0_34 W2 |
D26 Y2~IO_L4N_T0_34 Y2 |
C27 U2~IO_L2P_T0_34 U2 |
D27 V2~IO_L2N_T0_34 V2 |
C28 AA1~IO_L7P_T1_34 AA1 |
D28 AB1~IO_L7N_T1_34 AB1 |
C29 W1~IO_L5P_T0_34 W1 |
D29 Y1~IO_L5N_T0_34 Y1 |
C30 T1~IO_L1P_T0_34 T1 |
D30 U1~IO_L1N_T0_34 U1 |
|
- CLKOUT/FXCLK Y18 |
|
- IFCLK J19 |
|
- PB0/FD0 P20 |
- PB1/FD1 N17 |
- PB2/FD2 P21 |
- PB3/FD3 R21 |
- PB4/FD4 T21 |
- PB5/FD5 U21 |
- PB6/FD6 P19 |
- PB7/FD7 R19 |
|
- PD0/FD8 T20 |
- PD1/FD9 U20 |
- PD2/FD10 U18 |
- PD3/FD11 U17 |
- PD4/FD12 W19 |
- PD5/FD13 W20 |
- PD6/FD14 W21 |
- PD7/FD15 W22 |
|
- PA0/INT0# M22 |
- PA1/INT1# M21 |
- PA2/*SLOE M20 |
- PA3/*WU2 M18 |
- PA4/FIFOADR0 N19 |
- PA5/FIFOADR1 N18 |
- PA6/*PKTEND P17 |
- PA7/*FLAGD/SLCS# R18 |
|
- PC0/GPIFADR0 L20 |
- PC1/GPIFADR1 L19 |
- PC2/GPIFADR2 L18 |
- PC3/GPIFADR3 L16 |
- PC4/GPIFADR4 R22 |
- PC5/GPIFADR5 T19 |
- PC6/GPIFADR6 L12 |
- PC7/GPIFADR7 P22 |
|
- PE0/T0OUT G11 |
- PE1/T1OUT U12 |
- PE2/T2OUT V17 |
- PE3/RXD0OUT |
- PE4/RXD1OUT |
- PE5/INT6 AA19 |
- PE6/T2EX AB20 |
- PE7/GPIFADR8 |
|
- RDY0/*SLRD AB22 |
- RDY1/*SLWR AB21 |
- RDY2 AB18 |
- RDY3 AA21 |
- RDY4 AA20 |
- RDY5 AA18 |
|
- CTL0/*FLAGA K19 |
- CTL1/*FLAGB K18 |
- CTL2/*FLAGC L21 |
- CTL3 K22 |
- CTL4 K21 |
- CTL5 |
|
- INT4 G13 |
- INT5# V18 |
- T0 H22 |
|
- SCL H19 |
- SDA H20 |
|
- RxD0 J16 |
- TxD0 H15 |