OpenCores
URL https://opencores.org/ocsvn/usbhostslave/usbhostslave/trunk

Subversion Repositories usbhostslave

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Rev 43 → Rev 44

/trunk/RTL/hostController/usbHostControl.v
1,397 → 1,398
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostControl.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbHostControl(
busClk, rstSyncToBusClk,
usbClk, rstSyncToUsbClk,
//sendPacket
TxFifoRE, TxFifoData, TxFifoEmpty,
//getPacket
RxFifoWE, RxFifoData, RxFifoFull,
RxByteStatus, RxData, RxDataValid,
SIERxTimeOut, SIERxTimeOutEn,
//speedCtrlMux
fullSpeedRate, fullSpeedPol,
//HCTxPortArbiter
HCTxPortEn, HCTxPortRdy,
HCTxPortData, HCTxPortCtrl,
//rxStatusMonitor
connectStateIn,
resumeDetectedIn,
//USBHostControlBI
busAddress,
busDataIn,
busDataOut,
busWriteEn,
busStrobe_i,
SOFSentIntOut,
connEventIntOut,
resumeIntOut,
transDoneIntOut,
hostControlSelect
);
 
input busClk;
input rstSyncToBusClk;
input usbClk;
input rstSyncToUsbClk;
//sendPacket
output TxFifoRE;
input [7:0] TxFifoData;
input TxFifoEmpty;
//getPacket
output RxFifoWE;
output [7:0] RxFifoData;
input RxFifoFull;
input [7:0] RxByteStatus;
input [7:0] RxData;
input RxDataValid;
input SIERxTimeOut;
output SIERxTimeOutEn;
//speedCtrlMux
output fullSpeedRate;
output fullSpeedPol;
//HCTxPortArbiter
output HCTxPortEn;
input HCTxPortRdy;
output [7:0] HCTxPortData;
output [7:0] HCTxPortCtrl;
//rxStatusMonitor
input [1:0] connectStateIn;
input resumeDetectedIn;
//USBHostControlBI
input [3:0] busAddress;
input [7:0] busDataIn;
output [7:0] busDataOut;
input busWriteEn;
input busStrobe_i;
output SOFSentIntOut;
output connEventIntOut;
output resumeIntOut;
output transDoneIntOut;
input hostControlSelect;
 
wire busClk;
wire rstSyncToBusClk;
wire usbClk;
wire rstSyncToUsbClk;
wire [10:0] frameNum;
wire SOFSent;
wire TxFifoRE;
wire [7:0] TxFifoData;
wire TxFifoEmpty;
wire RxFifoWE;
wire [7:0] RxFifoData;
wire RxFifoFull;
wire [7:0] RxByteStatus;
wire [7:0] RxData;
wire RxDataValid;
wire SIERxTimeOut;
wire SIERxTimeOutEn;
wire fullSpeedRate;
wire fullSpeedPol;
wire HCTxPortEn;
wire HCTxPortRdy;
wire [7:0] HCTxPortData;
wire [7:0] HCTxPortCtrl;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
wire [3:0] busAddress;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire busWriteEn;
wire busStrobe_i;
wire SOFSentIntOut;
wire connEventIntOut;
wire resumeIntOut;
wire transDoneIntOut;
wire hostControlSelect;
 
//internal wiring
wire SOFTimerClr;
wire getPacketREn;
wire getPacketRdy;
wire HCTxGnt;
wire HCTxReq;
wire [3:0] HC_PID;
wire HC_SP_WEn;
wire SOFTxGnt;
wire SOFTxReq;
wire SOF_SP_WEn;
wire SOFEnable;
wire SOFSyncEn;
wire sendPacketCPReadyIn;
wire sendPacketCPReadyOut;
wire [3:0] sendPacketCPPIDIn;
wire [3:0] sendPacketCPPIDOut;
wire sendPacketCPWEnIn;
wire sendPacketCPWEnOut;
wire [7:0] SOFCntlCntl;
wire [7:0] SOFCntlData;
wire SOFCntlGnt;
wire SOFCntlReq;
wire SOFCntlWEn;
wire [7:0] directCntlCntl;
wire [7:0] directCntlData;
wire directCntlGnt;
wire directCntlReq;
wire directCntlWEn;
wire [7:0] sendPacketCntl;
wire [7:0] sendPacketData;
wire sendPacketGnt;
wire sendPacketReq;
wire sendPacketWEn;
wire [15:0] SOFTimer;
wire clrTxReq;
wire transDone;
wire transReq;
wire isoEn;
wire [1:0] transType;
wire preAmbleEnable;
wire [1:0] directLineState;
wire directLineCtrlEn;
wire [6:0] TxAddr;
wire [3:0] TxEndP;
wire [7:0] RxPktStatus;
wire [3:0] RxPID;
wire [1:0] connectStateOut;
wire resumeIntFromRxStatusMon;
wire connectionEventFromRxStatusMon;
 
USBHostControlBI u_USBHostControlBI
(.address(busAddress),
.dataIn(busDataIn),
.dataOut(busDataOut),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.SOFSentIntOut(SOFSentIntOut),
.connEventIntOut(connEventIntOut),
.resumeIntOut(resumeIntOut),
.transDoneIntOut(transDoneIntOut),
.TxTransTypeReg(transType),
.TxSOFEnableReg(SOFEnable),
.TxAddrReg(TxAddr),
.TxEndPReg(TxEndP),
.frameNumIn(frameNum),
.RxPktStatusIn(RxPktStatus),
.RxPIDIn(RxPID),
.connectStateIn(connectStateOut),
.SOFSentIn(SOFSent),
.connEventIn(connectionEventFromRxStatusMon),
.resumeIntIn(resumeIntFromRxStatusMon),
.transDoneIn(transDone),
.hostControlSelect(hostControlSelect),
.clrTransReq(clrTxReq),
.preambleEn(preAmbleEnable),
.SOFSync(SOFSyncEn),
.TxLineState(directLineState),
.LineDirectControlEn(directLineCtrlEn),
.fullSpeedPol(fullSpeedPol),
.fullSpeedRate(fullSpeedRate),
.transReq(transReq),
.isoEn(isoEn),
.SOFTimer(SOFTimer)
);
 
 
hostcontroller u_hostController
(.RXStatus(RxPktStatus),
.clearTXReq(clrTxReq),
.clk(usbClk),
.getPacketREn(getPacketREn),
.getPacketRdy(getPacketRdy),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(HCTxGnt),
.sendPacketArbiterReq(HCTxReq),
.sendPacketPID(HC_PID),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(HC_SP_WEn),
.transDone(transDone),
.transReq(transReq),
.transType(transType),
.isoEn(isoEn) );
 
SOFController u_SOFController
(.HCTxPortCntl(SOFCntlCntl),
.HCTxPortData(SOFCntlData),
.HCTxPortGnt(SOFCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(SOFCntlReq),
.HCTxPortWEn(SOFCntlWEn),
.SOFEnable(SOFEnable),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
 
SOFTransmit u_SOFTransmit
(.SOFEnable(SOFEnable),
.SOFSent(SOFSent),
.SOFSyncEn(SOFSyncEn),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(SOFTxGnt),
.sendPacketArbiterReq(SOFTxReq),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(SOF_SP_WEn) );
 
 
sendPacketArbiter u_sendPacketArbiter
(.HCTxGnt(HCTxGnt),
.HCTxReq(HCTxReq),
.HC_PID(HC_PID),
.HC_SP_WEn(HC_SP_WEn),
.SOFTxGnt(SOFTxGnt),
.SOFTxReq(SOFTxReq),
.SOF_SP_WEn(SOF_SP_WEn),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketPID(sendPacketCPPIDIn),
.sendPacketWEnable(sendPacketCPWEnIn) );
 
sendPacketCheckPreamble u_sendPacketCheckPreamble
(.sendPacketCPPID(sendPacketCPPIDIn),
.clk(usbClk),
.preAmbleEnable(preAmbleEnable),
.rst(rstSyncToUsbClk),
.sendPacketCPReady(sendPacketCPReadyOut),
.sendPacketCPWEn(sendPacketCPWEnIn),
.sendPacketPID(sendPacketCPPIDOut),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut) );
 
sendPacket u_sendPacket
(.HCTxPortCntl(sendPacketCntl),
.HCTxPortData(sendPacketData),
.HCTxPortGnt(sendPacketGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(sendPacketReq),
.HCTxPortWEn(sendPacketWEn),
.PID(sendPacketCPPIDOut),
.TxAddr(TxAddr),
.TxEndP(TxEndP),
.clk(usbClk),
.fifoData(TxFifoData),
.fifoEmpty(TxFifoEmpty),
.fifoReadEn(TxFifoRE),
.frameNum(frameNum),
.rst(rstSyncToUsbClk),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut),
.fullSpeedPolarity(fullSpeedPol) );
directControl u_directControl
(.HCTxPortCntl(directCntlCntl),
.HCTxPortData(directCntlData),
.HCTxPortGnt(directCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(directCntlReq),
.HCTxPortWEn(directCntlWEn),
.clk(usbClk),
.directControlEn(directLineCtrlEn),
.directControlLineState(directLineState),
.rst(rstSyncToUsbClk) );
 
HCTxPortArbiter u_HCTxPortArbiter
(.HCTxPortCntl(HCTxPortCtrl),
.HCTxPortData(HCTxPortData),
.HCTxPortWEnable(HCTxPortEn),
.SOFCntlCntl(SOFCntlCntl),
.SOFCntlData(SOFCntlData),
.SOFCntlGnt(SOFCntlGnt),
.SOFCntlReq(SOFCntlReq),
.SOFCntlWEn(SOFCntlWEn),
.clk(usbClk),
.directCntlCntl(directCntlCntl),
.directCntlData(directCntlData),
.directCntlGnt(directCntlGnt),
.directCntlReq(directCntlReq),
.directCntlWEn(directCntlWEn),
.rst(rstSyncToUsbClk),
.sendPacketCntl(sendPacketCntl),
.sendPacketData(sendPacketData),
.sendPacketGnt(sendPacketGnt),
.sendPacketReq(sendPacketReq),
.sendPacketWEn(sendPacketWEn) );
 
getPacket u_getPacket
(.RXDataIn(RxData),
.RXDataValid(RxDataValid),
.RXFifoData(RxFifoData),
.RXFifoFull(RxFifoFull),
.RXFifoWEn(RxFifoWE),
.RXPacketRdy(getPacketRdy),
.RXPktStatus(RxPktStatus),
.RXStreamStatusIn(RxByteStatus),
.RxPID(RxPID),
.SIERxTimeOut(SIERxTimeOut),
.SIERxTimeOutEn(SIERxTimeOutEn),
.clk(usbClk),
.getPacketEn(getPacketREn),
.rst(rstSyncToUsbClk) );
 
rxStatusMonitor u_rxStatusMonitor
(.connectStateIn(connectStateIn),
.connectStateOut(connectStateOut),
.resumeDetectedIn(resumeDetectedIn),
.connectionEventOut(connectionEventFromRxStatusMon),
.resumeIntOut(resumeIntFromRxStatusMon),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
 
endmodule
 
 
 
 
 
//////////////////////////////////////////////////////////////////////
//// ////
//// usbHostControl.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbHostControl(
busClk, rstSyncToBusClk,
usbClk, rstSyncToUsbClk,
//sendPacket
TxFifoRE, TxFifoData, TxFifoEmpty,
//getPacket
RxFifoWE, RxFifoData, RxFifoFull,
RxByteStatus, RxData, RxDataValid,
SIERxTimeOut, SIERxTimeOutEn,
//speedCtrlMux
fullSpeedRate, fullSpeedPol,
//HCTxPortArbiter
HCTxPortEn, HCTxPortRdy,
HCTxPortData, HCTxPortCtrl,
//rxStatusMonitor
connectStateIn,
resumeDetectedIn,
//USBHostControlBI
busAddress,
busDataIn,
busDataOut,
busWriteEn,
busStrobe_i,
SOFSentIntOut,
connEventIntOut,
resumeIntOut,
transDoneIntOut,
hostControlSelect
);
 
input busClk;
input rstSyncToBusClk;
input usbClk;
input rstSyncToUsbClk;
//sendPacket
output TxFifoRE;
input [7:0] TxFifoData;
input TxFifoEmpty;
//getPacket
output RxFifoWE;
output [7:0] RxFifoData;
input RxFifoFull;
input [7:0] RxByteStatus;
input [7:0] RxData;
input RxDataValid;
input SIERxTimeOut;
output SIERxTimeOutEn;
//speedCtrlMux
output fullSpeedRate;
output fullSpeedPol;
//HCTxPortArbiter
output HCTxPortEn;
input HCTxPortRdy;
output [7:0] HCTxPortData;
output [7:0] HCTxPortCtrl;
//rxStatusMonitor
input [1:0] connectStateIn;
input resumeDetectedIn;
//USBHostControlBI
input [3:0] busAddress;
input [7:0] busDataIn;
output [7:0] busDataOut;
input busWriteEn;
input busStrobe_i;
output SOFSentIntOut;
output connEventIntOut;
output resumeIntOut;
output transDoneIntOut;
input hostControlSelect;
 
wire busClk;
wire rstSyncToBusClk;
wire usbClk;
wire rstSyncToUsbClk;
wire [10:0] frameNum;
wire SOFSent;
wire TxFifoRE;
wire [7:0] TxFifoData;
wire TxFifoEmpty;
wire RxFifoWE;
wire [7:0] RxFifoData;
wire RxFifoFull;
wire [7:0] RxByteStatus;
wire [7:0] RxData;
wire RxDataValid;
wire SIERxTimeOut;
wire SIERxTimeOutEn;
wire fullSpeedRate;
wire fullSpeedPol;
wire HCTxPortEn;
wire HCTxPortRdy;
wire [7:0] HCTxPortData;
wire [7:0] HCTxPortCtrl;
wire [1:0] connectStateIn;
wire resumeDetectedIn;
wire [3:0] busAddress;
wire [7:0] busDataIn;
wire [7:0] busDataOut;
wire busWriteEn;
wire busStrobe_i;
wire SOFSentIntOut;
wire connEventIntOut;
wire resumeIntOut;
wire transDoneIntOut;
wire hostControlSelect;
 
//internal wiring
wire SOFTimerClr;
wire getPacketREn;
wire getPacketRdy;
wire HCTxGnt;
wire HCTxReq;
wire [3:0] HC_PID;
wire HC_SP_WEn;
wire SOFTxGnt;
wire SOFTxReq;
wire SOF_SP_WEn;
wire SOFEnable;
wire SOFSyncEn;
wire sendPacketCPReadyIn;
wire sendPacketCPReadyOut;
wire [3:0] sendPacketCPPIDIn;
wire [3:0] sendPacketCPPIDOut;
wire sendPacketCPWEnIn;
wire sendPacketCPWEnOut;
wire [7:0] SOFCntlCntl;
wire [7:0] SOFCntlData;
wire SOFCntlGnt;
wire SOFCntlReq;
wire SOFCntlWEn;
wire [7:0] directCntlCntl;
wire [7:0] directCntlData;
wire directCntlGnt;
wire directCntlReq;
wire directCntlWEn;
wire [7:0] sendPacketCntl;
wire [7:0] sendPacketData;
wire sendPacketGnt;
wire sendPacketReq;
wire sendPacketWEn;
wire [15:0] SOFTimer;
wire clrTxReq;
wire transDone;
wire transReq;
wire isoEn;
wire [1:0] transType;
wire preAmbleEnable;
wire [1:0] directLineState;
wire directLineCtrlEn;
wire [6:0] TxAddr;
wire [3:0] TxEndP;
wire [7:0] RxPktStatus;
wire [3:0] RxPID;
wire [1:0] connectStateOut;
wire resumeIntFromRxStatusMon;
wire connectionEventFromRxStatusMon;
 
USBHostControlBI u_USBHostControlBI
(.address(busAddress),
.dataIn(busDataIn),
.dataOut(busDataOut),
.writeEn(busWriteEn),
.strobe_i(busStrobe_i),
.busClk(busClk),
.rstSyncToBusClk(rstSyncToBusClk),
.usbClk(usbClk),
.rstSyncToUsbClk(rstSyncToUsbClk),
.SOFSentIntOut(SOFSentIntOut),
.connEventIntOut(connEventIntOut),
.resumeIntOut(resumeIntOut),
.transDoneIntOut(transDoneIntOut),
.TxTransTypeReg(transType),
.TxSOFEnableReg(SOFEnable),
.TxAddrReg(TxAddr),
.TxEndPReg(TxEndP),
.frameNumIn(frameNum),
.RxPktStatusIn(RxPktStatus),
.RxPIDIn(RxPID),
.connectStateIn(connectStateOut),
.SOFSentIn(SOFSent),
.connEventIn(connectionEventFromRxStatusMon),
.resumeIntIn(resumeIntFromRxStatusMon),
.transDoneIn(transDone),
.hostControlSelect(hostControlSelect),
.clrTransReq(clrTxReq),
.preambleEn(preAmbleEnable),
.SOFSync(SOFSyncEn),
.TxLineState(directLineState),
.LineDirectControlEn(directLineCtrlEn),
.fullSpeedPol(fullSpeedPol),
.fullSpeedRate(fullSpeedRate),
.transReq(transReq),
.isoEn(isoEn),
.SOFTimer(SOFTimer)
);
 
 
hostcontroller u_hostController
(.RXStatus(RxPktStatus),
.clearTXReq(clrTxReq),
.clk(usbClk),
.getPacketREn(getPacketREn),
.getPacketRdy(getPacketRdy),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(HCTxGnt),
.sendPacketArbiterReq(HCTxReq),
.sendPacketPID(HC_PID),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(HC_SP_WEn),
.transDone(transDone),
.transReq(transReq),
.transType(transType),
.isoEn(isoEn) );
 
SOFController u_SOFController
(.HCTxPortCntl(SOFCntlCntl),
.HCTxPortData(SOFCntlData),
.HCTxPortGnt(SOFCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(SOFCntlReq),
.HCTxPortWEn(SOFCntlWEn),
.SOFEnable(SOFEnable),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
 
SOFTransmit u_SOFTransmit
(.SOFEnable(SOFEnable),
.SOFSent(SOFSent),
.SOFSyncEn(SOFSyncEn),
.SOFTimerClr(SOFTimerClr),
.SOFTimer(SOFTimer),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketArbiterGnt(SOFTxGnt),
.sendPacketArbiterReq(SOFTxReq),
.sendPacketRdy(sendPacketCPReadyOut),
.sendPacketWEn(SOF_SP_WEn),
.fullSpeedRate(fullSpeedRate) );
 
 
sendPacketArbiter u_sendPacketArbiter
(.HCTxGnt(HCTxGnt),
.HCTxReq(HCTxReq),
.HC_PID(HC_PID),
.HC_SP_WEn(HC_SP_WEn),
.SOFTxGnt(SOFTxGnt),
.SOFTxReq(SOFTxReq),
.SOF_SP_WEn(SOF_SP_WEn),
.clk(usbClk),
.rst(rstSyncToUsbClk),
.sendPacketPID(sendPacketCPPIDIn),
.sendPacketWEnable(sendPacketCPWEnIn) );
 
sendPacketCheckPreamble u_sendPacketCheckPreamble
(.sendPacketCPPID(sendPacketCPPIDIn),
.clk(usbClk),
.preAmbleEnable(preAmbleEnable),
.rst(rstSyncToUsbClk),
.sendPacketCPReady(sendPacketCPReadyOut),
.sendPacketCPWEn(sendPacketCPWEnIn),
.sendPacketPID(sendPacketCPPIDOut),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut) );
 
sendPacket u_sendPacket
(.HCTxPortCntl(sendPacketCntl),
.HCTxPortData(sendPacketData),
.HCTxPortGnt(sendPacketGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(sendPacketReq),
.HCTxPortWEn(sendPacketWEn),
.PID(sendPacketCPPIDOut),
.TxAddr(TxAddr),
.TxEndP(TxEndP),
.clk(usbClk),
.fifoData(TxFifoData),
.fifoEmpty(TxFifoEmpty),
.fifoReadEn(TxFifoRE),
.frameNum(frameNum),
.rst(rstSyncToUsbClk),
.sendPacketRdy(sendPacketCPReadyIn),
.sendPacketWEn(sendPacketCPWEnOut),
.fullSpeedPolarity(fullSpeedPol) );
directControl u_directControl
(.HCTxPortCntl(directCntlCntl),
.HCTxPortData(directCntlData),
.HCTxPortGnt(directCntlGnt),
.HCTxPortRdy(HCTxPortRdy),
.HCTxPortReq(directCntlReq),
.HCTxPortWEn(directCntlWEn),
.clk(usbClk),
.directControlEn(directLineCtrlEn),
.directControlLineState(directLineState),
.rst(rstSyncToUsbClk) );
 
HCTxPortArbiter u_HCTxPortArbiter
(.HCTxPortCntl(HCTxPortCtrl),
.HCTxPortData(HCTxPortData),
.HCTxPortWEnable(HCTxPortEn),
.SOFCntlCntl(SOFCntlCntl),
.SOFCntlData(SOFCntlData),
.SOFCntlGnt(SOFCntlGnt),
.SOFCntlReq(SOFCntlReq),
.SOFCntlWEn(SOFCntlWEn),
.clk(usbClk),
.directCntlCntl(directCntlCntl),
.directCntlData(directCntlData),
.directCntlGnt(directCntlGnt),
.directCntlReq(directCntlReq),
.directCntlWEn(directCntlWEn),
.rst(rstSyncToUsbClk),
.sendPacketCntl(sendPacketCntl),
.sendPacketData(sendPacketData),
.sendPacketGnt(sendPacketGnt),
.sendPacketReq(sendPacketReq),
.sendPacketWEn(sendPacketWEn) );
 
getPacket u_getPacket
(.RXDataIn(RxData),
.RXDataValid(RxDataValid),
.RXFifoData(RxFifoData),
.RXFifoFull(RxFifoFull),
.RXFifoWEn(RxFifoWE),
.RXPacketRdy(getPacketRdy),
.RXPktStatus(RxPktStatus),
.RXStreamStatusIn(RxByteStatus),
.RxPID(RxPID),
.SIERxTimeOut(SIERxTimeOut),
.SIERxTimeOutEn(SIERxTimeOutEn),
.clk(usbClk),
.getPacketEn(getPacketREn),
.rst(rstSyncToUsbClk) );
 
rxStatusMonitor u_rxStatusMonitor
(.connectStateIn(connectStateIn),
.connectStateOut(connectStateOut),
.resumeDetectedIn(resumeDetectedIn),
.connectionEventOut(connectionEventFromRxStatusMon),
.resumeIntOut(resumeIntFromRxStatusMon),
.clk(usbClk),
.rst(rstSyncToUsbClk) );
 
endmodule
 
 
 
 
 
/trunk/RTL/hostController/softransmit.v
1,202 → 1,209
 
// File : ../RTL/hostController/softransmit.v
// Generated : 11/10/06 05:37:21
// From : ../RTL/hostController/softransmit.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// softransmit
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostControl_h.v"
 
 
module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn);
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
input SOFSyncEn;
input [15:0] SOFTimer;
input clk;
input rst;
input sendPacketArbiterGnt;
input sendPacketRdy;
output SOFSent; // single cycle pulse
output SOFTimerClr; // Single cycle pulse
output sendPacketArbiterReq;
output sendPacketWEn;
 
wire SOFEnable;
reg SOFSent, next_SOFSent;
wire SOFSyncEn;
reg SOFTimerClr, next_SOFTimerClr;
wire [15:0] SOFTimer;
wire clk;
wire rst;
wire sendPacketArbiterGnt;
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
wire sendPacketRdy;
reg sendPacketWEn, next_sendPacketWEn;
 
// diagram signals declarations
reg [7:0]i, next_i;
 
// BINARY ENCODED state machine: SOFTx
// State codes definitions:
`define START_STX 3'b000
`define WAIT_SOF_NEAR 3'b001
`define WAIT_SP_GNT 3'b010
`define WAIT_SOF_NOW 3'b011
`define SOF_FIN 3'b100
`define DLY_SOF_CHK1 3'b101
`define DLY_SOF_CHK2 3'b110
 
reg [2:0] CurrState_SOFTx;
reg [2:0] NextState_SOFTx;
 
 
//--------------------------------------------------------------------
// Machine: SOFTx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
begin : SOFTx_NextState
NextState_SOFTx <= CurrState_SOFTx;
// Set default values for outputs and signals
next_sendPacketArbiterReq <= sendPacketArbiterReq;
next_sendPacketWEn <= sendPacketWEn;
next_SOFTimerClr <= SOFTimerClr;
next_SOFSent <= SOFSent;
next_i <= i;
case (CurrState_SOFTx)
`START_STX:
NextState_SOFTx <= `WAIT_SOF_NEAR;
`WAIT_SOF_NEAR:
if (SOFTimer >= `SOF_TX_TIME - `SOF_TX_MARGIN ||
(SOFSyncEn == 1'b1 &&
SOFEnable == 1'b1))
begin
NextState_SOFTx <= `WAIT_SP_GNT;
next_sendPacketArbiterReq <= 1'b1;
end
`WAIT_SP_GNT:
if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
NextState_SOFTx <= `WAIT_SOF_NOW;
`WAIT_SOF_NOW:
if (SOFTimer >= `SOF_TX_TIME)
begin
NextState_SOFTx <= `SOF_FIN;
next_sendPacketWEn <= 1'b1;
next_SOFTimerClr <= 1'b1;
next_SOFSent <= 1'b1;
end
else if (SOFEnable == 1'b0)
begin
NextState_SOFTx <= `SOF_FIN;
next_SOFTimerClr <= 1'b1;
end
`SOF_FIN:
begin
next_sendPacketWEn <= 1'b0;
next_SOFTimerClr <= 1'b0;
next_SOFSent <= 1'b0;
if (sendPacketRdy == 1'b1)
begin
NextState_SOFTx <= `DLY_SOF_CHK1;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK1:
begin
next_i <= i + 1'b1;
if (i==8'hff)
begin
NextState_SOFTx <= `DLY_SOF_CHK2;
next_sendPacketArbiterReq <= 1'b0;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK2:
begin
next_i <= i + 1'b1;
if (i==8'hff)
NextState_SOFTx <= `WAIT_SOF_NEAR;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SOFTx_CurrentState
if (rst)
CurrState_SOFTx <= `START_STX;
else
CurrState_SOFTx <= NextState_SOFTx;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SOFTx_RegOutput
if (rst)
begin
i <= 8'h00;
SOFSent <= 1'b0;
SOFTimerClr <= 1'b0;
sendPacketArbiterReq <= 1'b0;
sendPacketWEn <= 1'b0;
end
else
begin
i <= next_i;
SOFSent <= next_SOFSent;
SOFTimerClr <= next_SOFTimerClr;
sendPacketArbiterReq <= next_sendPacketArbiterReq;
sendPacketWEn <= next_sendPacketWEn;
end
end
 
endmodule
 
// File : ../RTL/hostController/softransmit.v
// Generated : 11/10/06 05:37:21
// From : ../RTL/hostController/softransmit.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// softransmit
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbHostControl_h.v"
 
 
module SOFTransmit (SOFEnable, SOFSent, SOFSyncEn, SOFTimerClr, SOFTimer, clk, rst, sendPacketArbiterGnt, sendPacketArbiterReq, sendPacketRdy, sendPacketWEn, fullSpeedRate);
input SOFEnable; // After host software asserts SOFEnable, must wait TBD time before asserting SOFSyncEn
input SOFSyncEn;
input [15:0] SOFTimer;
input clk;
input rst;
input sendPacketArbiterGnt;
input sendPacketRdy;
output SOFSent; // single cycle pulse
output SOFTimerClr; // Single cycle pulse
output sendPacketArbiterReq;
output sendPacketWEn;
input fullSpeedRate;
 
wire SOFEnable;
reg SOFSent, next_SOFSent;
wire SOFSyncEn;
reg SOFTimerClr, next_SOFTimerClr;
wire [15:0] SOFTimer;
wire clk;
wire rst;
wire sendPacketArbiterGnt;
reg sendPacketArbiterReq, next_sendPacketArbiterReq;
wire sendPacketRdy;
reg sendPacketWEn, next_sendPacketWEn;
reg [15:0] SOFNearTime;
 
// diagram signals declarations
reg [7:0]i, next_i;
 
// BINARY ENCODED state machine: SOFTx
// State codes definitions:
`define START_STX 3'b000
`define WAIT_SOF_NEAR 3'b001
`define WAIT_SP_GNT 3'b010
`define WAIT_SOF_NOW 3'b011
`define SOF_FIN 3'b100
`define DLY_SOF_CHK1 3'b101
`define DLY_SOF_CHK2 3'b110
 
reg [2:0] CurrState_SOFTx;
reg [2:0] NextState_SOFTx;
 
 
//--------------------------------------------------------------------
// Machine: SOFTx
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (i or SOFTimer or SOFSyncEn or SOFEnable or sendPacketArbiterGnt or sendPacketRdy or sendPacketArbiterReq or sendPacketWEn or SOFTimerClr or SOFSent or CurrState_SOFTx)
begin : SOFTx_NextState
NextState_SOFTx <= CurrState_SOFTx;
// Set default values for outputs and signals
next_sendPacketArbiterReq <= sendPacketArbiterReq;
next_sendPacketWEn <= sendPacketWEn;
next_SOFTimerClr <= SOFTimerClr;
next_SOFSent <= SOFSent;
next_i <= i;
case (CurrState_SOFTx)
`START_STX:
NextState_SOFTx <= `WAIT_SOF_NEAR;
`WAIT_SOF_NEAR:
if (SOFTimer >= SOFNearTime ||
(SOFSyncEn == 1'b1 &&
SOFEnable == 1'b1))
begin
NextState_SOFTx <= `WAIT_SP_GNT;
next_sendPacketArbiterReq <= 1'b1;
end
`WAIT_SP_GNT:
if (sendPacketArbiterGnt == 1'b1 && sendPacketRdy == 1'b1)
NextState_SOFTx <= `WAIT_SOF_NOW;
`WAIT_SOF_NOW:
if (SOFTimer >= `SOF_TX_TIME)
begin
NextState_SOFTx <= `SOF_FIN;
next_sendPacketWEn <= 1'b1;
next_SOFTimerClr <= 1'b1;
next_SOFSent <= 1'b1;
end
else if (SOFEnable == 1'b0)
begin
NextState_SOFTx <= `SOF_FIN;
next_SOFTimerClr <= 1'b1;
end
`SOF_FIN:
begin
next_sendPacketWEn <= 1'b0;
next_SOFTimerClr <= 1'b0;
next_SOFSent <= 1'b0;
if (sendPacketRdy == 1'b1)
begin
NextState_SOFTx <= `DLY_SOF_CHK1;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK1:
begin
next_i <= i + 1'b1;
if (i==8'hff)
begin
NextState_SOFTx <= `DLY_SOF_CHK2;
next_sendPacketArbiterReq <= 1'b0;
next_i <= 8'h00;
end
end
`DLY_SOF_CHK2:
begin
next_i <= i + 1'b1;
if (i==8'hff)
NextState_SOFTx <= `WAIT_SOF_NEAR;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : SOFTx_CurrentState
if (rst)
CurrState_SOFTx <= `START_STX;
else
CurrState_SOFTx <= NextState_SOFTx;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : SOFTx_RegOutput
if (rst)
begin
i <= 8'h00;
SOFSent <= 1'b0;
SOFTimerClr <= 1'b0;
sendPacketArbiterReq <= 1'b0;
sendPacketWEn <= 1'b0;
SOFNearTime <= 16'h0000;
end
else
begin
i <= next_i;
SOFSent <= next_SOFSent;
SOFTimerClr <= next_SOFTimerClr;
sendPacketArbiterReq <= next_sendPacketArbiterReq;
sendPacketWEn <= next_sendPacketWEn;
if (fullSpeedRate == 1'b1)
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN;
else
SOFNearTime <= `SOF_TX_TIME - `SOF_TX_MARGIN_LOW_SPEED;
end
end
 
endmodule
/trunk/RTL/include/usbHostControl_h.v
1,75 → 1,74
//////////////////////////////////////////////////////////////////////
// usbHostControl_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostControl_h_vdefined
`else
`define usbHostControl_h_vdefined
 
//HCRegIndices
`define TX_CONTROL_REG 4'h0
`define TX_TRANS_TYPE_REG 4'h1
`define TX_LINE_CONTROL_REG 4'h2
`define TX_SOF_ENABLE_REG 4'h3
`define TX_ADDR_REG 4'h4
`define TX_ENDP_REG 4'h5
`define FRAME_NUM_MSB_REG 4'h6
`define FRAME_NUM_LSB_REG 4'h7
`define INTERRUPT_STATUS_REG 4'h8
`define INTERRUPT_MASK_REG 4'h9
`define RX_STATUS_REG 4'ha
`define RX_PID_REG 4'hb
`define RX_ADDR_REG 4'hc
`define RX_ENDP_REG 4'hd
`define RX_CONNECT_STATE_REG 4'he
`define HOST_SOF_TIMER_MSB_REG 4'hf
 
`define HCREG_BUFFER_LEN 4'hf
`define HCREG_MASK 4'hf
 
//TXControlRegIndices
`define TRANS_REQ_BIT 0
`define SOF_SYNC_BIT 1
`define PREAMBLE_ENABLE_BIT 2
`define ISO_ENABLE_BIT 3
 
//interruptRegIndices
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define CONNECTION_EVENT_BIT 2
`define SOF_SENT_BIT 3
 
//TXTransactionTypes
`define SETUP_TRANS 0
`define IN_TRANS 1
`define OUTDATA0_TRANS 2
`define OUTDATA1_TRANS 3
//TXLineControlIndices
`define TX_LINE_STATE_LSBIT 0
`define TX_LINE_STATE_MSBIT 1
`define DIRECT_CONTROL_BIT 2
`define FULL_SPEED_LINE_POLARITY_BIT 3
`define FULL_SPEED_LINE_RATE_BIT 4
 
//TXSOFEnableIndices
`define SOF_EN_BIT 0
 
//SOFTimeConstants
//`define SOF_TX_TIME 80 //Fix this. Need correct SOF TX interval
//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer
`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
//`define SOF_TX_MARGIN 2
`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
//Host RXStatusRegIndices
`define HC_CRC_ERROR_BIT 0
`define HC_BIT_STUFF_ERROR_BIT 1
`define HC_RX_OVERFLOW_BIT 2
`define HC_RX_TIME_OUT_BIT 3
`define HC_NAK_RXED_BIT 4
`define HC_STALL_RXED_BIT 5
`define HC_ACK_RXED_BIT 6
`define HC_DATA_SEQUENCE_BIT 7
 
`endif //usbHostControl_h_vdefined
//////////////////////////////////////////////////////////////////////
// usbHostControl_h.v
//////////////////////////////////////////////////////////////////////
 
`ifdef usbHostControl_h_vdefined
`else
`define usbHostControl_h_vdefined
 
//HCRegIndices
`define TX_CONTROL_REG 4'h0
`define TX_TRANS_TYPE_REG 4'h1
`define TX_LINE_CONTROL_REG 4'h2
`define TX_SOF_ENABLE_REG 4'h3
`define TX_ADDR_REG 4'h4
`define TX_ENDP_REG 4'h5
`define FRAME_NUM_MSB_REG 4'h6
`define FRAME_NUM_LSB_REG 4'h7
`define INTERRUPT_STATUS_REG 4'h8
`define INTERRUPT_MASK_REG 4'h9
`define RX_STATUS_REG 4'ha
`define RX_PID_REG 4'hb
`define RX_ADDR_REG 4'hc
`define RX_ENDP_REG 4'hd
`define RX_CONNECT_STATE_REG 4'he
`define HOST_SOF_TIMER_MSB_REG 4'hf
 
`define HCREG_BUFFER_LEN 4'hf
`define HCREG_MASK 4'hf
 
//TXControlRegIndices
`define TRANS_REQ_BIT 0
`define SOF_SYNC_BIT 1
`define PREAMBLE_ENABLE_BIT 2
`define ISO_ENABLE_BIT 3
 
//interruptRegIndices
`define TRANS_DONE_BIT 0
`define RESUME_INT_BIT 1
`define CONNECTION_EVENT_BIT 2
`define SOF_SENT_BIT 3
 
//TXTransactionTypes
`define SETUP_TRANS 0
`define IN_TRANS 1
`define OUTDATA0_TRANS 2
`define OUTDATA1_TRANS 3
//TXLineControlIndices
`define TX_LINE_STATE_LSBIT 0
`define TX_LINE_STATE_MSBIT 1
`define DIRECT_CONTROL_BIT 2
`define FULL_SPEED_LINE_POLARITY_BIT 3
`define FULL_SPEED_LINE_RATE_BIT 4
 
//TXSOFEnableIndices
`define SOF_EN_BIT 0
 
//SOFTimeConstants
//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer
`define SOF_TX_TIME 16'hbb7d //Correct SOF interval for 48MHz clock.
`define SOF_TX_MARGIN 16'h0c80 //This is the transmission time for 100 bytes at full speed
`define SOF_TX_MARGIN_LOW_SPEED 16'h6400 //100 bytes at low speed
//Host RXStatusRegIndices
`define HC_CRC_ERROR_BIT 0
`define HC_BIT_STUFF_ERROR_BIT 1
`define HC_RX_OVERFLOW_BIT 2
`define HC_RX_TIME_OUT_BIT 3
`define HC_NAK_RXED_BIT 4
`define HC_STALL_RXED_BIT 5
`define HC_ACK_RXED_BIT 6
`define HC_DATA_SEQUENCE_BIT 7
 
`endif //usbHostControl_h_vdefined
/trunk/RTL/include/usbHostSlave_h.v
74,10 → 74,15
// Created new control flow constant DATA_STOP_PRE. This allows PREAMBLE PID to completed
// without SEO (EOP), and ensures line state is left at state J.
// Prevented PREAMBLE PID from preceding SOF when PREAMBLE is enabled.
// Version 2.2 - March 18th 2011. Fixed more issues related to accessing low speed device via hub.
// Added 2 bit delay time from detection of low speed SEO (ie end of packet) to notification of
// higher level modules. This satisfies USB spec requirement of 2 bit times min turn around time
// Fixed SOF transmission to avoid collision with incoming ACK response in low speed mode.
// Fixed possible problem for full speed too.
 
// Most significant nibble corresponds to major revision.
// Least significant nibble corresponds to minor revision.
`define USBHOSTSLAVE_VERSION_NUM 8'h21
`define USBHOSTSLAVE_VERSION_NUM 8'h22
 
//Host slave common registers
`define HOST_SLAVE_CONTROL_REG 1'b0
/trunk/RTL/serialInterfaceEngine/processRxBit.v
1,403 → 1,422
 
// File : ../RTL/serialInterfaceEngine/processRxBit.v
// Generated : 11/10/06 05:37:22
// From : ../RTL/serialInterfaceEngine/processRxBit.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// processrxbit
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
 
module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst);
input [1:0] JBit;
input [1:0] KBit;
input [1:0] RxBitsIn;
input RxWireActive;
input clk;
input processRxBitsWEn;
input processRxByteRdy;
input rst;
output [7:0] RxCtrlOut;
output [7:0] RxDataOut;
output processRxBitRdy;
output processRxByteWEn;
output resumeDetected;
 
wire [1:0] JBit;
wire [1:0] KBit;
wire [1:0] RxBitsIn;
reg [7:0] RxCtrlOut, next_RxCtrlOut;
reg [7:0] RxDataOut, next_RxDataOut;
wire RxWireActive;
wire clk;
reg processRxBitRdy, next_processRxBitRdy;
wire processRxBitsWEn;
wire processRxByteRdy;
reg processRxByteWEn, next_processRxByteWEn;
reg resumeDetected, next_resumeDetected;
wire rst;
 
// diagram signals declarations
reg [3:0]RXBitCount, next_RXBitCount;
reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
reg [7:0]RXByte, next_RXByte;
reg [3:0]RXSameBitCount, next_RXSameBitCount;
reg [1:0]RxBits, next_RxBits;
reg bitStuffError, next_bitStuffError;
reg [1:0]oldRXBits, next_oldRXBits;
reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
 
// BINARY ENCODED state machine: prRxBit
// State codes definitions:
`define START 4'b0000
`define IDLE_FIRST_BIT 4'b0001
`define WAIT_BITS 4'b0010
`define IDLE_CHK_KBIT 4'b0011
`define DATA_RX_LAST_BIT 4'b0100
`define DATA_RX_CHK_SE0 4'b0101
`define DATA_RX_DATA_DESTUFF 4'b0110
`define DATA_RX_BYTE_SEND2 4'b0111
`define DATA_RX_BYTE_WAIT_RDY 4'b1000
`define RES_RX_CHK 4'b1001
`define DATA_RX_ERROR_CHK_RES 4'b1010
`define RES_END_CHK1 4'b1011
`define IDLE_WAIT_PRB_RDY 4'b1100
`define DATA_RX_WAIT_PRB_RDY 4'b1101
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
 
reg [3:0] CurrState_prRxBit;
reg [3:0] NextState_prRxBit;
 
 
//--------------------------------------------------------------------
// Machine: prRxBit
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (RxBitsIn or RxBits or oldRXBits or RXSameBitCount or RXBitCount or RXByte or JBit or KBit or resumeWaitCnt or processRxBitsWEn or RXBitStMachCurrState or RxWireActive or processRxByteRdy or bitStuffError or processRxByteWEn or RxCtrlOut or RxDataOut or resumeDetected or processRxBitRdy or CurrState_prRxBit)
begin : prRxBit_NextState
NextState_prRxBit <= CurrState_prRxBit;
// Set default values for outputs and signals
next_processRxByteWEn <= processRxByteWEn;
next_RxCtrlOut <= RxCtrlOut;
next_RxDataOut <= RxDataOut;
next_resumeDetected <= resumeDetected;
next_RXBitStMachCurrState <= RXBitStMachCurrState;
next_RxBits <= RxBits;
next_RXSameBitCount <= RXSameBitCount;
next_RXBitCount <= RXBitCount;
next_oldRXBits <= oldRXBits;
next_RXByte <= RXByte;
next_bitStuffError <= bitStuffError;
next_resumeWaitCnt <= resumeWaitCnt;
next_processRxBitRdy <= processRxBitRdy;
case (CurrState_prRxBit)
`START:
begin
next_processRxByteWEn <= 1'b0;
next_RxCtrlOut <= 8'h00;
next_RxDataOut <= 8'h00;
next_resumeDetected <= 1'b0;
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
next_RxBits <= 2'b00;
next_RXSameBitCount <= 4'h0;
next_RXBitCount <= 4'h0;
next_oldRXBits <= 2'b00;
next_RXByte <= 8'h00;
next_bitStuffError <= 1'b0;
next_resumeWaitCnt <= 5'h0;
next_processRxBitRdy <= 1'b1;
NextState_prRxBit <= `WAIT_BITS;
end
`WAIT_BITS:
if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
begin
NextState_prRxBit <= `RES_RX_CHK;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
begin
NextState_prRxBit <= `DATA_RX_CHK_SE0;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
begin
NextState_prRxBit <= `IDLE_CHK_KBIT;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
begin
NextState_prRxBit <= `RES_END_CHK1;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
`IDLE_FIRST_BIT:
begin
next_processRxByteWEn <= 1'b0;
next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
next_RXSameBitCount <= 4'h0;
next_RXBitCount <= 4'h1;
next_oldRXBits <= RxBits;
//zero is always the first RZ data bit of a new packet
next_RXByte <= 8'h00;
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`IDLE_CHK_KBIT:
if ((RxBits == KBit) && (RxWireActive == 1'b1))
NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
else
begin
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`IDLE_WAIT_PRB_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `IDLE_FIRST_BIT;
next_RxDataOut <= 8'h00;
//redundant data
next_RxCtrlOut <= `DATA_START;
//start of packet
next_processRxByteWEn <= 1'b1;
end
`DATA_RX_LAST_BIT:
begin
next_processRxByteWEn <= 1'b0;
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_CHK_SE0:
begin
next_bitStuffError <= 1'b0;
if (RxBits == `SE0)
NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
else
begin
NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
begin
next_RXSameBitCount <= RXSameBitCount + 1'b1;
//inc 'RXSameBitCount'
if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
next_bitStuffError <= 1'b1;
//flag 'bitStuffError'
else //else no bit stuffing error
begin
next_RXBitCount <= RXBitCount + 1'b1;
if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
next_processRxBitRdy <= 1'b1;
//early indication of ready
end
next_RXByte <= { 1'b1, RXByte[7:1]};
//RZ bit = 1 (ie no change in 'RxBits')
end
end
else //else current 'RxBits' are different from old 'RxBits'
begin
if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
begin
next_RXBitCount <= RXBitCount + 1'b1;
if (RXBitCount != 4'h7) begin
next_processRxBitRdy <= 1'b1;
//early indication of ready
end
next_RXByte <= {1'b0, RXByte[7:1]};
//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
end
next_RXSameBitCount <= 4'h0;
//reset 'RXSameBitCount'
end
next_oldRXBits <= RxBits;
end
end
`DATA_RX_WAIT_PRB_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `DATA_RX_LAST_BIT;
next_RxDataOut <= 8'h00;
//redundant data
next_RxCtrlOut <= `DATA_STOP;
//end of packet
next_processRxByteWEn <= 1'b1;
end
`DATA_RX_DATA_DESTUFF:
if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
else if (bitStuffError == 1'b1)
NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
else
begin
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_BYTE_SEND2:
begin
next_processRxByteWEn <= 1'b0;
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_BYTE_WAIT_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
next_RXBitCount <= 4'h0;
next_RxDataOut <= RXByte;
next_RxCtrlOut <= `DATA_STREAM;
next_processRxByteWEn <= 1'b1;
end
`DATA_RX_ERROR_CHK_RES:
begin
next_processRxByteWEn <= 1'b0;
if (RxBits == JBit) //if current bit is a JBit, then
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
//next state is idle
else //else
begin
next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
//check for resume
next_resumeWaitCnt <= 5'h0;
end
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_ERROR_WAIT_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
next_RxDataOut <= 8'h00;
//redundant data
next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
next_processRxByteWEn <= 1'b1;
end
`RES_RX_CHK:
begin
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
else
begin
next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
//if we've waited long enough, then
if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
begin
next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
next_resumeDetected <= 1'b1;
//report resume detected
end
end
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`RES_END_CHK1:
begin
if (RxBits != KBit) //line must leave KBit state for the end of resume
begin
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
next_resumeDetected <= 1'b0;
//clear resume detected flag
end
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxBit_CurrentState
if (rst)
CurrState_prRxBit <= `START;
else
CurrState_prRxBit <= NextState_prRxBit;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxBit_RegOutput
if (rst)
begin
RXBitStMachCurrState <= `IDLE_BIT_ST;
RxBits <= 2'b00;
RXSameBitCount <= 4'h0;
RXBitCount <= 4'h0;
oldRXBits <= 2'b00;
RXByte <= 8'h00;
bitStuffError <= 1'b0;
resumeWaitCnt <= 5'h0;
processRxByteWEn <= 1'b0;
RxCtrlOut <= 8'h00;
RxDataOut <= 8'h00;
resumeDetected <= 1'b0;
processRxBitRdy <= 1'b1;
end
else
begin
RXBitStMachCurrState <= next_RXBitStMachCurrState;
RxBits <= next_RxBits;
RXSameBitCount <= next_RXSameBitCount;
RXBitCount <= next_RXBitCount;
oldRXBits <= next_oldRXBits;
RXByte <= next_RXByte;
bitStuffError <= next_bitStuffError;
resumeWaitCnt <= next_resumeWaitCnt;
processRxByteWEn <= next_processRxByteWEn;
RxCtrlOut <= next_RxCtrlOut;
RxDataOut <= next_RxDataOut;
resumeDetected <= next_resumeDetected;
processRxBitRdy <= next_processRxBitRdy;
end
end
 
endmodule
 
// File : ../RTL/serialInterfaceEngine/processRxBit.v
// Generated : 11/10/06 05:37:22
// From : ../RTL/serialInterfaceEngine/processRxBit.asf
// By : FSM2VHDL ver. 5.0.0.9
 
//////////////////////////////////////////////////////////////////////
//// ////
//// processrxbit
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
 
 
module processRxBit (JBit, KBit, RxBitsIn, RxCtrlOut, RxDataOut, RxWireActive, clk, processRxBitRdy, processRxBitsWEn, processRxByteRdy, processRxByteWEn, resumeDetected, rst, fullSpeedBitRate);
input [1:0] JBit;
input [1:0] KBit;
input [1:0] RxBitsIn;
input RxWireActive;
input clk;
input processRxBitsWEn;
input processRxByteRdy;
input rst;
output [7:0] RxCtrlOut;
output [7:0] RxDataOut;
output processRxBitRdy;
output processRxByteWEn;
output resumeDetected;
input fullSpeedBitRate;
 
wire [1:0] JBit;
wire [1:0] KBit;
wire [1:0] RxBitsIn;
reg [7:0] RxCtrlOut, next_RxCtrlOut;
reg [7:0] RxDataOut, next_RxDataOut;
wire RxWireActive;
wire clk;
reg processRxBitRdy, next_processRxBitRdy;
wire processRxBitsWEn;
wire processRxByteRdy;
reg processRxByteWEn, next_processRxByteWEn;
reg resumeDetected, next_resumeDetected;
wire rst;
 
// diagram signals declarations
reg [3:0]RXBitCount, next_RXBitCount;
reg [1:0]RXBitStMachCurrState, next_RXBitStMachCurrState;
reg [7:0]RXByte, next_RXByte;
reg [3:0]RXSameBitCount, next_RXSameBitCount;
reg [1:0]RxBits, next_RxBits;
reg bitStuffError, next_bitStuffError;
reg [1:0]oldRXBits, next_oldRXBits;
reg [4:0]resumeWaitCnt, next_resumeWaitCnt;
reg [7:0]delayCnt, next_delayCnt;
 
// BINARY ENCODED state machine: prRxBit
// State codes definitions:
`define START 4'b0000
`define IDLE_FIRST_BIT 4'b0001
`define WAIT_BITS 4'b0010
`define IDLE_CHK_KBIT 4'b0011
`define DATA_RX_LAST_BIT 4'b0100
`define DATA_RX_CHK_SE0 4'b0101
`define DATA_RX_DATA_DESTUFF 4'b0110
`define DATA_RX_BYTE_SEND2 4'b0111
`define DATA_RX_BYTE_WAIT_RDY 4'b1000
`define RES_RX_CHK 4'b1001
`define DATA_RX_ERROR_CHK_RES 4'b1010
`define RES_END_CHK1 4'b1011
`define IDLE_WAIT_PRB_RDY 4'b1100
`define DATA_RX_WAIT_PRB_RDY 4'b1101
`define DATA_RX_ERROR_WAIT_RDY 4'b1110
`define LOW_SPEED_EOP_DELAY 4'b1111
 
reg [3:0] CurrState_prRxBit;
reg [3:0] NextState_prRxBit;
 
 
//--------------------------------------------------------------------
// Machine: prRxBit
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (*)
begin : prRxBit_NextState
NextState_prRxBit <= CurrState_prRxBit;
// Set default values for outputs and signals
next_processRxByteWEn <= processRxByteWEn;
next_RxCtrlOut <= RxCtrlOut;
next_RxDataOut <= RxDataOut;
next_resumeDetected <= resumeDetected;
next_RXBitStMachCurrState <= RXBitStMachCurrState;
next_RxBits <= RxBits;
next_RXSameBitCount <= RXSameBitCount;
next_RXBitCount <= RXBitCount;
next_oldRXBits <= oldRXBits;
next_RXByte <= RXByte;
next_bitStuffError <= bitStuffError;
next_resumeWaitCnt <= resumeWaitCnt;
next_delayCnt <= delayCnt;
next_processRxBitRdy <= processRxBitRdy;
case (CurrState_prRxBit)
`START:
begin
next_processRxByteWEn <= 1'b0;
next_RxCtrlOut <= 8'h00;
next_RxDataOut <= 8'h00;
next_resumeDetected <= 1'b0;
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
next_RxBits <= 2'b00;
next_RXSameBitCount <= 4'h0;
next_RXBitCount <= 4'h0;
next_oldRXBits <= 2'b00;
next_RXByte <= 8'h00;
next_bitStuffError <= 1'b0;
next_resumeWaitCnt <= 5'h0;
next_processRxBitRdy <= 1'b1;
NextState_prRxBit <= `WAIT_BITS;
end
`WAIT_BITS:
if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `WAIT_RESUME_ST))
begin
NextState_prRxBit <= `RES_RX_CHK;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `DATA_RECEIVE_BIT_ST))
begin
NextState_prRxBit <= `DATA_RX_CHK_SE0;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `IDLE_BIT_ST))
begin
NextState_prRxBit <= `IDLE_CHK_KBIT;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
else if ((processRxBitsWEn == 1'b1) && (RXBitStMachCurrState == `RESUME_END_WAIT_ST))
begin
NextState_prRxBit <= `RES_END_CHK1;
next_RxBits <= RxBitsIn;
next_processRxBitRdy <= 1'b0;
end
`IDLE_FIRST_BIT:
begin
next_processRxByteWEn <= 1'b0;
next_RXBitStMachCurrState <= `DATA_RECEIVE_BIT_ST;
next_RXSameBitCount <= 4'h0;
next_RXBitCount <= 4'h1;
next_oldRXBits <= RxBits;
//zero is always the first RZ data bit of a new packet
next_RXByte <= 8'h00;
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`IDLE_CHK_KBIT:
if ((RxBits == KBit) && (RxWireActive == 1'b1))
NextState_prRxBit <= `IDLE_WAIT_PRB_RDY;
else
begin
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`IDLE_WAIT_PRB_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `IDLE_FIRST_BIT;
next_RxDataOut <= 8'h00;
//redundant data
next_RxCtrlOut <= `DATA_START;
//start of packet
next_processRxByteWEn <= 1'b1;
end
`DATA_RX_LAST_BIT:
begin
next_processRxByteWEn <= 1'b0;
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_CHK_SE0:
begin
next_bitStuffError <= 1'b0;
if (RxBits == `SE0) begin
if (fullSpeedBitRate == 1'b0) begin
NextState_prRxBit <= `LOW_SPEED_EOP_DELAY;
next_delayCnt <= 8'h00;
end
else
NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
end
else
begin
NextState_prRxBit <= `DATA_RX_DATA_DESTUFF;
if (RxBits == oldRXBits) //if the current 'RxBits' are the same as the old 'RxBits', then
begin
next_RXSameBitCount <= RXSameBitCount + 1'b1;
//inc 'RXSameBitCount'
if (RXSameBitCount == `MAX_CONSEC_SAME_BITS) //if 'RXSameBitCount' == 6 there has been a bit stuff error
next_bitStuffError <= 1'b1;
//flag 'bitStuffError'
else //else no bit stuffing error
begin
next_RXBitCount <= RXBitCount + 1'b1;
if (RXBitCount != `MAX_CONSEC_SAME_BITS_PLUS1) begin
next_processRxBitRdy <= 1'b1;
//early indication of ready
end
next_RXByte <= { 1'b1, RXByte[7:1]};
//RZ bit = 1 (ie no change in 'RxBits')
end
end
else //else current 'RxBits' are different from old 'RxBits'
begin
if (RXSameBitCount != `MAX_CONSEC_SAME_BITS) //if this is not the RZ 0 bit after 6 consecutive RZ 1s, then
begin
next_RXBitCount <= RXBitCount + 1'b1;
if (RXBitCount != 4'h7) begin
next_processRxBitRdy <= 1'b1;
//early indication of ready
end
next_RXByte <= {1'b0, RXByte[7:1]};
//RZ bit = 0 (ie current'RxBits' is different than old 'RxBits')
end
next_RXSameBitCount <= 4'h0;
//reset 'RXSameBitCount'
end
next_oldRXBits <= RxBits;
end
end
`DATA_RX_WAIT_PRB_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `DATA_RX_LAST_BIT;
next_RxDataOut <= 8'h00;
//redundant data
next_RxCtrlOut <= `DATA_STOP;
//end of packet
next_processRxByteWEn <= 1'b1;
end
`DATA_RX_DATA_DESTUFF:
if (RXBitCount == 4'h8 & bitStuffError == 1'b0)
NextState_prRxBit <= `DATA_RX_BYTE_WAIT_RDY;
else if (bitStuffError == 1'b1)
NextState_prRxBit <= `DATA_RX_ERROR_WAIT_RDY;
else
begin
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_BYTE_SEND2:
begin
next_processRxByteWEn <= 1'b0;
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_BYTE_WAIT_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `DATA_RX_BYTE_SEND2;
next_RXBitCount <= 4'h0;
next_RxDataOut <= RXByte;
next_RxCtrlOut <= `DATA_STREAM;
next_processRxByteWEn <= 1'b1;
end
`DATA_RX_ERROR_CHK_RES:
begin
next_processRxByteWEn <= 1'b0;
if (RxBits == JBit) //if current bit is a JBit, then
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
//next state is idle
else //else
begin
next_RXBitStMachCurrState <= `WAIT_RESUME_ST;
//check for resume
next_resumeWaitCnt <= 5'h0;
end
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`DATA_RX_ERROR_WAIT_RDY:
if (processRxByteRdy == 1'b1)
begin
NextState_prRxBit <= `DATA_RX_ERROR_CHK_RES;
next_RxDataOut <= 8'h00;
//redundant data
next_RxCtrlOut <= `DATA_BIT_STUFF_ERROR;
next_processRxByteWEn <= 1'b1;
end
`RES_RX_CHK:
begin
if (RxBits != KBit) //can only be a resume if line remains in Kbit state
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
else
begin
next_resumeWaitCnt <= resumeWaitCnt + 1'b1;
//if we've waited long enough, then
if (resumeWaitCnt == `RESUME_RX_WAIT_TIME)
begin
next_RXBitStMachCurrState <= `RESUME_END_WAIT_ST;
next_resumeDetected <= 1'b1;
//report resume detected
end
end
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`RES_END_CHK1:
begin
if (RxBits != KBit) //line must leave KBit state for the end of resume
begin
next_RXBitStMachCurrState <= `IDLE_BIT_ST;
next_resumeDetected <= 1'b0;
//clear resume detected flag
end
NextState_prRxBit <= `WAIT_BITS;
next_processRxBitRdy <= 1'b1;
end
`LOW_SPEED_EOP_DELAY:
begin
//turn around time must be at least 2 low speed bit periods
next_delayCnt <= delayCnt + 1'b1;
if (delayCnt == `LS_OVER_SAMPLE_RATE * 2)
NextState_prRxBit <= `DATA_RX_WAIT_PRB_RDY;
end
endcase
end
 
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : prRxBit_CurrentState
if (rst)
CurrState_prRxBit <= `START;
else
CurrState_prRxBit <= NextState_prRxBit;
end
 
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : prRxBit_RegOutput
if (rst)
begin
RXBitStMachCurrState <= `IDLE_BIT_ST;
RxBits <= 2'b00;
RXSameBitCount <= 4'h0;
RXBitCount <= 4'h0;
oldRXBits <= 2'b00;
RXByte <= 8'h00;
bitStuffError <= 1'b0;
resumeWaitCnt <= 5'h0;
delayCnt <= 8'h00;
processRxByteWEn <= 1'b0;
RxCtrlOut <= 8'h00;
RxDataOut <= 8'h00;
resumeDetected <= 1'b0;
processRxBitRdy <= 1'b1;
end
else
begin
RXBitStMachCurrState <= next_RXBitStMachCurrState;
RxBits <= next_RxBits;
RXSameBitCount <= next_RXSameBitCount;
RXBitCount <= next_RXBitCount;
oldRXBits <= next_oldRXBits;
RXByte <= next_RXByte;
bitStuffError <= next_bitStuffError;
resumeWaitCnt <= next_resumeWaitCnt;
delayCnt <= next_delayCnt;
processRxByteWEn <= next_processRxByteWEn;
RxCtrlOut <= next_RxCtrlOut;
RxDataOut <= next_RxDataOut;
resumeDetected <= next_resumeDetected;
processRxBitRdy <= next_processRxBitRdy;
end
end
 
endmodule
/trunk/RTL/serialInterfaceEngine/usbSerialInterfaceEngine.v
1,394 → 1,396
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSerialInterfaceEngine.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbSerialInterfaceEngine(
clk, rst,
//readUSBWireData
USBWireDataIn,
USBWireDataInTick,
//writeUSBWireData
USBWireDataOut,
USBWireCtrlOut,
USBWireDataOutTick,
//SIEReceiver
connectState,
//processRxBit
resumeDetected,
//processRxByte
RxCtrlOut,
RxDataOutWEn,
RxDataOut,
//SIETransmitter
SIEPortCtrlIn,
SIEPortDataIn,
SIEPortTxRdy,
SIEPortWEn,
//lineControlUpdate
fullSpeedPolarity,
fullSpeedBitRate,
noActivityTimeOut,
noActivityTimeOutEnable
);
 
input clk, rst;
//readUSBWireData
input [1:0] USBWireDataIn;
output USBWireDataInTick;
output noActivityTimeOut;
input noActivityTimeOutEnable;
 
//writeUSBWireData
output [1:0] USBWireDataOut;
output USBWireCtrlOut;
output USBWireDataOutTick;
 
//SIEReceiver
output [1:0] connectState;
//processRxBit
output resumeDetected;
//processRxByte
output [7:0] RxCtrlOut;
output RxDataOutWEn;
output [7:0] RxDataOut;
//SIETransmitter
input [7:0] SIEPortCtrlIn;
input [7:0] SIEPortDataIn;
output SIEPortTxRdy;
input SIEPortWEn;
//lineControlUpdate
input fullSpeedPolarity;
input fullSpeedBitRate;
 
wire clk, rst;
//readUSBWireData
wire [1:0] USBWireDataIn;
wire USBWireDataInTick;
//writeUSBWireData
wire [1:0] USBWireDataOut;
wire USBWireCtrlOut;
wire noActivityTimeOut;
wire USBWireDataOutTick;
//SIEReceiver
wire [1:0] connectState;
//processRxBit
wire resumeDetected;
//processRxByte
wire [7:0] RxCtrlOut;
wire RxDataOutWEn;
wire [7:0] RxDataOut;
//SIETransmitter
wire [7:0] SIEPortCtrlIn;
wire [7:0] SIEPortDataIn;
wire SIEPortTxRdy;
wire SIEPortWEn;
//lineControlUpdate
wire fullSpeedPolarity;
wire fullSpeedBitRate;
 
//internal wiring
wire processRxBitsWEn;
wire processRxBitRdy;
wire [1:0] RxWireDataFromWireRx;
wire RxWireDataWEn;
wire TxWireActiveDrive;
wire [1:0] TxBitsFromArbToWire;
wire TxCtrlFromArbToWire;
wire USBWireRdy;
wire USBWireWEn;
wire USBWireReadyFromTxArb;
wire prcTxByteCtrl;
wire [1:0] prcTxByteData;
wire prcTxByteGnt;
wire prcTxByteReq;
wire prcTxByteWEn;
wire SIETxCtrl;
wire [1:0] SIETxData;
wire SIETxGnt;
wire SIETxReq;
wire SIETxWEn;
wire [7:0] TxByteFromSIEToPrcTxByte;
wire [7:0] TxCtrlFromSIEToPrcTxByte;
wire [1:0] JBit;
wire [1:0] KBit;
wire processRxByteWEn;
wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
wire processRxByteRdy;
//Rx CRC
wire RxCRC16En;
wire [15:0] RxCRC16Result;
wire RxCRC16UpdateRdy;
wire RxCRC5En;
wire [4:0] RxCRC5Result;
wire RxCRC5_8Bit;
wire [7:0] RxCRCData;
wire RxRstCRC;
wire RxCRC5UpdateRdy;
//Tx CRC
wire TxCRC16En;
wire [15:0] TxCRC16Result;
wire TxCRC16UpdateRdy;
wire TxCRC5En;
wire [4:0] TxCRC5Result;
wire TxCRC5_8Bit;
wire [7:0] TxCRCData;
wire TxRstCRC;
wire TxCRC5UpdateRdy;
 
wire processTxByteRdy;
wire processTxByteWEn;
 
wire SIEFsRate;
wire TxFSRateFromSIETxToPrcTxByte;
wire prcTxByteFSRate;
wire FSRateFromArbiterToWire;
 
wire RxWireActive;
 
lineControlUpdate u_lineControlUpdate
(.fullSpeedPolarity(fullSpeedPolarity),
.fullSpeedBitRate(fullSpeedBitRate),
.JBit(JBit),
.KBit(KBit) );
 
SIEReceiver u_SIEReceiver
(
.RxWireDataIn(RxWireDataFromWireRx),
.RxWireDataWEn(RxWireDataWEn),
.clk(clk),
.connectState(connectState),
.rst(rst) );
 
processRxBit u_processRxBit
(.JBit(JBit),
.KBit(KBit),
.RxBitsIn(RxWireDataFromWireRx),
.RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte),
.RxDataOut(RxDataFromPrcRxBitToPrcRxByte),
.clk(clk),
.processRxBitRdy(processRxBitRdy),
.processRxBitsWEn(RxWireDataWEn),
.processRxByteWEn(processRxByteWEn),
.resumeDetected(resumeDetected),
.rst(rst),
.processRxByteRdy(processRxByteRdy),
.RxWireActive(RxWireActive)
);
processRxByte u_processRxByte
(.CRC16En(RxCRC16En),
.CRC16Result(RxCRC16Result),
.CRC16UpdateRdy(RxCRC16UpdateRdy),
.CRC5En(RxCRC5En),
.CRC5Result(RxCRC5Result),
.CRC5_8Bit(RxCRC5_8Bit),
.CRC5UpdateRdy(RxCRC5UpdateRdy),
.CRCData(RxCRCData),
.RxByteIn(RxDataFromPrcRxBitToPrcRxByte),
.RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataOut),
.clk(clk),
.processRxDataInWEn(processRxByteWEn),
.rst(rst),
.rstCRC(RxRstCRC),
.processRxByteRdy(processRxByteRdy) );
updateCRC5 RxUpdateCRC5
(.rstCRC(RxRstCRC),
.CRCResult(RxCRC5Result),
.CRCEn(RxCRC5En),
.CRC5_8BitIn(RxCRC5_8Bit),
.dataIn(RxCRCData),
.ready(RxCRC5UpdateRdy),
.clk(clk),
.rst(rst) );
updateCRC16 RxUpdateCRC16
(.rstCRC(RxRstCRC),
.CRCResult(RxCRC16Result),
.CRCEn(RxCRC16En),
.dataIn(RxCRCData),
.ready(RxCRC16UpdateRdy),
.clk(clk),
.rst(rst) );
SIETransmitter u_SIETransmitter
(.CRC16En(TxCRC16En),
.CRC16Result(TxCRC16Result),
.CRC5En(TxCRC5En),
.CRC5Result(TxCRC5Result),
.CRC5_8Bit(TxCRC5_8Bit),
.CRCData(TxCRCData),
.CRC5UpdateRdy(TxCRC5UpdateRdy),
.CRC16UpdateRdy(TxCRC16UpdateRdy),
.JBit(JBit),
.KBit(KBit),
.SIEPortCtrlIn(SIEPortCtrlIn),
.SIEPortDataIn(SIEPortDataIn),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEn),
.TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte),
.TxByteOut(TxByteFromSIEToPrcTxByte),
.USBWireCtrl(SIETxCtrl),
.USBWireData(SIETxData),
.USBWireGnt(SIETxGnt),
.USBWireRdy(USBWireReadyFromTxArb),
.USBWireReq(SIETxReq),
.USBWireWEn(SIETxWEn),
.clk(clk),
.processTxByteRdy(processTxByteRdy),
.processTxByteWEn(processTxByteWEn),
.rst(rst),
.rstCRC(TxRstCRC),
.USBWireFullSpeedRate(SIEFsRate),
.TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
.fullSpeedRateIn(fullSpeedBitRate)
);
 
updateCRC5 TxUpdateCRC5
(.rstCRC(TxRstCRC),
.CRCResult(TxCRC5Result),
.CRCEn(TxCRC5En),
.CRC5_8BitIn(TxCRC5_8Bit),
.dataIn(TxCRCData),
.ready(TxCRC5UpdateRdy),
.clk(clk),
.rst(rst) );
updateCRC16 TxUpdateCRC16
(.rstCRC(TxRstCRC),
.CRCResult(TxCRC16Result),
.CRCEn(TxCRC16En),
.dataIn(TxCRCData),
.ready(TxCRC16UpdateRdy),
.clk(clk),
.rst(rst) );
 
processTxByte u_processTxByte
(.JBit(JBit),
.KBit(KBit),
.TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte),
.TxByteIn(TxByteFromSIEToPrcTxByte),
.USBWireCtrl(prcTxByteCtrl),
.USBWireData(prcTxByteData),
.USBWireGnt(prcTxByteGnt),
.USBWireRdy(USBWireReadyFromTxArb),
.USBWireReq(prcTxByteReq),
.USBWireWEn(prcTxByteWEn),
.clk(clk),
.processTxByteRdy(processTxByteRdy),
.processTxByteWEn(processTxByteWEn),
.rst(rst),
.USBWireFullSpeedRate(prcTxByteFSRate),
.TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
);
USBTxWireArbiter u_USBTxWireArbiter
(.SIETxCtrl(SIETxCtrl),
.SIETxData(SIETxData),
.SIETxGnt(SIETxGnt),
.SIETxReq(SIETxReq),
.SIETxWEn(SIETxWEn),
.TxBits(TxBitsFromArbToWire),
.TxCtl(TxCtrlFromArbToWire),
.USBWireRdyIn(USBWireRdy),
.USBWireRdyOut(USBWireReadyFromTxArb),
.USBWireWEn(USBWireWEn),
.clk(clk),
.prcTxByteCtrl(prcTxByteCtrl),
.prcTxByteData(prcTxByteData),
.prcTxByteGnt(prcTxByteGnt),
.prcTxByteReq(prcTxByteReq),
.prcTxByteWEn(prcTxByteWEn),
.rst(rst),
.SIETxFSRate(SIEFsRate),
.prcTxByteFSRate(prcTxByteFSRate),
.TxFSRate(FSRateFromArbiterToWire)
);
writeUSBWireData u_writeUSBWireData
(.TxBitsIn(TxBitsFromArbToWire),
.TxBitsOut(USBWireDataOut),
.TxDataOutTick(USBWireDataOutTick),
.TxCtrlIn(TxCtrlFromArbToWire),
.TxCtrlOut(USBWireCtrlOut),
.USBWireRdy(USBWireRdy),
.USBWireWEn(USBWireWEn),
.TxWireActiveDrive(TxWireActiveDrive),
.fullSpeedRate(FSRateFromArbiterToWire),
.clk(clk),
.rst(rst)
);
 
readUSBWireData u_readUSBWireData
(.RxBitsIn(USBWireDataIn),
.RxDataInTick(USBWireDataInTick),
.RxBitsOut(RxWireDataFromWireRx),
.SIERxRdyIn(processRxBitRdy),
.SIERxWEn(RxWireDataWEn),
.fullSpeedRate(fullSpeedBitRate),
.TxWireActiveDrive(TxWireActiveDrive),
.clk(clk),
.rst(rst),
.noActivityTimeOut(noActivityTimeOut),
.RxWireActive(RxWireActive),
.noActivityTimeOutEnable(noActivityTimeOutEnable)
);
 
 
endmodule
 
 
 
 
 
//////////////////////////////////////////////////////////////////////
//// ////
//// usbSerialInterfaceEngine.v ////
//// ////
//// This file is part of the usbhostslave opencores effort.
//// <http://www.opencores.org/cores//> ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, sfielding@base2designs.com ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from <http://www.opencores.org/lgpl.shtml> ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
module usbSerialInterfaceEngine(
clk, rst,
//readUSBWireData
USBWireDataIn,
USBWireDataInTick,
//writeUSBWireData
USBWireDataOut,
USBWireCtrlOut,
USBWireDataOutTick,
//SIEReceiver
connectState,
//processRxBit
resumeDetected,
//processRxByte
RxCtrlOut,
RxDataOutWEn,
RxDataOut,
//SIETransmitter
SIEPortCtrlIn,
SIEPortDataIn,
SIEPortTxRdy,
SIEPortWEn,
//lineControlUpdate
fullSpeedPolarity,
fullSpeedBitRate,
noActivityTimeOut,
noActivityTimeOutEnable
);
 
input clk, rst;
//readUSBWireData
input [1:0] USBWireDataIn;
output USBWireDataInTick;
output noActivityTimeOut;
input noActivityTimeOutEnable;
 
//writeUSBWireData
output [1:0] USBWireDataOut;
output USBWireCtrlOut;
output USBWireDataOutTick;
 
//SIEReceiver
output [1:0] connectState;
//processRxBit
output resumeDetected;
//processRxByte
output [7:0] RxCtrlOut;
output RxDataOutWEn;
output [7:0] RxDataOut;
//SIETransmitter
input [7:0] SIEPortCtrlIn;
input [7:0] SIEPortDataIn;
output SIEPortTxRdy;
input SIEPortWEn;
//lineControlUpdate
input fullSpeedPolarity;
input fullSpeedBitRate;
 
wire clk, rst;
//readUSBWireData
wire [1:0] USBWireDataIn;
wire USBWireDataInTick;
//writeUSBWireData
wire [1:0] USBWireDataOut;
wire USBWireCtrlOut;
wire noActivityTimeOut;
wire USBWireDataOutTick;
//SIEReceiver
wire [1:0] connectState;
//processRxBit
wire resumeDetected;
//processRxByte
wire [7:0] RxCtrlOut;
wire RxDataOutWEn;
wire [7:0] RxDataOut;
//SIETransmitter
wire [7:0] SIEPortCtrlIn;
wire [7:0] SIEPortDataIn;
wire SIEPortTxRdy;
wire SIEPortWEn;
//lineControlUpdate
wire fullSpeedPolarity;
wire fullSpeedBitRate;
 
//internal wiring
wire processRxBitsWEn;
wire processRxBitRdy;
wire [1:0] RxWireDataFromWireRx;
wire RxWireDataWEn;
wire TxWireActiveDrive;
wire [1:0] TxBitsFromArbToWire;
wire TxCtrlFromArbToWire;
wire USBWireRdy;
wire USBWireWEn;
wire USBWireReadyFromTxArb;
wire prcTxByteCtrl;
wire [1:0] prcTxByteData;
wire prcTxByteGnt;
wire prcTxByteReq;
wire prcTxByteWEn;
wire SIETxCtrl;
wire [1:0] SIETxData;
wire SIETxGnt;
wire SIETxReq;
wire SIETxWEn;
wire [7:0] TxByteFromSIEToPrcTxByte;
wire [7:0] TxCtrlFromSIEToPrcTxByte;
wire [1:0] JBit;
wire [1:0] KBit;
wire processRxByteWEn;
wire [7:0] RxDataFromPrcRxBitToPrcRxByte;
wire [7:0] RxCtrlFromPrcRxBitToPrcRxByte;
wire processRxByteRdy;
//Rx CRC
wire RxCRC16En;
wire [15:0] RxCRC16Result;
wire RxCRC16UpdateRdy;
wire RxCRC5En;
wire [4:0] RxCRC5Result;
wire RxCRC5_8Bit;
wire [7:0] RxCRCData;
wire RxRstCRC;
wire RxCRC5UpdateRdy;
//Tx CRC
wire TxCRC16En;
wire [15:0] TxCRC16Result;
wire TxCRC16UpdateRdy;
wire TxCRC5En;
wire [4:0] TxCRC5Result;
wire TxCRC5_8Bit;
wire [7:0] TxCRCData;
wire TxRstCRC;
wire TxCRC5UpdateRdy;
 
wire processTxByteRdy;
wire processTxByteWEn;
 
wire SIEFsRate;
wire TxFSRateFromSIETxToPrcTxByte;
wire prcTxByteFSRate;
wire FSRateFromArbiterToWire;
 
wire RxWireActive;
 
lineControlUpdate u_lineControlUpdate
(.fullSpeedPolarity(fullSpeedPolarity),
.fullSpeedBitRate(fullSpeedBitRate),
.JBit(JBit),
.KBit(KBit) );
 
SIEReceiver u_SIEReceiver
(
.RxWireDataIn(RxWireDataFromWireRx),
.RxWireDataWEn(RxWireDataWEn),
.clk(clk),
.connectState(connectState),
.rst(rst) );
 
processRxBit u_processRxBit
(.JBit(JBit),
.KBit(KBit),
.RxBitsIn(RxWireDataFromWireRx),
.RxCtrlOut(RxCtrlFromPrcRxBitToPrcRxByte),
.RxDataOut(RxDataFromPrcRxBitToPrcRxByte),
.clk(clk),
.processRxBitRdy(processRxBitRdy),
.processRxBitsWEn(RxWireDataWEn),
.processRxByteWEn(processRxByteWEn),
.resumeDetected(resumeDetected),
.rst(rst),
.processRxByteRdy(processRxByteRdy),
.RxWireActive(RxWireActive),
.fullSpeedBitRate(fullSpeedBitRate)
 
);
processRxByte u_processRxByte
(.CRC16En(RxCRC16En),
.CRC16Result(RxCRC16Result),
.CRC16UpdateRdy(RxCRC16UpdateRdy),
.CRC5En(RxCRC5En),
.CRC5Result(RxCRC5Result),
.CRC5_8Bit(RxCRC5_8Bit),
.CRC5UpdateRdy(RxCRC5UpdateRdy),
.CRCData(RxCRCData),
.RxByteIn(RxDataFromPrcRxBitToPrcRxByte),
.RxCtrlIn(RxCtrlFromPrcRxBitToPrcRxByte),
.RxCtrlOut(RxCtrlOut),
.RxDataOutWEn(RxDataOutWEn),
.RxDataOut(RxDataOut),
.clk(clk),
.processRxDataInWEn(processRxByteWEn),
.rst(rst),
.rstCRC(RxRstCRC),
.processRxByteRdy(processRxByteRdy) );
updateCRC5 RxUpdateCRC5
(.rstCRC(RxRstCRC),
.CRCResult(RxCRC5Result),
.CRCEn(RxCRC5En),
.CRC5_8BitIn(RxCRC5_8Bit),
.dataIn(RxCRCData),
.ready(RxCRC5UpdateRdy),
.clk(clk),
.rst(rst) );
updateCRC16 RxUpdateCRC16
(.rstCRC(RxRstCRC),
.CRCResult(RxCRC16Result),
.CRCEn(RxCRC16En),
.dataIn(RxCRCData),
.ready(RxCRC16UpdateRdy),
.clk(clk),
.rst(rst) );
SIETransmitter u_SIETransmitter
(.CRC16En(TxCRC16En),
.CRC16Result(TxCRC16Result),
.CRC5En(TxCRC5En),
.CRC5Result(TxCRC5Result),
.CRC5_8Bit(TxCRC5_8Bit),
.CRCData(TxCRCData),
.CRC5UpdateRdy(TxCRC5UpdateRdy),
.CRC16UpdateRdy(TxCRC16UpdateRdy),
.JBit(JBit),
.KBit(KBit),
.SIEPortCtrlIn(SIEPortCtrlIn),
.SIEPortDataIn(SIEPortDataIn),
.SIEPortTxRdy(SIEPortTxRdy),
.SIEPortWEn(SIEPortWEn),
.TxByteOutCtrl(TxCtrlFromSIEToPrcTxByte),
.TxByteOut(TxByteFromSIEToPrcTxByte),
.USBWireCtrl(SIETxCtrl),
.USBWireData(SIETxData),
.USBWireGnt(SIETxGnt),
.USBWireRdy(USBWireReadyFromTxArb),
.USBWireReq(SIETxReq),
.USBWireWEn(SIETxWEn),
.clk(clk),
.processTxByteRdy(processTxByteRdy),
.processTxByteWEn(processTxByteWEn),
.rst(rst),
.rstCRC(TxRstCRC),
.USBWireFullSpeedRate(SIEFsRate),
.TxByteOutFullSpeedRate(TxFSRateFromSIETxToPrcTxByte),
.fullSpeedRateIn(fullSpeedBitRate)
);
 
updateCRC5 TxUpdateCRC5
(.rstCRC(TxRstCRC),
.CRCResult(TxCRC5Result),
.CRCEn(TxCRC5En),
.CRC5_8BitIn(TxCRC5_8Bit),
.dataIn(TxCRCData),
.ready(TxCRC5UpdateRdy),
.clk(clk),
.rst(rst) );
updateCRC16 TxUpdateCRC16
(.rstCRC(TxRstCRC),
.CRCResult(TxCRC16Result),
.CRCEn(TxCRC16En),
.dataIn(TxCRCData),
.ready(TxCRC16UpdateRdy),
.clk(clk),
.rst(rst) );
 
processTxByte u_processTxByte
(.JBit(JBit),
.KBit(KBit),
.TxByteCtrlIn(TxCtrlFromSIEToPrcTxByte),
.TxByteIn(TxByteFromSIEToPrcTxByte),
.USBWireCtrl(prcTxByteCtrl),
.USBWireData(prcTxByteData),
.USBWireGnt(prcTxByteGnt),
.USBWireRdy(USBWireReadyFromTxArb),
.USBWireReq(prcTxByteReq),
.USBWireWEn(prcTxByteWEn),
.clk(clk),
.processTxByteRdy(processTxByteRdy),
.processTxByteWEn(processTxByteWEn),
.rst(rst),
.USBWireFullSpeedRate(prcTxByteFSRate),
.TxByteFullSpeedRateIn(TxFSRateFromSIETxToPrcTxByte)
);
USBTxWireArbiter u_USBTxWireArbiter
(.SIETxCtrl(SIETxCtrl),
.SIETxData(SIETxData),
.SIETxGnt(SIETxGnt),
.SIETxReq(SIETxReq),
.SIETxWEn(SIETxWEn),
.TxBits(TxBitsFromArbToWire),
.TxCtl(TxCtrlFromArbToWire),
.USBWireRdyIn(USBWireRdy),
.USBWireRdyOut(USBWireReadyFromTxArb),
.USBWireWEn(USBWireWEn),
.clk(clk),
.prcTxByteCtrl(prcTxByteCtrl),
.prcTxByteData(prcTxByteData),
.prcTxByteGnt(prcTxByteGnt),
.prcTxByteReq(prcTxByteReq),
.prcTxByteWEn(prcTxByteWEn),
.rst(rst),
.SIETxFSRate(SIEFsRate),
.prcTxByteFSRate(prcTxByteFSRate),
.TxFSRate(FSRateFromArbiterToWire)
);
writeUSBWireData u_writeUSBWireData
(.TxBitsIn(TxBitsFromArbToWire),
.TxBitsOut(USBWireDataOut),
.TxDataOutTick(USBWireDataOutTick),
.TxCtrlIn(TxCtrlFromArbToWire),
.TxCtrlOut(USBWireCtrlOut),
.USBWireRdy(USBWireRdy),
.USBWireWEn(USBWireWEn),
.TxWireActiveDrive(TxWireActiveDrive),
.fullSpeedRate(FSRateFromArbiterToWire),
.clk(clk),
.rst(rst)
);
 
readUSBWireData u_readUSBWireData
(.RxBitsIn(USBWireDataIn),
.RxDataInTick(USBWireDataInTick),
.RxBitsOut(RxWireDataFromWireRx),
.SIERxRdyIn(processRxBitRdy),
.SIERxWEn(RxWireDataWEn),
.fullSpeedRate(fullSpeedBitRate),
.TxWireActiveDrive(TxWireActiveDrive),
.clk(clk),
.rst(rst),
.noActivityTimeOut(noActivityTimeOut),
.RxWireActive(RxWireActive),
.noActivityTimeOutEnable(noActivityTimeOutEnable)
);
 
 
endmodule
 
 
 
 
 

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