URL
https://opencores.org/ocsvn/usimplez/usimplez/trunk
Subversion Repositories usimplez
Compare Revisions
- This comparison shows the changes necessary to convert path
/usimplez/trunk
- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/QuartusII/usimplez.map.summary
0,0 → 1,15
Analysis & Synthesis Status : Successful - Wed Nov 09 01:44:56 2011 |
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition |
Revision Name : usimplez |
Top-level Entity Name : usimplez_top |
Family : Stratix II |
Logic utilization : N/A |
Combinational ALUTs : 48 |
Dedicated logic registers : 63 |
Total registers : 63 |
Total pins : 7 |
Total virtual pins : 0 |
Total block memory bits : 6,144 |
DSP block 9-bit elements : 0 |
Total PLLs : 0 |
Total DLLs : 0 |
/QuartusII/usimplez.qws
0,0 → 1,7
[ProjectWorkspace] |
ptn_Child1=Frames |
[ProjectWorkspace.Frames] |
ptn_Child1=ChildFrames |
[ProjectWorkspace.Frames.ChildFrames] |
ptn_Child1=Document-0 |
ptn_Child2=Document-1 |
/QuartusII/usimplez.flow.rpt
0,0 → 1,117
Flow report for usimplez |
Wed Nov 09 01:53:40 2011 |
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition |
|
|
--------------------- |
; Table of Contents ; |
--------------------- |
1. Legal Notice |
2. Flow Summary |
3. Flow Settings |
4. Flow Non-Default Global Settings |
5. Flow Elapsed Time |
6. Flow OS Summary |
7. Flow Log |
|
|
|
---------------- |
; Legal Notice ; |
---------------- |
Copyright (C) 1991-2010 Altera Corporation |
Your use of Altera Corporation's design tools, logic functions |
and other software and tools, and its AMPP partner logic |
functions, and any output files from any of the foregoing |
(including device programming or simulation files), and any |
associated documentation or information are expressly subject |
to the terms and conditions of the Altera Program License |
Subscription Agreement, Altera MegaCore Function License |
Agreement, or other applicable license agreement, including, |
without limitation, that your use is for the sole purpose of |
programming logic devices manufactured by Altera and sold by |
Altera or its authorized distributors. Please refer to the |
applicable agreement for further details. |
|
|
|
+------------------------------------------------------------------------------+ |
; Flow Summary ; |
+-------------------------------+----------------------------------------------+ |
; Flow Status ; Successful - Wed Nov 09 01:53:40 2011 ; |
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; |
; Revision Name ; usimplez ; |
; Top-level Entity Name ; usimplez_top ; |
; Family ; Stratix II ; |
; Met timing requirements ; Yes ; |
; Logic utilization ; < 1 % ; |
; Combinational ALUTs ; 48 / 12,480 ( < 1 % ) ; |
; Dedicated logic registers ; 63 / 12,480 ( < 1 % ) ; |
; Total registers ; 63 ; |
; Total pins ; 7 / 343 ( 2 % ) ; |
; Total virtual pins ; 0 ; |
; Total block memory bits ; 6,144 / 419,328 ( 1 % ) ; |
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ; |
; Total PLLs ; 0 / 6 ( 0 % ) ; |
; Total DLLs ; 0 / 2 ( 0 % ) ; |
; Device ; EP2S15F484C3 ; |
; Timing Models ; Final ; |
+-------------------------------+----------------------------------------------+ |
|
|
+-----------------------------------------+ |
; Flow Settings ; |
+-------------------+---------------------+ |
; Option ; Setting ; |
+-------------------+---------------------+ |
; Start date & time ; 11/09/2011 01:44:44 ; |
; Main task ; Compilation ; |
; Revision Name ; usimplez ; |
+-------------------+---------------------+ |
|
|
+---------------------------------------------------------------------------------------------------------------------+ |
; Flow Non-Default Global Settings ; |
+------------------------------------+--------------------------------+---------------+--------------+----------------+ |
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; |
+------------------------------------+--------------------------------+---------------+--------------+----------------+ |
; COMPILER_SIGNATURE_ID ; 13608450046966.132081388303004 ; -- ; -- ; -- ; |
; PARTITION_COLOR ; 16764057 ; -- ; usimplez_top ; Top ; |
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; usimplez_top ; Top ; |
; TOP_LEVEL_ENTITY ; usimplez_top ; usimplez ; -- ; -- ; |
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; |
+------------------------------------+--------------------------------+---------------+--------------+----------------+ |
|
|
+-----------------------------------------------------------------------------------------------------------------------------+ |
; Flow Elapsed Time ; |
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ |
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; |
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ |
; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 195 MB ; 00:00:12 ; |
; Fitter ; 00:00:32 ; 1.0 ; 236 MB ; 00:00:27 ; |
; Classic Timing Analyzer ; 00:00:08 ; 1.0 ; 155 MB ; 00:00:08 ; |
; Total ; 00:00:57 ; -- ; -- ; 00:00:47 ; |
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ |
|
|
+---------------------------------------------------------------------------------------+ |
; Flow OS Summary ; |
+-------------------------+------------------+------------+------------+----------------+ |
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; |
+-------------------------+------------------+------------+------------+----------------+ |
; Analysis & Synthesis ; LAPTOP ; Windows XP ; 5.1 ; i686 ; |
; Fitter ; LAPTOP ; Windows XP ; 5.1 ; i686 ; |
; Classic Timing Analyzer ; LAPTOP ; Windows XP ; 5.1 ; i686 ; |
+-------------------------+------------------+------------+------------+----------------+ |
|
|
------------ |
; Flow Log ; |
------------ |
quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez |
quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez |
quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez |
|
|
|
/QuartusII/usimplez_ram.vhd.bak
0,0 → 1,97
--////////////////////////////////////////////////////////////////////// |
--//// //// |
--//// //// |
--//// //// |
--//// This file is part of the MicroSimplez project //// |
--//// http://opencores.org/project,usimplez //// |
--//// //// |
--//// Description //// |
--//// Implementation of MicroSimplez IP core according to //// |
--//// MicroSimplez IP core specification document. //// |
--//// //// |
--//// To Do: //// |
--//// - //// |
--//// //// |
--//// Author(s): //// |
--//// - Daniel Peralta, peraltahd@opencores.org, designer //// |
--//// - Martin Montero, monteromrtn@opencores.org, designer //// |
--//// - Julian Castro, julyan@opencores.org, reviewer //// |
--//// - Pablo A. Salvadeo, pas.@opencores, manager //// |
--//// //// |
--////////////////////////////////////////////////////////////////////// |
--//// //// |
--//// Copyright (C) 2011 Authors and OPENCORES.ORG //// |
--//// //// |
--//// This source file may be used and distributed without //// |
--//// restriction provided that this copyright statement is not //// |
--//// removed from the file and that any derivative work contains //// |
--//// the original copyright notice and the associated disclaimer. //// |
--//// //// |
--//// This source file is free software; you can redistribute it //// |
--//// and/or modify it under the terms of the GNU Lesser General //// |
--//// Public License as published by the Free Software Foundation; //// |
--//// either version 2.1 of the License, or (at your option) any //// |
--//// later version. //// |
--//// //// |
--//// This source is distributed in the hope that it will be //// |
--//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
--//// PURPOSE. See the GNU Lesser General Public License for more //// |
--//// details. //// |
--//// //// |
--//// You should have received WIDTH_ADDRESS copy of the GNU Lesser General //// |
--//// Public License along with this source; if not, download it //// |
--//// from http://www.opencores.org/lgpl.shtml //// |
--//// //// |
--////////////////////////////////////////////////////////////////////// |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
use ieee.numeric_std.all; |
|
entity usimplez_ram is |
|
generic( WIDTH_WORD: natural:= 12; |
WIDTH_ADDRESS: natural:= 9 |
); |
|
port |
( |
clk_i : in std_logic; |
addr_i : in unsigned((WIDTH_ADDRESS-1) downto 0); |
data_i : in std_logic_vector((WIDTH_WORD-1) downto 0); |
we_i : in std_logic ; |
data_o : out std_logic_vector((WIDTH_WORD-1) downto 0) |
); |
|
end usimplez_ram; |
|
architecture rtl of usimplez_ram is |
|
subtype word_t is std_logic_vector((WIDTH_WORD-1) downto 0); |
type memory_t is array(2**WIDTH_ADDRESS-1 downto 0) of word_t; |
|
signal ram : memory_t; |
attribute ram_init_file : string; |
-- attribute ram_init_file of ram : signal is "sumador.mif"; --code sumador.txt |
attribute ram_init_file of ram : signal is "fibonacci.mif"; --code fibonacci.txt |
|
signal addr_reg_s : unsigned((WIDTH_ADDRESS-1) downto 0); |
|
begin |
|
process(clk_i) |
begin |
if(falling_edge(clk_i)) then |
if(we_i = '1') then |
ram(to_integer(addr_i)) <= data_i; |
end if; |
|
addr_reg_s <= addr_i; |
end if; |
end process; |
|
data_o <= ram(to_integer(addr_reg_s)); |
|
end rtl; |
/QuartusII/db/usimplez.map.hdb
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QuartusII/db/usimplez.map.hdb
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.cmp.hdb
===================================================================
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Index: QuartusII/db/usimplez.cmp.hdb
===================================================================
--- QuartusII/db/usimplez.cmp.hdb (nonexistent)
+++ QuartusII/db/usimplez.cmp.hdb (revision 2)
QuartusII/db/usimplez.cmp.hdb
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+application/octet-stream
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Index: QuartusII/db/usimplez.map_bb.hdb
===================================================================
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Index: QuartusII/db/usimplez.map_bb.hdb
===================================================================
--- QuartusII/db/usimplez.map_bb.hdb (nonexistent)
+++ QuartusII/db/usimplez.map_bb.hdb (revision 2)
QuartusII/db/usimplez.map_bb.hdb
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Index: QuartusII/db/usimplez.ace_cmp.cdb
===================================================================
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Index: QuartusII/db/usimplez.ace_cmp.cdb
===================================================================
--- QuartusII/db/usimplez.ace_cmp.cdb (nonexistent)
+++ QuartusII/db/usimplez.ace_cmp.cdb (revision 2)
QuartusII/db/usimplez.ace_cmp.cdb
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Index: QuartusII/db/usimplez.(2).cnf.cdb
===================================================================
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Index: QuartusII/db/usimplez.(2).cnf.cdb
===================================================================
--- QuartusII/db/usimplez.(2).cnf.cdb (nonexistent)
+++ QuartusII/db/usimplez.(2).cnf.cdb (revision 2)
QuartusII/db/usimplez.(2).cnf.cdb
Property changes :
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## -0,0 +1 ##
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Index: QuartusII/db/usimplez.ace_cmp.ecobp
===================================================================
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Index: QuartusII/db/usimplez.ace_cmp.ecobp
===================================================================
--- QuartusII/db/usimplez.ace_cmp.ecobp (nonexistent)
+++ QuartusII/db/usimplez.ace_cmp.ecobp (revision 2)
QuartusII/db/usimplez.ace_cmp.ecobp
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Index: QuartusII/db/usimplez.pre_map.hdb
===================================================================
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Index: QuartusII/db/usimplez.pre_map.hdb
===================================================================
--- QuartusII/db/usimplez.pre_map.hdb (nonexistent)
+++ QuartusII/db/usimplez.pre_map.hdb (revision 2)
QuartusII/db/usimplez.pre_map.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: QuartusII/db/usimplez.(0).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
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Index: QuartusII/db/usimplez.(0).cnf.hdb
===================================================================
--- QuartusII/db/usimplez.(0).cnf.hdb (nonexistent)
+++ QuartusII/db/usimplez.(0).cnf.hdb (revision 2)
QuartusII/db/usimplez.(0).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
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Index: QuartusII/db/prev_cmp_usimplez.fit.qmsg
===================================================================
--- QuartusII/db/prev_cmp_usimplez.fit.qmsg (nonexistent)
+++ QuartusII/db/prev_cmp_usimplez.fit.qmsg (revision 2)
@@ -0,0 +1,41 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 01:45:59 2011 " "Info: Processing started: Wed Nov 09 01:45:59 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "usimplez " "Warning: Ignored assignments for entity \"usimplez\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "usimplez EP2S15F484C3 " "Info: Automatically selected device EP2S15F484C3 for design usimplez" { } { } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." { } { } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 473 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 7 " "Critical Warning: No exact pin location assignment(s) for 7 pins of 7 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "we_o " "Info: Pin we_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { we_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 61 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { we_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 80 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "in0_o " "Info: Pin in0_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { in0_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 62 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { in0_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 81 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "in1_o " "Info: Pin in1_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { in1_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 63 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { in1_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 82 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "op0_o " "Info: Pin op0_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { op0_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 64 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { op0_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 83 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "op1_o " "Info: Pin op1_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { op1_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 65 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { op1_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 84 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_i " "Info: Pin clk_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 78 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst_i " "Info: Pin rst_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 60 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 79 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_i (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 78 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 3.3V 1 5 0 " "Info: Number of I/O pins in group: 6 (unused VREF, 3.3V VCCIO, 1 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 44 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 49 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 35 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 40 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 34 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use undetermined 0 6 " "Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Info: Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.247 ns register register " "Info: Estimated most critical path is register to register delay of 5.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usimplez_cpu:cpu\|estado.In0 1 REG LAB_X19_Y12 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y12; Fanout = 5; REG Node = 'usimplez_cpu:cpu\|estado.In0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { usimplez_cpu:cpu|estado.In0 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.729 ns) + CELL(0.378 ns) 2.107 ns usimplez_cpu:cpu\|co_reg_s\[2\]~1 2 COMB LAB_X6_Y2 12 " "Info: 2: + IC(1.729 ns) + CELL(0.378 ns) = 2.107 ns; Loc. = LAB_X6_Y2; Fanout = 12; COMB Node = 'usimplez_cpu:cpu\|co_reg_s\[2\]~1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { usimplez_cpu:cpu|estado.In0 usimplez_cpu:cpu|co_reg_s[2]~1 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.394 ns) + CELL(0.746 ns) 5.247 ns usimplez_cpu:cpu\|cd_reg_s\[5\] 3 REG LAB_X21_Y15 2 " "Info: 3: + IC(2.394 ns) + CELL(0.746 ns) = 5.247 ns; Loc. = LAB_X21_Y15; Fanout = 2; REG Node = 'usimplez_cpu:cpu\|cd_reg_s\[5\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.140 ns" { usimplez_cpu:cpu|co_reg_s[2]~1 usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.124 ns ( 21.42 % ) " "Info: Total cell delay = 1.124 ns ( 21.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.123 ns ( 78.58 % ) " "Info: Total interconnect delay = 4.123 ns ( 78.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { usimplez_cpu:cpu|estado.In0 usimplez_cpu:cpu|co_reg_s[2]~1 usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X13_Y0 X26_Y13 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "we_o 0 " "Info: Pin \"we_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in0_o 0 " "Info: Pin \"in0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in1_o 0 " "Info: Pin \"in1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op0_o 0 " "Info: Pin \"op0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op1_o 0 " "Info: Pin \"op1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 01:46:26 2011 " "Info: Processing ended: Wed Nov 09 01:46:26 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Info: Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: QuartusII/db/usimplez.sim.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.sim.hdb
===================================================================
--- QuartusII/db/usimplez.sim.hdb (nonexistent)
+++ QuartusII/db/usimplez.sim.hdb (revision 2)
QuartusII/db/usimplez.sim.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.(4).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.(4).cnf.hdb
===================================================================
--- QuartusII/db/usimplez.(4).cnf.hdb (nonexistent)
+++ QuartusII/db/usimplez.(4).cnf.hdb (revision 2)
QuartusII/db/usimplez.(4).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.cmp.rdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.cmp.rdb
===================================================================
--- QuartusII/db/usimplez.cmp.rdb (nonexistent)
+++ QuartusII/db/usimplez.cmp.rdb (revision 2)
QuartusII/db/usimplez.cmp.rdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.cmp0.ddb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.cmp0.ddb
===================================================================
--- QuartusII/db/usimplez.cmp0.ddb (nonexistent)
+++ QuartusII/db/usimplez.cmp0.ddb (revision 2)
QuartusII/db/usimplez.cmp0.ddb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.cmp.tdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.cmp.tdb
===================================================================
--- QuartusII/db/usimplez.cmp.tdb (nonexistent)
+++ QuartusII/db/usimplez.cmp.tdb (revision 2)
QuartusII/db/usimplez.cmp.tdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.tis_db_list.ddb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.tis_db_list.ddb
===================================================================
--- QuartusII/db/usimplez.tis_db_list.ddb (nonexistent)
+++ QuartusII/db/usimplez.tis_db_list.ddb (revision 2)
QuartusII/db/usimplez.tis_db_list.ddb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.sgdiff.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.sgdiff.cdb
===================================================================
--- QuartusII/db/usimplez.sgdiff.cdb (nonexistent)
+++ QuartusII/db/usimplez.sgdiff.cdb (revision 2)
QuartusII/db/usimplez.sgdiff.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.map.bpm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.map.bpm
===================================================================
--- QuartusII/db/usimplez.map.bpm (nonexistent)
+++ QuartusII/db/usimplez.map.bpm (revision 2)
QuartusII/db/usimplez.map.bpm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.cmp.bpm
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.cmp.bpm
===================================================================
--- QuartusII/db/usimplez.cmp.bpm (nonexistent)
+++ QuartusII/db/usimplez.cmp.bpm (revision 2)
QuartusII/db/usimplez.cmp.bpm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.sim.rdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.sim.rdb
===================================================================
--- QuartusII/db/usimplez.sim.rdb (nonexistent)
+++ QuartusII/db/usimplez.sim.rdb (revision 2)
QuartusII/db/usimplez.sim.rdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.rtlv_sg_swap.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.rtlv_sg_swap.cdb
===================================================================
--- QuartusII/db/usimplez.rtlv_sg_swap.cdb (nonexistent)
+++ QuartusII/db/usimplez.rtlv_sg_swap.cdb (revision 2)
QuartusII/db/usimplez.rtlv_sg_swap.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/prev_cmp_usimplez.qmsg
===================================================================
--- QuartusII/db/prev_cmp_usimplez.qmsg (nonexistent)
+++ QuartusII/db/prev_cmp_usimplez.qmsg (revision 2)
@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 01:52:15 2011 " "Info: Processing started: Wed Nov 09 01:52:15 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off usimplez -c usimplez " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off usimplez -c usimplez" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "C:/Altera/qdesigns/usimplez/usimplez_top.vwf " "Info: Using vector source file \"C:/Altera/qdesigns/usimplez/usimplez_top.vwf\"" { } { } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." { } { } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0 -1} } { } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0 -1}
+{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" { } { } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0 -1}
+{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" " 89.76 % " "Info: Simulation coverage is 89.76 %" { } { } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "113895 " "Info: Number of transitions in simulation is 113895" { } { } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "121 " "Info: Peak virtual memory: 121 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 01:52:27 2011 " "Info: Processing ended: Wed Nov 09 01:52:27 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Info: Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: QuartusII/db/usimplez.smp_dump.txt
===================================================================
--- QuartusII/db/usimplez.smp_dump.txt (nonexistent)
+++ QuartusII/db/usimplez.smp_dump.txt (revision 2)
@@ -0,0 +1,7 @@
+
+State Machine - |usimplez_top|usimplez_cpu:cpu|estado
+Name estado.Op1 estado.Op0 estado.In1 estado.In0
+estado.In0 0 0 0 0
+estado.In1 0 0 1 1
+estado.Op0 0 1 0 1
+estado.Op1 1 0 0 1
Index: QuartusII/db/usimplez.hif
===================================================================
--- QuartusII/db/usimplez.hif (nonexistent)
+++ QuartusII/db/usimplez.hif (revision 2)
@@ -0,0 +1,690 @@
+Quartus II
+Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+7
+3700
+OFF
+OFF
+OFF
+ON
+ON
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+0
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+usimplez_top
+# storage
+db|usimplez.(0).cnf
+db|usimplez.(0).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+usimplez_top.vhd
+5a555d771d56de2c2c3f5581e572730
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+WIDTH_WORD
+12
+PARAMETER_SIGNED_DEC
+DEF
+WIDTH_ADDRESS
+9
+PARAMETER_SIGNED_DEC
+DEF
+}
+# hierarchies {
+|
+}
+# lmf
+|altera|quartus|lmf|maxplus2.lmf
+a36c8ec425c8a2589af98b2d4daabc3
+# macro_sequence
+
+# end
+# entity
+usimplez_cpu
+# storage
+db|usimplez.(1).cnf
+db|usimplez.(1).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+usimplez_cpu.vhd
+ccdcfc8f4418514cbcf83153114a85b
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+width_data_bus
+12
+PARAMETER_SIGNED_DEC
+USR
+width_operation_code
+3
+PARAMETER_SIGNED_DEC
+USR
+width_address
+9
+PARAMETER_SIGNED_DEC
+USR
+st
+000
+PARAMETER_UNSIGNED_BIN
+USR
+ld
+001
+PARAMETER_UNSIGNED_BIN
+USR
+add
+010
+PARAMETER_UNSIGNED_BIN
+USR
+br
+011
+PARAMETER_UNSIGNED_BIN
+USR
+bz
+100
+PARAMETER_UNSIGNED_BIN
+USR
+clr
+101
+PARAMETER_UNSIGNED_BIN
+USR
+dec
+110
+PARAMETER_UNSIGNED_BIN
+USR
+halt
+111
+PARAMETER_UNSIGNED_BIN
+USR
+ constraint(st)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(ld)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(add)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(br)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(bz)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(clr)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(dec)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(halt)
+2 downto 0
+PARAMETER_STRING
+USR
+ constraint(data_bus_i)
+11 downto 0
+PARAMETER_STRING
+USR
+ constraint(data_bus_o)
+11 downto 0
+PARAMETER_STRING
+USR
+ constraint(addr_bus_o)
+8 downto 0
+PARAMETER_STRING
+USR
+}
+# hierarchies {
+usimplez_cpu:cpu
+}
+# lmf
+|altera|quartus|lmf|maxplus2.lmf
+a36c8ec425c8a2589af98b2d4daabc3
+# macro_sequence
+
+# end
+# entity
+usimplez_ram
+# storage
+db|usimplez.(2).cnf
+db|usimplez.(2).cnf
+# logic_option {
+AUTO_RAM_RECOGNITION
+ON
+}
+# case_insensitive
+# source_file
+usimplez_ram.vhd
+50dc15cc97ba085c3fbb8b9a7d151
+5
+# internal_option {
+HDL_INITIAL_FANOUT_LIMIT
+OFF
+AUTO_RESOURCE_SHARING
+OFF
+AUTO_RAM_RECOGNITION
+ON
+AUTO_ROM_RECOGNITION
+ON
+}
+# user_parameter {
+width_word
+12
+PARAMETER_SIGNED_DEC
+USR
+width_address
+9
+PARAMETER_SIGNED_DEC
+USR
+ constraint(addr_i)
+8 downto 0
+PARAMETER_STRING
+USR
+ constraint(data_i)
+11 downto 0
+PARAMETER_STRING
+USR
+ constraint(data_o)
+11 downto 0
+PARAMETER_STRING
+USR
+}
+# hierarchies {
+usimplez_ram:ram
+}
+# lmf
+|altera|quartus|lmf|maxplus2.lmf
+a36c8ec425c8a2589af98b2d4daabc3
+# macro_sequence
+
+# end
+# entity
+altsyncram
+# storage
+db|usimplez.(3).cnf
+db|usimplez.(3).cnf
+# case_insensitive
+# source_file
+|altera|quartus|libraries|megafunctions|altsyncram.tdf
+67d9a3902c8a461c1d5750189e124f2
+7
+# user_parameter {
+BYTE_SIZE_BLOCK
+8
+PARAMETER_UNKNOWN
+DEF
+AUTO_CARRY_CHAINS
+ON
+AUTO_CARRY
+USR
+IGNORE_CARRY_BUFFERS
+OFF
+IGNORE_CARRY
+USR
+AUTO_CASCADE_CHAINS
+ON
+AUTO_CASCADE
+USR
+IGNORE_CASCADE_BUFFERS
+OFF
+IGNORE_CASCADE
+USR
+WIDTH_BYTEENA
+1
+PARAMETER_UNKNOWN
+DEF
+OPERATION_MODE
+SINGLE_PORT
+PARAMETER_UNKNOWN
+USR
+WIDTH_A
+12
+PARAMETER_UNKNOWN
+USR
+WIDTHAD_A
+9
+PARAMETER_UNKNOWN
+USR
+NUMWORDS_A
+512
+PARAMETER_UNKNOWN
+USR
+OUTDATA_REG_A
+UNREGISTERED
+PARAMETER_UNKNOWN
+USR
+ADDRESS_ACLR_A
+NONE
+PARAMETER_UNKNOWN
+USR
+OUTDATA_ACLR_A
+NONE
+PARAMETER_UNKNOWN
+USR
+WRCONTROL_ACLR_A
+NONE
+PARAMETER_UNKNOWN
+USR
+INDATA_ACLR_A
+NONE
+PARAMETER_UNKNOWN
+USR
+BYTEENA_ACLR_A
+NONE
+PARAMETER_UNKNOWN
+DEF
+WIDTH_B
+1
+PARAMETER_UNKNOWN
+DEF
+WIDTHAD_B
+1
+PARAMETER_UNKNOWN
+DEF
+NUMWORDS_B
+1
+PARAMETER_UNKNOWN
+DEF
+INDATA_REG_B
+CLOCK1
+PARAMETER_UNKNOWN
+DEF
+WRCONTROL_WRADDRESS_REG_B
+CLOCK1
+PARAMETER_UNKNOWN
+DEF
+RDCONTROL_REG_B
+CLOCK1
+PARAMETER_UNKNOWN
+DEF
+ADDRESS_REG_B
+CLOCK1
+PARAMETER_UNKNOWN
+DEF
+OUTDATA_REG_B
+UNREGISTERED
+PARAMETER_UNKNOWN
+DEF
+BYTEENA_REG_B
+CLOCK1
+PARAMETER_UNKNOWN
+DEF
+INDATA_ACLR_B
+NONE
+PARAMETER_UNKNOWN
+DEF
+WRCONTROL_ACLR_B
+NONE
+PARAMETER_UNKNOWN
+DEF
+ADDRESS_ACLR_B
+NONE
+PARAMETER_UNKNOWN
+DEF
+OUTDATA_ACLR_B
+NONE
+PARAMETER_UNKNOWN
+DEF
+RDCONTROL_ACLR_B
+NONE
+PARAMETER_UNKNOWN
+DEF
+BYTEENA_ACLR_B
+NONE
+PARAMETER_UNKNOWN
+DEF
+WIDTH_BYTEENA_A
+1
+PARAMETER_UNKNOWN
+DEF
+WIDTH_BYTEENA_B
+1
+PARAMETER_UNKNOWN
+DEF
+RAM_BLOCK_TYPE
+AUTO
+PARAMETER_UNKNOWN
+DEF
+BYTE_SIZE
+8
+PARAMETER_UNKNOWN
+DEF
+READ_DURING_WRITE_MODE_MIXED_PORTS
+DONT_CARE
+PARAMETER_UNKNOWN
+DEF
+READ_DURING_WRITE_MODE_PORT_A
+NEW_DATA_NO_NBE_READ
+PARAMETER_UNKNOWN
+DEF
+READ_DURING_WRITE_MODE_PORT_B
+NEW_DATA_NO_NBE_READ
+PARAMETER_UNKNOWN
+DEF
+INIT_FILE
+fibonacci.mif
+PARAMETER_UNKNOWN
+USR
+INIT_FILE_LAYOUT
+PORT_A
+PARAMETER_UNKNOWN
+DEF
+MAXIMUM_DEPTH
+0
+PARAMETER_UNKNOWN
+DEF
+CLOCK_ENABLE_INPUT_A
+NORMAL
+PARAMETER_UNKNOWN
+DEF
+CLOCK_ENABLE_INPUT_B
+NORMAL
+PARAMETER_UNKNOWN
+DEF
+CLOCK_ENABLE_OUTPUT_A
+NORMAL
+PARAMETER_UNKNOWN
+DEF
+CLOCK_ENABLE_OUTPUT_B
+NORMAL
+PARAMETER_UNKNOWN
+DEF
+CLOCK_ENABLE_CORE_A
+USE_INPUT_CLKEN
+PARAMETER_UNKNOWN
+DEF
+CLOCK_ENABLE_CORE_B
+USE_INPUT_CLKEN
+PARAMETER_UNKNOWN
+DEF
+ENABLE_ECC
+FALSE
+PARAMETER_UNKNOWN
+DEF
+DEVICE_FAMILY
+Stratix II
+PARAMETER_UNKNOWN
+USR
+CBXI_PARAMETER
+altsyncram_im61
+PARAMETER_UNKNOWN
+USR
+}
+# used_port {
+wren_a
+-1
+3
+q_a9
+-1
+3
+q_a8
+-1
+3
+q_a7
+-1
+3
+q_a6
+-1
+3
+q_a5
+-1
+3
+q_a4
+-1
+3
+q_a3
+-1
+3
+q_a2
+-1
+3
+q_a11
+-1
+3
+q_a10
+-1
+3
+q_a1
+-1
+3
+q_a0
+-1
+3
+data_a9
+-1
+3
+data_a8
+-1
+3
+data_a7
+-1
+3
+data_a6
+-1
+3
+data_a5
+-1
+3
+data_a4
+-1
+3
+data_a3
+-1
+3
+data_a2
+-1
+3
+data_a11
+-1
+3
+data_a10
+-1
+3
+data_a1
+-1
+3
+data_a0
+-1
+3
+clock0
+-1
+3
+address_a8
+-1
+3
+address_a7
+-1
+3
+address_a6
+-1
+3
+address_a5
+-1
+3
+address_a4
+-1
+3
+address_a3
+-1
+3
+address_a2
+-1
+3
+address_a1
+-1
+3
+address_a0
+-1
+3
+}
+# macro_sequence
+
+# end
+# entity
+altsyncram_im61
+# storage
+db|usimplez.(4).cnf
+db|usimplez.(4).cnf
+# case_insensitive
+# source_file
+db|altsyncram_im61.tdf
+15b372adebb3e965fe4fdfacc8eb62b0
+7
+# used_port {
+wren_a
+-1
+3
+q_a9
+-1
+3
+q_a8
+-1
+3
+q_a7
+-1
+3
+q_a6
+-1
+3
+q_a5
+-1
+3
+q_a4
+-1
+3
+q_a3
+-1
+3
+q_a2
+-1
+3
+q_a11
+-1
+3
+q_a10
+-1
+3
+q_a1
+-1
+3
+q_a0
+-1
+3
+data_a9
+-1
+3
+data_a8
+-1
+3
+data_a7
+-1
+3
+data_a6
+-1
+3
+data_a5
+-1
+3
+data_a4
+-1
+3
+data_a3
+-1
+3
+data_a2
+-1
+3
+data_a11
+-1
+3
+data_a10
+-1
+3
+data_a1
+-1
+3
+data_a0
+-1
+3
+clock0
+-1
+3
+address_a8
+-1
+3
+address_a7
+-1
+3
+address_a6
+-1
+3
+address_a5
+-1
+3
+address_a4
+-1
+3
+address_a3
+-1
+3
+address_a2
+-1
+3
+address_a1
+-1
+3
+address_a0
+-1
+3
+}
+# memory_file {
+fibonacci.mif
+44e8ed8bcde6c33480b853c940c61d96
+}
+# macro_sequence
+
+# end
+# complete
+
Index: QuartusII/db/prev_cmp_usimplez.map.qmsg
===================================================================
--- QuartusII/db/prev_cmp_usimplez.map.qmsg (nonexistent)
+++ QuartusII/db/prev_cmp_usimplez.map.qmsg (revision 2)
@@ -0,0 +1,16 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 01:44:42 2011 " "Info: Processing started: Wed Nov 09 01:44:42 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_top-str " "Info: Found design unit 1: usimplez_top-str" { } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 69 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_top " "Info: Found entity 1: usimplez_top" { } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 53 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_cpu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_cpu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_cpu-fsm " "Info: Found design unit 1: usimplez_cpu-fsm" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 86 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_cpu " "Info: Found entity 1: usimplez_cpu" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 52 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_ram-rtl " "Info: Found design unit 1: usimplez_ram-rtl" { } { { "usimplez_ram.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_ram.vhd" 70 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_ram " "Info: Found entity 1: usimplez_ram" { } { { "usimplez_ram.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_ram.vhd" 53 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "usimplez_top " "Info: Elaborating entity \"usimplez_top\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "usimplez_cpu usimplez_cpu:cpu " "Info: Elaborating entity \"usimplez_cpu\" for hierarchy \"usimplez_cpu:cpu\"" { } { { "usimplez_top.vhd" "cpu" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 123 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "usimplez_ram usimplez_ram:ram " "Info: Elaborating entity \"usimplez_ram\" for hierarchy \"usimplez_ram:ram\"" { } { { "usimplez_top.vhd" "ram" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 150 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "usimplez_ram:ram\|ram~22 " "Info: Inferred altsyncram megafunction from the following design logic: \"usimplez_ram:ram\|ram~22\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Info: Parameter OPERATION_MODE set to SINGLE_PORT" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 12 " "Info: Parameter WIDTH_A set to 12" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 9 " "Info: Parameter WIDTHAD_A set to 9" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 512 " "Info: Parameter NUMWORDS_A set to 512" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE fibonacci.mif " "Info: Parameter INIT_FILE set to fibonacci.mif" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} } { { "usimplez_ram.vhd" "ram~22" { Text "C:/Altera/qdesigns/usimplez/usimplez_ram.vhd" 75 -1 0 } } } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 -1} } { } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "usimplez_ram:ram\|altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"usimplez_ram:ram\|altsyncram:ram_rtl_0\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "usimplez_ram:ram\|altsyncram:ram_rtl_0 " "Info: Instantiated megafunction \"usimplez_ram:ram\|altsyncram:ram_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE SINGLE_PORT " "Info: Parameter \"OPERATION_MODE\" = \"SINGLE_PORT\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 12 " "Info: Parameter \"WIDTH_A\" = \"12\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 9 " "Info: Parameter \"WIDTHAD_A\" = \"9\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 512 " "Info: Parameter \"NUMWORDS_A\" = \"512\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Info: Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE fibonacci.mif " "Info: Parameter \"INIT_FILE\" = \"fibonacci.mif\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_im61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_im61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_im61 " "Info: Found entity 1: altsyncram_im61" { } { { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf" 27 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "usimplez " "Warning: Ignored assignments for entity \"usimplez\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "94 " "Info: Implemented 94 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Info: Implemented 75 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" { } { } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "195 " "Info: Peak virtual memory: 195 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 01:44:56 2011 " "Info: Processing ended: Wed Nov 09 01:44:56 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: QuartusII/db/usimplez.(3).cnf.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.(3).cnf.cdb
===================================================================
--- QuartusII/db/usimplez.(3).cnf.cdb (nonexistent)
+++ QuartusII/db/usimplez.(3).cnf.cdb (revision 2)
QuartusII/db/usimplez.(3).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.(1).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.(1).cnf.hdb
===================================================================
--- QuartusII/db/usimplez.(1).cnf.hdb (nonexistent)
+++ QuartusII/db/usimplez.(1).cnf.hdb (revision 2)
QuartusII/db/usimplez.(1).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.lpc.rdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.lpc.rdb
===================================================================
--- QuartusII/db/usimplez.lpc.rdb (nonexistent)
+++ QuartusII/db/usimplez.lpc.rdb (revision 2)
QuartusII/db/usimplez.lpc.rdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.syn_hier_info
===================================================================
Index: QuartusII/db/usimplez.cmp_merge.kpt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.cmp_merge.kpt
===================================================================
--- QuartusII/db/usimplez.cmp_merge.kpt (nonexistent)
+++ QuartusII/db/usimplez.cmp_merge.kpt (revision 2)
QuartusII/db/usimplez.cmp_merge.kpt
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.hier_info
===================================================================
--- QuartusII/db/usimplez.hier_info (nonexistent)
+++ QuartusII/db/usimplez.hier_info (revision 2)
@@ -0,0 +1,299 @@
+|usimplez_top
+clk_i => usimplez_cpu:cpu.clk_i
+clk_i => usimplez_ram:ram.clk_i
+rst_i => usimplez_cpu:cpu.rst_i
+we_o <= usimplez_cpu:cpu.we_o
+in0_o <= usimplez_cpu:cpu.in0_o
+in1_o <= usimplez_cpu:cpu.in1_o
+op0_o <= usimplez_cpu:cpu.op0_o
+op1_o <= usimplez_cpu:cpu.op1_o
+
+
+|usimplez_top|usimplez_cpu:cpu
+clk_i => Op1_o~reg0.CLK
+clk_i => Op0_o~reg0.CLK
+clk_i => In1_o~reg0.CLK
+clk_i => In0_o~reg0.CLK
+clk_i => we_o~reg0.CLK
+clk_i => data_bus_o[0]~reg0.CLK
+clk_i => data_bus_o[1]~reg0.CLK
+clk_i => data_bus_o[2]~reg0.CLK
+clk_i => data_bus_o[3]~reg0.CLK
+clk_i => data_bus_o[4]~reg0.CLK
+clk_i => data_bus_o[5]~reg0.CLK
+clk_i => data_bus_o[6]~reg0.CLK
+clk_i => data_bus_o[7]~reg0.CLK
+clk_i => data_bus_o[8]~reg0.CLK
+clk_i => data_bus_o[9]~reg0.CLK
+clk_i => data_bus_o[10]~reg0.CLK
+clk_i => data_bus_o[11]~reg0.CLK
+clk_i => addr_bus_o[0]~reg0.CLK
+clk_i => addr_bus_o[1]~reg0.CLK
+clk_i => addr_bus_o[2]~reg0.CLK
+clk_i => addr_bus_o[3]~reg0.CLK
+clk_i => addr_bus_o[4]~reg0.CLK
+clk_i => addr_bus_o[5]~reg0.CLK
+clk_i => addr_bus_o[6]~reg0.CLK
+clk_i => addr_bus_o[7]~reg0.CLK
+clk_i => addr_bus_o[8]~reg0.CLK
+clk_i => cp_reg_s[0].CLK
+clk_i => cp_reg_s[1].CLK
+clk_i => cp_reg_s[2].CLK
+clk_i => cp_reg_s[3].CLK
+clk_i => cp_reg_s[4].CLK
+clk_i => cp_reg_s[5].CLK
+clk_i => cp_reg_s[6].CLK
+clk_i => cp_reg_s[7].CLK
+clk_i => cp_reg_s[8].CLK
+clk_i => cd_reg_s[0].CLK
+clk_i => cd_reg_s[1].CLK
+clk_i => cd_reg_s[2].CLK
+clk_i => cd_reg_s[3].CLK
+clk_i => cd_reg_s[4].CLK
+clk_i => cd_reg_s[5].CLK
+clk_i => cd_reg_s[6].CLK
+clk_i => cd_reg_s[7].CLK
+clk_i => cd_reg_s[8].CLK
+clk_i => acumulador[0].CLK
+clk_i => acumulador[1].CLK
+clk_i => acumulador[2].CLK
+clk_i => acumulador[3].CLK
+clk_i => acumulador[4].CLK
+clk_i => acumulador[5].CLK
+clk_i => acumulador[6].CLK
+clk_i => acumulador[7].CLK
+clk_i => acumulador[8].CLK
+clk_i => acumulador[9].CLK
+clk_i => acumulador[10].CLK
+clk_i => acumulador[11].CLK
+clk_i => co_reg_s[0].CLK
+clk_i => co_reg_s[1].CLK
+clk_i => co_reg_s[2].CLK
+clk_i => estado~1.DATAIN
+rst_i => co_reg_s.OUTPUTSELECT
+rst_i => co_reg_s.OUTPUTSELECT
+rst_i => co_reg_s.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => acumulador.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cd_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => cp_reg_s.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => addr_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => data_bus_o.OUTPUTSELECT
+rst_i => we_o.OUTPUTSELECT
+rst_i => estado.OUTPUTSELECT
+rst_i => estado.OUTPUTSELECT
+rst_i => estado.OUTPUTSELECT
+rst_i => estado.OUTPUTSELECT
+rst_i => In0_o~reg0.ENA
+rst_i => In1_o~reg0.ENA
+rst_i => Op0_o~reg0.ENA
+rst_i => Op1_o~reg0.ENA
+data_bus_i[0] => Add2.IN12
+data_bus_i[0] => Mux43.IN1
+data_bus_i[0] => cd_reg_s.DATAB
+data_bus_i[1] => Add2.IN11
+data_bus_i[1] => Mux42.IN1
+data_bus_i[1] => cd_reg_s.DATAB
+data_bus_i[2] => Add2.IN10
+data_bus_i[2] => Mux41.IN1
+data_bus_i[2] => cd_reg_s.DATAB
+data_bus_i[3] => Add2.IN9
+data_bus_i[3] => Mux40.IN1
+data_bus_i[3] => cd_reg_s.DATAB
+data_bus_i[4] => Add2.IN8
+data_bus_i[4] => Mux39.IN1
+data_bus_i[4] => cd_reg_s.DATAB
+data_bus_i[5] => Add2.IN7
+data_bus_i[5] => Mux38.IN1
+data_bus_i[5] => cd_reg_s.DATAB
+data_bus_i[6] => Add2.IN6
+data_bus_i[6] => Mux37.IN1
+data_bus_i[6] => cd_reg_s.DATAB
+data_bus_i[7] => Add2.IN5
+data_bus_i[7] => Mux36.IN1
+data_bus_i[7] => cd_reg_s.DATAB
+data_bus_i[8] => Add2.IN4
+data_bus_i[8] => Mux35.IN1
+data_bus_i[8] => cd_reg_s.DATAB
+data_bus_i[9] => Add2.IN3
+data_bus_i[9] => Mux34.IN1
+data_bus_i[9] => co_reg_s.DATAB
+data_bus_i[10] => Add2.IN2
+data_bus_i[10] => Mux33.IN1
+data_bus_i[10] => co_reg_s.DATAB
+data_bus_i[11] => Add2.IN1
+data_bus_i[11] => Mux32.IN1
+data_bus_i[11] => co_reg_s.DATAB
+data_bus_o[0] <= data_bus_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[1] <= data_bus_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[2] <= data_bus_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[3] <= data_bus_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[4] <= data_bus_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[5] <= data_bus_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[6] <= data_bus_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[7] <= data_bus_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[8] <= data_bus_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[9] <= data_bus_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[10] <= data_bus_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+data_bus_o[11] <= data_bus_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[0] <= addr_bus_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[1] <= addr_bus_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[2] <= addr_bus_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[3] <= addr_bus_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[4] <= addr_bus_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[5] <= addr_bus_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[6] <= addr_bus_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[7] <= addr_bus_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+addr_bus_o[8] <= addr_bus_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
+we_o <= we_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
+In0_o <= In0_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
+In1_o <= In1_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
+Op0_o <= Op0_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
+Op1_o <= Op1_o~reg0.DB_MAX_OUTPUT_PORT_TYPE
+
+
+|usimplez_top|usimplez_ram:ram
+clk_i => ram~21.CLK
+clk_i => ram~0.CLK
+clk_i => ram~1.CLK
+clk_i => ram~2.CLK
+clk_i => ram~3.CLK
+clk_i => ram~4.CLK
+clk_i => ram~5.CLK
+clk_i => ram~6.CLK
+clk_i => ram~7.CLK
+clk_i => ram~8.CLK
+clk_i => ram~9.CLK
+clk_i => ram~10.CLK
+clk_i => ram~11.CLK
+clk_i => ram~12.CLK
+clk_i => ram~13.CLK
+clk_i => ram~14.CLK
+clk_i => ram~15.CLK
+clk_i => ram~16.CLK
+clk_i => ram~17.CLK
+clk_i => ram~18.CLK
+clk_i => ram~19.CLK
+clk_i => ram~20.CLK
+clk_i => addr_reg_s[0].CLK
+clk_i => addr_reg_s[1].CLK
+clk_i => addr_reg_s[2].CLK
+clk_i => addr_reg_s[3].CLK
+clk_i => addr_reg_s[4].CLK
+clk_i => addr_reg_s[5].CLK
+clk_i => addr_reg_s[6].CLK
+clk_i => addr_reg_s[7].CLK
+clk_i => addr_reg_s[8].CLK
+clk_i => ram.CLK0
+addr_i[0] => ram~8.DATAIN
+addr_i[0] => addr_reg_s[0].DATAIN
+addr_i[0] => ram.WADDR
+addr_i[1] => ram~7.DATAIN
+addr_i[1] => addr_reg_s[1].DATAIN
+addr_i[1] => ram.WADDR1
+addr_i[2] => ram~6.DATAIN
+addr_i[2] => addr_reg_s[2].DATAIN
+addr_i[2] => ram.WADDR2
+addr_i[3] => ram~5.DATAIN
+addr_i[3] => addr_reg_s[3].DATAIN
+addr_i[3] => ram.WADDR3
+addr_i[4] => ram~4.DATAIN
+addr_i[4] => addr_reg_s[4].DATAIN
+addr_i[4] => ram.WADDR4
+addr_i[5] => ram~3.DATAIN
+addr_i[5] => addr_reg_s[5].DATAIN
+addr_i[5] => ram.WADDR5
+addr_i[6] => ram~2.DATAIN
+addr_i[6] => addr_reg_s[6].DATAIN
+addr_i[6] => ram.WADDR6
+addr_i[7] => ram~1.DATAIN
+addr_i[7] => addr_reg_s[7].DATAIN
+addr_i[7] => ram.WADDR7
+addr_i[8] => ram~0.DATAIN
+addr_i[8] => addr_reg_s[8].DATAIN
+addr_i[8] => ram.WADDR8
+data_i[0] => ram~20.DATAIN
+data_i[0] => ram.DATAIN
+data_i[1] => ram~19.DATAIN
+data_i[1] => ram.DATAIN1
+data_i[2] => ram~18.DATAIN
+data_i[2] => ram.DATAIN2
+data_i[3] => ram~17.DATAIN
+data_i[3] => ram.DATAIN3
+data_i[4] => ram~16.DATAIN
+data_i[4] => ram.DATAIN4
+data_i[5] => ram~15.DATAIN
+data_i[5] => ram.DATAIN5
+data_i[6] => ram~14.DATAIN
+data_i[6] => ram.DATAIN6
+data_i[7] => ram~13.DATAIN
+data_i[7] => ram.DATAIN7
+data_i[8] => ram~12.DATAIN
+data_i[8] => ram.DATAIN8
+data_i[9] => ram~11.DATAIN
+data_i[9] => ram.DATAIN9
+data_i[10] => ram~10.DATAIN
+data_i[10] => ram.DATAIN10
+data_i[11] => ram~9.DATAIN
+data_i[11] => ram.DATAIN11
+we_i => ram~21.DATAIN
+we_i => ram.WE
+data_o[0] <= ram.DATAOUT
+data_o[1] <= ram.DATAOUT1
+data_o[2] <= ram.DATAOUT2
+data_o[3] <= ram.DATAOUT3
+data_o[4] <= ram.DATAOUT4
+data_o[5] <= ram.DATAOUT5
+data_o[6] <= ram.DATAOUT6
+data_o[7] <= ram.DATAOUT7
+data_o[8] <= ram.DATAOUT8
+data_o[9] <= ram.DATAOUT9
+data_o[10] <= ram.DATAOUT10
+data_o[11] <= ram.DATAOUT11
+
+
Index: QuartusII/db/usimplez.map.cdb
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.map.cdb
===================================================================
--- QuartusII/db/usimplez.map.cdb (nonexistent)
+++ QuartusII/db/usimplez.map.cdb (revision 2)
QuartusII/db/usimplez.map.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.map.ecobp
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.map.ecobp
===================================================================
--- QuartusII/db/usimplez.map.ecobp (nonexistent)
+++ QuartusII/db/usimplez.map.ecobp (revision 2)
QuartusII/db/usimplez.map.ecobp
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.cmp.ecobp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.cmp.ecobp
===================================================================
--- QuartusII/db/usimplez.cmp.ecobp (nonexistent)
+++ QuartusII/db/usimplez.cmp.ecobp (revision 2)
QuartusII/db/usimplez.cmp.ecobp
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.map_bb.logdb
===================================================================
--- QuartusII/db/usimplez.map_bb.logdb (nonexistent)
+++ QuartusII/db/usimplez.map_bb.logdb (revision 2)
@@ -0,0 +1 @@
+v1
Index: QuartusII/db/usimplez.cmp.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.cmp.cdb
===================================================================
--- QuartusII/db/usimplez.cmp.cdb (nonexistent)
+++ QuartusII/db/usimplez.cmp.cdb (revision 2)
QuartusII/db/usimplez.cmp.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.map_bb.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.map_bb.cdb
===================================================================
--- QuartusII/db/usimplez.map_bb.cdb (nonexistent)
+++ QuartusII/db/usimplez.map_bb.cdb (revision 2)
QuartusII/db/usimplez.map_bb.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.pre_map.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.pre_map.cdb
===================================================================
--- QuartusII/db/usimplez.pre_map.cdb (nonexistent)
+++ QuartusII/db/usimplez.pre_map.cdb (revision 2)
QuartusII/db/usimplez.pre_map.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.(0).cnf.cdb
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.(0).cnf.cdb
===================================================================
--- QuartusII/db/usimplez.(0).cnf.cdb (nonexistent)
+++ QuartusII/db/usimplez.(0).cnf.cdb (revision 2)
QuartusII/db/usimplez.(0).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.(4).cnf.cdb
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.(4).cnf.cdb
===================================================================
--- QuartusII/db/usimplez.(4).cnf.cdb (nonexistent)
+++ QuartusII/db/usimplez.(4).cnf.cdb (revision 2)
QuartusII/db/usimplez.(4).cnf.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.lpc.html
===================================================================
--- QuartusII/db/usimplez.lpc.html (nonexistent)
+++ QuartusII/db/usimplez.lpc.html (revision 2)
@@ -0,0 +1,50 @@
+
+
Index: QuartusII/db/usimplez.tmw_info
===================================================================
--- QuartusII/db/usimplez.tmw_info (nonexistent)
+++ QuartusII/db/usimplez.tmw_info (revision 2)
@@ -0,0 +1 @@
+start_timing_analyzer:s:00:00:11
Index: QuartusII/db/usimplez.ace_cmp.hdb
===================================================================
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Index: QuartusII/db/usimplez.ace_cmp.hdb
===================================================================
--- QuartusII/db/usimplez.ace_cmp.hdb (nonexistent)
+++ QuartusII/db/usimplez.ace_cmp.hdb (revision 2)
| Hierarchy | +Input | +Constant Input | +Unused Input | +Floating Input | +Output | +Constant Output | +Unused Output | +Floating Output | +Bidir | +Constant Bidir | +Unused Bidir | +Input only Bidir | +Output only Bidir | +
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ram | +23 | +0 | +0 | +0 | +12 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +
| cpu | +14 | +0 | +0 | +0 | +26 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +0 | +
QuartusII/db/usimplez.ace_cmp.hdb
Property changes :
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## -0,0 +1 ##
+application/octet-stream
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Index: QuartusII/db/usimplez.(2).cnf.hdb
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.(2).cnf.hdb
===================================================================
--- QuartusII/db/usimplez.(2).cnf.hdb (nonexistent)
+++ QuartusII/db/usimplez.(2).cnf.hdb (revision 2)
QuartusII/db/usimplez.(2).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.rtlv.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.rtlv.hdb
===================================================================
--- QuartusII/db/usimplez.rtlv.hdb (nonexistent)
+++ QuartusII/db/usimplez.rtlv.hdb (revision 2)
QuartusII/db/usimplez.rtlv.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: QuartusII/db/usimplez.fit.qmsg
===================================================================
--- QuartusII/db/usimplez.fit.qmsg (nonexistent)
+++ QuartusII/db/usimplez.fit.qmsg (revision 2)
@@ -0,0 +1,41 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 01:45:59 2011 " "Info: Processing started: Wed Nov 09 01:45:59 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "usimplez " "Warning: Ignored assignments for entity \"usimplez\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "usimplez EP2S15F484C3 " "Info: Automatically selected device EP2S15F484C3 for design usimplez" { } { } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." { } { } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 473 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1}
+{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 7 " "Critical Warning: No exact pin location assignment(s) for 7 pins of 7 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "we_o " "Info: Pin we_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { we_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 61 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { we_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 80 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "in0_o " "Info: Pin in0_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { in0_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 62 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { in0_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 81 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "in1_o " "Info: Pin in1_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { in1_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 63 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { in1_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 82 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "op0_o " "Info: Pin op0_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { op0_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 64 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { op0_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 83 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "op1_o " "Info: Pin op1_o not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { op1_o } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 65 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { op1_o } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 84 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_i " "Info: Pin clk_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 78 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst_i " "Info: Pin rst_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 60 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 79 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_i (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/usimplez/" 0 { } { { 0 { 0 ""} 0 78 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "6 unused 3.3V 1 5 0 " "Info: Number of I/O pins in group: 6 (unused VREF, 3.3V VCCIO, 1 input, 5 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 44 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 49 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 35 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 40 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 34 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use undetermined 0 6 " "Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Info: Fitter preparation operations ending: elapsed time is 00:00:02" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.247 ns register register " "Info: Estimated most critical path is register to register delay of 5.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usimplez_cpu:cpu\|estado.In0 1 REG LAB_X19_Y12 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y12; Fanout = 5; REG Node = 'usimplez_cpu:cpu\|estado.In0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { usimplez_cpu:cpu|estado.In0 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.729 ns) + CELL(0.378 ns) 2.107 ns usimplez_cpu:cpu\|co_reg_s\[2\]~1 2 COMB LAB_X6_Y2 12 " "Info: 2: + IC(1.729 ns) + CELL(0.378 ns) = 2.107 ns; Loc. = LAB_X6_Y2; Fanout = 12; COMB Node = 'usimplez_cpu:cpu\|co_reg_s\[2\]~1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.107 ns" { usimplez_cpu:cpu|estado.In0 usimplez_cpu:cpu|co_reg_s[2]~1 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.394 ns) + CELL(0.746 ns) 5.247 ns usimplez_cpu:cpu\|cd_reg_s\[5\] 3 REG LAB_X21_Y15 2 " "Info: 3: + IC(2.394 ns) + CELL(0.746 ns) = 5.247 ns; Loc. = LAB_X21_Y15; Fanout = 2; REG Node = 'usimplez_cpu:cpu\|cd_reg_s\[5\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.140 ns" { usimplez_cpu:cpu|co_reg_s[2]~1 usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.124 ns ( 21.42 % ) " "Info: Total cell delay = 1.124 ns ( 21.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.123 ns ( 78.58 % ) " "Info: Total interconnect delay = 4.123 ns ( 78.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.247 ns" { usimplez_cpu:cpu|estado.In0 usimplez_cpu:cpu|co_reg_s[2]~1 usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X13_Y0 X26_Y13 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "we_o 0 " "Info: Pin \"we_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in0_o 0 " "Info: Pin \"in0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in1_o 0 " "Info: Pin \"in1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op0_o 0 " "Info: Pin \"op0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op1_o 0 " "Info: Pin \"op1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 8 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "236 " "Info: Peak virtual memory: 236 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 01:46:26 2011 " "Info: Processing ended: Wed Nov 09 01:46:26 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:23 " "Info: Total CPU time (on all processors): 00:00:23" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: QuartusII/db/usimplez.tan.qmsg
===================================================================
--- QuartusII/db/usimplez.tan.qmsg (nonexistent)
+++ QuartusII/db/usimplez.tan.qmsg (revision 2)
@@ -0,0 +1,13 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 01:53:37 2011 " "Info: Processing started: Wed Nov 09 01:53:37 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "usimplez " "Warning: Ignored assignments for entity \"usimplez\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "5 " "Warning: Found 5 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "we_o 0 " "Info: Pin \"we_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in0_o 0 " "Info: Pin \"in0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "in1_o 0 " "Info: Pin \"in1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op0_o 0 " "Info: Pin \"op0_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "op1_o 0 " "Info: Pin \"op1_o\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_i " "Info: Assuming node \"clk_i\" is an undefined clock" { } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } { "c:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_i" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_i memory usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a0~porta_we_reg register usimplez_cpu:cpu\|acumulador\[11\] 130.28 MHz 7.676 ns Internal " "Info: Clock \"clk_i\" has Internal fmax of 130.28 MHz between source memory \"usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a0~porta_we_reg\" and destination register \"usimplez_cpu:cpu\|acumulador\[11\]\" (period= 7.676 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.761 ns + Longest memory register " "Info: + Longest memory to register delay is 3.761 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a0~porta_we_reg 1 MEM M4K_X20_Y15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X20_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a0~porta_we_reg'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.850 ns) 1.850 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a1 2 MEM M4K_X20_Y15 4 " "Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X20_Y15; Fanout = 4; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 } "NODE_NAME" } } { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf" 56 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.436 ns) 3.135 ns usimplez_cpu:cpu\|Add2~7 3 COMB LCCOMB_X21_Y13_N2 2 " "Info: 3: + IC(0.849 ns) + CELL(0.436 ns) = 3.135 ns; Loc. = LCCOMB_X21_Y13_N2; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~7'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 usimplez_cpu:cpu|Add2~7 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.170 ns usimplez_cpu:cpu\|Add2~11 4 COMB LCCOMB_X21_Y13_N4 2 " "Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 3.170 ns; Loc. = LCCOMB_X21_Y13_N4; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~11'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~7 usimplez_cpu:cpu|Add2~11 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.205 ns usimplez_cpu:cpu\|Add2~15 5 COMB LCCOMB_X21_Y13_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 3.205 ns; Loc. = LCCOMB_X21_Y13_N6; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~15'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~11 usimplez_cpu:cpu|Add2~15 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.240 ns usimplez_cpu:cpu\|Add2~19 6 COMB LCCOMB_X21_Y13_N8 2 " "Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 3.240 ns; Loc. = LCCOMB_X21_Y13_N8; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~19'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.275 ns usimplez_cpu:cpu\|Add2~23 7 COMB LCCOMB_X21_Y13_N10 2 " "Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 3.275 ns; Loc. = LCCOMB_X21_Y13_N10; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~23'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.310 ns usimplez_cpu:cpu\|Add2~27 8 COMB LCCOMB_X21_Y13_N12 2 " "Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 3.310 ns; Loc. = LCCOMB_X21_Y13_N12; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~27'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.124 ns) 3.434 ns usimplez_cpu:cpu\|Add2~31 9 COMB LCCOMB_X21_Y13_N14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.124 ns) = 3.434 ns; Loc. = LCCOMB_X21_Y13_N14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~31'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.124 ns" { usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.469 ns usimplez_cpu:cpu\|Add2~35 10 COMB LCCOMB_X21_Y13_N16 2 " "Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 3.469 ns; Loc. = LCCOMB_X21_Y13_N16; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~35'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.504 ns usimplez_cpu:cpu\|Add2~39 11 COMB LCCOMB_X21_Y13_N18 2 " "Info: 11: + IC(0.000 ns) + CELL(0.035 ns) = 3.504 ns; Loc. = LCCOMB_X21_Y13_N18; Fanout = 2; COMB Node = 'usimplez_cpu:cpu\|Add2~39'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 3.539 ns usimplez_cpu:cpu\|Add2~43 12 COMB LCCOMB_X21_Y13_N20 1 " "Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 3.539 ns; Loc. = LCCOMB_X21_Y13_N20; Fanout = 1; COMB Node = 'usimplez_cpu:cpu\|Add2~43'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.035 ns" { usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 3.664 ns usimplez_cpu:cpu\|Add2~46 13 COMB LCCOMB_X21_Y13_N22 1 " "Info: 13: + IC(0.000 ns) + CELL(0.125 ns) = 3.664 ns; Loc. = LCCOMB_X21_Y13_N22; Fanout = 1; COMB Node = 'usimplez_cpu:cpu\|Add2~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 206 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.097 ns) 3.761 ns usimplez_cpu:cpu\|acumulador\[11\] 14 REG LCFF_X21_Y13_N23 3 " "Info: 14: + IC(0.000 ns) + CELL(0.097 ns) = 3.761 ns; Loc. = LCFF_X21_Y13_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu\|acumulador\[11\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.097 ns" { usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|acumulador[11] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.912 ns ( 77.43 % ) " "Info: Total cell delay = 2.912 ns ( 77.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.849 ns ( 22.57 % ) " "Info: Total interconnect delay = 0.849 ns ( 22.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.761 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 usimplez_cpu:cpu|Add2~7 usimplez_cpu:cpu|Add2~11 usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|acumulador[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.761 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 {} usimplez_cpu:cpu|Add2~7 {} usimplez_cpu:cpu|Add2~11 {} usimplez_cpu:cpu|Add2~15 {} usimplez_cpu:cpu|Add2~19 {} usimplez_cpu:cpu|Add2~23 {} usimplez_cpu:cpu|Add2~27 {} usimplez_cpu:cpu|Add2~31 {} usimplez_cpu:cpu|Add2~35 {} usimplez_cpu:cpu|Add2~39 {} usimplez_cpu:cpu|Add2~43 {} usimplez_cpu:cpu|Add2~46 {} usimplez_cpu:cpu|acumulador[11] {} } { 0.000ns 0.000ns 0.849ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.850ns 0.436ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.124ns 0.035ns 0.035ns 0.035ns 0.125ns 0.097ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.149 ns - Smallest " "Info: - Smallest clock skew is 0.149 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.483 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_i\" to destination register is 2.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.618 ns) 2.483 ns usimplez_cpu:cpu\|acumulador\[11\] 3 REG LCFF_X21_Y13_N23 3 " "Info: 3: + IC(0.668 ns) + CELL(0.618 ns) = 2.483 ns; Loc. = LCFF_X21_Y13_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu\|acumulador\[11\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { clk_i~clkctrl usimplez_cpu:cpu|acumulador[11] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.28 % ) " "Info: Total cell delay = 1.472 ns ( 59.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.011 ns ( 40.72 % ) " "Info: Total interconnect delay = 1.011 ns ( 40.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|acumulador[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.483 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|acumulador[11] {} } { 0.000ns 0.000ns 0.343ns 0.668ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.334 ns - Longest memory " "Info: - Longest clock path from clock \"clk_i\" to source memory is 2.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.656 ns) + CELL(0.481 ns) 2.334 ns usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X20_Y15 3 " "Info: 3: + IC(0.656 ns) + CELL(0.481 ns) = 2.334 ns; Loc. = M4K_X20_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram\|altsyncram:ram_rtl_0\|altsyncram_im61:auto_generated\|ram_block1a0~porta_we_reg'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.137 ns" { clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf" 36 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.335 ns ( 57.20 % ) " "Info: Total cell delay = 1.335 ns ( 57.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 42.80 % ) " "Info: Total interconnect delay = 0.999 ns ( 42.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk_i clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.656ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|acumulador[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.483 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|acumulador[11] {} } { 0.000ns 0.000ns 0.343ns 0.668ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk_i clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.656ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.136 ns + " "Info: + Micro clock to output delay of source is 0.136 ns" { } { { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf" 36 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf" 36 2 0 } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.761 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 usimplez_cpu:cpu|Add2~7 usimplez_cpu:cpu|Add2~11 usimplez_cpu:cpu|Add2~15 usimplez_cpu:cpu|Add2~19 usimplez_cpu:cpu|Add2~23 usimplez_cpu:cpu|Add2~27 usimplez_cpu:cpu|Add2~31 usimplez_cpu:cpu|Add2~35 usimplez_cpu:cpu|Add2~39 usimplez_cpu:cpu|Add2~43 usimplez_cpu:cpu|Add2~46 usimplez_cpu:cpu|acumulador[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.761 ns" { usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 {} usimplez_cpu:cpu|Add2~7 {} usimplez_cpu:cpu|Add2~11 {} usimplez_cpu:cpu|Add2~15 {} usimplez_cpu:cpu|Add2~19 {} usimplez_cpu:cpu|Add2~23 {} usimplez_cpu:cpu|Add2~27 {} usimplez_cpu:cpu|Add2~31 {} usimplez_cpu:cpu|Add2~35 {} usimplez_cpu:cpu|Add2~39 {} usimplez_cpu:cpu|Add2~43 {} usimplez_cpu:cpu|Add2~46 {} usimplez_cpu:cpu|acumulador[11] {} } { 0.000ns 0.000ns 0.849ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.850ns 0.436ns 0.035ns 0.035ns 0.035ns 0.035ns 0.035ns 0.124ns 0.035ns 0.035ns 0.035ns 0.125ns 0.097ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|acumulador[11] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.483 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|acumulador[11] {} } { 0.000ns 0.000ns 0.343ns 0.668ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk_i clk_i~clkctrl usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.656ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "usimplez_cpu:cpu\|cd_reg_s\[5\] rst_i clk_i 5.847 ns register " "Info: tsu for register \"usimplez_cpu:cpu\|cd_reg_s\[5\]\" (data pin = \"rst_i\", clock pin = \"clk_i\") is 5.847 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.233 ns + Longest pin register " "Info: + Longest pin to register delay is 8.233 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.827 ns) 0.827 ns rst_i 1 PIN PIN_W12 49 " "Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_W12; Fanout = 49; PIN Node = 'rst_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.472 ns) + CELL(0.366 ns) 5.665 ns usimplez_cpu:cpu\|co_reg_s\[2\]~1 2 COMB LCCOMB_X6_Y2_N6 12 " "Info: 2: + IC(4.472 ns) + CELL(0.366 ns) = 5.665 ns; Loc. = LCCOMB_X6_Y2_N6; Fanout = 12; COMB Node = 'usimplez_cpu:cpu\|co_reg_s\[2\]~1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.838 ns" { rst_i usimplez_cpu:cpu|co_reg_s[2]~1 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.822 ns) + CELL(0.746 ns) 8.233 ns usimplez_cpu:cpu\|cd_reg_s\[5\] 3 REG LCFF_X21_Y15_N29 2 " "Info: 3: + IC(1.822 ns) + CELL(0.746 ns) = 8.233 ns; Loc. = LCFF_X21_Y15_N29; Fanout = 2; REG Node = 'usimplez_cpu:cpu\|cd_reg_s\[5\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.568 ns" { usimplez_cpu:cpu|co_reg_s[2]~1 usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.939 ns ( 23.55 % ) " "Info: Total cell delay = 1.939 ns ( 23.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.294 ns ( 76.45 % ) " "Info: Total interconnect delay = 6.294 ns ( 76.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { rst_i usimplez_cpu:cpu|co_reg_s[2]~1 usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|co_reg_s[2]~1 {} usimplez_cpu:cpu|cd_reg_s[5] {} } { 0.000ns 0.000ns 4.472ns 1.822ns } { 0.000ns 0.827ns 0.366ns 0.746ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.476 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_i\" to destination register is 2.476 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.661 ns) + CELL(0.618 ns) 2.476 ns usimplez_cpu:cpu\|cd_reg_s\[5\] 3 REG LCFF_X21_Y15_N29 2 " "Info: 3: + IC(0.661 ns) + CELL(0.618 ns) = 2.476 ns; Loc. = LCFF_X21_Y15_N29; Fanout = 2; REG Node = 'usimplez_cpu:cpu\|cd_reg_s\[5\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.279 ns" { clk_i~clkctrl usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 109 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.45 % ) " "Info: Total cell delay = 1.472 ns ( 59.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.004 ns ( 40.55 % ) " "Info: Total interconnect delay = 1.004 ns ( 40.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.476 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.476 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|cd_reg_s[5] {} } { 0.000ns 0.000ns 0.343ns 0.661ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.233 ns" { rst_i usimplez_cpu:cpu|co_reg_s[2]~1 usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.233 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|co_reg_s[2]~1 {} usimplez_cpu:cpu|cd_reg_s[5] {} } { 0.000ns 0.000ns 4.472ns 1.822ns } { 0.000ns 0.827ns 0.366ns 0.746ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.476 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|cd_reg_s[5] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.476 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|cd_reg_s[5] {} } { 0.000ns 0.000ns 0.343ns 0.661ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_i op0_o usimplez_cpu:cpu\|Op0_o 7.162 ns register " "Info: tco from clock \"clk_i\" to destination pin \"op0_o\" through register \"usimplez_cpu:cpu\|Op0_o\" is 7.162 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.490 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to source register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns usimplez_cpu:cpu\|Op0_o 3 REG LCFF_X6_Y2_N1 1 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X6_Y2_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu\|Op0_o'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk_i~clkctrl usimplez_cpu:cpu|Op0_o } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|Op0_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|Op0_o {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 79 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.578 ns + Longest register pin " "Info: + Longest register to pin delay is 4.578 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns usimplez_cpu:cpu\|Op0_o 1 REG LCFF_X6_Y2_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y2_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu\|Op0_o'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { usimplez_cpu:cpu|Op0_o } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 79 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.616 ns) + CELL(1.962 ns) 4.578 ns op0_o 2 PIN PIN_D14 0 " "Info: 2: + IC(2.616 ns) + CELL(1.962 ns) = 4.578 ns; Loc. = PIN_D14; Fanout = 0; PIN Node = 'op0_o'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.578 ns" { usimplez_cpu:cpu|Op0_o op0_o } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 64 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.962 ns ( 42.86 % ) " "Info: Total cell delay = 1.962 ns ( 42.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.616 ns ( 57.14 % ) " "Info: Total interconnect delay = 2.616 ns ( 57.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.578 ns" { usimplez_cpu:cpu|Op0_o op0_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "4.578 ns" { usimplez_cpu:cpu|Op0_o {} op0_o {} } { 0.000ns 2.616ns } { 0.000ns 1.962ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|Op0_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|Op0_o {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.578 ns" { usimplez_cpu:cpu|Op0_o op0_o } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "4.578 ns" { usimplez_cpu:cpu|Op0_o {} op0_o {} } { 0.000ns 2.616ns } { 0.000ns 1.962ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "usimplez_cpu:cpu\|estado.In1 rst_i clk_i -2.805 ns register " "Info: th for register \"usimplez_cpu:cpu\|estado.In1\" (data pin = \"rst_i\", clock pin = \"clk_i\") is -2.805 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.490 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to destination register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 107 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 59 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns usimplez_cpu:cpu\|estado.In1 3 REG LCFF_X6_Y2_N25 42 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X6_Y2_N25; Fanout = 42; REG Node = 'usimplez_cpu:cpu\|estado.In1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk_i~clkctrl usimplez_cpu:cpu|estado.In1 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|estado.In1 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|estado.In1 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 89 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.444 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.444 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.827 ns) 0.827 ns rst_i 1 PIN PIN_W12 49 " "Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_W12; Fanout = 49; PIN Node = 'rst_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 60 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.409 ns) + CELL(0.053 ns) 5.289 ns usimplez_cpu:cpu\|estado~7 2 COMB LCCOMB_X6_Y2_N24 1 " "Info: 2: + IC(4.409 ns) + CELL(0.053 ns) = 5.289 ns; Loc. = LCCOMB_X6_Y2_N24; Fanout = 1; COMB Node = 'usimplez_cpu:cpu\|estado~7'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.462 ns" { rst_i usimplez_cpu:cpu|estado~7 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 5.444 ns usimplez_cpu:cpu\|estado.In1 3 REG LCFF_X6_Y2_N25 42 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.444 ns; Loc. = LCFF_X6_Y2_N25; Fanout = 42; REG Node = 'usimplez_cpu:cpu\|estado.In1'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { usimplez_cpu:cpu|estado~7 usimplez_cpu:cpu|estado.In1 } "NODE_NAME" } } { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.035 ns ( 19.01 % ) " "Info: Total cell delay = 1.035 ns ( 19.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.409 ns ( 80.99 % ) " "Info: Total interconnect delay = 4.409 ns ( 80.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.444 ns" { rst_i usimplez_cpu:cpu|estado~7 usimplez_cpu:cpu|estado.In1 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.444 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|estado~7 {} usimplez_cpu:cpu|estado.In1 {} } { 0.000ns 0.000ns 4.409ns 0.000ns } { 0.000ns 0.827ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk_i clk_i~clkctrl usimplez_cpu:cpu|estado.In1 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} usimplez_cpu:cpu|estado.In1 {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.444 ns" { rst_i usimplez_cpu:cpu|estado~7 usimplez_cpu:cpu|estado.In1 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.444 ns" { rst_i {} rst_i~combout {} usimplez_cpu:cpu|estado~7 {} usimplez_cpu:cpu|estado.In1 {} } { 0.000ns 0.000ns 4.409ns 0.000ns } { 0.000ns 0.827ns 0.053ns 0.155ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 5 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "155 " "Info: Peak virtual memory: 155 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 01:53:41 2011 " "Info: Processing ended: Wed Nov 09 01:53:41 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: QuartusII/db/usimplez.lpc.txt
===================================================================
--- QuartusII/db/usimplez.lpc.txt (nonexistent)
+++ QuartusII/db/usimplez.lpc.txt (revision 2)
@@ -0,0 +1,8 @@
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Legal Partition Candidates ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
+; ram ; 23 ; 0 ; 0 ; 0 ; 12 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; cpu ; 14 ; 0 ; 0 ; 0 ; 26 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
Index: QuartusII/db/usimplez.sim.cvwf
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.sim.cvwf
===================================================================
--- QuartusII/db/usimplez.sim.cvwf (nonexistent)
+++ QuartusII/db/usimplez.sim.cvwf (revision 2)
QuartusII/db/usimplez.sim.cvwf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.sgdiff.hdb
===================================================================
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Index: QuartusII/db/usimplez.sgdiff.hdb
===================================================================
--- QuartusII/db/usimplez.sgdiff.hdb (nonexistent)
+++ QuartusII/db/usimplez.sgdiff.hdb (revision 2)
QuartusII/db/usimplez.sgdiff.hdb
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.sim.qmsg
===================================================================
--- QuartusII/db/usimplez.sim.qmsg (nonexistent)
+++ QuartusII/db/usimplez.sim.qmsg (revision 2)
@@ -0,0 +1,9 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 01:52:15 2011 " "Info: Processing started: Wed Nov 09 01:52:15 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off usimplez -c usimplez " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off usimplez -c usimplez" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "C:/Altera/qdesigns/usimplez/usimplez_top.vwf " "Info: Using vector source file \"C:/Altera/qdesigns/usimplez/usimplez_top.vwf\"" { } { } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." { } { } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0 -1} } { } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0 -1}
+{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" { } { } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0 -1}
+{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" " 89.76 % " "Info: Simulation coverage is 89.76 %" { } { } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "113895 " "Info: Number of transitions in simulation is 113895" { } { } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "121 " "Info: Peak virtual memory: 121 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 01:52:27 2011 " "Info: Processing ended: Wed Nov 09 01:52:27 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Info: Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: QuartusII/db/usimplez.eds_overflow
===================================================================
--- QuartusII/db/usimplez.eds_overflow (nonexistent)
+++ QuartusII/db/usimplez.eds_overflow (revision 2)
@@ -0,0 +1 @@
+4000
\ No newline at end of file
Index: QuartusII/db/usimplez.ace_cmp.bpm
===================================================================
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Index: QuartusII/db/usimplez.ace_cmp.bpm
===================================================================
--- QuartusII/db/usimplez.ace_cmp.bpm (nonexistent)
+++ QuartusII/db/usimplez.ace_cmp.bpm (revision 2)
QuartusII/db/usimplez.ace_cmp.bpm
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/logic_util_heursitic.dat
===================================================================
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Index: QuartusII/db/logic_util_heursitic.dat
===================================================================
--- QuartusII/db/logic_util_heursitic.dat (nonexistent)
+++ QuartusII/db/logic_util_heursitic.dat (revision 2)
QuartusII/db/logic_util_heursitic.dat
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.sld_design_entry.sci
===================================================================
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Index: QuartusII/db/usimplez.sld_design_entry.sci
===================================================================
--- QuartusII/db/usimplez.sld_design_entry.sci (nonexistent)
+++ QuartusII/db/usimplez.sld_design_entry.sci (revision 2)
QuartusII/db/usimplez.sld_design_entry.sci
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.map.kpt
===================================================================
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Index: QuartusII/db/usimplez.map.kpt
===================================================================
--- QuartusII/db/usimplez.map.kpt (nonexistent)
+++ QuartusII/db/usimplez.map.kpt (revision 2)
QuartusII/db/usimplez.map.kpt
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.cbx.xml
===================================================================
--- QuartusII/db/usimplez.cbx.xml (nonexistent)
+++ QuartusII/db/usimplez.cbx.xml (revision 2)
@@ -0,0 +1,6 @@
+
+
+
+
+
Index: QuartusII/db/usimplez.cmp.kpt
===================================================================
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Index: QuartusII/db/usimplez.cmp.kpt
===================================================================
--- QuartusII/db/usimplez.cmp.kpt (nonexistent)
+++ QuartusII/db/usimplez.cmp.kpt (revision 2)
QuartusII/db/usimplez.cmp.kpt
Property changes :
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## -0,0 +1 ##
+application/octet-stream
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Index: QuartusII/db/usimplez.(1).cnf.cdb
===================================================================
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Index: QuartusII/db/usimplez.(1).cnf.cdb
===================================================================
--- QuartusII/db/usimplez.(1).cnf.cdb (nonexistent)
+++ QuartusII/db/usimplez.(1).cnf.cdb (revision 2)
QuartusII/db/usimplez.(1).cnf.cdb
Property changes :
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/altsyncram_im61.tdf
===================================================================
--- QuartusII/db/altsyncram_im61.tdf (nonexistent)
+++ QuartusII/db/altsyncram_im61.tdf (revision 2)
@@ -0,0 +1,297 @@
+--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" INIT_FILE="fibonacci.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=512 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=12 WIDTHAD_A=9 WRCONTROL_ACLR_A="NONE" address_a clock0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
+--VERSION_BEGIN 9.1SP2 cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+
+FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
+WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE)
+RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
+
+--synthesis_resources = ram_bits (AUTO) 6144
+OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
+
+SUBDESIGN altsyncram_im61
+(
+ address_a[8..0] : input;
+ clock0 : input;
+ data_a[11..0] : input;
+ q_a[11..0] : output;
+ wren_a : input;
+)
+VARIABLE
+ ram_block1a0 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 0,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a1 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 1,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a2 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 2,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a3 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 3,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a4 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 4,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a5 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 5,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a6 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 6,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a7 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 7,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a8 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 8,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a9 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 9,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a10 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 10,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ ram_block1a11 : stratixii_ram_block
+ WITH (
+ CONNECTIVITY_CHECKING = "OFF",
+ INIT_FILE = "fibonacci.mif",
+ INIT_FILE_LAYOUT = "port_a",
+ LOGICAL_RAM_NAME = "ALTSYNCRAM",
+ OPERATION_MODE = "single_port",
+ PORT_A_ADDRESS_WIDTH = 9,
+ PORT_A_DATA_OUT_CLEAR = "none",
+ PORT_A_DATA_OUT_CLOCK = "none",
+ PORT_A_DATA_WIDTH = 1,
+ PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
+ PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
+ PORT_A_FIRST_ADDRESS = 0,
+ PORT_A_FIRST_BIT_NUMBER = 11,
+ PORT_A_LAST_ADDRESS = 511,
+ PORT_A_LOGICAL_RAM_DEPTH = 512,
+ PORT_A_LOGICAL_RAM_WIDTH = 12,
+ RAM_BLOCK_TYPE = "AUTO"
+ );
+ address_a_wire[8..0] : WIRE;
+
+BEGIN
+ ram_block1a[11..0].clk0 = clock0;
+ ram_block1a[11..0].portaaddr[] = ( address_a_wire[8..0]);
+ ram_block1a[0].portadatain[] = ( data_a[0..0]);
+ ram_block1a[1].portadatain[] = ( data_a[1..1]);
+ ram_block1a[2].portadatain[] = ( data_a[2..2]);
+ ram_block1a[3].portadatain[] = ( data_a[3..3]);
+ ram_block1a[4].portadatain[] = ( data_a[4..4]);
+ ram_block1a[5].portadatain[] = ( data_a[5..5]);
+ ram_block1a[6].portadatain[] = ( data_a[6..6]);
+ ram_block1a[7].portadatain[] = ( data_a[7..7]);
+ ram_block1a[8].portadatain[] = ( data_a[8..8]);
+ ram_block1a[9].portadatain[] = ( data_a[9..9]);
+ ram_block1a[10].portadatain[] = ( data_a[10..10]);
+ ram_block1a[11].portadatain[] = ( data_a[11..11]);
+ ram_block1a[11..0].portawe = wren_a;
+ address_a_wire[] = address_a[];
+ q_a[] = ( ram_block1a[11..0].portadataout[0..0]);
+END;
+--VALID FILE
Index: QuartusII/db/usimplez.map.qmsg
===================================================================
--- QuartusII/db/usimplez.map.qmsg (nonexistent)
+++ QuartusII/db/usimplez.map.qmsg (revision 2)
@@ -0,0 +1,16 @@
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 09 01:44:42 2011 " "Info: Processing started: Wed Nov 09 01:44:42 2011" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_top-str " "Info: Found design unit 1: usimplez_top-str" { } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 69 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_top " "Info: Found entity 1: usimplez_top" { } { { "usimplez_top.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 53 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_cpu.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_cpu.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_cpu-fsm " "Info: Found design unit 1: usimplez_cpu-fsm" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 86 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_cpu " "Info: Found entity 1: usimplez_cpu" { } { { "usimplez_cpu.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd" 52 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usimplez_ram.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usimplez_ram.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usimplez_ram-rtl " "Info: Found design unit 1: usimplez_ram-rtl" { } { { "usimplez_ram.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_ram.vhd" 70 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 usimplez_ram " "Info: Found entity 1: usimplez_ram" { } { { "usimplez_ram.vhd" "" { Text "C:/Altera/qdesigns/usimplez/usimplez_ram.vhd" 53 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_TOP" "usimplez_top " "Info: Elaborating entity \"usimplez_top\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "usimplez_cpu usimplez_cpu:cpu " "Info: Elaborating entity \"usimplez_cpu\" for hierarchy \"usimplez_cpu:cpu\"" { } { { "usimplez_top.vhd" "cpu" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 123 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "usimplez_ram usimplez_ram:ram " "Info: Elaborating entity \"usimplez_ram\" for hierarchy \"usimplez_ram:ram\"" { } { { "usimplez_top.vhd" "ram" { Text "C:/Altera/qdesigns/usimplez/usimplez_top.vhd" 150 0 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
+{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "usimplez_ram:ram\|ram~22 " "Info: Inferred altsyncram megafunction from the following design logic: \"usimplez_ram:ram\|ram~22\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE SINGLE_PORT " "Info: Parameter OPERATION_MODE set to SINGLE_PORT" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 12 " "Info: Parameter WIDTH_A set to 12" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 9 " "Info: Parameter WIDTHAD_A set to 9" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 512 " "Info: Parameter NUMWORDS_A set to 512" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE fibonacci.mif " "Info: Parameter INIT_FILE set to fibonacci.mif" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} } { { "usimplez_ram.vhd" "ram~22" { Text "C:/Altera/qdesigns/usimplez/usimplez_ram.vhd" 75 -1 0 } } } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 -1} } { } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1}
+{ "Info" "ISGN_ELABORATION_HEADER" "usimplez_ram:ram\|altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"usimplez_ram:ram\|altsyncram:ram_rtl_0\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ISGN_MEGAFN_PARAM_TOP" "usimplez_ram:ram\|altsyncram:ram_rtl_0 " "Info: Instantiated megafunction \"usimplez_ram:ram\|altsyncram:ram_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE SINGLE_PORT " "Info: Parameter \"OPERATION_MODE\" = \"SINGLE_PORT\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 12 " "Info: Parameter \"WIDTH_A\" = \"12\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 9 " "Info: Parameter \"WIDTHAD_A\" = \"9\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 512 " "Info: Parameter \"NUMWORDS_A\" = \"512\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Info: Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE fibonacci.mif " "Info: Parameter \"INIT_FILE\" = \"fibonacci.mif\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_im61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_im61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_im61 " "Info: Found entity 1: altsyncram_im61" { } { { "db/altsyncram_im61.tdf" "" { Text "C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf" 27 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WQCU_FOUND_UNUSABLE_ASSIGNMENTS_FOR_ENTITY" "usimplez " "Warning: Ignored assignments for entity \"usimplez\" -- entity does not exist in design" { { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} { "Warning" "WQCU_IGNORED_ENTITY_ASSIGNMENT" "set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" " "Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id \"Root Region\" was ignored" { } { } 0 0 "Assignment for entity %1!s! was ignored" 0 0 "" 0 -1} } { } 0 0 "Ignored assignments for entity \"%1!s!\" -- entity does not exist in design" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "94 " "Info: Implemented 94 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "5 " "Info: Implemented 5 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "75 " "Info: Implemented 75 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" { } { } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "195 " "Info: Peak virtual memory: 195 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 09 01:44:56 2011 " "Info: Processing ended: Wed Nov 09 01:44:56 2011" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:14 " "Info: Elapsed time: 00:00:14" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Index: QuartusII/db/usimplez.(3).cnf.hdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.(3).cnf.hdb
===================================================================
--- QuartusII/db/usimplez.(3).cnf.hdb (nonexistent)
+++ QuartusII/db/usimplez.(3).cnf.hdb (revision 2)
QuartusII/db/usimplez.(3).cnf.hdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.eco.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.eco.cdb
===================================================================
--- QuartusII/db/usimplez.eco.cdb (nonexistent)
+++ QuartusII/db/usimplez.eco.cdb (revision 2)
QuartusII/db/usimplez.eco.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.db_info
===================================================================
--- QuartusII/db/usimplez.db_info (nonexistent)
+++ QuartusII/db/usimplez.db_info (revision 2)
@@ -0,0 +1,3 @@
+Quartus_Version = Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+Version_Index = 184638978
+Creation_Time = Wed Nov 09 01:39:00 2011
Index: QuartusII/db/usimplez.smart_action.txt
===================================================================
--- QuartusII/db/usimplez.smart_action.txt (nonexistent)
+++ QuartusII/db/usimplez.smart_action.txt (revision 2)
@@ -0,0 +1 @@
+SOURCE
Index: QuartusII/db/usimplez.sld_design_entry_dsc.sci
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.sld_design_entry_dsc.sci
===================================================================
--- QuartusII/db/usimplez.sld_design_entry_dsc.sci (nonexistent)
+++ QuartusII/db/usimplez.sld_design_entry_dsc.sci (revision 2)
QuartusII/db/usimplez.sld_design_entry_dsc.sci
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/db/usimplez.map.logdb
===================================================================
--- QuartusII/db/usimplez.map.logdb (nonexistent)
+++ QuartusII/db/usimplez.map.logdb (revision 2)
@@ -0,0 +1 @@
+v1
Index: QuartusII/db/usimplez.cmp.logdb
===================================================================
--- QuartusII/db/usimplez.cmp.logdb (nonexistent)
+++ QuartusII/db/usimplez.cmp.logdb (revision 2)
@@ -0,0 +1,61 @@
+v1
+RAM_PACKING,0,M4K,9,9,TrueDual,0,7,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a10,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,6,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a9,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,8,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a11,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,5,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a8,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,4,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a7,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,3,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a6,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,2,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a5,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,1,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a4,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,0,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3,
+RAM_PACKING,1,M4K,9,9,TrueDual,0,2,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a2,
+RAM_PACKING,1,M4K,9,9,TrueDual,0,1,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1,
+RAM_PACKING,1,M4K,9,9,TrueDual,0,0,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0,
+IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
+IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
+IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
+IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
+IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No PCI I/O assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No PCI I/O assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
+IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
+IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,,
+IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,,
+IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
+IO_RULES,IO_REG_AND_SERDES_NOT_USED_AT_SAME_XY_LOC,INAPPLICABLE,IO_000032,I/O Properties Checks for Multiple I/Os,I/O registers and SERDES should not be used at the same XY location.,Critical,No I/O Registers or Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os.,Critical,0 such failures found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 1 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_IO_AND_DIFF_IO_NOT_COEXIST_IN_PLL_OUTPUT_IO_BANK,INAPPLICABLE,IO_000037,SI Related Distance Checks,Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank.,High,No Differential I/O Standard assignments found.,,I/O,,
+IO_RULES,SINGLE_ENDED_OUTPUTS_AND_LVDS_NOT_COEXIST_IN_IO_BANK,INAPPLICABLE,IO_000038,SI Related SSO Limit Checks,Single-ended outputs and High-speed LVDS should not coexist in an I/O bank.,High,No High-speed LVDS found.,,I/O,,
+IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
+IO_RULES,TOTAL_DRIVE_STRENGTH_FOR_SINGLE_ENDED_OUTPUTS_IN_DPA_NOT_EXCEED_CURRENT_VALUE,INAPPLICABLE,IO_000040,SI Related SSO Limit Checks,The total drive strength of single ended outputs in a DPA bank should not exceed 120mA.,High,No DPA found.,,I/O,,
+IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000032;IO_000033;IO_000034;IO_000037;IO_000038;IO_000042;IO_000040,
+IO_RULES_MATRIX,Total Pass,0;0;0;0;0;7;0;0;7;7;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;7;0;0;0;0;0,
+IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,Total Inapplicable,7;7;7;7;7;0;7;7;0;0;7;7;7;7;7;7;7;7;7;7;7;7;7;7;7;0;7;7;7;7;7,
+IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
+IO_RULES_MATRIX,we_o,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in0_o,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,in1_o,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,op0_o,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,op1_o,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,clk_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_MATRIX,rst_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable,
+IO_RULES_SUMMARY,Total I/O Rules,31,
+IO_RULES_SUMMARY,Number of I/O Rules Passed,4,
+IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
+IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
+IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,27,
Index: QuartusII/db/wed.wsf
===================================================================
--- QuartusII/db/wed.wsf (nonexistent)
+++ QuartusII/db/wed.wsf (revision 2)
@@ -0,0 +1,1131 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+
+VECTOR("C:/Altera/qdesigns/usimplez/db/usimplez.sim.cvwf")
+{
+ ZOOM{
+ ZBEGIN = 0;
+ ZEND = 1723586;
+ NUMERATOR = 542;
+ DENOMINATOR = 1723586;
+ TOP_INDEX = 0;
+ }
+ CLOCK{
+ PERIOD = 10000;
+ OFFSET = 0;
+ DUTY_CYCLE = 50;
+ }
+ RANDOM_VALUE{
+ INTERVAL_TYPE = HALF_GRID;
+ }
+ LINE{
+ SIGNAL = "rst_i";
+ INDEX = 0;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "clk_i";
+ INDEX = 1;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "we_o";
+ INDEX = 2;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "in0_o";
+ INDEX = 3;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "in1_o";
+ INDEX = 4;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "op0_o";
+ INDEX = 5;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "op1_o";
+ INDEX = 6;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador";
+ INDEX = 7;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[11]";
+ INDEX = 8;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[10]";
+ INDEX = 9;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[9]";
+ INDEX = 10;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[8]";
+ INDEX = 11;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[7]";
+ INDEX = 12;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[6]";
+ INDEX = 13;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[5]";
+ INDEX = 14;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[4]";
+ INDEX = 15;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[3]";
+ INDEX = 16;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[2]";
+ INDEX = 17;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[1]";
+ INDEX = 18;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[0]";
+ INDEX = 19;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o";
+ INDEX = 20;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[8]";
+ INDEX = 21;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[7]";
+ INDEX = 22;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[6]";
+ INDEX = 23;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[5]";
+ INDEX = 24;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[4]";
+ INDEX = 25;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[3]";
+ INDEX = 26;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[2]";
+ INDEX = 27;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[1]";
+ INDEX = 28;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[0]";
+ INDEX = 29;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s";
+ INDEX = 30;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[8]";
+ INDEX = 31;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[7]";
+ INDEX = 32;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[6]";
+ INDEX = 33;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[5]";
+ INDEX = 34;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[4]";
+ INDEX = 35;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[3]";
+ INDEX = 36;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[2]";
+ INDEX = 37;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[1]";
+ INDEX = 38;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[0]";
+ INDEX = 39;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s";
+ INDEX = 40;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s[2]";
+ INDEX = 41;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s[1]";
+ INDEX = 42;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s[0]";
+ INDEX = 43;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s";
+ INDEX = 44;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[8]";
+ INDEX = 45;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[7]";
+ INDEX = 46;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[6]";
+ INDEX = 47;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[5]";
+ INDEX = 48;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[4]";
+ INDEX = 49;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[3]";
+ INDEX = 50;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[2]";
+ INDEX = 51;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[1]";
+ INDEX = 52;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[0]";
+ INDEX = 53;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o";
+ INDEX = 54;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[11]";
+ INDEX = 55;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[10]";
+ INDEX = 56;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[9]";
+ INDEX = 57;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[8]";
+ INDEX = 58;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[7]";
+ INDEX = 59;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[6]";
+ INDEX = 60;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[5]";
+ INDEX = 61;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[4]";
+ INDEX = 62;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[3]";
+ INDEX = 63;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[2]";
+ INDEX = 64;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[1]";
+ INDEX = 65;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[0]";
+ INDEX = 66;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+}
+
+VECTOR("C:/Altera/qdesigns/usimplez/usimplez_top.vwf")
+{
+ ZOOM{
+ ZBEGIN = 0;
+ ZEND = 269600;
+ NUMERATOR = 674;
+ DENOMINATOR = 269600;
+ TOP_INDEX = 0;
+ }
+ CLOCK{
+ PERIOD = 50000;
+ OFFSET = 0;
+ DUTY_CYCLE = 50;
+ }
+ RANDOM_VALUE{
+ INTERVAL_TYPE = HALF_GRID;
+ }
+ LINE{
+ SIGNAL = "rst_i";
+ INDEX = 0;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "clk_i";
+ INDEX = 1;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "we_o";
+ INDEX = 2;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "in0_o";
+ INDEX = 3;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "in1_o";
+ INDEX = 4;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "op0_o";
+ INDEX = 5;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "op1_o";
+ INDEX = 6;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador";
+ INDEX = 7;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[11]";
+ INDEX = 8;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[10]";
+ INDEX = 9;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[9]";
+ INDEX = 10;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[8]";
+ INDEX = 11;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[7]";
+ INDEX = 12;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[6]";
+ INDEX = 13;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[5]";
+ INDEX = 14;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[4]";
+ INDEX = 15;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[3]";
+ INDEX = 16;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[2]";
+ INDEX = 17;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[1]";
+ INDEX = 18;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|acumulador[0]";
+ INDEX = 19;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o";
+ INDEX = 20;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[8]";
+ INDEX = 21;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[7]";
+ INDEX = 22;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[6]";
+ INDEX = 23;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[5]";
+ INDEX = 24;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[4]";
+ INDEX = 25;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[3]";
+ INDEX = 26;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[2]";
+ INDEX = 27;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[1]";
+ INDEX = 28;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|addr_bus_o[0]";
+ INDEX = 29;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s";
+ INDEX = 30;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[8]";
+ INDEX = 31;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[7]";
+ INDEX = 32;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[6]";
+ INDEX = 33;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[5]";
+ INDEX = 34;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[4]";
+ INDEX = 35;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[3]";
+ INDEX = 36;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[2]";
+ INDEX = 37;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[1]";
+ INDEX = 38;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cd_reg_s[0]";
+ INDEX = 39;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s";
+ INDEX = 40;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s[2]";
+ INDEX = 41;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s[1]";
+ INDEX = 42;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|co_reg_s[0]";
+ INDEX = 43;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s";
+ INDEX = 44;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[8]";
+ INDEX = 45;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[7]";
+ INDEX = 46;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[6]";
+ INDEX = 47;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[5]";
+ INDEX = 48;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[4]";
+ INDEX = 49;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[3]";
+ INDEX = 50;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[2]";
+ INDEX = 51;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[1]";
+ INDEX = 52;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|cp_reg_s[0]";
+ INDEX = 53;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o";
+ INDEX = 54;
+ FORMAT = T;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[11]";
+ INDEX = 55;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[10]";
+ INDEX = 56;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[9]";
+ INDEX = 57;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[8]";
+ INDEX = 58;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[7]";
+ INDEX = 59;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[6]";
+ INDEX = 60;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[5]";
+ INDEX = 61;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[4]";
+ INDEX = 62;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[3]";
+ INDEX = 63;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[2]";
+ INDEX = 64;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[1]";
+ INDEX = 65;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+ LINE{
+ SIGNAL = "usimplez_cpu:cpu|data_bus_o[0]";
+ INDEX = 66;
+ FORMAT = E;
+ SCALE = 1;
+ VISIBLE = Y;
+ FLAG = N;
+ }
+}
Index: QuartusII/db/usimplez.rtlv_sg.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/db/usimplez.rtlv_sg.cdb
===================================================================
--- QuartusII/db/usimplez.rtlv_sg.cdb (nonexistent)
+++ QuartusII/db/usimplez.rtlv_sg.cdb (revision 2)
QuartusII/db/usimplez.rtlv_sg.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/usimplez.fit.summary
===================================================================
--- QuartusII/usimplez.fit.summary (nonexistent)
+++ QuartusII/usimplez.fit.summary (revision 2)
@@ -0,0 +1,17 @@
+Fitter Status : Successful - Wed Nov 09 01:46:25 2011
+Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+Revision Name : usimplez
+Top-level Entity Name : usimplez_top
+Family : Stratix II
+Device : EP2S15F484C3
+Timing Models : Final
+Logic utilization : < 1 %
+ Combinational ALUTs : 48 / 12,480 ( < 1 % )
+ Dedicated logic registers : 63 / 12,480 ( < 1 % )
+Total registers : 63
+Total pins : 7 / 343 ( 2 % )
+Total virtual pins : 0
+Total block memory bits : 6,144 / 419,328 ( 1 % )
+DSP block 9-bit elements : 0 / 96 ( 0 % )
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 2 ( 0 % )
Index: QuartusII/usimplez.tan.summary
===================================================================
--- QuartusII/usimplez.tan.summary (nonexistent)
+++ QuartusII/usimplez.tan.summary (revision 2)
@@ -0,0 +1,56 @@
+--------------------------------------------------------------------------------------
+Timing Analyzer Summary
+--------------------------------------------------------------------------------------
+
+Type : Worst-case tsu
+Slack : N/A
+Required Time : None
+Actual Time : 5.847 ns
+From : rst_i
+To : usimplez_cpu:cpu|cd_reg_s[8]
+From Clock : --
+To Clock : clk_i
+Failed Paths : 0
+
+Type : Worst-case tco
+Slack : N/A
+Required Time : None
+Actual Time : 7.162 ns
+From : usimplez_cpu:cpu|Op0_o
+To : op0_o
+From Clock : clk_i
+To Clock : --
+Failed Paths : 0
+
+Type : Worst-case th
+Slack : N/A
+Required Time : None
+Actual Time : -2.805 ns
+From : rst_i
+To : usimplez_cpu:cpu|estado.In1
+From Clock : --
+To Clock : clk_i
+Failed Paths : 0
+
+Type : Clock Setup: 'clk_i'
+Slack : N/A
+Required Time : None
+Actual Time : 130.28 MHz ( period = 7.676 ns )
+From : usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8
+To : usimplez_cpu:cpu|acumulador[11]
+From Clock : clk_i
+To Clock : clk_i
+Failed Paths : 0
+
+Type : Total number of failed paths
+Slack :
+Required Time :
+Actual Time :
+From :
+To :
+From Clock :
+To Clock :
+Failed Paths : 0
+
+--------------------------------------------------------------------------------------
+
Index: QuartusII/usimplez_ram.vhd
===================================================================
--- QuartusII/usimplez_ram.vhd (nonexistent)
+++ QuartusII/usimplez_ram.vhd (revision 2)
@@ -0,0 +1,97 @@
+--//////////////////////////////////////////////////////////////////////
+--//// ////
+--//// ////
+--//// ////
+--//// This file is part of the MicroSimplez project ////
+--//// http://opencores.org/project,usimplez ////
+--//// ////
+--//// Description ////
+--//// Implementation of MicroSimplez IP core according to ////
+--//// MicroSimplez IP core specification document. ////
+--//// ////
+--//// To Do: ////
+--//// - ////
+--//// ////
+--//// Author(s): ////
+--//// - Daniel Peralta, peraltahd@opencores.org, designer ////
+--//// - Martin Montero, monteromrtn@opencores.org, designer ////
+--//// - Julian Castro, julyan@opencores.org, reviewer ////
+--//// - Pablo A. Salvadeo, pas.@opencores, manager ////
+--//// ////
+--//////////////////////////////////////////////////////////////////////
+--//// ////
+--//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
+--//// ////
+--//// This source file may be used and distributed without ////
+--//// restriction provided that this copyright statement is not ////
+--//// removed from the file and that any derivative work contains ////
+--//// the original copyright notice and the associated disclaimer. ////
+--//// ////
+--//// This source file is free software; you can redistribute it ////
+--//// and/or modify it under the terms of the GNU Lesser General ////
+--//// Public License as published by the Free Software Foundation; ////
+--//// either version 2.1 of the License, or (at your option) any ////
+--//// later version. ////
+--//// ////
+--//// This source is distributed in the hope that it will be ////
+--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+--//// PURPOSE. See the GNU Lesser General Public License for more ////
+--//// details. ////
+--//// ////
+--//// You should have received WIDTH_ADDRESS copy of the GNU Lesser General ////
+--//// Public License along with this source; if not, download it ////
+--//// from http://www.opencores.org/lgpl.shtml ////
+--//// ////
+--//////////////////////////////////////////////////////////////////////
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity usimplez_ram is
+
+generic( WIDTH_WORD: natural:= 12;
+ WIDTH_ADDRESS: natural:= 9
+ );
+
+ port
+ (
+ clk_i : in std_logic;
+ addr_i : in unsigned((WIDTH_ADDRESS-1) downto 0);
+ data_i : in std_logic_vector((WIDTH_WORD-1) downto 0);
+ we_i : in std_logic ;
+ data_o : out std_logic_vector((WIDTH_WORD-1) downto 0)
+ );
+
+end usimplez_ram;
+
+architecture rtl of usimplez_ram is
+
+ subtype word_t is std_logic_vector((WIDTH_WORD-1) downto 0);
+ type memory_t is array(2**WIDTH_ADDRESS-1 downto 0) of word_t;
+
+ signal ram : memory_t;
+ attribute ram_init_file : string;
+-- attribute ram_init_file of ram : signal is "adder.mif"; --code adder.txt
+ attribute ram_init_file of ram : signal is "fibonacci.mif"; --code fibonacci.txt
+
+ signal addr_reg_s : unsigned((WIDTH_ADDRESS-1) downto 0);
+
+begin
+
+ process(clk_i)
+ begin
+ if(falling_edge(clk_i)) then
+ if(we_i = '1') then
+ ram(to_integer(addr_i)) <= data_i;
+ end if;
+
+ addr_reg_s <= addr_i;
+ end if;
+ end process;
+
+ data_o <= ram(to_integer(addr_reg_s));
+
+end rtl;
Index: QuartusII/fibonacci.mif
===================================================================
--- QuartusII/fibonacci.mif (nonexistent)
+++ QuartusII/fibonacci.mif (revision 2)
@@ -0,0 +1,41 @@
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- Quartus II generated Memory Initialization File (.mif)
+
+WIDTH=12;
+DEPTH=512;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+ 0 : 1541;
+ 1 : 0;
+ 2 : 1;
+ 3 : 0;
+ 4 : 101;
+ 5 : 516;
+ 6 : 3072;
+ 7 : 4;
+ 8 : 513;
+ 9 : 1026;
+ 10 : 3;
+ 11 : 514;
+ 12 : 1;
+ 13 : 515;
+ 14 : 2;
+ 15 : 1540;
+ [16..511] : 0;
+END;
Index: QuartusII/usimplez.map.rpt
===================================================================
--- QuartusII/usimplez.map.rpt (nonexistent)
+++ QuartusII/usimplez.map.rpt (revision 2)
@@ -0,0 +1,476 @@
+Analysis & Synthesis report for usimplez
+Wed Nov 09 01:44:56 2011
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. Analysis & Synthesis RAM Summary
+ 8. State Machine - |usimplez_top|usimplez_cpu:cpu|estado
+ 9. General Register Statistics
+ 10. Registers Packed Into Inferred Megafunctions
+ 11. Multiplexer Restructuring Statistics (Restructuring Performed)
+ 12. Source assignments for usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated
+ 13. Parameter Settings for User Entity Instance: Top-level Entity: |usimplez_top
+ 14. Parameter Settings for User Entity Instance: usimplez_cpu:cpu
+ 15. Parameter Settings for User Entity Instance: usimplez_ram:ram
+ 16. Parameter Settings for Inferred Entity Instance: usimplez_ram:ram|altsyncram:ram_rtl_0
+ 17. altsyncram Parameter Settings by Entity Instance
+ 18. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++-------------------------------+----------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Wed Nov 09 01:44:56 2011 ;
+; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
+; Revision Name ; usimplez ;
+; Top-level Entity Name ; usimplez_top ;
+; Family ; Stratix II ;
+; Logic utilization ; N/A ;
+; Combinational ALUTs ; 48 ;
+; Dedicated logic registers ; 63 ;
+; Total registers ; 63 ;
+; Total pins ; 7 ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 6,144 ;
+; DSP block 9-bit elements ; 0 ;
+; Total PLLs ; 0 ;
+; Total DLLs ; 0 ;
++-------------------------------+----------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+; Top-level entity name ; usimplez_top ; usimplez ;
+; Family name ; Stratix II ; Stratix II ;
+; Use Generated Physical Constraints File ; Off ; ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; On ; On ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM Block Balancing ; On ; On ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Timing-Driven Synthesis ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Auto Gated Clock Conversion ; Off ; Off ;
+; Block Design Naming ; Auto ; Auto ;
+; SDC constraint protection ; Off ; Off ;
+; Synthesis Effort ; Auto ; Auto ;
+; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
+; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
+; Resource Aware Inference For Block RAM ; On ; On ;
++----------------------------------------------------------------------------+--------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+
+; usimplez_top.vhd ; yes ; User VHDL File ; C:/Altera/qdesigns/usimplez/usimplez_top.vhd ;
+; usimplez_cpu.vhd ; yes ; User VHDL File ; C:/Altera/qdesigns/usimplez/usimplez_cpu.vhd ;
+; usimplez_ram.vhd ; yes ; User VHDL File ; C:/Altera/qdesigns/usimplez/usimplez_ram.vhd ;
+; fibonacci.mif ; yes ; User Memory Initialization File ; C:/Altera/qdesigns/usimplez/fibonacci.mif ;
+; altsyncram.tdf ; yes ; Megafunction ; c:/altera/quartus/libraries/megafunctions/altsyncram.tdf ;
+; db/altsyncram_im61.tdf ; yes ; Auto-Generated Megafunction ; C:/Altera/qdesigns/usimplez/db/altsyncram_im61.tdf ;
++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+
+
+
++-------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++-----------------------------------------------+-------+
+; Resource ; Usage ;
++-----------------------------------------------+-------+
+; Estimated ALUTs Used ; 48 ;
+; Dedicated logic registers ; 63 ;
+; ; ;
+; Estimated ALUTs Unavailable ; 1 ;
+; ; ;
+; Total combinational functions ; 48 ;
+; Combinational ALUT usage by number of inputs ; ;
+; -- 7 input functions ; 1 ;
+; -- 6 input functions ; 6 ;
+; -- 5 input functions ; 4 ;
+; -- 4 input functions ; 0 ;
+; -- <=3 input functions ; 37 ;
+; ; ;
+; Combinational ALUTs by mode ; ;
+; -- normal mode ; 26 ;
+; -- extended LUT mode ; 1 ;
+; -- arithmetic mode ; 21 ;
+; -- shared arithmetic mode ; 0 ;
+; ; ;
+; Estimated ALUT/register pairs used ; 73 ;
+; ; ;
+; Total registers ; 63 ;
+; -- Dedicated logic registers ; 63 ;
+; -- I/O registers ; 0 ;
+; ; ;
+; Estimated ALMs: partially or completely used ; 37 ;
+; ; ;
+; I/O pins ; 7 ;
+; Total block memory bits ; 6144 ;
+; Maximum fan-out node ; clk_i ;
+; Maximum fan-out ; 75 ;
+; Total fan-out ; 599 ;
+; Average fan-out ; 4.61 ;
++-----------------------------------------------+-------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
++-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------------------------------------------------------------+--------------+
+; |usimplez_top ; 48 (0) ; 63 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; |usimplez_top ; work ;
+; |usimplez_cpu:cpu| ; 48 (48) ; 63 (63) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_cpu:cpu ; ;
+; |usimplez_ram:ram| ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_ram:ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_im61:auto_generated| ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated ; ;
++-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary ;
++---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+---------------+
+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
++---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+---------------+
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 512 ; 12 ; -- ; -- ; 6144 ; fibonacci.mif ;
++---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+---------------+
+
+
+Encoding Type: One-Hot
++----------------------------------------------------------------+
+; State Machine - |usimplez_top|usimplez_cpu:cpu|estado ;
++------------+------------+------------+------------+------------+
+; Name ; estado.Op1 ; estado.Op0 ; estado.In1 ; estado.In0 ;
++------------+------------+------------+------------+------------+
+; estado.In0 ; 0 ; 0 ; 0 ; 0 ;
+; estado.In1 ; 0 ; 0 ; 1 ; 1 ;
+; estado.Op0 ; 0 ; 1 ; 0 ; 1 ;
+; estado.Op1 ; 1 ; 0 ; 0 ; 1 ;
++------------+------------+------------+------------+------------+
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 63 ;
+; Number of registers using Synchronous Clear ; 46 ;
+; Number of registers using Synchronous Load ; 30 ;
+; Number of registers using Asynchronous Clear ; 0 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 58 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++-----------------------------------------------------------------+
+; Registers Packed Into Inferred Megafunctions ;
++--------------------------------+-------------------------+------+
+; Register Name ; Megafunction ; Type ;
++--------------------------------+-------------------------+------+
+; usimplez_ram:ram|addr_reg_s[8] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[7] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[6] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[5] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[4] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[3] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[2] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[1] ; usimplez_ram:ram|ram~22 ; RAM ;
+; usimplez_ram:ram|addr_reg_s[0] ; usimplez_ram:ram|ram~22 ; RAM ;
++--------------------------------+-------------------------+------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Multiplexer Restructuring Statistics (Restructuring Performed) ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
+; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
+; 3:1 ; 12 bits ; 24 ALUTs ; 0 ALUTs ; 24 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ;
+; 4:1 ; 12 bits ; 24 ALUTs ; 0 ALUTs ; 24 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ;
+; 8:1 ; 9 bits ; 45 ALUTs ; 0 ALUTs ; 45 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ;
+; 10:1 ; 9 bits ; 54 ALUTs ; 18 ALUTs ; 36 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ;
+; 10:1 ; 12 bits ; 72 ALUTs ; 0 ALUTs ; 72 ALUTs ; Yes ; |usimplez_top|usimplez_cpu:cpu|acumulador[0] ;
++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------+
+
+
++---------------------------------------------------------------------------------------------+
+; Source assignments for usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated ;
++---------------------------------+--------------------+------+-------------------------------+
+; Assignment ; Value ; From ; To ;
++---------------------------------+--------------------+------+-------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
++---------------------------------+--------------------+------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: Top-level Entity: |usimplez_top ;
++----------------+-------+-----------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+-----------------------------------------------------+
+; WIDTH_WORD ; 12 ; Signed Integer ;
+; WIDTH_ADDRESS ; 9 ; Signed Integer ;
++----------------+-------+-----------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: usimplez_cpu:cpu ;
++----------------------+-------+--------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------------+-------+--------------------------------+
+; width_data_bus ; 12 ; Signed Integer ;
+; width_operation_code ; 3 ; Signed Integer ;
+; width_address ; 9 ; Signed Integer ;
+; st ; 000 ; Unsigned Binary ;
+; ld ; 001 ; Unsigned Binary ;
+; add ; 010 ; Unsigned Binary ;
+; br ; 011 ; Unsigned Binary ;
+; bz ; 100 ; Unsigned Binary ;
+; clr ; 101 ; Unsigned Binary ;
+; dec ; 110 ; Unsigned Binary ;
+; halt ; 111 ; Unsigned Binary ;
++----------------------+-------+--------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: usimplez_ram:ram ;
++----------------+-------+--------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------+
+; width_word ; 12 ; Signed Integer ;
+; width_address ; 9 ; Signed Integer ;
++----------------+-------+--------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++----------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: usimplez_ram:ram|altsyncram:ram_rtl_0 ;
++------------------------------------+----------------------+----------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------------------+----------------------+----------------------------+
+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+; WIDTH_BYTEENA ; 1 ; Untyped ;
+; OPERATION_MODE ; SINGLE_PORT ; Untyped ;
+; WIDTH_A ; 12 ; Untyped ;
+; WIDTHAD_A ; 9 ; Untyped ;
+; NUMWORDS_A ; 512 ; Untyped ;
+; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
+; ADDRESS_ACLR_A ; NONE ; Untyped ;
+; OUTDATA_ACLR_A ; NONE ; Untyped ;
+; WRCONTROL_ACLR_A ; NONE ; Untyped ;
+; INDATA_ACLR_A ; NONE ; Untyped ;
+; BYTEENA_ACLR_A ; NONE ; Untyped ;
+; WIDTH_B ; 1 ; Untyped ;
+; WIDTHAD_B ; 1 ; Untyped ;
+; NUMWORDS_B ; 1 ; Untyped ;
+; INDATA_REG_B ; CLOCK1 ; Untyped ;
+; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
+; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
+; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
+; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
+; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
+; INDATA_ACLR_B ; NONE ; Untyped ;
+; WRCONTROL_ACLR_B ; NONE ; Untyped ;
+; ADDRESS_ACLR_B ; NONE ; Untyped ;
+; OUTDATA_ACLR_B ; NONE ; Untyped ;
+; RDCONTROL_ACLR_B ; NONE ; Untyped ;
+; BYTEENA_ACLR_B ; NONE ; Untyped ;
+; WIDTH_BYTEENA_A ; 1 ; Untyped ;
+; WIDTH_BYTEENA_B ; 1 ; Untyped ;
+; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
+; BYTE_SIZE ; 8 ; Untyped ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; INIT_FILE ; fibonacci.mif ; Untyped ;
+; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
+; MAXIMUM_DEPTH ; 0 ; Untyped ;
+; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
+; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
+; ENABLE_ECC ; FALSE ; Untyped ;
+; DEVICE_FAMILY ; Stratix II ; Untyped ;
+; CBXI_PARAMETER ; altsyncram_im61 ; Untyped ;
++------------------------------------+----------------------+----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++-----------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance ;
++-------------------------------------------+---------------------------------------+
+; Name ; Value ;
++-------------------------------------------+---------------------------------------+
+; Number of entity instances ; 1 ;
+; Entity Instance ; usimplez_ram:ram|altsyncram:ram_rtl_0 ;
+; -- OPERATION_MODE ; SINGLE_PORT ;
+; -- WIDTH_A ; 12 ;
+; -- NUMWORDS_A ; 512 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 1 ;
+; -- NUMWORDS_B ; 1 ;
+; -- ADDRESS_REG_B ; CLOCK1 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
++-------------------------------------------+---------------------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+ Info: Processing started: Wed Nov 09 01:44:42 2011
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usimplez -c usimplez
+Info: Found 2 design units, including 1 entities, in source file usimplez_top.vhd
+ Info: Found design unit 1: usimplez_top-str
+ Info: Found entity 1: usimplez_top
+Info: Found 2 design units, including 1 entities, in source file usimplez_cpu.vhd
+ Info: Found design unit 1: usimplez_cpu-fsm
+ Info: Found entity 1: usimplez_cpu
+Info: Found 2 design units, including 1 entities, in source file usimplez_ram.vhd
+ Info: Found design unit 1: usimplez_ram-rtl
+ Info: Found entity 1: usimplez_ram
+Info: Elaborating entity "usimplez_top" for the top level hierarchy
+Info: Elaborating entity "usimplez_cpu" for hierarchy "usimplez_cpu:cpu"
+Info: Elaborating entity "usimplez_ram" for hierarchy "usimplez_ram:ram"
+Info: Inferred 1 megafunctions from design logic
+ Info: Inferred altsyncram megafunction from the following design logic: "usimplez_ram:ram|ram~22"
+ Info: Parameter OPERATION_MODE set to SINGLE_PORT
+ Info: Parameter WIDTH_A set to 12
+ Info: Parameter WIDTHAD_A set to 9
+ Info: Parameter NUMWORDS_A set to 512
+ Info: Parameter OUTDATA_REG_A set to UNREGISTERED
+ Info: Parameter ADDRESS_ACLR_A set to NONE
+ Info: Parameter OUTDATA_ACLR_A set to NONE
+ Info: Parameter INDATA_ACLR_A set to NONE
+ Info: Parameter WRCONTROL_ACLR_A set to NONE
+ Info: Parameter INIT_FILE set to fibonacci.mif
+Info: Elaborated megafunction instantiation "usimplez_ram:ram|altsyncram:ram_rtl_0"
+Info: Instantiated megafunction "usimplez_ram:ram|altsyncram:ram_rtl_0" with the following parameter:
+ Info: Parameter "OPERATION_MODE" = "SINGLE_PORT"
+ Info: Parameter "WIDTH_A" = "12"
+ Info: Parameter "WIDTHAD_A" = "9"
+ Info: Parameter "NUMWORDS_A" = "512"
+ Info: Parameter "OUTDATA_REG_A" = "UNREGISTERED"
+ Info: Parameter "ADDRESS_ACLR_A" = "NONE"
+ Info: Parameter "OUTDATA_ACLR_A" = "NONE"
+ Info: Parameter "INDATA_ACLR_A" = "NONE"
+ Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
+ Info: Parameter "INIT_FILE" = "fibonacci.mif"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_im61.tdf
+ Info: Found entity 1: altsyncram_im61
+Warning: Ignored assignments for entity "usimplez" -- entity does not exist in design
+ Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id "Root Region" was ignored
+ Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id "Root Region" was ignored
+Info: Implemented 94 device resources after synthesis - the final resource count might be different
+ Info: Implemented 2 input pins
+ Info: Implemented 5 output pins
+ Info: Implemented 75 logic cells
+ Info: Implemented 12 RAM segments
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
+ Info: Peak virtual memory: 195 megabytes
+ Info: Processing ended: Wed Nov 09 01:44:56 2011
+ Info: Elapsed time: 00:00:14
+ Info: Total CPU time (on all processors): 00:00:09
+
+
Index: QuartusII/adder.mif
===================================================================
--- QuartusII/adder.mif (nonexistent)
+++ QuartusII/adder.mif (revision 2)
@@ -0,0 +1,34 @@
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- Quartus II generated Memory Initialization File (.mif)
+
+WIDTH=12;
+DEPTH=512;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=BIN;
+
+CONTENT BEGIN
+ 0 : 011000000100;
+ 1 : 000000000110;
+ 2 : 000000001000;
+ 3 : 000000000000;
+ 4 : 001000000001;
+ 5 : 010000000010;
+ 6 : 000000000011;
+ 7 : 001000000011;
+ 8 : 111000000000;
+ [9..511] : 000000000000;
+END;
Index: QuartusII/usimplez_top.vwf
===================================================================
--- QuartusII/usimplez_top.vwf (nonexistent)
+++ QuartusII/usimplez_top.vwf (revision 2)
@@ -0,0 +1,1929 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+*/
+
+HEADER
+{
+ VERSION = 1;
+ TIME_UNIT = ns;
+ DATA_OFFSET = 0.0;
+ DATA_DURATION = 100000.0;
+ SIMULATION_TIME = 0.0;
+ GRID_PHASE = 0.0;
+ GRID_PERIOD = 10.0;
+ GRID_DUTY_CYCLE = 50;
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 12;
+ LSB_INDEX = 0;
+ DIRECTION = REGISTERED;
+ PARENT = "";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[11]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[10]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[9]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|acumulador[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|acumulador";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 9;
+ LSB_INDEX = 0;
+ DIRECTION = REGISTERED;
+ PARENT = "";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|addr_bus_o[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|addr_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 9;
+ LSB_INDEX = 0;
+ DIRECTION = REGISTERED;
+ PARENT = "";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cd_reg_s[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cd_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|co_reg_s")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 3;
+ LSB_INDEX = 0;
+ DIRECTION = REGISTERED;
+ PARENT = "";
+}
+
+SIGNAL("usimplez_cpu:cpu|co_reg_s[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|co_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|co_reg_s[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|co_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|co_reg_s[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|co_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 9;
+ LSB_INDEX = 0;
+ DIRECTION = REGISTERED;
+ PARENT = "";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|cp_reg_s[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|cp_reg_s";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = BUS;
+ WIDTH = 12;
+ LSB_INDEX = 0;
+ DIRECTION = REGISTERED;
+ PARENT = "";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[11]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[10]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[9]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[8]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[7]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[6]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[5]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[4]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[3]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[2]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[1]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("usimplez_cpu:cpu|data_bus_o[0]")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = REGISTERED;
+ PARENT = "usimplez_cpu:cpu|data_bus_o";
+}
+
+SIGNAL("clk_i")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("in0_o")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("in1_o")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("op0_o")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("op1_o")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+SIGNAL("rst_i")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = INPUT;
+ PARENT = "";
+}
+
+SIGNAL("we_o")
+{
+ VALUE_TYPE = NINE_LEVEL_BIT;
+ SIGNAL_TYPE = SINGLE_BIT;
+ WIDTH = 1;
+ LSB_INDEX = -1;
+ DIRECTION = OUTPUT;
+ PARENT = "";
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[11]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[10]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[9]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|acumulador[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|addr_bus_o[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cd_reg_s[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|co_reg_s[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|co_reg_s[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|co_reg_s[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|cp_reg_s[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[11]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[10]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[9]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[8]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[7]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[6]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[5]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[4]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[3]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[2]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[1]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("usimplez_cpu:cpu|data_bus_o[0]")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL U FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("clk_i")
+{
+ NODE
+ {
+ REPEAT = 1;
+ NODE
+ {
+ REPEAT = 2000;
+ LEVEL 0 FOR 25.0;
+ LEVEL 1 FOR 25.0;
+ }
+ }
+}
+
+TRANSITION_LIST("in0_o")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("in1_o")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("op0_o")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("op1_o")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 100000.0;
+ }
+}
+
+TRANSITION_LIST("rst_i")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL 0 FOR 4.0;
+ LEVEL 1 FOR 11.6;
+ LEVEL 0 FOR 99984.4;
+ }
+}
+
+TRANSITION_LIST("we_o")
+{
+ NODE
+ {
+ REPEAT = 1;
+ LEVEL X FOR 100000.0;
+ }
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "rst_i";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 0;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "clk_i";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 1;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "we_o";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 2;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "in0_o";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 3;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "in1_o";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 4;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "op0_o";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 5;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "op1_o";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 6;
+ TREE_LEVEL = 0;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 7;
+ TREE_LEVEL = 0;
+ CHILDREN = 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[11]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 8;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[10]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 9;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[9]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 10;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 11;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 12;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 13;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 14;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 15;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 16;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 17;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 18;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|acumulador[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 19;
+ TREE_LEVEL = 1;
+ PARENT = 7;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 20;
+ TREE_LEVEL = 0;
+ CHILDREN = 21, 22, 23, 24, 25, 26, 27, 28, 29;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 21;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 22;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 23;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 24;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 25;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 26;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 27;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 28;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|addr_bus_o[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 29;
+ TREE_LEVEL = 1;
+ PARENT = 20;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 30;
+ TREE_LEVEL = 0;
+ CHILDREN = 31, 32, 33, 34, 35, 36, 37, 38, 39;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 31;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 32;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 33;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 34;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 35;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 36;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 37;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 38;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cd_reg_s[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 39;
+ TREE_LEVEL = 1;
+ PARENT = 30;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|co_reg_s";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 40;
+ TREE_LEVEL = 0;
+ CHILDREN = 41, 42, 43;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|co_reg_s[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 41;
+ TREE_LEVEL = 1;
+ PARENT = 40;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|co_reg_s[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 42;
+ TREE_LEVEL = 1;
+ PARENT = 40;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|co_reg_s[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 43;
+ TREE_LEVEL = 1;
+ PARENT = 40;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 44;
+ TREE_LEVEL = 0;
+ CHILDREN = 45, 46, 47, 48, 49, 50, 51, 52, 53;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 45;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 46;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 47;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 48;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 49;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 50;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 51;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 52;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|cp_reg_s[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 53;
+ TREE_LEVEL = 1;
+ PARENT = 44;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 54;
+ TREE_LEVEL = 0;
+ CHILDREN = 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[11]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 55;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[10]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 56;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[9]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 57;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[8]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 58;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[7]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 59;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[6]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 60;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[5]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 61;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[4]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 62;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[3]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 63;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[2]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 64;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[1]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 65;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+DISPLAY_LINE
+{
+ CHANNEL = "usimplez_cpu:cpu|data_bus_o[0]";
+ EXPAND_STATUS = COLLAPSED;
+ RADIX = Unsigned;
+ TREE_INDEX = 66;
+ TREE_LEVEL = 1;
+ PARENT = 54;
+}
+
+TIME_BAR
+{
+ TIME = 9575;
+ MASTER = TRUE;
+}
+;
Index: QuartusII/fibonacci.txt
===================================================================
--- QuartusII/fibonacci.txt (nonexistent)
+++ QuartusII/fibonacci.txt (revision 2)
@@ -0,0 +1,16 @@
+0 br 5 011000000101
+1 0 000000000000 n-2
+2 1 000000000001 n-1
+3 0 000000000000 n
+4 st i 000001100101 i, (val_ini = 100);
+5 ld 4 001000000100
+6 dec 110000000000 ( i=i-1;
+7 st 4 000000000100 )
+8 ld 1 001000000001
+9 add 2 010000000010
+10 st 3 000000000011
+11 ld 2 001000000010
+12 st 1 000000000001
+13 ld 3 001000000011
+14 st 2 000000000010
+15 br 4 011000000100
\ No newline at end of file
Index: QuartusII/usimplez.done
===================================================================
--- QuartusII/usimplez.done (nonexistent)
+++ QuartusII/usimplez.done (revision 2)
@@ -0,0 +1 @@
+Wed Nov 09 01:53:41 2011
Index: QuartusII/usimplez.fit.rpt
===================================================================
--- QuartusII/usimplez.fit.rpt (nonexistent)
+++ QuartusII/usimplez.fit.rpt (revision 2)
@@ -0,0 +1,1385 @@
+Fitter report for usimplez
+Wed Nov 09 01:46:25 2011
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Fitter Summary
+ 3. Fitter Settings
+ 4. I/O Assignment Warnings
+ 5. Incremental Compilation Preservation Summary
+ 6. Incremental Compilation Partition Settings
+ 7. Incremental Compilation Placement Preservation
+ 8. Pin-Out File
+ 9. Fitter Resource Usage Summary
+ 10. Input Pins
+ 11. Output Pins
+ 12. I/O Bank Usage
+ 13. All Package Pins
+ 14. Output Pin Default Load For Reported TCO
+ 15. Fitter Resource Utilization by Entity
+ 16. Delay Chain Summary
+ 17. Pad To Core Delay Chain Fanout
+ 18. Control Signals
+ 19. Global & Other Fast Signals
+ 20. Non-Global High Fan-Out Signals
+ 21. Fitter RAM Summary
+ 22. Interconnect Usage Summary
+ 23. LAB Logic Elements
+ 24. LAB-wide Signals
+ 25. LAB Signals Sourced
+ 26. LAB Signals Sourced Out
+ 27. LAB Distinct Inputs
+ 28. I/O Rules Summary
+ 29. I/O Rules Details
+ 30. I/O Rules Matrix
+ 31. Fitter Device Options
+ 32. Operating Settings and Conditions
+ 33. Estimated Delay Added for Hold Timing
+ 34. Fitter Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------------+
+; Fitter Summary ;
++-------------------------------+----------------------------------------------+
+; Fitter Status ; Successful - Wed Nov 09 01:46:25 2011 ;
+; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
+; Revision Name ; usimplez ;
+; Top-level Entity Name ; usimplez_top ;
+; Family ; Stratix II ;
+; Device ; EP2S15F484C3 ;
+; Timing Models ; Final ;
+; Logic utilization ; < 1 % ;
+; Combinational ALUTs ; 48 / 12,480 ( < 1 % ) ;
+; Dedicated logic registers ; 63 / 12,480 ( < 1 % ) ;
+; Total registers ; 63 ;
+; Total pins ; 7 / 343 ( 2 % ) ;
+; Total virtual pins ; 0 ;
+; Total block memory bits ; 6,144 / 419,328 ( 1 % ) ;
+; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
+; Total PLLs ; 0 / 6 ( 0 % ) ;
+; Total DLLs ; 0 / 2 ( 0 % ) ;
++-------------------------------+----------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Settings ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+; Device ; AUTO ; ;
+; Fit Attempts to Skip ; 0 ; 0.0 ;
+; Use smart compilation ; Off ; Off ;
+; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
+; Enable compact report table ; Off ; Off ;
+; Use TimeQuest Timing Analyzer ; Off ; Off ;
+; Router Timing Optimization Level ; Normal ; Normal ;
+; Placement Effort Multiplier ; 1.0 ; 1.0 ;
+; Router Effort Multiplier ; 1.0 ; 1.0 ;
+; Always Enable Input Buffers ; Off ; Off ;
+; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
+; Optimize Multi-Corner Timing ; Off ; Off ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; Optimize Timing ; Normal compilation ; Normal compilation ;
+; Optimize Timing for ECOs ; Off ; Off ;
+; Regenerate full fit report during ECO compiles ; Off ; Off ;
+; Optimize IOC Register Placement for Timing ; On ; On ;
+; Limit to One Fitting Attempt ; Off ; Off ;
+; Final Placement Optimizations ; Automatically ; Automatically ;
+; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
+; Fitter Initial Placement Seed ; 1 ; 1 ;
+; PCI I/O ; Off ; Off ;
+; Weak Pull-Up Resistor ; Off ; Off ;
+; Enable Bus-Hold Circuitry ; Off ; Off ;
+; Auto Global Memory Control Signals ; Off ; Off ;
+; Auto Packed Registers ; Auto ; Auto ;
+; Auto Delay Chains ; On ; On ;
+; Auto Merge PLLs ; On ; On ;
+; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
+; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
+; Perform Register Duplication for Performance ; Off ; Off ;
+; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
+; Perform Register Retiming for Performance ; Off ; Off ;
+; Perform Asynchronous Signal Pipelining ; Off ; Off ;
+; Fitter Effort ; Auto Fit ; Auto Fit ;
+; Physical Synthesis Effort Level ; Normal ; Normal ;
+; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
+; Auto Register Duplication ; Auto ; Auto ;
+; Auto Global Clock ; On ; On ;
+; Auto Global Register Control Signals ; On ; On ;
+; Stop After Congestion Map Generation ; Off ; Off ;
+; Save Intermediate Fitting Results ; Off ; Off ;
+; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+; Use Best Effort Settings for Compilation ; Off ; Off ;
++----------------------------------------------------------------------------+--------------------------------+--------------------------------+
+
+
++------------------------------------------+
+; I/O Assignment Warnings ;
++----------+-------------------------------+
+; Pin Name ; Reason ;
++----------+-------------------------------+
+; we_o ; Incomplete set of assignments ;
+; in0_o ; Incomplete set of assignments ;
+; in1_o ; Incomplete set of assignments ;
+; op0_o ; Incomplete set of assignments ;
+; op1_o ; Incomplete set of assignments ;
+; clk_i ; Incomplete set of assignments ;
+; rst_i ; Incomplete set of assignments ;
++----------+-------------------------------+
+
+
++----------------------------------------------+
+; Incremental Compilation Preservation Summary ;
++-------------------------+--------------------+
+; Type ; Value ;
++-------------------------+--------------------+
+; Placement ; ;
+; -- Requested ; 0 / 133 ( 0.00 % ) ;
+; -- Achieved ; 0 / 133 ( 0.00 % ) ;
+; ; ;
+; Routing (by Connection) ; ;
+; -- Requested ; 0 / 0 ( 0.00 % ) ;
+; -- Achieved ; 0 / 0 ( 0.00 % ) ;
++-------------------------+--------------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------+
+; Incremental Compilation Partition Settings ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
+
+
++--------------------------------------------------------------------------------------------+
+; Incremental Compilation Placement Preservation ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
++----------------+---------+-------------------+-------------------------+-------------------+
+; Top ; 133 ; 0 ; N/A ; Source File ;
++----------------+---------+-------------------+-------------------------+-------------------+
+
+
++--------------+
+; Pin-Out File ;
++--------------+
+The pin-out file can be found in C:/Altera/qdesigns/usimplez/usimplez.pin.
+
+
++-------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++-----------------------------------------------------------------------------------+-------------------------+
+; Resource ; Usage ;
++-----------------------------------------------------------------------------------+-------------------------+
+; Combinational ALUTs ; 48 / 12,480 ( < 1 % ) ;
+; Dedicated logic registers ; 63 / 12,480 ( < 1 % ) ;
+; ; ;
+; Combinational ALUT usage by number of inputs ; ;
+; -- 7 input functions ; 1 ;
+; -- 6 input functions ; 6 ;
+; -- 5 input functions ; 4 ;
+; -- 4 input functions ; 0 ;
+; -- <=3 input functions ; 37 ;
+; ; ;
+; Combinational ALUTs by mode ; ;
+; -- normal mode ; 26 ;
+; -- extended LUT mode ; 1 ;
+; -- arithmetic mode ; 21 ;
+; -- shared arithmetic mode ; 0 ;
+; ; ;
+; Logic utilization ; 81 / 12,480 ( < 1 % ) ;
+; -- Difficulty Clustering Design ; Low ;
+; -- Combinational ALUT/register pairs used in final Placement ; 72 ;
+; -- Combinational with no register ; 9 ;
+; -- Register only ; 24 ;
+; -- Combinational with a register ; 39 ;
+; -- Estimated pairs recoverable by pairing ALUTs and registers as design grows ; -1 ;
+; -- Estimated Combinational ALUT/register pairs unavailable ; 10 ;
+; -- Unavailable due to unpartnered 7 LUTs ; 1 ;
+; -- Unavailable due to unpartnered 6 LUTs ; 2 ;
+; -- Unavailable due to unpartnered 5 LUTs ; 0 ;
+; -- Unavailable due to LAB-wide signal conflicts ; 5 ;
+; -- Unavailable due to LAB input limits ; 0 ;
+; -- Unavailable due to location constrained logic ; 2 ;
+; ; ;
+; Total registers* ; 63 / 14,410 ( < 1 % ) ;
+; -- Dedicated logic registers ; 63 / 12,480 ( < 1 % ) ;
+; -- I/O registers ; 0 / 1,930 ( 0 % ) ;
+; ; ;
+; ALMs: partially or completely used ; 40 / 6,240 ( < 1 % ) ;
+; ; ;
+; Total LABs: partially or completely used ; 7 / 780 ( < 1 % ) ;
+; ; ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 7 / 343 ( 2 % ) ;
+; -- Clock pins ; 3 / 16 ( 19 % ) ;
+; Global signals ; 1 ;
+; M512s ; 0 / 104 ( 0 % ) ;
+; M4Ks ; 2 / 78 ( 3 % ) ;
+; Total block memory bits ; 6,144 / 419,328 ( 1 % ) ;
+; Total block memory implementation bits ; 9,216 / 419,328 ( 2 % ) ;
+; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
+; PLLs ; 0 / 6 ( 0 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; Regional clocks ; 0 / 32 ( 0 % ) ;
+; SERDES transmitters ; 0 / 38 ( 0 % ) ;
+; SERDES receivers ; 0 / 42 ( 0 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Remote update blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
+; Peak interconnect usage (total/H/V) ; 1% / 1% / 1% ;
+; Maximum fan-out node ; clk_i~clkctrl ;
+; Maximum fan-out ; 65 ;
+; Highest non-global fan-out signal ; rst_i ;
+; Highest non-global fan-out ; 49 ;
+; Total fan-out ; 506 ;
+; Average fan-out ; 3.67 ;
++-----------------------------------------------------------------------------------+-------------------------+
+* Register count does not include registers inside block RAM or DSP blocks.
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Input Pins ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+; clk_i ; N20 ; 1 ; 0 ; 10 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
+; rst_i ; W12 ; 8 ; 17 ; 0 ; 0 ; 49 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;
++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++-------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++-------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+; in0_o ; V2 ; 6 ; 40 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ;
+; in1_o ; C12 ; 4 ; 22 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
+; op0_o ; D14 ; 3 ; 10 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
+; op1_o ; A10 ; 9 ; 25 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
+; we_o ; B13 ; 3 ; 18 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ;
++-------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+
+
+
++----------------------------------------------------------+
+; I/O Bank Usage ;
++----------+----------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+----------------+---------------+--------------+
+; 1 ; 1 / 40 ( 3 % ) ; 3.3V ; -- ;
+; 2 ; 0 / 44 ( 0 % ) ; 3.3V ; -- ;
+; 3 ; 3 / 50 ( 6 % ) ; 3.3V ; -- ;
+; 4 ; 1 / 35 ( 3 % ) ; 3.3V ; -- ;
+; 5 ; 0 / 44 ( 0 % ) ; 3.3V ; -- ;
+; 6 ; 1 / 40 ( 3 % ) ; 3.3V ; -- ;
+; 7 ; 0 / 34 ( 0 % ) ; 3.3V ; -- ;
+; 8 ; 1 / 43 ( 2 % ) ; 3.3V ; -- ;
+; 9 ; 1 / 6 ( 17 % ) ; 3.3V ; -- ;
+; 10 ; 0 / 6 ( 0 % ) ; 3.3V ; -- ;
++----------+----------------+---------------+--------------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A2 ; ; ; TEMPDIODEp ; ; ; ; -- ; ; -- ; -- ;
+; A3 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A4 ; 277 ; 4 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
+; A5 ; 307 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A6 ; 311 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A7 ; 315 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A8 ; 318 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A10 ; 323 ; 9 ; op1_o ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; A11 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A13 ; 329 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; A15 ; 343 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A16 ; 347 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A17 ; 351 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A18 ; 350 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A19 ; 375 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; A20 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; A21 ; 383 ; 3 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
+; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA3 ; 191 ; 7 ; ^nCEO ; ; ; ; -- ; ; -- ; -- ;
+; AA4 ; 181 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA5 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA6 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA7 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA8 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA9 ; 144 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA10 ; 147 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA11 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA12 ; 138 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA13 ; 137 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA14 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ;
+; AA15 ; 127 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA16 ; 123 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA17 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA18 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AA19 ; 85 ; 8 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; AA20 ; 86 ; 8 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AA22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB2 ; 190 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; ; -- ; -- ;
+; AB3 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB5 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB6 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB7 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB8 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB10 ; 145 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB11 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB13 ; 139 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; AB15 ; 125 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB16 ; 124 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB17 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB18 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; AB19 ; 87 ; 8 ; #TRST ; input ; ; ; -- ; ; -- ; -- ;
+; AB20 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; AB21 ; 84 ; 8 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B3 ; 276 ; 4 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; B4 ; 279 ; 4 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
+; B5 ; 305 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B6 ; 309 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B7 ; 313 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B8 ; 317 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B9 ; 320 ; 9 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B10 ; 321 ; 9 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B11 ; 327 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B12 ; 328 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B13 ; 331 ; 3 ; we_o ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; B14 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ;
+; B15 ; 341 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B16 ; 345 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B17 ; 349 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B18 ; 353 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B19 ; 377 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; B20 ; 381 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
+; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; B22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; C1 ; 275 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; C2 ; 273 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; C3 ; ; ; TEMPDIODEn ; ; ; ; -- ; ; -- ; -- ;
+; C4 ; 285 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C5 ; 306 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C6 ; 308 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C7 ; 316 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C8 ; 314 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C9 ; 319 ; 9 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C10 ; 324 ; 9 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C11 ; 325 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C12 ; 326 ; 4 ; in1_o ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; C13 ; 330 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C14 ; 354 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C15 ; 342 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C16 ; 344 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C17 ; 352 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C18 ; 355 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C19 ; 369 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; C20 ; 384 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
+; C21 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; C22 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; D1 ; 271 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; D2 ; 269 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; D3 ; 287 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D4 ; 278 ; 4 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
+; D5 ; 283 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D6 ; 293 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D7 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ;
+; D8 ; 297 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D9 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ;
+; D10 ; 322 ; 9 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D11 ; 337 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D12 ; 333 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D13 ; 332 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D14 ; 356 ; 3 ; op0_o ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; D15 ; 361 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D16 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ;
+; D17 ; 373 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D18 ; 379 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D19 ; 382 ; 3 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;
+; D20 ; 371 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; D21 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; D22 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E1 ; 267 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E2 ; 265 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E3 ; 274 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E4 ; 272 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E5 ; 280 ; 4 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
+; E6 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E7 ; 289 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E8 ; 298 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E9 ; 301 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E10 ; 312 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E11 ; 335 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E12 ; 339 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E13 ; 338 ; 3 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; E14 ; 357 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E15 ; 365 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E16 ; 374 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E17 ; 376 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E18 ; 380 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; E19 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E20 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E21 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; E22 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F1 ; 263 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F2 ; 261 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F3 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ;
+; F4 ; 270 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F5 ; 268 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F6 ; 288 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F7 ; 296 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F8 ; 294 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F9 ; 300 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F10 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F11 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ;
+; F12 ; ; ; VCCA_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; F13 ; 346 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F14 ; 358 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F15 ; 367 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F16 ; 362 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F17 ; 378 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; F18 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ;
+; F19 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F20 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F21 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; F22 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G1 ; 255 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G2 ; 253 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G3 ; 262 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G4 ; 260 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G5 ; 266 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G6 ; 264 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G7 ; 286 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G8 ; 291 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G9 ; 302 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G10 ; ; 9 ; VCC_PLL5_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; G11 ; ; ; VCCD_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; G12 ; 336 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G13 ; 348 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G14 ; 359 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G15 ; 366 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G16 ; 370 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; G17 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G18 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G19 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G20 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G21 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; G22 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H1 ; 251 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H2 ; 249 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H3 ; 259 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H4 ; 257 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H5 ; 254 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H6 ; 252 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H7 ; 284 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; H9 ; 304 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H10 ; ; 4 ; VCCPD4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; H11 ; 334 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H12 ; 340 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H13 ; ; 3 ; VCCPD3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; H14 ; 360 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; H16 ; 368 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; H17 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H18 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H19 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H20 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H21 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; H22 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J2 ; 247 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J3 ; 245 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J4 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ;
+; J5 ; 250 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J6 ; 248 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J7 ; 258 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J8 ; 256 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; J15 ; 364 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; J16 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J17 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J18 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J19 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J20 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J21 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; J22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K1 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K2 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K3 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K4 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K5 ; 246 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K6 ; 244 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K7 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K8 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; K14 ; ; 2 ; VCCPD2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; K15 ; 35 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K16 ; 33 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K17 ; 31 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K18 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K19 ; 34 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K20 ; 32 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K21 ; 38 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; K22 ; 36 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; L2 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L3 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L4 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; L5 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;
+; L6 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L7 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L8 ; 236 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L9 ; ; 5 ; VCCPD5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; L15 ; 39 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L16 ; 37 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L17 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; L18 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;
+; L19 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ;
+; L20 ; 40 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L21 ; 42 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; L22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; M1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; M2 ; 232 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; M3 ; 234 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; M4 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M6 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; M16 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M17 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M18 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M19 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; M20 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; M21 ; 43 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; M22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; N1 ; 231 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; N2 ; 229 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; N3 ; 230 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; N4 ; 228 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; N5 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; N6 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;
+; N7 ; 226 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; N8 ; 224 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; N9 ; ; 6 ; VCCPD6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; N15 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; N16 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; N17 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; N18 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;
+; N19 ; 47 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
+; N20 ; 45 ; 1 ; clk_i ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; N21 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; N22 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P2 ; 227 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P3 ; 225 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P4 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ;
+; P5 ; 222 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P6 ; 220 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P7 ; 218 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P8 ; 216 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P10 ; ; 7 ; VCCPD7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; P11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; P15 ; ; 1 ; VCCPD1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; P16 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P17 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P18 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P19 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P20 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P21 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; P22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R1 ; 223 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R2 ; 221 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R3 ; 215 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R4 ; 213 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R5 ; 214 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R6 ; 212 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R7 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R8 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R9 ; 168 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; R10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
+; R11 ; ; 10 ; VCC_PLL6_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; R12 ; ; ; VCCA_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; R13 ; ; 8 ; VCCPD8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; R14 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; R15 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; R16 ; 83 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R17 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R18 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R19 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ;
+; R21 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; R22 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T1 ; 219 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T2 ; 217 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T3 ; 207 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T4 ; 205 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T5 ; 210 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T6 ; 208 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T7 ; 186 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T8 ; 172 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T9 ; 170 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T10 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T11 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ;
+; T12 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ;
+; T13 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T14 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T15 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T16 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; T17 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T18 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T19 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T20 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T21 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; T22 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U1 ; 211 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U2 ; 209 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U3 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ;
+; U4 ; 206 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U5 ; 204 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U6 ; 179 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U7 ; 180 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U8 ; 173 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U9 ; 171 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U10 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U11 ; ; ; VCCD_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
+; U12 ; 130 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U13 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U14 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U15 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U16 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; U17 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U18 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U19 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U20 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U21 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; U22 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V1 ; 203 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V2 ; 201 ; 6 ; in0_o ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
+; V3 ; 198 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V4 ; 196 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V5 ; 188 ; 7 ; ^PORSEL ; ; ; ; -- ; ; -- ; -- ;
+; V6 ; 185 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V7 ; 175 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V8 ; 166 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V9 ; 149 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V10 ; 165 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V11 ; 132 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V12 ; 134 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V13 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V14 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V15 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V16 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; V17 ; 90 ; 8 ; ^VCCSEL ; ; ; ; -- ; ; -- ; -- ;
+; V18 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V19 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ;
+; V21 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; V22 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W1 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W2 ; 197 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W3 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W4 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W5 ; 182 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W6 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;
+; W7 ; 177 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W8 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;
+; W9 ; 148 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W10 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W11 ; 133 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W12 ; 135 ; 8 ; rst_i ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
+; W13 ; 128 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W14 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W15 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W16 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W17 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; W18 ; 88 ; 8 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
+; W19 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W20 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W21 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; W22 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; Y1 ; 195 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; Y2 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; Y3 ; 184 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y4 ; 189 ; 7 ; PLL_ENA ; ; ; ; -- ; ; -- ; -- ;
+; Y5 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y6 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y7 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y8 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y9 ; 146 ; 10 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y10 ; 140 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y11 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y12 ; 136 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y13 ; 131 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y14 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y15 ; 126 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y16 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y17 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y18 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y19 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ;
+; Y20 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; Y21 ; 82 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; Y22 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
+Note: Pin directions (input, output or bidir) are based on device operating in user mode.
+
+
++-------------------------------------------------------------------------------+
+; Output Pin Default Load For Reported TCO ;
++----------------------------------+-------+------------------------------------+
+; I/O Standard ; Load ; Termination Resistance ;
++----------------------------------+-------+------------------------------------+
+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;
+; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;
+; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;
+; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;
+; LVDS ; 0 pF ; 100 Ohm (Differential) ;
+; HyperTransport ; 0 pF ; 100 Ohm (Differential) ;
+; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;
+; 3.3-V LVTTL ; 0 pF ; Not Available ;
+; 3.3-V LVCMOS ; 0 pF ; Not Available ;
+; 2.5 V ; 0 pF ; Not Available ;
+; 1.8 V ; 0 pF ; Not Available ;
+; 1.5 V ; 0 pF ; Not Available ;
+; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;
+; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;
+; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;
+; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;
+; 1.2-V HSTL ; 0 pF ; Not Available ;
+; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;
+; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;
+; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;
+; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;
+; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;
+; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;
+; Differential 1.2-V HSTL ; 0 pF ; Not Available ;
++----------------------------------+-------+------------------------------------+
+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++-------------------------------------------+---------------------+---------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Combinational ALUTs ; ALMs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Combinational with no register ; Register-Only ; Combinational with a register ; Full Hierarchy Name ; Library Name ;
+; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ALUT/register pair ; ALUT/register pair ; ALUT/register pair ; ; ;
++-------------------------------------------+---------------------+---------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+------------------------------------------------------------------------------------+--------------+
+; |usimplez_top ; 48 (0) ; 40 (0) ; 63 (0) ; 0 (0) ; 6144 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 9 (0) ; 24 (0) ; 39 (0) ; |usimplez_top ; work ;
+; |usimplez_cpu:cpu| ; 48 (48) ; 40 (40) ; 63 (63) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 (9) ; 24 (24) ; 39 (39) ; |usimplez_top|usimplez_cpu:cpu ; ;
+; |usimplez_ram:ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |usimplez_top|usimplez_ram:ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_im61:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 6144 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated ; ;
++-------------------------------------------+---------------------+---------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+------------------------------------------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++-------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; DQS bus ; NDQS bus ; DQS output ;
++-------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+
+; we_o ; Output ; -- ; -- ; -- ; -- ; (0) 52 ps ; -- ; -- ; -- ;
+; in0_o ; Output ; -- ; -- ; -- ; -- ; (0) 52 ps ; -- ; -- ; -- ;
+; in1_o ; Output ; -- ; -- ; -- ; -- ; (0) 52 ps ; -- ; -- ; -- ;
+; op0_o ; Output ; -- ; -- ; -- ; -- ; (0) 52 ps ; -- ; -- ; -- ;
+; op1_o ; Output ; -- ; -- ; -- ; -- ; (0) 52 ps ; -- ; -- ; -- ;
+; clk_i ; Input ; (0) 206 ps ; (0) 206 ps ; -- ; -- ; -- ; -- ; -- ; -- ;
+; rst_i ; Input ; (7) 2996 ps ; (7) 2996 ps ; -- ; -- ; -- ; -- ; -- ; -- ;
++-------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+
+
+
++-----------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++-----------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++-----------------------------------------+-------------------+---------+
+; clk_i ; ; ;
+; rst_i ; ; ;
+; - usimplez_cpu:cpu|co_reg_s[2] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[3] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[7] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[1] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[8] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|co_reg_s[1] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|co_reg_s[0] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[5] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[6] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[2] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[0] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cd_reg_s[4] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[4] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[5] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[6] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[7] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[8] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[9] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[10] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[11] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[2] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[0] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[1] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[3] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|In0_o ; 0 ; 7 ;
+; - usimplez_cpu:cpu|In1_o ; 0 ; 7 ;
+; - usimplez_cpu:cpu|Op0_o ; 0 ; 7 ;
+; - usimplez_cpu:cpu|Op1_o ; 0 ; 7 ;
+; - usimplez_cpu:cpu|we_o ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[0] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[1] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[2] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[3] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[4] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[5] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[6] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[7] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[8] ; 0 ; 7 ;
+; - usimplez_cpu:cpu|estado~6 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|estado~7 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|estado~8 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|co_reg_s[2]~1 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|estado~9 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|data_bus_o[4]~0 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|addr_bus_o[5]~5 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|acumulador[0]~0 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|acumulador[0]~2 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cp_reg_s[6]~2 ; 0 ; 7 ;
+; - usimplez_cpu:cpu|cp_reg_s[6]~3 ; 0 ; 7 ;
++-----------------------------------------+-------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++----------------------------------+--------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++----------------------------------+--------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
+; clk_i ; PIN_N20 ; 65 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;
+; rst_i ; PIN_W12 ; 49 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|acumulador[0]~0 ; LCCOMB_X19_Y12_N12 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|acumulador[0]~1 ; LCCOMB_X19_Y12_N26 ; 12 ; Sync. load ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|acumulador[0]~2 ; LCCOMB_X19_Y12_N30 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|addr_bus_o[5]~5 ; LCCOMB_X19_Y12_N6 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|co_reg_s[2]~1 ; LCCOMB_X6_Y2_N6 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|cp_reg_s[6]~2 ; LCCOMB_X21_Y15_N20 ; 9 ; Sync. clear ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|cp_reg_s[6]~3 ; LCCOMB_X19_Y12_N14 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|data_bus_o[4]~0 ; LCCOMB_X19_Y12_N20 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|estado.In1 ; LCFF_X6_Y2_N25 ; 31 ; Sync. load ; no ; -- ; -- ; -- ;
+; usimplez_cpu:cpu|we_o ; LCFF_X21_Y15_N1 ; 4 ; Write enable ; no ; -- ; -- ; -- ;
++----------------------------------+--------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+
+
+
++--------------------------------------------------------------------------------------------------+
+; Global & Other Fast Signals ;
++-------+----------+---------+----------------------+------------------+---------------------------+
+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
++-------+----------+---------+----------------------+------------------+---------------------------+
+; clk_i ; PIN_N20 ; 65 ; Global Clock ; GCLK3 ; -- ;
++-------+----------+---------+----------------------+------------------+---------------------------+
+
+
++----------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++------------------------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++------------------------------------------------------------------------------------+---------+
+; rst_i ; 49 ;
+; usimplez_cpu:cpu|estado.In1 ; 31 ;
+; usimplez_cpu:cpu|acumulador[0]~2 ; 12 ;
+; usimplez_cpu:cpu|acumulador[0]~1 ; 12 ;
+; usimplez_cpu:cpu|acumulador[0]~0 ; 12 ;
+; usimplez_cpu:cpu|data_bus_o[4]~0 ; 12 ;
+; usimplez_cpu:cpu|co_reg_s[2]~1 ; 12 ;
+; usimplez_cpu:cpu|cp_reg_s[6]~3 ; 9 ;
+; usimplez_cpu:cpu|cp_reg_s[6]~2 ; 9 ;
+; usimplez_cpu:cpu|addr_bus_o[5]~5 ; 9 ;
+; usimplez_cpu:cpu|addr_bus_o[5]~3 ; 9 ;
+; usimplez_cpu:cpu|estado.Op0 ; 9 ;
+; usimplez_cpu:cpu|co_reg_s[2] ; 9 ;
+; usimplez_cpu:cpu|co_reg_s[1] ; 9 ;
+; usimplez_cpu:cpu|co_reg_s[0] ; 7 ;
+; usimplez_cpu:cpu|estado.In0 ; 5 ;
+; usimplez_cpu:cpu|we_o ; 4 ;
+; usimplez_cpu:cpu|addr_bus_o[5]~0 ; 3 ;
+; usimplez_cpu:cpu|estado.Op1 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a2 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a4 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a5 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a6 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a7 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a8 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a9 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a10 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a11 ; 3 ;
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; 3 ;
+; usimplez_cpu:cpu|acumulador[7] ; 3 ;
+; usimplez_cpu:cpu|acumulador[6] ; 3 ;
+; usimplez_cpu:cpu|acumulador[8] ; 3 ;
+; usimplez_cpu:cpu|acumulador[9] ; 3 ;
+; usimplez_cpu:cpu|acumulador[11] ; 3 ;
+; usimplez_cpu:cpu|acumulador[1] ; 3 ;
+; usimplez_cpu:cpu|acumulador[0] ; 3 ;
+; usimplez_cpu:cpu|acumulador[2] ; 3 ;
+; usimplez_cpu:cpu|acumulador[3] ; 3 ;
+; usimplez_cpu:cpu|acumulador[4] ; 3 ;
+; usimplez_cpu:cpu|acumulador[5] ; 3 ;
+; usimplez_cpu:cpu|acumulador[10] ; 3 ;
+; usimplez_cpu:cpu|cp_reg_s[8] ; 2 ;
+; usimplez_cpu:cpu|cd_reg_s[8] ; 2 ;
+; usimplez_cpu:cpu|cp_reg_s[7] ; 2 ;
+; usimplez_cpu:cpu|cd_reg_s[7] ; 2 ;
+; usimplez_cpu:cpu|cp_reg_s[6] ; 2 ;
+; usimplez_cpu:cpu|cd_reg_s[6] ; 2 ;
+; usimplez_cpu:cpu|cp_reg_s[5] ; 2 ;
++------------------------------------------------------------------------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary ;
++---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+---------------+--------------------------+
+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M512s ; M4Ks ; M-RAMs ; MIF ; Location ;
++---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+---------------+--------------------------+
+; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 512 ; 12 ; -- ; -- ; yes ; no ; -- ; -- ; 6144 ; 512 ; 12 ; -- ; -- ; 6144 ; 0 ; 2 ; 0 ; fibonacci.mif ; M4K_X20_Y13, M4K_X20_Y15 ;
++---------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+---------------+--------------------------+
+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+
+
++--------------------------------------------------------------------+
+; Interconnect Usage Summary ;
++-------------------------------------------+------------------------+
+; Interconnect Resource Type ; Usage ;
++-------------------------------------------+------------------------+
+; Block interconnects ; 140 / 51,960 ( < 1 % ) ;
+; C16 interconnects ; 19 / 1,680 ( 1 % ) ;
+; C4 interconnects ; 153 / 38,400 ( < 1 % ) ;
+; DPA clocks ; 0 / 4 ( 0 % ) ;
+; DQS bus muxes ; 0 / 18 ( 0 % ) ;
+; DQS-18 I/O buses ; 0 / 4 ( 0 % ) ;
+; DQS-4 I/O buses ; 0 / 18 ( 0 % ) ;
+; DQS-9 I/O buses ; 0 / 8 ( 0 % ) ;
+; Differential I/O clocks ; 0 / 32 ( 0 % ) ;
+; Direct links ; 2 / 51,960 ( < 1 % ) ;
+; Global clocks ; 1 / 16 ( 6 % ) ;
+; Local interconnects ; 18 / 12,480 ( < 1 % ) ;
+; NDQS bus muxes ; 0 / 18 ( 0 % ) ;
+; NDQS-18 I/O buses ; 0 / 4 ( 0 % ) ;
+; NDQS-4 I/O buses ; 0 / 18 ( 0 % ) ;
+; NDQS-9 I/O buses ; 0 / 8 ( 0 % ) ;
+; PLL transmitter or receiver load enables ; 0 / 8 ( 0 % ) ;
+; PLL transmitter or receiver synch. clocks ; 0 / 8 ( 0 % ) ;
+; R24 interconnects ; 10 / 1,664 ( < 1 % ) ;
+; R24/C16 interconnect drivers ; 28 / 4,160 ( < 1 % ) ;
+; R4 interconnects ; 193 / 59,488 ( < 1 % ) ;
+; Regional clocks ; 0 / 32 ( 0 % ) ;
++-------------------------------------------+------------------------+
+
+
++----------------------------------------------------------------+
+; LAB Logic Elements ;
++----------------------------------+-----------------------------+
+; Number of ALMs (Average = 5.71) ; Number of LABs (Total = 7) ;
++----------------------------------+-----------------------------+
+; 1 ; 1 ;
+; 2 ; 1 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 1 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 4 ;
++----------------------------------+-----------------------------+
+
+
++------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+-----------------------------+
+; LAB-wide Signals (Average = 3.00) ; Number of LABs (Total = 7) ;
++------------------------------------+-----------------------------+
+; 1 Clock ; 7 ;
+; 1 Clock enable ; 6 ;
+; 1 Sync. clear ; 4 ;
+; 1 Sync. load ; 3 ;
+; 2 Clock enables ; 1 ;
++------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-----------------------------+
+; Number of Signals Sourced (Average = 15.14) ; Number of LABs (Total = 7) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 0 ;
+; 19 ; 0 ;
+; 20 ; 0 ;
+; 21 ; 0 ;
+; 22 ; 1 ;
+; 23 ; 0 ;
+; 24 ; 0 ;
+; 25 ; 1 ;
+; 26 ; 0 ;
+; 27 ; 0 ;
+; 28 ; 0 ;
+; 29 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++--------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++--------------------------------------------------+-----------------------------+
+; Number of Signals Sourced Out (Average = 10.57) ; Number of LABs (Total = 7) ;
++--------------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 1 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 1 ;
+; 14 ; 1 ;
+; 15 ; 1 ;
+; 16 ; 0 ;
+; 17 ; 0 ;
+; 18 ; 1 ;
++--------------------------------------------------+-----------------------------+
+
+
++----------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-----------------------------+
+; Number of Distinct Inputs (Average = 14.43) ; Number of LABs (Total = 7) ;
++----------------------------------------------+-----------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 0 ;
+; 4 ; 1 ;
+; 5 ; 0 ;
+; 6 ; 1 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 0 ;
+; 10 ; 0 ;
+; 11 ; 0 ;
+; 12 ; 0 ;
+; 13 ; 1 ;
+; 14 ; 1 ;
+; 15 ; 0 ;
+; 16 ; 0 ;
+; 17 ; 1 ;
+; 18 ; 0 ;
+; 19 ; 0 ;
+; 20 ; 0 ;
+; 21 ; 0 ;
+; 22 ; 0 ;
+; 23 ; 1 ;
+; 24 ; 1 ;
++----------------------------------------------+-----------------------------+
+
+
++------------------------------------------+
+; I/O Rules Summary ;
++----------------------------------+-------+
+; I/O Rules Statistic ; Total ;
++----------------------------------+-------+
+; Total I/O Rules ; 31 ;
+; Number of I/O Rules Passed ; 4 ;
+; Number of I/O Rules Failed ; 0 ;
+; Number of I/O Rules Unchecked ; 0 ;
+; Number of I/O Rules Inapplicable ; 27 ;
++----------------------------------+-------+
+
+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Details ;
++--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
++--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
+; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
+; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
+; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
+; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
+; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
+; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
+; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;
+; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
+; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;
+; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
+; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
+; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
+; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
+; Inapplicable ; IO_000032 ; I/O Properties Checks for Multiple I/Os ; I/O registers and SERDES should not be used at the same XY location. ; Critical ; No I/O Registers or Differential I/O Standard assignments found. ; I/O ; ;
+; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
+; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 1 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
+; Inapplicable ; IO_000037 ; SI Related Distance Checks ; Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
+; Inapplicable ; IO_000038 ; SI Related SSO Limit Checks ; Single-ended outputs and High-speed LVDS should not coexist in an I/O bank. ; High ; No High-speed LVDS found. ; I/O ; ;
+; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
+; Inapplicable ; IO_000040 ; SI Related SSO Limit Checks ; The total drive strength of single ended outputs in a DPA bank should not exceed 120mA. ; High ; No DPA found. ; I/O ; ;
++--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; I/O Rules Matrix ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
+; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000032 ; IO_000033 ; IO_000034 ; IO_000037 ; IO_000038 ; IO_000042 ; IO_000040 ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
+; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; Total Inapplicable ; 7 ; 7 ; 7 ; 7 ; 7 ; 0 ; 7 ; 7 ; 0 ; 0 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 7 ; 0 ; 7 ; 7 ; 7 ; 7 ; 7 ;
+; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; we_o ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in0_o ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; in1_o ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; op0_o ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; op1_o ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; clk_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
+; rst_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;
++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+
+
+
++-------------------------------------------------------------------------+
+; Fitter Device Options ;
++----------------------------------------------+--------------------------+
+; Option ; Setting ;
++----------------------------------------------+--------------------------+
+; Enable user-supplied start-up clock (CLKUSR) ; Off ;
+; Enable device-wide reset (DEV_CLRn) ; Off ;
+; Enable device-wide output enable (DEV_OE) ; Off ;
+; Enable INIT_DONE output ; Off ;
+; Configuration scheme ; Passive Serial ;
+; Error detection CRC ; Off ;
+; Configuration Voltage Level ; Auto ;
+; Force Configuration Voltage Level ; Off ;
+; nWS, nRS, nCS, CS ; Unreserved ;
+; RDYnBUSY ; Unreserved ;
+; Data[7..1] ; Unreserved ;
+; Data[0] ; As input tri-stated ;
+; ASDO,nCSO ; Unreserved ;
+; Reserve all unused pins ; As output driving ground ;
+; Base pin-out file on sameframe device ; Off ;
++----------------------------------------------+--------------------------+
+
+
++------------------------------------+
+; Operating Settings and Conditions ;
++---------------------------+--------+
+; Setting ; Value ;
++---------------------------+--------+
+; Nominal Core Voltage ; 1.20 V ;
+; Low Junction Temperature ; 0 °C ;
+; High Junction Temperature ; 85 °C ;
++---------------------------+--------+
+
+
++------------------------------------------------------------+
+; Estimated Delay Added for Hold Timing ;
++-----------------+----------------------+-------------------+
+; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
++-----------------+----------------------+-------------------+
+
+
++-----------------+
+; Fitter Messages ;
++-----------------+
+Info: *******************************************************************
+Info: Running Quartus II Fitter
+ Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+ Info: Processing started: Wed Nov 09 01:45:59 2011
+Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off usimplez -c usimplez
+Warning: Ignored assignments for entity "usimplez" -- entity does not exist in design
+ Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id "Root Region" was ignored
+ Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id "Root Region" was ignored
+Info: Automatically selected device EP2S15F484C3 for design usimplez
+Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature.
+Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
+Info: Fitter converted 1 user pins into dedicated programming pins
+ Info: Pin ~DATA0~ is reserved at location E13
+Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning: No exact pin location assignment(s) for 7 pins of 7 total pins
+ Info: Pin we_o not assigned to an exact location on the device
+ Info: Pin in0_o not assigned to an exact location on the device
+ Info: Pin in1_o not assigned to an exact location on the device
+ Info: Pin op0_o not assigned to an exact location on the device
+ Info: Pin op1_o not assigned to an exact location on the device
+ Info: Pin clk_i not assigned to an exact location on the device
+ Info: Pin rst_i not assigned to an exact location on the device
+Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info: Timing-driven compilation is using the Classic Timing Analyzer
+Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
+Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))
+ Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
+Info: Starting register packing
+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density
+Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks
+Info: Finished register packing
+ Extra Info: No registers were packed into other blocks
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 6 (unused VREF, 3.3V VCCIO, 1 input, 5 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVTTL.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available
+ Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available
+ Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available
+ Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available
+ Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available
+ Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available
+ Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
+ Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available
+Info: Fitter preparation operations ending: elapsed time is 00:00:02
+Info: Fitter placement preparation operations beginning
+Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
+Info: Fitter placement operations beginning
+Info: Fitter placement was successful
+Info: Fitter placement operations ending: elapsed time is 00:00:01
+Info: Estimated most critical path is register to register delay of 5.247 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X19_Y12; Fanout = 5; REG Node = 'usimplez_cpu:cpu|estado.In0'
+ Info: 2: + IC(1.729 ns) + CELL(0.378 ns) = 2.107 ns; Loc. = LAB_X6_Y2; Fanout = 12; COMB Node = 'usimplez_cpu:cpu|co_reg_s[2]~1'
+ Info: 3: + IC(2.394 ns) + CELL(0.746 ns) = 5.247 ns; Loc. = LAB_X21_Y15; Fanout = 2; REG Node = 'usimplez_cpu:cpu|cd_reg_s[5]'
+ Info: Total cell delay = 1.124 ns ( 21.42 % )
+ Info: Total interconnect delay = 4.123 ns ( 78.58 % )
+Info: Fitter routing operations beginning
+Info: Average interconnect usage is 0% of the available device resources
+ Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13
+Info: Fitter routing operations ending: elapsed time is 00:00:01
+Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
+ Info: Optimizations that may affect the design's routability were skipped
+ Info: Optimizations that may affect the design's timing were skipped
+Info: Started post-fitting delay annotation
+Warning: Found 5 output pins without output pin load capacitance assignment
+ Info: Pin "we_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "in0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "in1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "op0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "op1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
+Info: Quartus II Fitter was successful. 0 errors, 8 warnings
+ Info: Peak virtual memory: 236 megabytes
+ Info: Processing ended: Wed Nov 09 01:46:26 2011
+ Info: Elapsed time: 00:00:27
+ Info: Total CPU time (on all processors): 00:00:23
+
+
Index: QuartusII/usimplez.tan.rpt
===================================================================
--- QuartusII/usimplez.tan.rpt (nonexistent)
+++ QuartusII/usimplez.tan.rpt (revision 2)
@@ -0,0 +1,560 @@
+Classic Timing Analyzer report for usimplez
+Wed Nov 09 01:53:40 2011
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Timing Analyzer Summary
+ 3. Timing Analyzer Settings
+ 4. Clock Settings Summary
+ 5. Clock Setup: 'clk_i'
+ 6. tsu
+ 7. tco
+ 8. th
+ 9. Timing Analyzer Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Summary ;
++------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+--------------+
+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
++------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+--------------+
+; Worst-case tsu ; N/A ; None ; 5.847 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[8] ; -- ; clk_i ; 0 ;
+; Worst-case tco ; N/A ; None ; 7.162 ns ; usimplez_cpu:cpu|Op0_o ; op0_o ; clk_i ; -- ; 0 ;
+; Worst-case th ; N/A ; None ; -2.805 ns ; rst_i ; usimplez_cpu:cpu|estado.In1 ; -- ; clk_i ; 0 ;
+; Clock Setup: 'clk_i' ; N/A ; None ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; 0 ;
+; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
++------------------------------+-------+---------------+----------------------------------+------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+--------------+
+
+
++-----------------------------------------------------------------------------------------------------------------------------------------------------+
+; Timing Analyzer Settings ;
++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
+; Option ; Setting ; From ; To ; Entity Name ;
++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
+; Device Name ; EP2S15F484C3 ; ; ; ;
+; Timing Models ; Final ; ; ; ;
+; Default hold multicycle ; Same as Multicycle ; ; ; ;
+; Cut paths between unrelated clock domains ; On ; ; ; ;
+; Cut off read during write signal paths ; On ; ; ; ;
+; Cut off feedback from I/O pins ; On ; ; ; ;
+; Report Combined Fast/Slow Timing ; Off ; ; ; ;
+; Ignore Clock Settings ; Off ; ; ; ;
+; Analyze latches as synchronous elements ; On ; ; ; ;
+; Enable Recovery/Removal analysis ; Off ; ; ; ;
+; Enable Clock Latency ; Off ; ; ; ;
+; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+; Number of source nodes to report per destination node ; 10 ; ; ; ;
+; Number of destination nodes to report ; 10 ; ; ; ;
+; Number of paths to report ; 200 ; ; ; ;
+; Report Minimum Timing Checks ; Off ; ; ; ;
+; Use Fast Timing Models ; Off ; ; ; ;
+; Report IO Paths Separately ; Off ; ; ; ;
+; Perform Multicorner Analysis ; On ; ; ; ;
+; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+; Reports worst-case timing paths for each clock domain and analysis ; Off ; ; ; ;
+; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ;
+; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+; Output I/O Timing Endpoint ; Near End ; ; ; ;
++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Settings Summary ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+; clk_i ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Clock Setup: 'clk_i' ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 130.28 MHz ( period = 7.676 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.761 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 131.48 MHz ( period = 7.606 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.726 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 132.70 MHz ( period = 7.536 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.691 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 133.94 MHz ( period = 7.466 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.656 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 138.54 MHz ( period = 7.218 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.532 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 139.90 MHz ( period = 7.148 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.497 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 141.28 MHz ( period = 7.078 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.462 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 142.69 MHz ( period = 7.008 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[4] ; clk_i ; clk_i ; None ; None ; 3.427 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.13 MHz ( period = 6.938 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[3] ; clk_i ; clk_i ; None ; None ; 3.392 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 144.34 MHz ( period = 6.928 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[11] ; clk_i ; clk_i ; None ; None ; 3.380 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.60 MHz ( period = 6.868 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[2] ; clk_i ; clk_i ; None ; None ; 3.357 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 145.82 MHz ( period = 6.858 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[10] ; clk_i ; clk_i ; None ; None ; 3.345 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 147.32 MHz ( period = 6.788 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[9] ; clk_i ; clk_i ; None ; None ; 3.310 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.63 MHz ( period = 6.728 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[1] ; clk_i ; clk_i ; None ; None ; 3.287 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 148.85 MHz ( period = 6.718 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[8] ; clk_i ; clk_i ; None ; None ; 3.275 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 149.70 MHz ( period = 6.680 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ; clk_i ; None ; None ; 3.249 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.56 MHz ( period = 6.470 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[7] ; clk_i ; clk_i ; None ; None ; 3.151 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 154.70 MHz ( period = 6.464 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[0] ; clk_i ; clk_i ; None ; None ; 3.155 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 156.25 MHz ( period = 6.400 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[6] ; clk_i ; clk_i ; None ; None ; 3.116 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_we_reg ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg0 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg1 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg2 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg3 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg4 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg5 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg6 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg7 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; N/A ; 157.98 MHz ( period = 6.330 ns ) ; usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3~porta_address_reg8 ; usimplez_cpu:cpu|acumulador[5] ; clk_i ; clk_i ; None ; None ; 3.081 ns ;
+; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------+---------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; tsu ;
++-------+--------------+------------+-------+---------------------------------+----------+
+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
++-------+--------------+------------+-------+---------------------------------+----------+
+; N/A ; None ; 5.847 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[5] ; clk_i ;
+; N/A ; None ; 5.847 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[6] ; clk_i ;
+; N/A ; None ; 5.847 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[7] ; clk_i ;
+; N/A ; None ; 5.847 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[8] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[2] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[1] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[2] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ;
+; N/A ; None ; 5.836 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[0] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[1] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[2] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[3] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[4] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[5] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[6] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[7] ; clk_i ;
+; N/A ; None ; 5.751 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[0] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[1] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[2] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[3] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[4] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[5] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[6] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[7] ; clk_i ;
+; N/A ; None ; 5.151 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[8] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[3] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[4] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[5] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[6] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[7] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[8] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[9] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[10] ; clk_i ;
+; N/A ; None ; 4.900 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[11] ; clk_i ;
+; N/A ; None ; 4.882 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[0] ; clk_i ;
+; N/A ; None ; 4.882 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[1] ; clk_i ;
+; N/A ; None ; 4.882 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[3] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[4] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[5] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[6] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[7] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[8] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[9] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[10] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[11] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[1] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[2] ; clk_i ;
+; N/A ; None ; 4.658 ns ; rst_i ; usimplez_cpu:cpu|acumulador[0] ; clk_i ;
+; N/A ; None ; 3.991 ns ; rst_i ; usimplez_cpu:cpu|In1_o ; clk_i ;
+; N/A ; None ; 3.991 ns ; rst_i ; usimplez_cpu:cpu|Op1_o ; clk_i ;
+; N/A ; None ; 3.722 ns ; rst_i ; usimplez_cpu:cpu|we_o ; clk_i ;
+; N/A ; None ; 3.567 ns ; rst_i ; usimplez_cpu:cpu|In0_o ; clk_i ;
+; N/A ; None ; 3.567 ns ; rst_i ; usimplez_cpu:cpu|Op0_o ; clk_i ;
+; N/A ; None ; 3.441 ns ; rst_i ; usimplez_cpu:cpu|estado.Op1 ; clk_i ;
+; N/A ; None ; 3.327 ns ; rst_i ; usimplez_cpu:cpu|estado.In0 ; clk_i ;
+; N/A ; None ; 3.232 ns ; rst_i ; usimplez_cpu:cpu|estado.Op0 ; clk_i ;
+; N/A ; None ; 3.044 ns ; rst_i ; usimplez_cpu:cpu|estado.In1 ; clk_i ;
++-------+--------------+------------+-------+---------------------------------+----------+
+
+
++---------------------------------------------------------------------------------+
+; tco ;
++-------+--------------+------------+------------------------+-------+------------+
+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
++-------+--------------+------------+------------------------+-------+------------+
+; N/A ; None ; 7.162 ns ; usimplez_cpu:cpu|Op0_o ; op0_o ; clk_i ;
+; N/A ; None ; 6.363 ns ; usimplez_cpu:cpu|In0_o ; in0_o ; clk_i ;
+; N/A ; None ; 5.545 ns ; usimplez_cpu:cpu|we_o ; we_o ; clk_i ;
+; N/A ; None ; 5.283 ns ; usimplez_cpu:cpu|Op1_o ; op1_o ; clk_i ;
+; N/A ; None ; 5.116 ns ; usimplez_cpu:cpu|In1_o ; in1_o ; clk_i ;
++-------+--------------+------------+------------------------+-------+------------+
+
+
++----------------------------------------------------------------------------------------------+
+; th ;
++---------------+-------------+-----------+-------+---------------------------------+----------+
+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
++---------------+-------------+-----------+-------+---------------------------------+----------+
+; N/A ; None ; -2.805 ns ; rst_i ; usimplez_cpu:cpu|estado.In1 ; clk_i ;
+; N/A ; None ; -2.993 ns ; rst_i ; usimplez_cpu:cpu|estado.Op0 ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[0] ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[1] ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|co_reg_s[2] ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[0] ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[1] ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[2] ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[3] ; clk_i ;
+; N/A ; None ; -3.008 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[4] ; clk_i ;
+; N/A ; None ; -3.088 ns ; rst_i ; usimplez_cpu:cpu|estado.In0 ; clk_i ;
+; N/A ; None ; -3.202 ns ; rst_i ; usimplez_cpu:cpu|estado.Op1 ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[0] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[1] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[2] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[3] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[4] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[5] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[6] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[7] ; clk_i ;
+; N/A ; None ; -3.227 ns ; rst_i ; usimplez_cpu:cpu|addr_bus_o[8] ; clk_i ;
+; N/A ; None ; -3.280 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[0] ; clk_i ;
+; N/A ; None ; -3.280 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[1] ; clk_i ;
+; N/A ; None ; -3.280 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[2] ; clk_i ;
+; N/A ; None ; -3.328 ns ; rst_i ; usimplez_cpu:cpu|In0_o ; clk_i ;
+; N/A ; None ; -3.328 ns ; rst_i ; usimplez_cpu:cpu|Op0_o ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|we_o ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[3] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[4] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[5] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[6] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[7] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[8] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[9] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[10] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|data_bus_o[11] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[5] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[6] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[7] ; clk_i ;
+; N/A ; None ; -3.483 ns ; rst_i ; usimplez_cpu:cpu|cd_reg_s[8] ; clk_i ;
+; N/A ; None ; -3.752 ns ; rst_i ; usimplez_cpu:cpu|In1_o ; clk_i ;
+; N/A ; None ; -3.752 ns ; rst_i ; usimplez_cpu:cpu|Op1_o ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[3] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[4] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[5] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[6] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[7] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[8] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[9] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[10] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[11] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[1] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[2] ; clk_i ;
+; N/A ; None ; -4.255 ns ; rst_i ; usimplez_cpu:cpu|acumulador[0] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[0] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[1] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[2] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[3] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[4] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[5] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[6] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[7] ; clk_i ;
+; N/A ; None ; -4.890 ns ; rst_i ; usimplez_cpu:cpu|cp_reg_s[8] ; clk_i ;
++---------------+-------------+-----------+-------+---------------------------------+----------+
+
+
++--------------------------+
+; Timing Analyzer Messages ;
++--------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Classic Timing Analyzer
+ Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+ Info: Processing started: Wed Nov 09 01:53:37 2011
+Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off usimplez -c usimplez
+Warning: Ignored assignments for entity "usimplez" -- entity does not exist in design
+ Warning: Assignment for entity set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id "Root Region" was ignored
+ Warning: Assignment for entity set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id "Root Region" was ignored
+Info: Started post-fitting delay annotation
+Warning: Found 5 output pins without output pin load capacitance assignment
+ Info: Pin "we_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "in0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "in1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "op0_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+ Info: Pin "op1_o" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
+Info: Delay annotation completed successfully
+Warning: Found pins functioning as undefined clocks and/or memory enables
+ Info: Assuming node "clk_i" is an undefined clock
+Info: Clock "clk_i" has Internal fmax of 130.28 MHz between source memory "usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg" and destination register "usimplez_cpu:cpu|acumulador[11]" (period= 7.676 ns)
+ Info: + Longest memory to register delay is 3.761 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X20_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg'
+ Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X20_Y15; Fanout = 4; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1'
+ Info: 3: + IC(0.849 ns) + CELL(0.436 ns) = 3.135 ns; Loc. = LCCOMB_X21_Y13_N2; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~7'
+ Info: 4: + IC(0.000 ns) + CELL(0.035 ns) = 3.170 ns; Loc. = LCCOMB_X21_Y13_N4; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~11'
+ Info: 5: + IC(0.000 ns) + CELL(0.035 ns) = 3.205 ns; Loc. = LCCOMB_X21_Y13_N6; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~15'
+ Info: 6: + IC(0.000 ns) + CELL(0.035 ns) = 3.240 ns; Loc. = LCCOMB_X21_Y13_N8; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~19'
+ Info: 7: + IC(0.000 ns) + CELL(0.035 ns) = 3.275 ns; Loc. = LCCOMB_X21_Y13_N10; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~23'
+ Info: 8: + IC(0.000 ns) + CELL(0.035 ns) = 3.310 ns; Loc. = LCCOMB_X21_Y13_N12; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~27'
+ Info: 9: + IC(0.000 ns) + CELL(0.124 ns) = 3.434 ns; Loc. = LCCOMB_X21_Y13_N14; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~31'
+ Info: 10: + IC(0.000 ns) + CELL(0.035 ns) = 3.469 ns; Loc. = LCCOMB_X21_Y13_N16; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~35'
+ Info: 11: + IC(0.000 ns) + CELL(0.035 ns) = 3.504 ns; Loc. = LCCOMB_X21_Y13_N18; Fanout = 2; COMB Node = 'usimplez_cpu:cpu|Add2~39'
+ Info: 12: + IC(0.000 ns) + CELL(0.035 ns) = 3.539 ns; Loc. = LCCOMB_X21_Y13_N20; Fanout = 1; COMB Node = 'usimplez_cpu:cpu|Add2~43'
+ Info: 13: + IC(0.000 ns) + CELL(0.125 ns) = 3.664 ns; Loc. = LCCOMB_X21_Y13_N22; Fanout = 1; COMB Node = 'usimplez_cpu:cpu|Add2~46'
+ Info: 14: + IC(0.000 ns) + CELL(0.097 ns) = 3.761 ns; Loc. = LCFF_X21_Y13_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu|acumulador[11]'
+ Info: Total cell delay = 2.912 ns ( 77.43 % )
+ Info: Total interconnect delay = 0.849 ns ( 22.57 % )
+ Info: - Smallest clock skew is 0.149 ns
+ Info: + Shortest clock path from clock "clk_i" to destination register is 2.483 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
+ Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
+ Info: 3: + IC(0.668 ns) + CELL(0.618 ns) = 2.483 ns; Loc. = LCFF_X21_Y13_N23; Fanout = 3; REG Node = 'usimplez_cpu:cpu|acumulador[11]'
+ Info: Total cell delay = 1.472 ns ( 59.28 % )
+ Info: Total interconnect delay = 1.011 ns ( 40.72 % )
+ Info: - Longest clock path from clock "clk_i" to source memory is 2.334 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
+ Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
+ Info: 3: + IC(0.656 ns) + CELL(0.481 ns) = 2.334 ns; Loc. = M4K_X20_Y15; Fanout = 3; MEM Node = 'usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0~porta_we_reg'
+ Info: Total cell delay = 1.335 ns ( 57.20 % )
+ Info: Total interconnect delay = 0.999 ns ( 42.80 % )
+ Info: + Micro clock to output delay of source is 0.136 ns
+ Info: + Micro setup delay of destination is 0.090 ns
+ Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
+Info: tsu for register "usimplez_cpu:cpu|cd_reg_s[5]" (data pin = "rst_i", clock pin = "clk_i") is 5.847 ns
+ Info: + Longest pin to register delay is 8.233 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_W12; Fanout = 49; PIN Node = 'rst_i'
+ Info: 2: + IC(4.472 ns) + CELL(0.366 ns) = 5.665 ns; Loc. = LCCOMB_X6_Y2_N6; Fanout = 12; COMB Node = 'usimplez_cpu:cpu|co_reg_s[2]~1'
+ Info: 3: + IC(1.822 ns) + CELL(0.746 ns) = 8.233 ns; Loc. = LCFF_X21_Y15_N29; Fanout = 2; REG Node = 'usimplez_cpu:cpu|cd_reg_s[5]'
+ Info: Total cell delay = 1.939 ns ( 23.55 % )
+ Info: Total interconnect delay = 6.294 ns ( 76.45 % )
+ Info: + Micro setup delay of destination is 0.090 ns
+ Info: - Shortest clock path from clock "clk_i" to destination register is 2.476 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
+ Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
+ Info: 3: + IC(0.661 ns) + CELL(0.618 ns) = 2.476 ns; Loc. = LCFF_X21_Y15_N29; Fanout = 2; REG Node = 'usimplez_cpu:cpu|cd_reg_s[5]'
+ Info: Total cell delay = 1.472 ns ( 59.45 % )
+ Info: Total interconnect delay = 1.004 ns ( 40.55 % )
+Info: tco from clock "clk_i" to destination pin "op0_o" through register "usimplez_cpu:cpu|Op0_o" is 7.162 ns
+ Info: + Longest clock path from clock "clk_i" to source register is 2.490 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
+ Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
+ Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X6_Y2_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu|Op0_o'
+ Info: Total cell delay = 1.472 ns ( 59.12 % )
+ Info: Total interconnect delay = 1.018 ns ( 40.88 % )
+ Info: + Micro clock to output delay of source is 0.094 ns
+ Info: + Longest register to pin delay is 4.578 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X6_Y2_N1; Fanout = 1; REG Node = 'usimplez_cpu:cpu|Op0_o'
+ Info: 2: + IC(2.616 ns) + CELL(1.962 ns) = 4.578 ns; Loc. = PIN_D14; Fanout = 0; PIN Node = 'op0_o'
+ Info: Total cell delay = 1.962 ns ( 42.86 % )
+ Info: Total interconnect delay = 2.616 ns ( 57.14 % )
+Info: th for register "usimplez_cpu:cpu|estado.In1" (data pin = "rst_i", clock pin = "clk_i") is -2.805 ns
+ Info: + Longest clock path from clock "clk_i" to destination register is 2.490 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'
+ Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 107; COMB Node = 'clk_i~clkctrl'
+ Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X6_Y2_N25; Fanout = 42; REG Node = 'usimplez_cpu:cpu|estado.In1'
+ Info: Total cell delay = 1.472 ns ( 59.12 % )
+ Info: Total interconnect delay = 1.018 ns ( 40.88 % )
+ Info: + Micro hold delay of destination is 0.149 ns
+ Info: - Shortest pin to register delay is 5.444 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.827 ns) = 0.827 ns; Loc. = PIN_W12; Fanout = 49; PIN Node = 'rst_i'
+ Info: 2: + IC(4.409 ns) + CELL(0.053 ns) = 5.289 ns; Loc. = LCCOMB_X6_Y2_N24; Fanout = 1; COMB Node = 'usimplez_cpu:cpu|estado~7'
+ Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 5.444 ns; Loc. = LCFF_X6_Y2_N25; Fanout = 42; REG Node = 'usimplez_cpu:cpu|estado.In1'
+ Info: Total cell delay = 1.035 ns ( 19.01 % )
+ Info: Total interconnect delay = 4.409 ns ( 80.99 % )
+Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 5 warnings
+ Info: Peak virtual memory: 155 megabytes
+ Info: Processing ended: Wed Nov 09 01:53:41 2011
+ Info: Elapsed time: 00:00:04
+ Info: Total CPU time (on all processors): 00:00:04
+
+
Index: QuartusII/usimplez.qpf
===================================================================
--- QuartusII/usimplez.qpf (nonexistent)
+++ QuartusII/usimplez.qpf (revision 2)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 01:39:00 November 09, 2011
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "9.1"
+DATE = "01:39:00 November 09, 2011"
+
+# Revisions
+
+PROJECT_REVISION = "usimplez"
Index: QuartusII/adder.txt
===================================================================
--- QuartusII/adder.txt (nonexistent)
+++ QuartusII/adder.txt (revision 2)
@@ -0,0 +1,9 @@
+0 br 4 011000000100
+1 6 000000000110
+2 8 000000001000
+3 0 000000000000
+4 ld 1 001000000001
+5 add 2 010000000010
+6 st 3 000000000011
+7 ld 3 001000000011
+8 halt 111000000000
\ No newline at end of file
Index: QuartusII/usimplez.pin
===================================================================
--- QuartusII/usimplez.pin (nonexistent)
+++ QuartusII/usimplez.pin (revision 2)
@@ -0,0 +1,559 @@
+ -- Copyright (C) 1991-2010 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- Bank 9: 3.3V
+ -- Bank 10: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND*
+ -- either individually through a 10k Ohm resistor to GND or tie all pins
+ -- together and connect through a single 10k Ohm resistor to GND.
+ -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+CHIP "usimplez" ASSIGNED TO AN: EP2S15F484C3
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A1 : gnd : : : :
+TEMPDIODEp : A2 : : : : :
+VCCIO4 : A3 : power : : 3.3V : 4 :
+MSEL3 : A4 : : : : 4 :
+GND* : A5 : : : : 4 :
+GND* : A6 : : : : 4 :
+GND* : A7 : : : : 4 :
+GND* : A8 : : : : 4 :
+GND : A9 : gnd : : : :
+op1_o : A10 : output : 3.3-V LVTTL : : 9 : N
+VCCIO4 : A11 : power : : 3.3V : 4 :
+VCCIO3 : A12 : power : : 3.3V : 3 :
+GND* : A13 : : : : 3 :
+GND : A14 : gnd : : : :
+GND* : A15 : : : : 3 :
+GND* : A16 : : : : 3 :
+GND* : A17 : : : : 3 :
+GND* : A18 : : : : 3 :
+GND* : A19 : : : : 3 :
+VCCIO3 : A20 : power : : 3.3V : 3 :
+nCE : A21 : : : : 3 :
+GND : A22 : gnd : : : :
+VCCIO6 : AA1 : power : : 3.3V : 6 :
+GND : AA2 : gnd : : : :
+nCEO : AA3 : : : : 7 :
+GND* : AA4 : : : : 7 :
+GND* : AA5 : : : : 7 :
+GND* : AA6 : : : : 7 :
+GND* : AA7 : : : : 7 :
+GND* : AA8 : : : : 7 :
+GND* : AA9 : : : : 10 :
+GND* : AA10 : : : : 10 :
+GND* : AA11 : : : : 7 :
+GND* : AA12 : : : : 8 :
+GND* : AA13 : : : : 8 :
+VREFB8 : AA14 : power : : : 8 :
+GND* : AA15 : : : : 8 :
+GND* : AA16 : : : : 8 :
+GND* : AA17 : : : : 8 :
+GND* : AA18 : : : : 8 :
+TCK : AA19 : input : : : 8 :
+TMS : AA20 : input : : : 8 :
+GND : AA21 : gnd : : : :
+VCCIO1 : AA22 : power : : 3.3V : 1 :
+GND : AB1 : gnd : : : :
+nIO_PULLUP : AB2 : : : : 7 :
+VCCIO7 : AB3 : power : : 3.3V : 7 :
+GND : AB4 : gnd : : : :
+GND* : AB5 : : : : 7 :
+GND* : AB6 : : : : 7 :
+GND* : AB7 : : : : 7 :
+GND* : AB8 : : : : 7 :
+GND : AB9 : gnd : : : :
+GND* : AB10 : : : : 10 :
+VCCIO7 : AB11 : power : : 3.3V : 7 :
+VCCIO8 : AB12 : power : : 3.3V : 8 :
+GND* : AB13 : : : : 8 :
+GND : AB14 : gnd : : : :
+GND* : AB15 : : : : 8 :
+GND* : AB16 : : : : 8 :
+GND* : AB17 : : : : 8 :
+GND* : AB18 : : : : 8 :
+TRST : AB19 : input : : : 8 :
+VCCIO8 : AB20 : power : : 3.3V : 8 :
+TDI : AB21 : input : : : 8 :
+GND : AB22 : gnd : : : :
+VCCIO5 : B1 : power : : 3.3V : 5 :
+GND : B2 : gnd : : : :
+TDO : B3 : output : : : 4 :
+MSEL2 : B4 : : : : 4 :
+GND* : B5 : : : : 4 :
+GND* : B6 : : : : 4 :
+GND* : B7 : : : : 4 :
+GND* : B8 : : : : 4 :
+GND* : B9 : : : : 9 :
+GND* : B10 : : : : 9 :
+GND* : B11 : : : : 4 :
+GND* : B12 : : : : 4 :
+we_o : B13 : output : 3.3-V LVTTL : : 3 : N
+VREFB3 : B14 : power : : : 3 :
+GND* : B15 : : : : 3 :
+GND* : B16 : : : : 3 :
+GND* : B17 : : : : 3 :
+GND* : B18 : : : : 3 :
+GND* : B19 : : : : 3 :
+nSTATUS : B20 : : : : 3 :
+GND : B21 : gnd : : : :
+VCCIO2 : B22 : power : : 3.3V : 2 :
+GND* : C1 : : : : 5 :
+GND* : C2 : : : : 5 :
+TEMPDIODEn : C3 : : : : :
+GND* : C4 : : : : 4 :
+GND* : C5 : : : : 4 :
+GND* : C6 : : : : 4 :
+GND* : C7 : : : : 4 :
+GND* : C8 : : : : 4 :
+GND* : C9 : : : : 9 :
+GND* : C10 : : : : 9 :
+GND* : C11 : : : : 4 :
+in1_o : C12 : output : 3.3-V LVTTL : : 4 : N
+GND* : C13 : : : : 3 :
+GND* : C14 : : : : 3 :
+GND* : C15 : : : : 3 :
+GND* : C16 : : : : 3 :
+GND* : C17 : : : : 3 :
+GND* : C18 : : : : 3 :
+GND* : C19 : : : : 3 :
+CONF_DONE : C20 : : : : 3 :
+GND* : C21 : : : : 2 :
+GND* : C22 : : : : 2 :
+GND* : D1 : : : : 5 :
+GND* : D2 : : : : 5 :
+GND* : D3 : : : : 4 :
+MSEL1 : D4 : : : : 4 :
+GND* : D5 : : : : 4 :
+GND* : D6 : : : : 4 :
+VREFB4 : D7 : power : : : 4 :
+GND* : D8 : : : : 4 :
+VREFB4 : D9 : power : : : 4 :
+GND* : D10 : : : : 9 :
+GND* : D11 : : : : 3 :
+GND* : D12 : : : : 3 :
+GND* : D13 : : : : 3 :
+op0_o : D14 : output : 3.3-V LVTTL : : 3 : N
+GND* : D15 : : : : 3 :
+VREFB3 : D16 : power : : : 3 :
+GND* : D17 : : : : 3 :
+GND* : D18 : : : : 3 :
+DCLK : D19 : : : : 3 :
+GND* : D20 : : : : 3 :
+GND* : D21 : : : : 2 :
+GND* : D22 : : : : 2 :
+GND* : E1 : : : : 5 :
+GND* : E2 : : : : 5 :
+GND* : E3 : : : : 5 :
+GND* : E4 : : : : 5 :
+MSEL0 : E5 : : : : 4 :
+GND* : E6 : : : : 4 :
+GND* : E7 : : : : 4 :
+GND* : E8 : : : : 4 :
+GND* : E9 : : : : 4 :
+GND* : E10 : : : : 4 :
+GND* : E11 : : : : 3 :
+GND* : E12 : : : : 3 :
+~DATA0~ / RESERVED_INPUT : E13 : input : 3.3-V LVTTL : : 3 : N
+GND* : E14 : : : : 3 :
+GND* : E15 : : : : 3 :
+GND* : E16 : : : : 3 :
+GND* : E17 : : : : 3 :
+GND* : E18 : : : : 3 :
+GND* : E19 : : : : 2 :
+GND* : E20 : : : : 2 :
+GND* : E21 : : : : 2 :
+GND* : E22 : : : : 2 :
+GND* : F1 : : : : 5 :
+GND* : F2 : : : : 5 :
+VREFB5 : F3 : power : : : 5 :
+GND* : F4 : : : : 5 :
+GND* : F5 : : : : 5 :
+GND* : F6 : : : : 4 :
+GND* : F7 : : : : 4 :
+GND* : F8 : : : : 4 :
+GND* : F9 : : : : 4 :
+GNDA_PLL5 : F10 : gnd : : : :
+GNDA_PLL5 : F11 : gnd : : : :
+VCCA_PLL5 : F12 : power : : 1.2V : :
+GND* : F13 : : : : 3 :
+GND* : F14 : : : : 3 :
+GND* : F15 : : : : 3 :
+GND* : F16 : : : : 3 :
+GND* : F17 : : : : 3 :
+VREFB2 : F18 : power : : : 2 :
+GND* : F19 : : : : 2 :
+GND* : F20 : : : : 2 :
+GND* : F21 : : : : 2 :
+GND* : F22 : : : : 2 :
+GND* : G1 : : : : 5 :
+GND* : G2 : : : : 5 :
+GND* : G3 : : : : 5 :
+GND* : G4 : : : : 5 :
+GND* : G5 : : : : 5 :
+GND* : G6 : : : : 5 :
+GND* : G7 : : : : 4 :
+GND* : G8 : : : : 4 :
+GND* : G9 : : : : 4 :
+VCC_PLL5_OUT : G10 : power : : 3.3V : 9 :
+VCCD_PLL5 : G11 : power : : 1.2V : :
+GND* : G12 : : : : 3 :
+GND* : G13 : : : : 3 :
+GND* : G14 : : : : 3 :
+GND* : G15 : : : : 3 :
+GND* : G16 : : : : 3 :
+GND* : G17 : : : : 2 :
+GND* : G18 : : : : 2 :
+GND* : G19 : : : : 2 :
+GND* : G20 : : : : 2 :
+GND* : G21 : : : : 2 :
+GND* : G22 : : : : 2 :
+GND* : H1 : : : : 5 :
+GND* : H2 : : : : 5 :
+GND* : H3 : : : : 5 :
+GND* : H4 : : : : 5 :
+GND* : H5 : : : : 5 :
+GND* : H6 : : : : 5 :
+GND* : H7 : : : : 4 :
+VCCINT : H8 : power : : 1.2V : :
+GND* : H9 : : : : 4 :
+VCCPD4 : H10 : power : : 3.3V : 4 :
+GND* : H11 : : : : 3 :
+GND* : H12 : : : : 3 :
+VCCPD3 : H13 : power : : 3.3V : 3 :
+GND* : H14 : : : : 3 :
+GND : H15 : gnd : : : :
+GND* : H16 : : : : 3 :
+GND* : H17 : : : : 2 :
+GND* : H18 : : : : 2 :
+GND* : H19 : : : : 2 :
+GND* : H20 : : : : 2 :
+GND* : H21 : : : : 2 :
+GND* : H22 : : : : 2 :
+GND : J1 : gnd : : : :
+GND* : J2 : : : : 5 :
+GND* : J3 : : : : 5 :
+VREFB5 : J4 : power : : : 5 :
+GND* : J5 : : : : 5 :
+GND* : J6 : : : : 5 :
+GND* : J7 : : : : 5 :
+GND* : J8 : : : : 5 :
+VCCINT : J9 : power : : 1.2V : :
+GND : J10 : gnd : : : :
+VCCINT : J11 : power : : 1.2V : :
+GND : J12 : gnd : : : :
+VCCINT : J13 : power : : 1.2V : :
+GND : J14 : gnd : : : :
+GND* : J15 : : : : 3 :
+GND* : J16 : : : : 2 :
+GND* : J17 : : : : 2 :
+GND* : J18 : : : : 2 :
+GND* : J19 : : : : 2 :
+GND* : J20 : : : : 2 :
+GND* : J21 : : : : 2 :
+GND : J22 : gnd : : : :
+GND* : K1 : : : : 5 :
+GND* : K2 : : : : 5 :
+GND* : K3 : : : : 5 :
+GND* : K4 : : : : 5 :
+GND* : K5 : : : : 5 :
+GND* : K6 : : : : 5 :
+GND* : K7 : : : : 5 :
+GND* : K8 : : : : 5 :
+GND : K9 : gnd : : : :
+VCCINT : K10 : power : : 1.2V : :
+GND : K11 : gnd : : : :
+VCCINT : K12 : power : : 1.2V : :
+GND : K13 : gnd : : : :
+VCCPD2 : K14 : power : : 3.3V : 2 :
+GND* : K15 : : : : 2 :
+GND* : K16 : : : : 2 :
+GND* : K17 : : : : 2 :
+GND* : K18 : : : : 2 :
+GND* : K19 : : : : 2 :
+GND* : K20 : : : : 2 :
+GND* : K21 : : : : 2 :
+GND* : K22 : : : : 2 :
+VCCIO5 : L1 : power : : 3.3V : 5 :
+GND* : L2 : : : : 5 :
+GND* : L3 : : : : 5 :
+GNDA_PLL4 : L4 : gnd : : : :
+GNDA_PLL4 : L5 : gnd : : : :
+VCCD_PLL4 : L6 : power : : 1.2V : :
+GND* : L7 : : : : 5 :
+GND* : L8 : : : : 5 :
+VCCPD5 : L9 : power : : 3.3V : 5 :
+GND : L10 : gnd : : : :
+VCCINT : L11 : power : : 1.2V : :
+GND : L12 : gnd : : : :
+VCCINT : L13 : power : : 1.2V : :
+GND : L14 : gnd : : : :
+GND* : L15 : : : : 2 :
+GND* : L16 : : : : 2 :
+GNDA_PLL1 : L17 : gnd : : : :
+GNDA_PLL1 : L18 : gnd : : : :
+VREFB2 : L19 : power : : : 2 :
+GND* : L20 : : : : 2 :
+GND* : L21 : : : : 2 :
+VCCIO2 : L22 : power : : 3.3V : 2 :
+VCCIO6 : M1 : power : : 3.3V : 6 :
+GND+ : M2 : : : : 5 :
+GND+ : M3 : : : : 5 :
+VCCA_PLL3 : M4 : power : : 1.2V : :
+VCCD_PLL3 : M5 : power : : 1.2V : :
+VCCA_PLL4 : M6 : power : : 1.2V : :
+GND : M7 : gnd : : : :
+VCCINT : M8 : power : : 1.2V : :
+GND : M9 : gnd : : : :
+VCCINT : M10 : power : : 1.2V : :
+GND : M11 : gnd : : : :
+VCCINT : M12 : power : : 1.2V : :
+GND : M13 : gnd : : : :
+VCCINT : M14 : power : : 1.2V : :
+GND : M15 : gnd : : : :
+VCCD_PLL1 : M16 : power : : 1.2V : :
+VCCA_PLL1 : M17 : power : : 1.2V : :
+VCCD_PLL2 : M18 : power : : 1.2V : :
+VCCA_PLL2 : M19 : power : : 1.2V : :
+GND+ : M20 : : : : 2 :
+GND+ : M21 : : : : 2 :
+VCCIO1 : M22 : power : : 3.3V : 1 :
+GND* : N1 : : : : 6 :
+GND* : N2 : : : : 6 :
+GND+ : N3 : : : : 6 :
+GND+ : N4 : : : : 6 :
+GNDA_PLL3 : N5 : gnd : : : :
+GNDA_PLL3 : N6 : gnd : : : :
+GND* : N7 : : : : 6 :
+GND* : N8 : : : : 6 :
+VCCPD6 : N9 : power : : 3.3V : 6 :
+GND : N10 : gnd : : : :
+VCCINT : N11 : power : : 1.2V : :
+GND : N12 : gnd : : : :
+VCCINT : N13 : power : : 1.2V : :
+GND : N14 : gnd : : : :
+GND* : N15 : : : : 1 :
+GND* : N16 : : : : 1 :
+GNDA_PLL2 : N17 : gnd : : : :
+GNDA_PLL2 : N18 : gnd : : : :
+GND+ : N19 : : : : 1 :
+clk_i : N20 : input : 3.3-V LVTTL : : 1 : N
+GND* : N21 : : : : 1 :
+GND* : N22 : : : : 1 :
+GND : P1 : gnd : : : :
+GND* : P2 : : : : 6 :
+GND* : P3 : : : : 6 :
+VREFB6 : P4 : power : : : 6 :
+GND* : P5 : : : : 6 :
+GND* : P6 : : : : 6 :
+GND* : P7 : : : : 6 :
+GND* : P8 : : : : 6 :
+VCCINT : P9 : power : : 1.2V : :
+VCCPD7 : P10 : power : : 3.3V : 7 :
+GND : P11 : gnd : : : :
+VCCINT : P12 : power : : 1.2V : :
+GND : P13 : gnd : : : :
+VCCINT : P14 : power : : 1.2V : :
+VCCPD1 : P15 : power : : 3.3V : 1 :
+GND* : P16 : : : : 1 :
+GND* : P17 : : : : 1 :
+GND* : P18 : : : : 1 :
+GND* : P19 : : : : 1 :
+GND* : P20 : : : : 1 :
+GND* : P21 : : : : 1 :
+GND : P22 : gnd : : : :
+GND* : R1 : : : : 6 :
+GND* : R2 : : : : 6 :
+GND* : R3 : : : : 6 :
+GND* : R4 : : : : 6 :
+GND* : R5 : : : : 6 :
+GND* : R6 : : : : 6 :
+GND* : R7 : : : : 6 :
+GND* : R8 : : : : 6 :
+GND* : R9 : : : : 7 :
+GND : R10 : gnd : : : :
+VCC_PLL6_OUT : R11 : power : : 3.3V : 10 :
+VCCA_PLL6 : R12 : power : : 1.2V : :
+VCCPD8 : R13 : power : : 3.3V : 8 :
+GND* : R14 : : : : 8 :
+GND* : R15 : : : : 8 :
+GND* : R16 : : : : 1 :
+GND* : R17 : : : : 1 :
+GND* : R18 : : : : 1 :
+GND* : R19 : : : : 1 :
+VREFB1 : R20 : power : : : 1 :
+GND* : R21 : : : : 1 :
+GND* : R22 : : : : 1 :
+GND* : T1 : : : : 6 :
+GND* : T2 : : : : 6 :
+GND* : T3 : : : : 6 :
+GND* : T4 : : : : 6 :
+GND* : T5 : : : : 6 :
+GND* : T6 : : : : 6 :
+GND* : T7 : : : : 7 :
+GND* : T8 : : : : 7 :
+GND* : T9 : : : : 7 :
+GND* : T10 : : : : 7 :
+GNDA_PLL6 : T11 : gnd : : : :
+GNDA_PLL6 : T12 : gnd : : : :
+GND* : T13 : : : : 8 :
+GND* : T14 : : : : 8 :
+GND* : T15 : : : : 8 :
+GND* : T16 : : : : 8 :
+GND* : T17 : : : : 1 :
+GND* : T18 : : : : 1 :
+GND* : T19 : : : : 1 :
+GND* : T20 : : : : 1 :
+GND* : T21 : : : : 1 :
+GND* : T22 : : : : 1 :
+GND* : U1 : : : : 6 :
+GND* : U2 : : : : 6 :
+VREFB6 : U3 : power : : : 6 :
+GND* : U4 : : : : 6 :
+GND* : U5 : : : : 6 :
+GND* : U6 : : : : 7 :
+GND* : U7 : : : : 7 :
+GND* : U8 : : : : 7 :
+GND* : U9 : : : : 7 :
+GND* : U10 : : : : 7 :
+VCCD_PLL6 : U11 : power : : 1.2V : :
+GND* : U12 : : : : 8 :
+GND* : U13 : : : : 8 :
+GND* : U14 : : : : 8 :
+GND* : U15 : : : : 8 :
+GND* : U16 : : : : 8 :
+GND* : U17 : : : : 1 :
+GND* : U18 : : : : 1 :
+GND* : U19 : : : : 1 :
+GND* : U20 : : : : 1 :
+GND* : U21 : : : : 1 :
+GND* : U22 : : : : 1 :
+GND* : V1 : : : : 6 :
+in0_o : V2 : output : 3.3-V LVTTL : : 6 : N
+GND* : V3 : : : : 6 :
+GND* : V4 : : : : 6 :
+PORSEL : V5 : : : : 7 :
+GND* : V6 : : : : 7 :
+GND* : V7 : : : : 7 :
+GND* : V8 : : : : 7 :
+GND* : V9 : : : : 10 :
+GND* : V10 : : : : 7 :
+GND* : V11 : : : : 8 :
+GND* : V12 : : : : 8 :
+GND* : V13 : : : : 8 :
+GND* : V14 : : : : 8 :
+GND* : V15 : : : : 8 :
+GND* : V16 : : : : 8 :
+VCCSEL : V17 : : : : 8 :
+GND* : V18 : : : : 1 :
+GND* : V19 : : : : 1 :
+VREFB1 : V20 : power : : : 1 :
+GND* : V21 : : : : 1 :
+GND* : V22 : : : : 1 :
+GND* : W1 : : : : 6 :
+GND* : W2 : : : : 6 :
+GND* : W3 : : : : 6 :
+GND* : W4 : : : : 6 :
+GND* : W5 : : : : 7 :
+VREFB7 : W6 : power : : : 7 :
+GND* : W7 : : : : 7 :
+VREFB7 : W8 : power : : : 7 :
+GND* : W9 : : : : 10 :
+GND* : W10 : : : : 7 :
+GND* : W11 : : : : 8 :
+rst_i : W12 : input : 3.3-V LVTTL : : 8 : N
+GND* : W13 : : : : 8 :
+GND* : W14 : : : : 8 :
+GND* : W15 : : : : 8 :
+GND* : W16 : : : : 8 :
+GND* : W17 : : : : 8 :
+nCONFIG : W18 : : : : 8 :
+GND* : W19 : : : : 1 :
+GND* : W20 : : : : 1 :
+GND* : W21 : : : : 1 :
+GND* : W22 : : : : 1 :
+GND* : Y1 : : : : 6 :
+GND* : Y2 : : : : 6 :
+GND* : Y3 : : : : 7 :
+PLL_ENA : Y4 : : : : 7 :
+GND* : Y5 : : : : 7 :
+GND* : Y6 : : : : 7 :
+GND* : Y7 : : : : 7 :
+GND* : Y8 : : : : 7 :
+GND* : Y9 : : : : 10 :
+GND* : Y10 : : : : 7 :
+GND* : Y11 : : : : 7 :
+GND* : Y12 : : : : 8 :
+GND* : Y13 : : : : 8 :
+GND* : Y14 : : : : 8 :
+GND* : Y15 : : : : 8 :
+GND* : Y16 : : : : 8 :
+GND* : Y17 : : : : 8 :
+GND* : Y18 : : : : 8 :
+VREFB8 : Y19 : power : : : 8 :
+GND* : Y20 : : : : 8 :
+GND* : Y21 : : : : 1 :
+GND* : Y22 : : : : 1 :
Index: QuartusII/usimplez_cpu.vhd
===================================================================
--- QuartusII/usimplez_cpu.vhd (nonexistent)
+++ QuartusII/usimplez_cpu.vhd (revision 2)
@@ -0,0 +1,229 @@
+--//////////////////////////////////////////////////////////////////////
+--//// ////
+--//// ////
+--//// ////
+--//// This file is part of the MicroSimplez project ////
+--//// http://opencores.org/project,usimplez ////
+--//// ////
+--//// Description ////
+--//// Implementation of MicroSimplez IP core according to ////
+--//// MicroSimplez IP core specification document. ////
+--//// ////
+--//// To Do: ////
+--//// - ////
+--//// ////
+--//// Author(s): ////
+--//// - Daniel Peralta, peraltahd@opencores.org, designer ////
+--//// - Martin Montero, monteromrtn@opencores.org, designer ////
+--//// - Julian Castro, julyan@opencores.org, reviewer ////
+--//// - Pablo A. Salvadeo, pas.@opencores, manager ////
+--//// ////
+--//////////////////////////////////////////////////////////////////////
+--//// ////
+--//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
+--//// ////
+--//// This source file may be used and distributed without ////
+--//// restriction provided that this copyright statement is not ////
+--//// removed from the file and that any derivative work contains ////
+--//// the original copyright notice and the associated disclaimer. ////
+--//// ////
+--//// This source file is free software; you can redistribute it ////
+--//// and/or modify it under the terms of the GNU Lesser General ////
+--//// Public License as published by the Free Software Foundation; ////
+--//// either version 2.1 of the License, or (at your option) any ////
+--//// later version. ////
+--//// ////
+--//// This source is distributed in the hope that it will be ////
+--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+--//// PURPOSE. See the GNU Lesser General Public License for more ////
+--//// details. ////
+--//// ////
+--//// You should have received a copy of the GNU Lesser General ////
+--//// Public License along with this source; if not, download it ////
+--//// from http://www.opencores.org/lgpl.shtml ////
+--//// ////
+--//////////////////////////////////////////////////////////////////////
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity usimplez_cpu is
+
+ generic(
+ WIDTH_DATA_BUS: natural:=12;
+ WIDTH_OPERATION_CODE: natural:=3;
+ WIDTH_ADDRESS: natural:=9;
+ --Instructions:
+ ST: unsigned:="000";
+ LD: unsigned:="001";
+ ADD: unsigned:="010";
+ BR: unsigned:="011";
+ BZ: unsigned:="100";
+ CLR: unsigned:="101";
+ DEC: unsigned:="110";
+ HALT: unsigned:="111"
+ );
+
+ port(
+ clk_i: in std_logic;
+ rst_i: in std_logic;
+ data_bus_i: in std_logic_vector((WIDTH_DATA_BUS-1) downto 0);
+ data_bus_o: out std_logic_vector((WIDTH_DATA_BUS-1) downto 0);
+ addr_bus_o: out std_logic_vector((WIDTH_ADDRESS-1) downto 0);
+ we_o: out std_logic;
+ --To Debug:
+ In0_o: out std_logic;
+ In1_o: out std_logic;
+ Op0_o: out std_logic;
+ Op1_o: out std_logic
+ --
+ );
+
+end usimplez_cpu;
+
+architecture fsm of usimplez_cpu is
+
+ type T_estado is (In0,In1,Op0,Op1);
+ signal estado: T_estado;
+ --Bit Cero <- '1' si AC = 0;
+ signal z_bit_s:std_logic;
+ --Acumulador (AC)
+ signal acumulador: unsigned((WIDTH_DATA_BUS-1) downto 0);
+ --Registro CO
+ signal co_reg_s: unsigned((WIDTH_OPERATION_CODE-1) downto 0);
+ --Registro CD
+ signal cd_reg_s: unsigned((WIDTH_ADDRESS-1) downto 0);
+ --BD
+ signal data_bus_s: unsigned((WIDTH_DATA_BUS-1) downto 0);
+ --Registro CP
+ signal cp_reg_s: unsigned((WIDTH_ADDRESS-1) downto 0);
+ --Bus Dir
+ signal addr_bus_s: unsigned((WIDTH_ADDRESS-1) downto 0);
+
+begin
+
+ process(clk_i,rst_i)
+ begin
+ if(rising_edge(clk_i)) then
+ if(rst_i='1') then
+ co_reg_s <= (others=>'0');
+ acumulador <= (others=>'0');
+ cd_reg_s <= (others=>'0');
+ cp_reg_s <= (others=>'0');
+ addr_bus_o <= (others=>'1');
+ data_bus_o <= (others=>'0');
+ we_o<='0';
+ --
+ estado <= In0;
+ --
+ else
+ case estado is
+ when In0 =>
+ -- (MP[RA])->RI;
+ co_reg_s<=unsigned(data_bus_i(11 downto 9));
+ cd_reg_s<=unsigned(data_bus_i(8 downto 0));
+ -- (cp_reg_s)+1->cp_reg_s
+ cp_reg_s<=cp_reg_s+1;
+ --
+ In0_o<='1';
+ In1_o<='0';
+ Op0_o<='0';
+ Op1_o<='0';
+ --
+ estado<=In1;
+ when In1 =>
+ --
+ In0_o<='0';
+ In1_o<='1';
+ Op0_o<='0';
+ Op1_o<='0';
+ --
+ case (co_reg_s) is
+ when CLR =>
+ -- 0->AC
+ acumulador<=(others=>'0');
+ -- (cp_reg_s)->RA
+ addr_bus_o<=std_logic_vector(cp_reg_s);
+ estado<=In0;
+ when DEC =>
+ -- (AC)-1 -> AC
+ acumulador<=acumulador-1;
+ -- (cp_reg_s)->RA
+ addr_bus_o<=std_logic_vector(cp_reg_s);
+ estado<=In0;
+ when BR =>
+ -- (cd_reg_s)->cp_reg_s,RA
+ cp_reg_s<=cd_reg_s;
+ addr_bus_o<=std_logic_vector(cd_reg_s);
+ estado<=In0;
+ when BZ =>
+ --Si z_bit_s=1 igual BR
+ if(acumulador=0) then
+ cp_reg_s<=cp_reg_s;
+ addr_bus_o<=std_logic_vector(cd_reg_s);
+ else
+ --Si no (cp_reg_s)->RA
+ addr_bus_o<=std_logic_vector(cp_reg_s);
+ end if;
+ estado<=In0;
+ when HALT =>
+ -- 0->cp_reg_s
+ cp_reg_s<=(others=>'0');
+ estado<=In0;
+ when LD =>
+ -- (cd_reg_s)->RA
+ addr_bus_o<=std_logic_vector(cd_reg_s);
+ estado<=Op0;
+ when ST =>
+ addr_bus_o<=std_logic_vector(cd_reg_s);
+ estado<=Op0;
+ when ADD =>
+ addr_bus_o<=std_logic_vector(cd_reg_s);
+ estado<=Op0;
+ when others=>
+ estado<=In0;
+ end case;
+ when Op0 =>
+ --
+ In0_o<='0';
+ In1_o<='0';
+ Op0_o<='1';
+ Op1_o<='0';
+ --
+ case (co_reg_s) is
+ when LD =>
+ -- (MP[RA])->AC
+ acumulador<=unsigned(data_bus_i);
+ estado<=Op1;
+ when ST =>
+ -- (AC)->MP[RA]
+ data_bus_o<=std_logic_vector(acumulador);
+ we_o<='1';
+ estado<=Op1;
+ when ADD =>
+ acumulador<=acumulador+unsigned(data_bus_i);
+ estado<=Op1;
+ when others =>
+ estado<=In0;
+ end case;
+ when OP1 =>
+ -- (cp_reg_s)->RA
+ addr_bus_o<=std_logic_vector(cp_reg_s);
+ we_o<='0';
+ estado<=In0;
+ --
+ In0_o<='0';
+ In1_o<='0';
+ Op0_o<='0';
+ Op1_o<='1';
+ --
+ when others =>
+ estado<=In0;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end fsm;
\ No newline at end of file
Index: QuartusII/usimplez.qsf
===================================================================
--- QuartusII/usimplez.qsf (nonexistent)
+++ QuartusII/usimplez.qsf (revision 2)
@@ -0,0 +1,60 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 01:39:00 November 09, 2011
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# usimplez_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name TOP_LEVEL_ENTITY usimplez_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:39:00 NOVEMBER 09, 2011"
+set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
+set_global_assignment -name VHDL_FILE usimplez_top.vhd
+set_global_assignment -name VHDL_FILE usimplez_cpu.vhd
+set_global_assignment -name VHDL_FILE usimplez_ram.vhd
+set_global_assignment -name TEXT_FILE adder.txt
+set_global_assignment -name MIF_FILE fibonacci.mif
+set_global_assignment -name TEXT_FILE fibonacci.txt
+set_global_assignment -name MIF_FILE adder.mif
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -entity usimplez -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -entity usimplez -section_id "Root Region"
+set_global_assignment -name VECTOR_WAVEFORM_FILE usimplez_top.vwf
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE usimplez_top.vwf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: QuartusII/usimplez.sim.rpt
===================================================================
--- QuartusII/usimplez.sim.rpt (nonexistent)
+++ QuartusII/usimplez.sim.rpt (revision 2)
@@ -0,0 +1,352 @@
+Simulator report for usimplez
+Wed Nov 09 01:52:21 2011
+Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Simulator Summary
+ 3. Simulator Settings
+ 4. Simulation Waveforms
+ 5. |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM
+ 6. Coverage Summary
+ 7. Complete 1/0-Value Coverage
+ 8. Missing 1-Value Coverage
+ 9. Missing 0-Value Coverage
+ 10. Simulator INI Usage
+ 11. Simulator Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++--------------------------------------------+
+; Simulator Summary ;
++-----------------------------+--------------+
+; Type ; Value ;
++-----------------------------+--------------+
+; Simulation Start Time ; 0 ps ;
+; Simulation End Time ; 100.0 us ;
+; Simulation Netlist Size ; 137 nodes ;
+; Simulation Coverage ; 89.76 % ;
+; Total Number of Transitions ; 113895 ;
+; Simulation Breakpoints ; 0 ;
+; Family ; Stratix II ;
+; Device ; EP2S15F484C3 ;
++-----------------------------+--------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------+
+; Simulator Settings ;
++--------------------------------------------------------------------------------------------+------------------+---------------+
+; Option ; Setting ; Default Value ;
++--------------------------------------------------------------------------------------------+------------------+---------------+
+; Simulation mode ; Timing ; Timing ;
+; Start time ; 0 ns ; 0 ns ;
+; Simulation results format ; CVWF ; ;
+; Vector input source ; usimplez_top.vwf ; ;
+; Add pins automatically to simulation output waveforms ; On ; On ;
+; Check outputs ; Off ; Off ;
+; Report simulation coverage ; On ; On ;
+; Display complete 1/0 value coverage report ; On ; On ;
+; Display missing 1-value coverage report ; On ; On ;
+; Display missing 0-value coverage report ; On ; On ;
+; Detect setup and hold time violations ; Off ; Off ;
+; Detect glitches ; Off ; Off ;
+; Disable timing delays in Timing Simulation ; Off ; Off ;
+; Generate Signal Activity File ; Off ; Off ;
+; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
+; Group bus channels in simulation results ; Off ; Off ;
+; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
+; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
+; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
+; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ;
+; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
++--------------------------------------------------------------------------------------------+------------------+---------------+
+
+
++----------------------+
+; Simulation Waveforms ;
++----------------------+
+Waveform report data cannot be output to ASCII.
+Please use Quartus II to view the waveform report data.
+
+
++-----------------------------------------------------------------------------------------------+
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ALTSYNCRAM ;
++-----------------------------------------------------------------------------------------------+
+Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII.
+
+
++--------------------------------------------------------------------+
+; Coverage Summary ;
++-----------------------------------------------------+--------------+
+; Type ; Value ;
++-----------------------------------------------------+--------------+
+; Total coverage as a percentage ; 89.76 % ;
+; Total nodes checked ; 137 ;
+; Total output ports checked ; 166 ;
+; Total output ports with complete 1/0-value coverage ; 149 ;
+; Total output ports with no 1/0-value coverage ; 17 ;
+; Total output ports with no 1-value coverage ; 17 ;
+; Total output ports with no 0-value coverage ; 17 ;
++-----------------------------------------------------+--------------+
+
+
+The following table displays output ports that toggle between 1 and 0 during simulation.
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Complete 1/0-Value Coverage ;
++-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
+; |usimplez_top|usimplez_cpu:cpu|we_o ; |usimplez_top|usimplez_cpu:cpu|we_o ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|co_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[1] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|co_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[0] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[0] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[0] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[1] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[1] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[2] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[2] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[3] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[3] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[4] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[4] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[6] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[6] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[10] ; |usimplez_top|usimplez_cpu:cpu|acumulador[10] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[0] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[5] ; |usimplez_top|usimplez_cpu:cpu|acumulador[5] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[4] ; |usimplez_top|usimplez_cpu:cpu|acumulador[4] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[3] ; |usimplez_top|usimplez_cpu:cpu|acumulador[3] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[2] ; |usimplez_top|usimplez_cpu:cpu|acumulador[2] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[0] ; |usimplez_top|usimplez_cpu:cpu|acumulador[0] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[1] ; |usimplez_top|usimplez_cpu:cpu|acumulador[1] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[11] ; |usimplez_top|usimplez_cpu:cpu|acumulador[11] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[9] ; |usimplez_top|usimplez_cpu:cpu|acumulador[9] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[8] ; |usimplez_top|usimplez_cpu:cpu|acumulador[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[6] ; |usimplez_top|usimplez_cpu:cpu|acumulador[6] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[7] ; |usimplez_top|usimplez_cpu:cpu|acumulador[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[0] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[0] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[1] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[1] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[1] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[2] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[2] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[2] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[3] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[3] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[3] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[4] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[4] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[4] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6] ; regout ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; portadataout0 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a4 ; portadataout1 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a5 ; portadataout2 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a6 ; portadataout3 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a7 ; portadataout4 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a8 ; portadataout5 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a9 ; portadataout6 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a10 ; portadataout7 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a11 ; portadataout8 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; portadataout0 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1 ; portadataout1 ;
+; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0 ; |usimplez_top|usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a2 ; portadataout2 ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~2 ; |usimplez_top|usimplez_cpu:cpu|Add2~3 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~6 ; |usimplez_top|usimplez_cpu:cpu|Add2~7 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~10 ; |usimplez_top|usimplez_cpu:cpu|Add2~11 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~14 ; |usimplez_top|usimplez_cpu:cpu|Add2~15 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~18 ; |usimplez_top|usimplez_cpu:cpu|Add2~19 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~22 ; |usimplez_top|usimplez_cpu:cpu|Add2~23 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~26 ; |usimplez_top|usimplez_cpu:cpu|Add2~27 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~30 ; |usimplez_top|usimplez_cpu:cpu|Add2~31 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~34 ; |usimplez_top|usimplez_cpu:cpu|Add2~35 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~38 ; |usimplez_top|usimplez_cpu:cpu|Add2~39 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~42 ; |usimplez_top|usimplez_cpu:cpu|Add2~43 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add2~46 ; |usimplez_top|usimplez_cpu:cpu|Add2~46 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~1 ; |usimplez_top|usimplez_cpu:cpu|Add0~2 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~5 ; |usimplez_top|usimplez_cpu:cpu|Add0~6 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~9 ; |usimplez_top|usimplez_cpu:cpu|Add0~10 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~13 ; |usimplez_top|usimplez_cpu:cpu|Add0~14 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~17 ; |usimplez_top|usimplez_cpu:cpu|Add0~18 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[2] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[2] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[1] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[1] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[0] ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[0] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|Selector31~0 ; |usimplez_top|usimplez_cpu:cpu|Selector31~0 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|In0_o ; |usimplez_top|usimplez_cpu:cpu|In0_o ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|In1_o ; |usimplez_top|usimplez_cpu:cpu|In1_o ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|Op0_o ; |usimplez_top|usimplez_cpu:cpu|Op0_o ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|Op1_o ; |usimplez_top|usimplez_cpu:cpu|Op1_o ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|estado.Op0 ; |usimplez_top|usimplez_cpu:cpu|estado.Op0 ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|estado.In1 ; |usimplez_top|usimplez_cpu:cpu|estado.In1 ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|estado.In0 ; |usimplez_top|usimplez_cpu:cpu|estado.In0 ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|estado.Op1 ; |usimplez_top|usimplez_cpu:cpu|estado.Op1 ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|estado~6 ; |usimplez_top|usimplez_cpu:cpu|estado~6 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|estado~7 ; |usimplez_top|usimplez_cpu:cpu|estado~7 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~0 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~0 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|estado~8 ; |usimplez_top|usimplez_cpu:cpu|estado~8 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2]~1 ; |usimplez_top|usimplez_cpu:cpu|co_reg_s[2]~1 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|estado~9 ; |usimplez_top|usimplez_cpu:cpu|estado~9 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~0 ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~0 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~1 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~1 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~2 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~2 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~3 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~3 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~4 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~4 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~5 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[5]~5 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~6 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~6 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~7 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~7 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~8 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~8 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~9 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~9 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~10 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~10 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~11 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~11 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[0]~0 ; |usimplez_top|usimplez_cpu:cpu|acumulador[0]~0 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[0]~1 ; |usimplez_top|usimplez_cpu:cpu|acumulador[0]~1 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|acumulador[0]~2 ; |usimplez_top|usimplez_cpu:cpu|acumulador[0]~2 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~2 ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~2 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~3 ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6]~3 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|In0_o~0 ; |usimplez_top|usimplez_cpu:cpu|In0_o~0 ; combout ;
+; |usimplez_top|we_o ; |usimplez_top|we_o ; padio ;
+; |usimplez_top|in0_o ; |usimplez_top|in0_o ; padio ;
+; |usimplez_top|in1_o ; |usimplez_top|in1_o ; padio ;
+; |usimplez_top|op0_o ; |usimplez_top|op0_o ; padio ;
+; |usimplez_top|op1_o ; |usimplez_top|op1_o ; padio ;
+; |usimplez_top|clk_i ; |usimplez_top|clk_i~corein ; combout ;
+; |usimplez_top|rst_i ; |usimplez_top|rst_i~corein ; combout ;
+; |usimplez_top|clk_i~clkctrl ; |usimplez_top|clk_i~clkctrl ; outclk ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[10]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[5]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[4]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[3]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[11]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[9]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[8]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[6]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7]~feeder ; |usimplez_top|usimplez_cpu:cpu|data_bus_o[7]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[6]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5]~feeder ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[5]~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|Op0_o~feeder ; |usimplez_top|usimplez_cpu:cpu|Op0_o~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|In1_o~feeder ; |usimplez_top|usimplez_cpu:cpu|In1_o~feeder ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|Op1_o~feeder ; |usimplez_top|usimplez_cpu:cpu|Op1_o~feeder ; combout ;
++-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------------+
+
+
+The following table displays output ports that do not toggle to 1 during simulation.
++----------------------------------------------------------------------------------------------------------------+
+; Missing 1-Value Coverage ;
++----------------------------------------------+----------------------------------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++----------------------------------------------+----------------------------------------------+------------------+
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~22 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~26 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~30 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; combout ;
++----------------------------------------------+----------------------------------------------+------------------+
+
+
+The following table displays output ports that do not toggle to 0 during simulation.
++----------------------------------------------------------------------------------------------------------------+
+; Missing 0-Value Coverage ;
++----------------------------------------------+----------------------------------------------+------------------+
+; Node Name ; Output Port Name ; Output Port Type ;
++----------------------------------------------+----------------------------------------------+------------------+
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[5] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[6] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[7] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cd_reg_s[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; |usimplez_top|usimplez_cpu:cpu|cp_reg_s[8] ; regout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~21 ; |usimplez_top|usimplez_cpu:cpu|Add0~22 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~25 ; |usimplez_top|usimplez_cpu:cpu|Add0~26 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~29 ; |usimplez_top|usimplez_cpu:cpu|Add0~30 ; cout ;
+; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; |usimplez_top|usimplez_cpu:cpu|Add0~33 ; sumout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~12 ; combout ;
+; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; |usimplez_top|usimplez_cpu:cpu|addr_bus_o~13 ; combout ;
++----------------------------------------------+----------------------------------------------+------------------+
+
+
++---------------------+
+; Simulator INI Usage ;
++--------+------------+
+; Option ; Usage ;
++--------+------------+
+
+
++--------------------+
+; Simulator Messages ;
++--------------------+
+Info: *******************************************************************
+Info: Running Quartus II Simulator
+ Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+ Info: Processing started: Wed Nov 09 01:52:15 2011
+Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off usimplez -c usimplez
+Info: Using vector source file "C:/Altera/qdesigns/usimplez/usimplez_top.vwf"
+Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
+ Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
+Info: Simulation partitioned into 1 sub-simulations
+Info: Simulation coverage is 89.76 %
+Info: Number of transitions in simulation is 113895
+Info: Quartus II Simulator was successful. 0 errors, 0 warnings
+ Info: Peak virtual memory: 121 megabytes
+ Info: Processing ended: Wed Nov 09 01:52:27 2011
+ Info: Elapsed time: 00:00:12
+ Info: Total CPU time (on all processors): 00:00:11
+
+
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.rcfdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.rcfdb
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.rcfdb (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.rcfdb (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.rcfdb
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.re.rcfdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.re.rcfdb
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.re.rcfdb (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.re.rcfdb (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.re.rcfdb
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Added: svn:mime-type
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+application/octet-stream
\ No newline at end of property
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.cdb
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.cdb (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.cdb (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.cdb
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.logdb
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.logdb (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.logdb (revision 2)
@@ -0,0 +1,13 @@
+v1
+RAM_PACKING,0,M4K,9,9,TrueDual,0,7,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a10,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,6,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a9,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,8,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a11,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,5,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a8,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,4,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a7,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,3,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a6,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,2,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a5,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,1,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a4,
+RAM_PACKING,0,M4K,9,9,TrueDual,0,0,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a3,
+RAM_PACKING,1,M4K,9,9,TrueDual,0,2,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a2,
+RAM_PACKING,1,M4K,9,9,TrueDual,0,1,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a1,
+RAM_PACKING,1,M4K,9,9,TrueDual,0,0,10000010,usimplez_ram:ram|altsyncram:ram_rtl_0|altsyncram_im61:auto_generated|ram_block1a0,
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.cdb
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.cdb
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.cdb (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.cdb (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.cdb
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.dfp
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.dfp
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.dfp (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.dfp (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.dfp
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+application/octet-stream
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Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.dpi
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.dpi
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.dpi (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.dpi (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.dpi
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Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.hdb
===================================================================
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Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.hdb
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.hdb (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.hdb (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.hdb
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Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.kpt
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.kpt
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.kpt (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.kpt (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.map.kpt
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Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.hdb
===================================================================
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svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.hdb
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.hdb (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.hdb (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.hdb
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Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.kpt
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.kpt
===================================================================
--- QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.kpt (nonexistent)
+++ QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.kpt (revision 2)
QuartusII/incremental_db/compiled_partitions/usimplez.root_partition.cmp.kpt
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Index: QuartusII/incremental_db/README
===================================================================
--- QuartusII/incremental_db/README (nonexistent)
+++ QuartusII/incremental_db/README (revision 2)
@@ -0,0 +1,11 @@
+This folder contains data for incremental compilation.
+
+The compiled_partitions sub-folder contains previous compilation results for each partition.
+As long as this folder is preserved, incremental compilation results from earlier compiles
+can be re-used. To perform a clean compilation from source files for all partitions, both
+the db and incremental_db folder should be removed.
+
+The imported_partitions sub-folder contains the last imported QXP for each imported partition.
+As long as this folder is preserved, imported partitions will be automatically re-imported
+when the db or incremental_db/compiled_partitions folders are removed.
+
Index: QuartusII/usimplez_top.vhd
===================================================================
--- QuartusII/usimplez_top.vhd (nonexistent)
+++ QuartusII/usimplez_top.vhd (revision 2)
@@ -0,0 +1,163 @@
+--//////////////////////////////////////////////////////////////////////
+--//// ////
+--//// ////
+--//// ////
+--//// This file is part of the MicroSimplez project ////
+--//// http://opencores.org/project,usimplez ////
+--//// ////
+--//// Description ////
+--//// Implementation of MicroSimplez IP core according to ////
+--//// MicroSimplez IP core specification document. ////
+--//// ////
+--//// To Do: ////
+--//// - ////
+--//// ////
+--//// Author(s): ////
+--//// - Daniel Peralta, peraltahd@opencores.org, designer ////
+--//// - Martin Montero, monteromrtn@opencores.org, designer ////
+--//// - Julian Castro, julyan@opencores.org, reviewer ////
+--//// - Pablo A. Salvadeo, pas.@opencores, manager ////
+--//// ////
+--//////////////////////////////////////////////////////////////////////
+--//// ////
+--//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
+--//// ////
+--//// This source file may be used and distributed without ////
+--//// restriction provided that this copyright statement is not ////
+--//// removed from the file and that any derivative work contains ////
+--//// the original copyright notice and the associated disclaimer. ////
+--//// ////
+--//// This source file is free software; you can redistribute it ////
+--//// and/or modify it under the terms of the GNU Lesser General ////
+--//// Public License as published by the Free Software Foundation; ////
+--//// either version 2.1 of the License, or (at your option) any ////
+--//// later version. ////
+--//// ////
+--//// This source is distributed in the hope that it will be ////
+--//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+--//// PURPOSE. See the GNU Lesser General Public License for more ////
+--//// details. ////
+--//// ////
+--//// You should have received a copy of the GNU Lesser General ////
+--//// Public License along with this source; if not, download it ////
+--//// from http://www.opencores.org/lgpl.shtml ////
+--//// ////
+--//////////////////////////////////////////////////////////////////////
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+
+entity usimplez_top is
+ generic
+ ( WIDTH_WORD: natural:= 12;
+ WIDTH_ADDRESS: natural:= 9
+ );
+ port
+ ( clk_i : in std_logic;
+ rst_i : in std_logic;
+ we_o : out std_logic;
+ in0_o : out std_logic;
+ in1_o : out std_logic;
+ op0_o : out std_logic;
+ op1_o : out std_logic
+ );
+end usimplez_top;
+
+architecture str of usimplez_top is
+
+ component usimplez_cpu
+ generic
+ ( WIDTH_DATA_BUS: natural;
+ WIDTH_OPERATION_CODE: natural;
+ WIDTH_ADDRESS: natural;
+ --Instructions:
+ ST: std_logic_vector(2 downto 0);
+ LD: std_logic_vector(2 downto 0);
+ ADD: std_logic_vector(2 downto 0);
+ BR: std_logic_vector(2 downto 0);
+ BZ: std_logic_vector(2 downto 0);
+ CLR: std_logic_vector(2 downto 0);
+ DEC: std_logic_vector(2 downto 0);
+ HALT: std_logic_vector(2 downto 0)
+ );
+ port
+ ( clk_i : in std_logic;
+ rst_i : in std_logic;
+ data_bus_i : in std_logic_vector(WIDTH_DATA_BUS-1 downto 0); --here
+ we_o : out std_logic;
+ in0_o : out std_logic;
+ in1_o : out std_logic;
+ op0_o : out std_logic;
+ op1_o : out std_logic;
+ addr_bus_o : out std_logic_vector(8 downto 0);
+ data_bus_o : out std_logic_vector(11 downto 0)
+ );
+ end component;
+
+ component usimplez_ram
+ generic
+ ( WIDTH_ADDRESS : natural;
+ WIDTH_WORD : natural
+ );
+ port
+ ( clk_i : in std_logic;
+ we_i : in std_logic;
+ addr_i : in std_logic_vector(8 downto 0);
+ data_i : in std_logic_vector(11 downto 0);
+ data_o : out std_logic_vector(11 downto 0)
+ );
+ end component;
+
+ signal rd_data_bus_s : std_logic_vector(WIDTH_WORD-1 downto 0);
+ signal we_s : std_logic;
+ signal addr_bus_s : std_logic_vector(WIDTH_ADDRESS-1 downto 0);
+ signal wr_data_bus_s : std_logic_vector(WIDTH_WORD-1 downto 0);
+
+begin
+
+we_o <= we_s;
+
+cpu:usimplez_cpu
+ generic map
+ ( WIDTH_DATA_BUS => 12,
+ WIDTH_ADDRESS => 9,
+ WIDTH_OPERATION_CODE => 3,
+ ST => "000",
+ LD => "001",
+ ADD => "010",
+ BR => "011",
+ BZ => "100",
+ CLR => "101",
+ DEC => "110",
+ HALT => "111"
+ )
+ port map
+ ( clk_i => clk_i,
+ rst_i => rst_i,
+ data_bus_i => rd_data_bus_s,
+ we_o => we_s,
+ in0_o => in0_o,
+ in1_o => in1_o,
+ op0_o => op0_o,
+ op1_o => op1_o,
+ addr_bus_o => addr_bus_s,
+ data_bus_o => wr_data_bus_s
+ );
+
+ram:usimplez_ram
+ generic map
+ ( WIDTH_ADDRESS => 9,
+ WIDTH_WORD => 12
+ )
+ port map
+ ( clk_i => clk_i,
+ we_i => we_s,
+ addr_i => addr_bus_s,
+ data_i => wr_data_bus_s,
+ data_o => rd_data_bus_s
+ );
+
+end str;
\ No newline at end of file