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    /v586/trunk
    from Rev 104 to Rev 105
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Rev 104 → Rev 105

/rtl/TOP_SYS_128.v File deleted
/rtl/TOP_SYS.v
1,10 → 1,24
`define simu
//
module TOP_SYS(
clk100,rstn,gpio_in,
clk100,rstn,
// uart
TXD,RXD,
// psram
extA,extDB,extWEN,extUB,extLB,extCSN,//extWAIT,
extOE,extCLK,extADV,extCRE,
// DDR2
DDR2DQ,
DDR2DQS_N,
DDR2DQS_P,
DDR2ADDR,
DDR2BA,
DDR2RAS_N,
DDR2CAS_N,
DDR2WE_N,
DDR2CK_P,
DDR2CK_N,
DDR2CKE,
DDR2CS_N,
DDR2DM,
DDR2ODT,
// spi flash
sdin,sdout,sdwp,sdhld,sdcs,sdreset,
// gpio it87xx
24,15 → 38,30
mosi,
sclk,
aclInt1,
aclInt2
aclInt2,
debug
);
input clk100;
input rstn;
output TXD;
input [6:0] gpio_in;
output extCLK,extCRE;
output extADV,extUB,extLB,extWEN,extCSN,extOE;
wire [6:0] gpio_in;
 
inout wire [15:0] DDR2DQ;
inout wire [1:0] DDR2DQS_N;
inout wire [1:0] DDR2DQS_P;
output wire [12:0] DDR2ADDR;
output wire [2:0] DDR2BA;
output wire DDR2RAS_N;
output wire DDR2CAS_N;
output wire DDR2WE_N;
output wire DDR2CK_P;
output wire DDR2CK_N;
output wire DDR2CKE;
output wire DDR2CS_N;
output wire [1:0] DDR2DM;
output wire DDR2ODT;
 
input RXD;
output sdout,sdwp,sdhld,sdcs;
input sdin;
45,11 → 74,6
output sclk;
input aclInt1,aclInt2;
 
// external mem I/F
inout [15:0] extDB;
output [23:0] extA;
 
 
// ethernet
output PhyMdc;
inout PhyMdio;
66,6 → 90,10
output [1:0] PhyTxd;
output reg PhyClk50Mhz;
 
output reg [3:0] debug;
 
wire [4:0] debug_int;
 
wire rmii2mac_tx_clk;
wire rmii2mac_rx_clk;
wire rmii2mac_crs;
76,7 → 104,6
wire mac2rmii_tx_en;
wire [3:0] mac2rmii_txd;
wire mac2rmii_tx_er;
reg PhyClk25Mhz;
 
// axi cpu bus
wire [31:0] M_AXI_AW, M_AXI_AR;
156,10 → 183,29
wire int_pic,iack;
wire [7:0] ivect;
wire clk;
wire clk200;
wire dram_rst_out;
wire ui_clk_sync_rst;
wire init_calib_complete;
wire rstn_ddr;
wire locked;
 
assign gpio_in = 0;
 
assign clk =clk100;
clk_wiz_0 i_clk_wiz_0
(.clk_in1(clk100),
.clk_out1(),
.clk_out2(),
.clk_out3(clk200),
.locked(locked)
);
always @(posedge clk200) debug <= debug_int[3:0];
 
RSTGEN rstgen(.CLK(clk200), .RST_X_I(~(~rstn | dram_rst_out)), .RST_X_O(rstn_ddr));
 
assign dram_rst_out = (ui_clk_sync_rst | ~init_calib_complete);
 
STARTUPE2 #(
.PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams.
.SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation.
181,7 → 227,7
);
 
v586 v586 (
.m00_AXI_RSTN(rstn),.m00_AXI_CLK(clk),
.m00_AXI_RSTN(rstn_ddr),.m00_AXI_CLK(clk),
// axi interface 32bit
.m00_AXI_AWADDR(M_AXI_AW), .m00_AXI_AWVALID(M_AXI_AWVALID), .m00_AXI_AWREADY(M_AXI_AWREADY),
.m00_AXI_AWBURST(M_AXI_AWBURST), .m00_AXI_AWLEN(M_AXI_AWLEN), .m00_AXI_AWSIZE(M_AXI_AWSIZE),
199,79 → 245,95
.m01_AXI_RDATA(M_IO_AXI_R), .m01_AXI_RVALID(M_IO_AXI_RVALID), .m01_AXI_RREADY(M_IO_AXI_RREADY), .m01_AXI_RLAST(M_IO_AXI_RLAST),
.m01_AXI_BVALID(1'b1),.m01_AXI_BREADY(M_IO_AXI_BREADY),
// interrupts
.int_pic(int_pic),.ivect(ivect),.iack(iack)
.int_pic(int_pic),.ivect(ivect),.iack(iack), .debug(debug_int)
);
 
psram_axi psram_axi(
// MEM
.MEM_ADDR_OUT(extA[23:1]),
.MEM_CEN(extCSN),
.MEM_OEN(extOE),
.MEM_WEN(extWEN),
.MEM_BEN({extUB,extLB}),
.MEM_ADV(extADV),
.MEM_CRE(extCRE),
.MEM_DATA_I(extDB),
.MEM_DATA_O(extDBo),
.MEM_DATA_T(extDBt),
// CTRL
.s00_axi_aclk(clk),
.s00_axi_aresetn(rstn),
 
ddr_axi i_ddr_axi (
// Inouts
.ddr2_dq(DDR2DQ),
.ddr2_dqs_n(DDR2DQS_N),
.ddr2_dqs_p(DDR2DQS_P),
// Outputs
.ddr2_addr(DDR2ADDR),
.ddr2_ba(DDR2BA),
.ddr2_ras_n(DDR2RAS_N),
.ddr2_cas_n(DDR2CAS_N),
.ddr2_we_n(DDR2WE_N),
.ddr2_ck_p(DDR2CK_P),
.ddr2_ck_n(DDR2CK_N),
.ddr2_cke(DDR2CKE),
.ddr2_cs_n(DDR2CS_N),
.ddr2_dm(DDR2DM),
.ddr2_odt(DDR2ODT),
// Inputs
// Single-ended system clock
.sys_clk_i(clk200),
// Single-ended iodelayctrl clk (reference clock)
.clk_ref_i(clk200),
// user interface signals
.ui_clk(clk),
.ui_clk_sync_rst(ui_clk_sync_rst),
.mmcm_locked(),
.aresetn(rstn),
.app_sr_req(0),
.app_ref_req(0),
.app_zq_req(0),
.app_sr_active(),
.app_ref_ack(),
.app_zq_ack(),
// AXI
// AW CHANNEL
.s00_axi_awid(2'b00),
.s00_axi_awaddr(S_AXI_AW_ram[23:0]),
.s00_axi_awlen(S_AXI_AWLEN_ram),
.s00_axi_awsize(S_AXI_AWSIZE_ram),
.s00_axi_awburst(S_AXI_AWBURST_ram),
.s00_axi_awlock(1'b0),
.s00_axi_awcache(4'h0),
.s00_axi_awprot(3'h0),
.s00_axi_awqos(4'h0),
.s00_axi_awregion(4'h0),
.s00_axi_awuser(2'h0),
.s00_axi_awvalid(S_AXI_AWVALID_ram),
.s00_axi_awready(S_AXI_AWREADY_ram),
// W CHANNEL
.s00_axi_wdata(S_AXI_W_ram),
.s00_axi_wstrb(S_AXI_WSTRB_ram),
.s00_axi_wlast(S_AXI_WLAST_ram),
.s00_axi_wuser(2'b0),
.s00_axi_wvalid(S_AXI_WVALID_ram),
.s00_axi_wready(S_AXI_WREADY_ram),
// B CHANNEL
.s00_axi_bid(),
.s00_axi_bresp(),
.s00_axi_buser(),
.s00_axi_bvalid(),
.s00_axi_bready(1'b1),
// AR CHANNEL
.s00_axi_arid(2'b0),
.s00_axi_araddr(S_AXI_AR_ram[23:0]),
.s00_axi_arlen(S_AXI_ARLEN_ram),
.s00_axi_arsize(S_AXI_ARSIZE_ram),
.s00_axi_arburst(S_AXI_ARBURST_ram),
.s00_axi_arlock(1'b0),
.s00_axi_arcache(4'h0),
.s00_axi_arprot(3'h0),
.s00_axi_arqos(4'h0),
.s00_axi_arregion(4'h0),
.s00_axi_aruser(2'h0),
.s00_axi_arvalid(S_AXI_ARVALID_ram),
.s00_axi_arready(S_AXI_ARREADY_ram),
// R CHANNEL
.s00_axi_rid(),
.s00_axi_rdata(S_AXI_R_ram),
.s00_axi_rresp(),
.s00_axi_rlast(S_AXI_RLAST_ram),
.s00_axi_ruser(),
.s00_axi_rvalid(S_AXI_RVALID_ram),
.s00_axi_rready(S_AXI_RREADY_ram)
);
// AW CHANNEL
.s_axi_awid(4'b00),
.s_axi_awaddr(S_AXI_AW_ram),
.s_axi_awlen(S_AXI_AWLEN_ram),
.s_axi_awsize(S_AXI_AWSIZE_ram),
.s_axi_awburst(S_AXI_AWBURST_ram),
.s_axi_awlock(1'b0),
.s_axi_awcache(4'h0),
.s_axi_awprot(3'h0),
.s_axi_awqos(4'h0),
.s_axi_awvalid(S_AXI_AWVALID_ram),
.s_axi_awready(S_AXI_AWREADY_ram),
// W CHANNEL
.s_axi_wdata(S_AXI_W_ram),
.s_axi_wstrb(S_AXI_WSTRB_ram),
.s_axi_wlast(S_AXI_WLAST_ram),
.s_axi_wvalid(S_AXI_WVALID_ram),
.s_axi_wready(S_AXI_WREADY_ram),
// B CHANNEL
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b1),
// AR CHANNEL
.s_axi_arid(4'b0),
.s_axi_araddr(S_AXI_AR_ram),
.s_axi_arlen(S_AXI_ARLEN_ram),
.s_axi_arsize(S_AXI_ARSIZE_ram),
.s_axi_arburst(S_AXI_ARBURST_ram),
.s_axi_arlock(1'b0),
.s_axi_arcache(4'h0),
.s_axi_arprot(3'h0),
.s_axi_arqos(4'h0),
.s_axi_arvalid(S_AXI_ARVALID_ram),
.s_axi_arready(S_AXI_ARREADY_ram),
// R CHANNEL
.s_axi_rid(),
.s_axi_rdata(S_AXI_R_ram),
.s_axi_rresp(),
.s_axi_rlast(S_AXI_RLAST_ram),
.s_axi_rvalid(S_AXI_RVALID_ram),
.s_axi_rready(S_AXI_RREADY_ram),
.init_calib_complete(init_calib_complete),
.sys_rst(~locked)
);
 
axi_rom bootrom (
.clk(clk),
.rstn(rstn),
.rstn(rstn_ddr),
.axi_ARVALID(S_AXI_ARVALID_rom),
.axi_ARREADY(S_AXI_ARREADY_rom),
.axi_AR(S_AXI_AR_rom),
283,10 → 345,9
.axi_RREADY(S_AXI_RREADY_rom)
);
 
`ifndef simu
axi_ethernetlite_0 i_etherlite (
.s_axi_aclk(clk),
.s_axi_aresetn(rstn),
.s_axi_aresetn(rstn_ddr),
.ip2intc_irpt(int_net),
 
332,6 → 393,7
.phy_rx_er(rmii2mac_rx_er),
.phy_tx_en(mac2rmii_tx_en),
//.phy_tx_data(PhyTxd),
.phy_rst_n(PhyRstn),
.phy_mdio_i(PhyMdio_i),
.phy_mdio_o(PhyMdio_o),
338,75 → 400,7
.phy_mdio_t(PhyMdio_t),
.phy_mdc(PhyMdc)
);
`endif
 
`ifdef simu
axi_ethernetlite_0 i_etherlite (
.s_axi_aclk(clk),
.s_axi_aresetn(rstn),
.ip2intc_irpt(int_net),
 
.s_axi_awid(4'b000),
.s_axi_awaddr(S_AXI_AW_net[12:0]),
.s_axi_awlen(S_AXI_AWLEN_net),
.s_axi_awsize(S_AXI_AWSIZE_net),
.s_axi_awburst(S_AXI_AWBURST_net),
.s_axi_awcache(4'b0000),
.s_axi_awvalid(S_AXI_AWVALID_net),
.s_axi_awready(S_AXI_AWREADY_net),
.s_axi_wdata(S_AXI_W_net),
.s_axi_wstrb(S_AXI_WSTRB_net),
.s_axi_wlast(S_AXI_WLAST_net),
.s_axi_wvalid(S_AXI_WVALID_net),
.s_axi_wready(S_AXI_WREADY_net),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'b1),
.s_axi_arid(4'b0),
.s_axi_araddr(S_AXI_AR_net[12:0]),
.s_axi_arlen(S_AXI_ARLEN_net),
.s_axi_arsize(S_AXI_ARSIZE_net),
.s_axi_arburst(S_AXI_ARBURST_net),
.s_axi_arcache(4'b0),
.s_axi_arvalid(S_AXI_ARVALID_net),
.s_axi_arready(S_AXI_ARREADY_net),
.s_axi_rid(),
.s_axi_rdata(S_AXI_R_net),
.s_axi_rresp(),
.s_axi_rlast(S_AXI_RLAST_net),
.s_axi_rvalid(S_AXI_RVALID_net),
.s_axi_rready(S_AXI_RREADY_net),
// to RMII converter
//.phy_tx_clk(rmii2mac_tx_clk),
//.phy_rx_clk(rmii2mac_rx_clk),
.phy_tx_clk(PhyClk25Mhz),
.phy_rx_clk(PhyClk25Mhz),
//.phy_crs(rmii2mac_crs),
.phy_crs(1'b0),
//.phy_dv(rmii2mac_rx_dv),
.phy_dv(1'b0),
//.phy_rx_data(rmii2mac_rxd),
.phy_rx_data(4'b0),
.phy_tx_data(mac2rmii_txd),
//.phy_col(rmii2mac_col),
.phy_col(1'b0),
//.phy_rx_er(rmii2mac_rx_er),
.phy_rx_er(1'b0),
.phy_tx_en(mac2rmii_tx_en),
.phy_rst_n(PhyRstn),
//.phy_mdio_i(PhyMdio_i),
.phy_mdio_i(1'b0),
.phy_mdio_o(PhyMdio_o),
.phy_mdio_t(PhyMdio_t),
.phy_mdc(PhyMdc)
);
`endif
 
 
IOBUF i_iobuf_mdio(
.O(PhyMdio_i),
.IO(PhyMdio),
415,7 → 409,7
axi_crossbar_0 i_axi_crossbar_0 (
.aclk(clk),
.aresetn(rstn),
.aresetn(rstn_ddr),
.m_axi_awaddr({S_AXI_AW_net,S_AXI_AW_rom,S_AXI_AW_ram}),
.m_axi_awlen({S_AXI_AWLEN_net,S_AXI_AWLEN_rom,S_AXI_AWLEN_ram}),
473,12 → 467,9
);
 
 
always @(posedge clk) if (rstn == 0) sdreset <=1; else sdreset <=0;
always @(posedge clk) if (rstn == 0) PhyClk50Mhz <=0; else PhyClk50Mhz <=~PhyClk50Mhz;
always @(posedge clk) if (rstn == 0) PhyClk25Mhz <=0; else PhyClk25Mhz <=~PhyClk25Mhz;
always @(posedge clk) if (rstn_ddr == 0) sdreset <=1; else sdreset <=0;
always @(posedge clk) if (rstn_ddr == 0) PhyClk50Mhz <=0; else PhyClk50Mhz <=~PhyClk50Mhz;
 
assign extCLK = 0;
assign extDB = extOE ? extDBo : 32'bz ;
assign gpioA[0] = (gpioA_dir[0] == 0) ? 1'bz : gpioA_out[0];
assign gpioA[1] = (gpioA_dir[1] == 0) ? 1'bz : gpioA_out[1];
assign gpioA[2] = (gpioA_dir[2] == 0) ? 1'bz : gpioA_out[2];
499,7 → 490,7
assign sdhld = 1'b1;
 
periph i_periph (
.s00_AXI_RSTN(rstn),
.s00_AXI_RSTN(rstn_ddr),
.s00_AXI_CLK(clk),
.cfg(gpio_in[6:0]),
// spi

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