OpenCores

/trunk/mcs/v586_img.prm File deleted

/trunk/mcs/v586_img.cfi File deleted

/trunk/mcs/v586_img.mcs File deleted

/trunk/doc/v586_manual.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

trunk/doc/v586_manual.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/tb/run_sw.scr =================================================================== --- trunk/tb/run_sw.scr (revision 118) +++ trunk/tb/run_sw.scr (nonexistent) @@ -1,29 +0,0 @@ -echo "Generating vmlinux mem file for simulation ..." -ln -s ../bin/vmlinux.bin bin2v.bin -./bin2v.tcl -\cp bin2v-1.mem vmlinux-1.mem -\cp bin2v-2.mem vmlinux-2.mem -\cp bin2v-3.mem vmlinux-3.mem -\cp bin2v-4.mem vmlinux-4.mem -\rm bin2v.bin - -echo "Generating root mem file for simulation ..." -ln -s ../bin/root.bin bin2v.bin -./bin2v.tcl -\cp bin2v-1.mem root-1.mem -\cp bin2v-2.mem root-2.mem -\cp bin2v-3.mem root-3.mem -\cp bin2v-4.mem root-4.mem -\rm bin2v.bin - -echo "Generating boot mem file for simulation ..." -\rm test.asm -#gcc -m32 -c tests/test.s -o test.o -as ../boot/test.s -o test.o -objcopy -O ihex test.o test.ihex -objdump -m i8086 -d test.o > test.asm -./ihex2mem4.tcl -ihex test.ihex -out code.mem -mem_size 1024 -\cp code1.mem boot-1.mem -\cp code2.mem boot-2.mem -\cp code3.mem boot-3.mem -\cp code4.mem boot-4.mem Index: trunk/tb/ihex2mem4.tcl =================================================================== --- trunk/tb/ihex2mem4.tcl (revision 118) +++ trunk/tb/ihex2mem4.tcl (nonexistent) @@ -1,158 +0,0 @@ -#!/usr/bin/tclsh -#------------------------------------------------------------------------------ -# Copyright (C) 2001 Authors -# -# This source file may be used and distributed without restriction provided -# that this copyright statement is not removed from the file and that any -# derivative work contains the original copyright notice and the associated -# disclaimer. -# -# This source file is free software; you can redistribute it and/or modify -# it under the terms of the GNU Lesser General Public License as published -# by the Free Software Foundation; either version 2.1 of the License, or -# (at your option) any later version. -# -# This source is distributed in the hope that it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public -# License for more details. -# -# You should have received a copy of the GNU Lesser General Public License -# along with this source; if not, write to the Free Software Foundation, -# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -# -#------------------------------------------------------------------------------ -# -# File Name: ihex2mem.tcl -# -# Author(s): -# - Olivier Girard, olgirard@gmail.com -# -#------------------------------------------------------------------------------ -# $Rev: 17 $ -# $LastChangedBy: olivier.girard $ -# $LastChangedDate: 2009-08-04 14:15:39 -0700 (Tue, 04 Aug 2009) $ -#------------------------------------------------------------------------------ - -############################################################################### -# PARAMETER CHECK # -############################################################################### - -if {$argc != 6} { - puts "ERROR : wrong number of arguments" - puts "USAGE : ihex2mem.tcl -ihex -out -mem_size " - puts "Example : ihex2mem.tcl -ihex rom.ihex -out rom.mem -mem_size 2048" - exit 1 -} - -# default values -set ihex empty.in -set out empty.out -set mem_size -1 - -# parse arguments -for {set i 0} {$i < $argc} {incr i} { - switch -exact -- [lindex $argv $i] { - -ihex {set ihex [lindex $argv [expr $i+1]]; incr i} - -out {set out [lindex $argv [expr $i+1]]; incr i} - -mem_size {set mem_size [lindex $argv [expr $i+1]]; incr i} - } -} - -# Make sure arugments were specified -if {[string eq $ihex empty.in]} { - puts "IHEX input file isn't specified" - exit 1 -} -if {[string eq $out empty.out]} { - puts "MEMH output file isn't specified" - exit 1 -} -if {[string eq $mem_size -1]} { - puts "Memory size isn't specified" - exit 1 -} - - -############################################################################### -# CONVERSION PROCEDURE # -############################################################################### - -#-----------------------------------------------------------------------------# -# OPEN FILES # -#-----------------------------------------------------------------------------# - -# IHEX Input -if [catch {open $ihex r} f_ihex] { - puts "ERROR Cannot open input file $ihex" - exit 1 -} - -# MEMH Output -set f_out [open code.mem w] - -#-----------------------------------------------------------------------------# -# CONVERSION # -#-----------------------------------------------------------------------------# - - -# Conversions procedure -proc hex2dec { val } { - set val [format "%u" 0x[string trimleft $val]] - return $val -} - - -# Initialize memory array (8 bit words) -set num_word [expr ($mem_size)-1] -for {set i 0} {$i <= $num_word} {incr i} { - set mem_arr($i) 90909090 -} - - -# Calculate Address offset (offset=(0x10000-memory_size)) -set mem_offset 0 -set segment 0 - - -# Process input file -while {[gets $f_ihex line] >= 0} { - - # Process line - set byte_count [hex2dec [string range $line 1 2]] - set start_addr [expr ([hex2dec [string range $line 3 6]] + $mem_offset)] - set rec_type [string range $line 7 8] - if {[string compare $rec_type "02"] == 0} { set segment [expr $segment + 16384 ] } - - if {[string compare $rec_type "00"] == 0} { - for {set i 0} {$i < $byte_count*2} {set i [expr $i+2]} { - set mem_l [string range $line [expr $i+9] [expr $i+10]] - - if {[string length $mem_l] == 0} {set mem_l "90"} - - set addr [expr ($start_addr+$i/2) + $segment] - set mem_arr($addr) "$mem_l" - #puts "$addr $mem_l" - } - } -} -close $f_ihex - - -# Writing memory array to file -for {set i 0} {$i <= $num_word} {incr i} { - - puts $f_out " [format "%02s" [string range $mem_arr($i) 0 1] ]" -} - -puts $f_out "\n" - - -if { "$out"!="-"} { - close $f_out - -} - -exit 0 -Show details -

trunk/tb/ihex2mem4.tcl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/tb/extram.v =================================================================== --- trunk/tb/extram.v (revision 118) +++ trunk/tb/extram.v (nonexistent) @@ -1,65 +0,0 @@ -/* verilator lint_off UNUSED */ -/* verilator lint_off CASEX */ -module extram(clk,DB,A,UB,LB,WEN,OE); - -input clk; -input [23:0] A; -inout [15:0] DB; -input UB,LB; -input WEN; -input OE; - -reg [7:0] Mem1 [(4096*1024-1):0]; -reg [7:0] Mem2 [(4096*1024-1):0]; -reg [7:0] Mem3 [(4096*1024-1):0]; -reg [7:0] Mem4 [(4096*1024-1):0]; - -wire [21:0] A0; -reg [21:0] k; -reg A1r; -reg [31:0] Qint; - -assign A0 = A[23:2]; - -initial -begin -$display ("init ram..."); -for (k = 0; k < (4096*1024-1); k = k + 1) -begin - Mem1[k] = 255; - Mem2[k] = 255; - Mem3[k] = 255; - Mem4[k] = 255; -end -$display ("filled ram(s)..."); - -$readmemh("/home/leo/cpu/mem/vmlinux-1.mem", Mem1 , 32'h0100000/4); -$readmemh("/home/leo/cpu/mem/vmlinux-2.mem", Mem2 , 32'h0100000/4); -$readmemh("/home/leo/cpu/mem/vmlinux-3.mem", Mem3 , 32'h0100000/4); -$readmemh("/home/leo/cpu/mem/vmlinux-4.mem", Mem4 , 32'h0100000/4); - - -$readmemh("/home/leo/cpu/mem/root-1.mem" , Mem1 , 32'h0400000/4); -$readmemh("/home/leo/cpu/mem/root-2.mem" , Mem2 , 32'h0400000/4); -$readmemh("/home/leo/cpu/mem/root-3.mem" , Mem3 , 32'h0400000/4); -$readmemh("/home/leo/cpu/mem/root-4.mem" , Mem4 , 32'h0400000/4); - -end - -// Read process -always @(posedge clk) Qint[ 7: 0] <= Mem1[A0]; -always @(posedge clk) Qint[15: 8] <= Mem2[A0]; -always @(posedge clk) Qint[23:16] <= Mem3[A0]; -always @(posedge clk) Qint[31:24] <= Mem4[A0]; -always @(posedge clk) A1r <= A[1]; -assign DB = OE ? 16'bz : - A1r ? Qint[31:16] : Qint[15:0]; - -// Write Process -always @(posedge clk) if ((WEN == 0) && (LB==0) &&(A[1]==0)) Mem1[A0] <= DB[ 7: 0]; -always @(posedge clk) if ((WEN == 0) && (UB==0) &&(A[1]==0)) Mem2[A0] <= DB[15: 8]; - -always @(posedge clk) if ((WEN == 0) && (LB==0) &&(A[1]==1)) Mem3[A0] <= DB[ 7: 0]; -always @(posedge clk) if ((WEN == 0) && (UB==0) &&(A[1]==1)) Mem4[A0] <= DB[15: 8]; - -endmodule Index: trunk/tb/tb_top.v =================================================================== --- trunk/tb/tb_top.v (revision 118) +++ trunk/tb/tb_top.v (nonexistent) @@ -1,37 +0,0 @@ -/* verilator lint_off UNUSED */ -/* verilator lint_off CASEX */ -/* verilator lint_off PINNOCONNECT */ -/* verilator lint_off PINMISSING */ -/* verilator lint_off IMPLICIT */ -/* verilator lint_off WIDTH */ -/* verilator lint_off COMBDLY */ - -module tb_top (); -wire [1:0] Ae; -wire [15:0] DB; -wire [23:0] Ad; -wire LB,UB; -reg RXD,clk,rstn; - -TOP_SYS U_TOP ( -.TXD(TXD),.rstn(rstn),.clk100(clk), .RXD(RXD), -.extWEN(WEN),.extUB(UB),.extLB(LB),.extA(Ad),.extDB(DB), .extOE(OE), .extCRE(CRE), .extADV(ADV), .extCLK(memCLK),.extCSN(memCE), -.gpio_in(7'b000_0000)//, .extWAIT(1'b0) -); - -extram uextram(.clk(clk) , .DB(DB) , .A(Ad) , .WEN(WEN) ,.LB(LB), .UB(UB), .OE(OE) ); - -initial -begin -RXD =1; -clk=0; -rstn =0; -#1000; -rstn = 1; -#100000 -$finish; -end - -always #5 clk<=~clk; - -endmodule Index: trunk/tb/bin2v.tcl =================================================================== --- trunk/tb/bin2v.tcl (revision 118) +++ trunk/tb/bin2v.tcl (nonexistent) @@ -1,22 +0,0 @@ -#!/usr/bin/tclsh - -set fbin [open bin2v.bin r] -fconfigure $fbin -translation binary -set f_out [open bin2v.mem w] - -while (1) { - set line [read $fbin 1] - - if {[eof $fbin]} { - break - } - - binary scan $line H* value - puts $f_out $value -} - -close $f_out -close $fbin - -exit 0 -

trunk/tb/bin2v.tcl Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/bin/readme =================================================================== --- trunk/bin/readme (revision 118) +++ trunk/bin/readme (nonexistent) @@ -1,12 +0,0 @@ -mkdir temp -cd temp -cpio -idv < ../rootfs.cpio -\rm sbin/init -\rm init -cp ../init . -chmod ugo+rx init - -find . | cpio -H newc -o > ../initramfs.cpio -cd .. -cat initramfs.cpio | gzip > initramfs.igz - Index: trunk/bin/vmlinux.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/bin/vmlinux.bin =================================================================== --- trunk/bin/vmlinux.bin (revision 118) +++ trunk/bin/vmlinux.bin (nonexistent)

trunk/bin/vmlinux.bin Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: trunk/bin/root.bin =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/bin/root.bin =================================================================== --- trunk/bin/root.bin (revision 118) +++ trunk/bin/root.bin (nonexistent)

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-mov $0x0FFFF0,%edi -mov $0x0c8000,%esi -call fill_spi - -call banner - -mov $6,%al -mov $0x500,%edx -out %al,(%dx) -mov $2,%al -mov $0x500,%edx -out %al,(%dx) -movb $0x03,%bl -call send8b_spi -movb $0x7F,%bl -call send8b_spi -movb $0xFF,%bl -call send8b_spi -movb $0xF0,%bl -call send8b_spi - -mov $0x4FFFF0,%edi -mov $0x0c0000,%esi -call fill_spi - -call banner - -jmp boot_linux - -fill_spi: -call recv32b_spi -mov %ebx ,%eax -rol $8,%eax -mov %al , (%edi) -inc %edi -rol $8,%eax -mov %al , (%edi) -inc %edi -rol $8,%eax -mov %al , (%edi) -inc %edi -rol $8,%eax -mov %al , (%edi) -mov (%edi), %bl -cmp %al , %bl -jz okpass -push edi -push esi -call banner -pop esi -pop edi -okpass: -inc %edi -dec %esi -jnz fill_spi -ret - - -// send %bl to spi , msb first -send8b_spi: -movw $0x500,%dx -movb $8,%cl -rol $1,%bl -nextbit: -mov %bl , %al -and $1, %al -outb %al, (%dx) -or $2, %al -outb %al, (%dx) -xor $2, %al -outb %al, (%dx) -rol $1,%bl -dec %cl -jnz nextbit -ret - -//init spi -mov $6,%al -mov $0x500,%edx -out %al,(%dx) -mov $2,%al -mov $0x500,%edx -out %al,(%dx) -mov $0xF0,%bl -call sen8b_spi -mov $6,%al -mov $0x500,%edx -out %al,(%dx) -ret - - -// receive spi to %ebx -recv32b_spi: -movw $0x504,%dx -movb $32,%al -outb %al, (%dx) -mov $30,%ecx -waitloop: -dec %ecx -jnz waitloop -in (%dx), %eax -in (%dx), %eax -in (%dx), %eax -mov %eax,%ebx -ret - -boot_linux: -movl $0x1000, %esp - -call init_uart -/* setup ebda ptr at 0x40e*/ -movl $0x0fff00 , %ebx -movl $0x040e , %ecx -mov %ebx , (%ecx) - -/* eax = ram size */ -/* ebx = ramd size */ -/* ecx = ptr to cmdline */ - -mov $0x90000, %edi -mov $0x400 , %ecx -mov $0 , %eax -rep -stosl - -/* command line */ -mov $0x90800, %edi -mov %edi , 0x90228 -mov $0xfff20, %esi -mov $0x100 , %ecx -rep -movsb - -/* loader type */ -mov $1, %al -mov %eax , 0x90210 - -/* mem size */ -//movl $0x003c00 , %eax -movl $0x01fc00 , %eax - -mov %eax , 0x901e0 - -/* initrd start */ -mov $0x00500000 , %eax -/* mov $0, %eax */ -mov %eax , 0x90218 - -/* initrd size */ -movl $0x00300000 , %eax -/* movl $501047 , %eax */ -/* movl $0 , %eax */ -mov %eax , 0x9021c - -/* row cols */ -mov $80,%al -mov %al,0x90007 -mov $25,%al -mov %al,0x9000e - -call banner - -/* Jump to Uncompressed Kernel */ -movl $0x00090000, %esi -ljmp $0x10, $0x00100000 - -/* Other sub procs */ - -sendchar: -push %eax -push %edx -/* wait if there is character to be sent */ -wait_rdy: -movl $0x3fd, %edx -in (%dx),%al -andb $0x20,%al -jz wait_rdy -movl $0x3f8, %edx -mov %bl, %al -outb %al, (%dx) -pop %edx -pop %eax -ret - -init_uart: -/* set 8N1 flow dlab =1*/ -movl $0x3fb, %edx -movb $0x83 , %al -outb %al , (%dx) - -/* set DLL divisor 1 = 115200 bauds , 2= 57600 bauds , ...*/ -movl $0x3f8, %edx -movb $1 ,%al -outb %al , (%dx) -movl $0x3f9, %edx -movb $0 ,%al -outb %al , (%dx) - -/* set 8N1 flow dlab=0*/ -movl $0x3fb, %edx -movb $0x3 , %al -outb %al , (%dx) - -/* disable fifo*/ -movl $0x3fa, %edx -movb $0x7 , %al -outb %al , (%dx) - -/* */ -movb $0 ,%al -movl $0x3f9, %edx -outb %al , (%dx) -movl $0x3fc, %edx -outb %al , (%dx) -/* test char */ -movl $0x3f8, %edx -ret - -banner: -mov $0xfffb0, %esi -banner_loop: -movb (%esi),%bl -mov $0,%al -cmp %al,%bl -jz exit_banner -inc %esi -call sendchar -jmp banner_loop -exit_banner: -ret - -final: -jmp final - -/* ebda */ -.org 0x0300 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 -.byte 0 - -/* cmdline */ -.org 0x0320 -.asciz "console=ttyS0,115200n8 root=/dev/ram0 rw" - -/* banner */ -.org 0x03b0 -.ascii "Boot step.." -.byte 10 -.byte 13 -.byte 0 - -/* init jump bios */ -.org 0x3d0 -.code16 -start2: -jmp start - -.org 0x3f0 -.code16 -jmp start2 Index: trunk/uart_16750/slib_fifo_cyclone2.vhd =================================================================== --- trunk/uart_16750/slib_fifo_cyclone2.vhd (revision 118) +++ trunk/uart_16750/slib_fifo_cyclone2.vhd (nonexistent) @@ -1,85 +0,0 @@ --- --- FIFO (using Altera scfifo for Cyclone II) --- --- Author: Sebastian Witt --- Date: 07.03.2008 --- Version: 1.0 --- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -entity slib_fifo is - generic ( - WIDTH : integer := 8; -- FIFO width - SIZE_E : integer := 6 -- FIFO size (2^SIZE_E) - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear FIFO - WRITE : in std_logic; -- Write to FIFO - READ : in std_logic; -- Read from FIFO - D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input - Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output - EMPTY : out std_logic; -- FIFO is empty - FULL : out std_logic; -- FIFO is full - USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage - ); -end slib_fifo; - -architecture altera of slib_fifo is - COMPONENT scfifo - GENERIC ( - add_ram_output_register : STRING; - intended_device_family : STRING; - lpm_numwords : NATURAL; - lpm_showahead : STRING; - lpm_type : STRING; - lpm_width : NATURAL; - lpm_widthu : NATURAL; - overflow_checking : STRING; - underflow_checking : STRING; - use_eab : STRING - ); - PORT ( - usedw : OUT STD_LOGIC_VECTOR (SIZE_E-1 DOWNTO 0); - rdreq : IN STD_LOGIC ; - sclr : IN STD_LOGIC ; - empty : OUT STD_LOGIC ; - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0); - wrreq : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0); - full : OUT STD_LOGIC - ); - END COMPONENT; - -begin - scfifo_component : scfifo - GENERIC MAP ( - add_ram_output_register => "OFF", - intended_device_family => "Cyclone II", - lpm_numwords => 2**SIZE_E, - lpm_showahead => "ON", - lpm_type => "scfifo", - lpm_width => WIDTH, - lpm_widthu => SIZE_E, - overflow_checking => "ON", - underflow_checking => "ON", - use_eab => "ON" - ) - PORT MAP ( - rdreq => READ, - sclr => CLEAR, - clock => CLK, - wrreq => WRITE, - data => D, - usedw => USAGE, - empty => EMPTY, - q => Q, - full => FULL - ); -end altera; - - Index: trunk/uart_16750/slib_fifo.vhd =================================================================== --- trunk/uart_16750/slib_fifo.vhd (revision 118) +++ trunk/uart_16750/slib_fifo.vhd (nonexistent) @@ -1,132 +0,0 @@ --- --- FIFO --- --- Author: Sebastian Witt --- Date: 29.01.2008 --- Version: 1.3 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - - -entity slib_fifo is - generic ( - WIDTH : integer := 8; -- FIFO width - SIZE_E : integer := 6 -- FIFO size (2^SIZE_E) - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear FIFO - WRITE : in std_logic; -- Write to FIFO - READ : in std_logic; -- Read from FIFO - D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input - Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output - EMPTY : out std_logic; -- FIFO is empty - FULL : out std_logic; -- FIFO is full - USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage - ); -end slib_fifo; - -architecture rtl of slib_fifo is - -- Signals - signal iEMPTY : std_logic; -- Internal EMPTY - signal iFULL : std_logic; -- Internal FULL - signal iWRAddr : unsigned(SIZE_E downto 0); -- FIFO write address - signal iRDAddr : unsigned(SIZE_E downto 0); -- FIFO read address - signal iUSAGE : unsigned(SIZE_E-1 downto 0); -- FIFO usage - -- FIFO memory - type FIFO_Mem_Type is array (2**SIZE_E-1 downto 0) of std_logic_vector(WIDTH-1 downto 0); - signal iFIFOMem : FIFO_Mem_Type := (others => (others => '0')); - -begin - -- Full signal (biggest difference of read and write address) - iFULL <= '1' when (iRDAddr(SIZE_E-1 downto 0) = iWRAddr(SIZE_E-1 downto 0)) and - (iRDAddr(SIZE_E) /= iWRAddr(SIZE_E)) else '0'; - - -- Write/read address counter and empty signal - FF_ADDR: process (RST, CLK) - begin - if (RST = '1') then - iWRAddr <= (others => '0'); - iRDAddr <= (others => '0'); - iEMPTY <= '1'; - elsif (CLK'event and CLK='1') then - if (WRITE = '1' and iFULL = '0') then -- Write to FIFO - iWRAddr <= iWRAddr + 1; - end if; - - if (READ = '1' and iEMPTY = '0') then -- Read from FIFO - iRDAddr <= iRDAddr + 1; - end if; - - if (CLEAR = '1') then -- Reset FIFO - iWRAddr <= (others => '0'); - iRDAddr <= (others => '0'); - end if; - - if (iRDAddr = iWRAddr) then -- Empty signal (read address same as write address) - iEMPTY <= '1'; - else - iEMPTY <= '0'; - end if; - end if; - end process; - - -- FIFO memory process - FF_MEM: process (RST, CLK) - begin - if (RST = '1') then - --iFIFOMem(2**SIZE_E-1 downto 0) <= (others => (others => '0')); - elsif (CLK'event and CLK = '1') then - if (WRITE = '1' and iFULL = '0') then - iFIFOMem(to_integer(iWRAddr(SIZE_E-1 downto 0))) <= D; - end if; - Q <= iFIFOMem(to_integer(iRDAddr(SIZE_E-1 downto 0))); - end if; - end process; - - -- Usage counter - FF_USAGE: process (RST, CLK) - begin - if (RST = '1') then - iUSAGE <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (CLEAR = '1') then - iUSAGE <= (others => '0'); - else - if (READ = '0' and WRITE = '1' and iFULL = '0') then - iUSAGE <= iUSAGE + 1; - end if; - if (WRITE = '0' and READ = '1' and iEMPTY = '0') then - iUSAGE <= iUSAGE - 1; - end if; - end if; - end if; - end process; - - -- Output signals - EMPTY <= iEMPTY; - FULL <= iFULL; - USAGE <= std_logic_vector(iUSAGE); - -end rtl; - - Index: trunk/uart_16750/uart_16750.vhd =================================================================== --- trunk/uart_16750/uart_16750.vhd (revision 118) +++ trunk/uart_16750/uart_16750.vhd (nonexistent) @@ -1,1050 +0,0 @@ --- --- UART 16750 --- --- Author: Sebastian Witt --- Date: 29.01.2008 --- Version: 1.5 --- --- History: 1.0 - Initial version --- 1.1 - THR empty interrupt register connected to RST --- 1.2 - Registered outputs --- 1.3 - Automatic flow control --- 1.4 - De-assert IIR FIFO64 when FIFO is disabled --- 1.5 - Inverted low active outputs when RST is active --- --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART -entity uart_16750 is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - BAUDCE : in std_logic; -- Baudrate generator clock enable - CS : in std_logic; -- Chip select - WR : in std_logic; -- Write to UART - RD : in std_logic; -- Read from UART - A : in std_logic_vector(2 downto 0); -- Register select - DIN : in std_logic_vector(7 downto 0); -- Data bus input - DOUT : out std_logic_vector(7 downto 0); -- Data bus output - DDIS : out std_logic; -- Driver disable - INT : out std_logic; -- Interrupt output - OUT1N : out std_logic; -- Output 1 - OUT2N : out std_logic; -- Output 2 - RCLK : in std_logic; -- Receiver clock (16x baudrate) - BAUDOUTN : out std_logic; -- Baudrate generator output (16x baudrate) - RTSN : out std_logic; -- RTS output - DTRN : out std_logic; -- DTR output - CTSN : in std_logic; -- CTS input - DSRN : in std_logic; -- DSR input - DCDN : in std_logic; -- DCD input - RIN : in std_logic; -- RI input - SIN : in std_logic; -- Receiver input - SOUT : out std_logic -- Transmitter output - ); -end uart_16750; - -architecture rtl of uart_16750 is - -- UART transmitter - component uart_transmitter is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - TXCLK : in std_logic; -- Transmitter clock (2x baudrate) - TXSTART : in std_logic; -- Start transmitter - CLEAR : in std_logic; -- Clear transmitter state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - BC : in std_logic; -- Break control - DIN : in std_logic_vector(7 downto 0); -- Input data - TXFINISHED : out std_logic; -- Transmitter operation finished - SOUT : out std_logic -- Transmitter output - ); - end component; - -- UART receiver - component uart_receiver is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - RXCLK : in std_logic; -- Receiver clock (16x baudrate) - RXCLEAR : in std_logic; -- Reset receiver state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - SIN : in std_logic; -- Receiver input - PE : out std_logic; -- Parity error - FE : out std_logic; -- Framing error - BI : out std_logic; -- Break interrupt - DOUT : out std_logic_vector(7 downto 0); -- Output data - RXFINISHED : out std_logic -- Receiver operation finished - ); - end component; - -- UART interrupt control - component uart_interrupt is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - IER : in std_logic_vector(3 downto 0); -- IER 3:0 - LSR : in std_logic_vector(4 downto 0); -- LSR 4:0 - THI : in std_logic; -- Transmitter holding register empty interrupt - RDA : in std_logic; -- Receiver data available - CTI : in std_logic; -- Character timeout indication - AFE : in std_logic; -- Automatic flow control enable - MSR : in std_logic_vector(3 downto 0); -- MSR 3:0 - IIR : out std_logic_vector(3 downto 0); -- IIR 3:0 - INT : out std_logic -- Interrupt - ); - end component; - -- UART baudrate generator - component uart_baudgen is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - CLEAR : in std_logic; -- Reset generator (synchronization) - DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider - BAUDTICK : out std_logic -- 16xBaudrate tick - ); - end component; - -- UART FIFO - component slib_fifo is - generic ( - WIDTH : integer := 8; -- FIFO width - SIZE_E : integer := 6 -- FIFO size (2^SIZE_E) - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear FIFO - WRITE : in std_logic; -- Write to FIFO - READ : in std_logic; -- Read from FIFO - D : in std_logic_vector(WIDTH-1 downto 0); -- FIFO input - Q : out std_logic_vector(WIDTH-1 downto 0); -- FIFO output - EMPTY : out std_logic; -- FIFO is empty - FULL : out std_logic; -- FIFO is full - USAGE : out std_logic_vector(SIZE_E-1 downto 0) -- FIFO usage - ); - end component; - -- Edge detect - component slib_edge_detect is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - RE : out std_logic; -- Rising edge detected - FE : out std_logic -- Falling edge detected - ); - end component; - -- Input synchronization - component slib_input_sync is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); - end component; - -- Input filter - component slib_input_filter is - generic ( - SIZE : natural := 4 -- Filter width - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); - end component; - -- Clock enable generation - component slib_clock_div is - generic ( - RATIO : integer := 8 -- Clock divider ratio - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable input - Q : out std_logic -- New clock enable output - ); - end component; - - -- Global device signals - signal iCSWR : std_logic; -- Chipselect and write - signal iCSRD : std_logic; -- Chipselect and read - signal iWriteFE : std_logic; -- Write falling edge - signal iReadFE : std_logic; -- Read falling edge - signal iWrite : std_logic; -- Write to UART - signal iRead : std_logic; -- Read from UART - signal iA : std_logic_vector(2 downto 0); -- UART register address - signal iDIN : std_logic_vector(7 downto 0); -- UART data input - - -- UART registers read/write signals - signal iRBRRead : std_logic; -- Read from RBR - signal iTHRWrite : std_logic; -- Write to THR - signal iDLLWrite : std_logic; -- Write to DLL - signal iDLMWrite : std_logic; -- Write to DLM - signal iIERWrite : std_logic; -- Write to IER - signal iIIRRead : std_logic; -- Read from IIR - signal iFCRWrite : std_logic; -- Write to FCR - signal iLCRWrite : std_logic; -- Write to LCR - signal iMCRWrite : std_logic; -- Write to MCR - signal iLSRRead : std_logic; -- Read from LSR - signal iMSRRead : std_logic; -- Read from MSR - signal iSCRWrite : std_logic; -- Write to SCR - - -- UART registers - signal iTSR : std_logic_vector(7 downto 0); -- Transmitter holding register - signal iRBR : std_logic_vector(7 downto 0); -- Receiver buffer register - signal iDLL : std_logic_vector(7 downto 0); -- Divisor latch LSB - signal iDLM : std_logic_vector(7 downto 0); -- Divisor latch MSB - signal iIER : std_logic_vector(7 downto 0); -- Interrupt enable register - signal iIIR : std_logic_vector(7 downto 0); -- Interrupt identification register - signal iFCR : std_logic_vector(7 downto 0); -- FIFO control register - signal iLCR : std_logic_vector(7 downto 0); -- Line control register - signal iMCR : std_logic_vector(7 downto 0); -- Modem control register - signal iLSR : std_logic_vector(7 downto 0); -- Line status register - signal iMSR : std_logic_vector(7 downto 0); -- Modem status register - signal iSCR : std_logic_vector(7 downto 0); -- Scratch register - - -- IER register signals - signal iIER_ERBI : std_logic; -- IER: Enable received data available interrupt - signal iIER_ETBEI : std_logic; -- IER: Enable transmitter holding register empty interrupt - signal iIER_ELSI : std_logic; -- IER: Enable receiver line status interrupt - signal iIER_EDSSI : std_logic; -- IER: Enable modem status interrupt - - -- IIR register signals - signal iIIR_PI : std_logic; -- IIR: Pending interrupt - signal iIIR_ID0 : std_logic; -- IIR: Interrupt ID0 - signal iIIR_ID1 : std_logic; -- IIR: Interrupt ID1 - signal iIIR_ID2 : std_logic; -- IIR: Interrupt ID2 - signal iIIR_FIFO64 : std_logic; -- IIR: 64 byte FIFO enabled - - -- FCR register signals - signal iFCR_FIFOEnable : std_logic; -- FCR: FIFO enable - signal iFCR_RXFIFOReset : std_logic; -- FCR: Receiver FIFO reset - signal iFCR_TXFIFOReset : std_logic; -- FCR: Transmitter FIFO reset - signal iFCR_DMAMode : std_logic; -- FCR: DMA mode select - signal iFCR_FIFO64E : std_logic; -- FCR: 64 byte FIFO enable - signal iFCR_RXTrigger : std_logic_vector(1 downto 0); -- FCR: Receiver trigger - - -- LCR register signals - signal iLCR_WLS : std_logic_vector(1 downto 0); -- LCR: Word length select - signal iLCR_STB : std_logic; -- LCR: Number of stop bits - signal iLCR_PEN : std_logic; -- LCR: Parity enable - signal iLCR_EPS : std_logic; -- LCR: Even parity select - signal iLCR_SP : std_logic; -- LCR: Sticky parity - signal iLCR_BC : std_logic; -- LCR: Break control - signal iLCR_DLAB : std_logic; -- LCR: Divisor latch access bit - - -- MCR register signals - signal iMCR_DTR : std_logic; -- MCR: Data terminal ready - signal iMCR_RTS : std_logic; -- MCR: Request to send - signal iMCR_OUT1 : std_logic; -- MCR: OUT1 - signal iMCR_OUT2 : std_logic; -- MCR: OUT2 - signal iMCR_LOOP : std_logic; -- MCR: Loop - signal iMCR_AFE : std_logic; -- MCR: Auto flow control enable - - -- LSR register signals - signal iLSR_DR : std_logic; -- LSR: Data ready - signal iLSR_OE : std_logic; -- LSR: Overrun error - signal iLSR_PE : std_logic; -- LSR: Parity error - signal iLSR_FE : std_logic; -- LSR: Framing error - signal iLSR_BI : std_logic; -- LSR: Break Interrupt - signal iLSR_THRE : std_logic; -- LSR: Transmitter holding register empty - signal iLSR_TEMT : std_logic; -- LSR: Transmitter empty - signal iLSR_FIFOERR : std_logic; -- LSR: Error in receiver FIFO - - -- MSR register signals - signal iMSR_dCTS : std_logic; -- MSR: Delta CTS - signal iMSR_dDSR : std_logic; -- MSR: Delta DSR - signal iMSR_TERI : std_logic; -- MSR: Trailing edge ring indicator - signal iMSR_dDCD : std_logic; -- MSR: Delta DCD - signal iMSR_CTS : std_logic; -- MSR: CTS - signal iMSR_DSR : std_logic; -- MSR: DSR - signal iMSR_RI : std_logic; -- MSR: RI - signal iMSR_DCD : std_logic; -- MSR: DCD - - -- UART MSR signals - signal iCTSNs : std_logic; -- Synchronized CTSN input - signal iDSRNs : std_logic; -- Synchronized DSRN input - signal iDCDNs : std_logic; -- Synchronized DCDN input - signal iRINs : std_logic; -- Synchronized RIN input - signal iCTSn : std_logic; -- Filtered CTSN input - signal iDSRn : std_logic; -- Filtered DSRN input - signal iDCDn : std_logic; -- Filtered DCDN input - signal iRIn : std_logic; -- Filtered RIN input - signal iCTSnRE : std_logic; -- CTSn rising edge - signal iCTSnFE : std_logic; -- CTSn falling edge - signal iDSRnRE : std_logic; -- DSRn rising edge - signal iDSRnFE : std_logic; -- DSRn falling edge - signal iDCDnRE : std_logic; -- DCDn rising edge - signal iDCDnFE : std_logic; -- DCDn falling edge - signal iRInRE : std_logic; -- RIn rising edge - signal iRInFE : std_logic; -- RIn falling edge - - -- UART baudrate generation signals - signal iBaudgenDiv : std_logic_vector(15 downto 0); -- Baudrate divider - signal iBaudtick16x : std_logic; -- 16x Baudrate output from baudrate generator - signal iBaudtick2x : std_logic; -- 2x Baudrate for transmitter - signal iRCLK : std_logic; -- 16x Baudrate for receiver - - -- UART FIFO signals - signal iTXFIFOClear : std_logic; -- Clear TX FIFO - signal iTXFIFOWrite : std_logic; -- Write to TX FIFO - signal iTXFIFORead : std_logic; -- Read from TX FIFO - signal iTXFIFOEmpty : std_logic; -- TX FIFO is empty - signal iTXFIFOFull : std_logic; -- TX FIFO is full - signal iTXFIFO16Full : std_logic; -- TX FIFO 16 byte mode is full - signal iTXFIFO64Full : std_logic; -- TX FIFO 64 byte mode is full - signal iTXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage - signal iTXFIFOQ : std_logic_vector(7 downto 0); -- TX FIFO output - signal iRXFIFOClear : std_logic; -- Clear RX FIFO - signal iRXFIFOWrite : std_logic; -- Write to RX FIFO - signal iRXFIFORead : std_logic; -- Read from RX FIFO - signal iRXFIFOEmpty : std_logic; -- RX FIFO is empty - signal iRXFIFOFull : std_logic; -- RX FIFO is full - signal iRXFIFO16Full : std_logic; -- RX FIFO 16 byte mode is full - signal iRXFIFO64Full : std_logic; -- RX FIFO 64 byte mode is full - signal iRXFIFOD : std_logic_vector(10 downto 0); -- RX FIFO input - signal iRXFIFOQ : std_logic_vector(10 downto 0); -- RX FIFO output - signal iRXFIFOUsage : std_logic_vector(5 downto 0); -- RX FIFO usage - signal iRXFIFOTrigger : std_logic; -- FIFO trigger level reached - signal iRXFIFO16Trigger : std_logic; -- FIFO 16 byte mode trigger level reached - signal iRXFIFO64Trigger : std_logic; -- FIFO 64 byte mode trigger level reached - signal iRXFIFOPE : std_logic; -- Parity error from FIFO - signal iRXFIFOFE : std_logic; -- Frame error from FIFO - signal iRXFIFOBI : std_logic; -- Break interrupt from FIFO - - -- UART transmitter signals - signal iSOUT : std_logic; -- Transmitter output - signal iTXStart : std_logic; -- Start transmitter - signal iTXClear : std_logic; -- Clear transmitter status - signal iTXFinished : std_logic; -- TX finished, character transmitted - signal iTXRunning : std_logic; -- TX in progress - - -- UART receiver signals - signal iSINr : std_logic; -- Synchronized SIN input - signal iSIN : std_logic; -- Receiver input - signal iRXFinished : std_logic; -- RX finished, character received - signal iRXClear : std_logic; -- Clear receiver status - signal iRXData : std_logic_vector(7 downto 0); -- RX data - signal iRXPE : std_logic; -- RX parity error - signal iRXFE : std_logic; -- RX frame error - signal iRXBI : std_logic; -- RX break interrupt - - -- UART control signals - signal iFERE : std_logic; -- Frame error detected - signal iPERE : std_logic; -- Parity error detected - signal iBIRE : std_logic; -- Break interrupt detected - signal iFECounter : integer range 0 to 64; -- FIFO error counter - signal iFEIncrement : std_logic; -- FIFO error counter increment - signal iFEDecrement : std_logic; -- FIFO error counter decrement - signal iRDAInterrupt : std_logic; -- Receiver data available interrupt (DA or FIFO trigger level) - signal iTimeoutCount : unsigned(5 downto 0); -- Character timeout counter (FIFO mode) - signal iCharTimeout : std_logic; -- Character timeout indication (FIFO mode) - signal iLSR_THRERE : std_logic; -- LSR THRE rising edge for interrupt generation - signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt - signal iTXEnable : std_logic; -- Transmitter enable signal - signal iRTS : std_logic; -- Internal RTS signal with/without automatic flow control - - -begin - - -- Global device signals - iCSWR <= '1' when CS = '1' and WR = '1' else '0'; - iCSRD <= '1' when CS = '1' and RD = '1' else '0'; - UART_ED_WRITE: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSWR, FE => iWriteFE); - UART_ED_READ: slib_edge_detect port map (CLK => CLK, RST => RST, D => iCSRD, FE => iReadFE); - iWrite <= '1' when iWriteFE = '1' else '0'; - iRead <= '1' when iReadFE = '1' else '0'; - - -- UART registers read/write signals - iRBRRead <= '1' when iRead = '1' and iA = "000" and iLCR_DLAB = '0' else '0'; - iTHRWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '0' else '0'; - iDLLWrite <= '1' when iWrite = '1' and iA = "000" and iLCR_DLAB = '1' else '0'; - iDLMWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '1' else '0'; - iIERWrite <= '1' when iWrite = '1' and iA = "001" and iLCR_DLAB = '0' else '0'; - iIIRRead <= '1' when iRead = '1' and iA = "010" else '0'; - iFCRWrite <= '1' when iWrite = '1' and iA = "010" else '0'; - iLCRWrite <= '1' when iWrite = '1' and iA = "011" else '0'; - iMCRWrite <= '1' when iWrite = '1' and iA = "100" else '0'; - iLSRRead <= '1' when iRead = '1' and iA = "101" else '0'; - iMSRRead <= '1' when iRead = '1' and iA = "110" else '0'; - iSCRWrite <= '1' when iWrite = '1' and iA = "111" else '0'; - - -- Async. input synchronization - UART_IS_SIN: slib_input_sync port map (CLK, RST, SIN, iSINr); - UART_IS_CTS: slib_input_sync port map (CLK, RST, CTSN, iCTSNs); - UART_IS_DSR: slib_input_sync port map (CLK, RST, DSRN, iDSRNs); - UART_IS_DCD: slib_input_sync port map (CLK, RST, DCDN, iDCDNs); - UART_IS_RI: slib_input_sync port map (CLK, RST, RIN, iRINs); - - -- Input filter for UART control signals - UART_IF_CTS: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iCTSNs, iCTSn); - UART_IF_DSR: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDSRNs, iDSRn); - UART_IF_DCD: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iDCDNs, iDCDn); - UART_IF_RI: slib_input_filter generic map (SIZE => 2) port map (CLK, RST, iBaudtick2x, iRINs, iRIn); - - -- Sync. input synchronization - UART_SIS: process (CLK, RST) - begin - if (RST = '1') then - iA <= (others => '0'); - iDIN <= (others => '0'); - elsif (CLK'event and CLK = '1') then - iA <= A; - iDIN <= DIN; - end if; - end process; - - - -- Divisor latch register - UART_DLR: process (CLK, RST) - begin - if (RST = '1') then - iDLL <= (others => '0'); - iDLM <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iDLLWrite = '1') then - iDLL <= iDIN; - end if; - if (iDLMWrite = '1') then - iDLM <= iDIN; - end if; - end if; - end process; - - -- Interrupt enable register - UART_IER: process (CLK, RST) - begin - if (RST = '1') then - iIER(3 downto 0) <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iIERWrite = '1') then - iIER(3 downto 0) <= iDIN(3 downto 0); - end if; - end if; - end process; - - iIER_ERBI <= iIER(0); - iIER_ETBEI <= iIER(1); - iIER_ELSI <= iIER(2); - iIER_EDSSI <= iIER(3); - iIER(7 downto 4) <= (others => '0'); - - -- Interrupt control and IIR - UART_IIC: uart_interrupt port map (CLK => CLK, - RST => RST, - IER => iIER(3 downto 0), - LSR => iLSR(4 downto 0), - THI => iTHRInterrupt, - RDA => iRDAInterrupt, - CTI => iCharTimeout, - AFE => iMCR_AFE, - MSR => iMSR(3 downto 0), - IIR => iIIR(3 downto 0), - INT => INT - ); - -- THR empty interrupt - UART_IIC_THRE_ED: slib_edge_detect port map (CLK => CLK, RST => RST, D => iLSR_THRE, RE => iLSR_THRERE); - UART_IIC_THREI: process (CLK, RST) - begin - if (RST = '1') then - iTHRInterrupt <= '0'; - elsif (CLK'event and CLK = '1') then - if (iLSR_THRERE = '1' or iFCR_TXFIFOReset = '1' or (iIERWrite = '1' and iDIN(1) = '1' and iLSR_THRE = '1')) then - iTHRInterrupt <= '1'; -- Set on THRE, TX FIFO reset (FIFO enable) or ETBEI enable - elsif ((iIIRRead = '1' and iIIR(3 downto 1) = "001") or iTHRWrite = '1') then - iTHRInterrupt <= '0'; -- Clear on IIR read (if source of interrupt) or THR write - end if; - end if; - end process; - - iRDAInterrupt <= '1' when (iFCR_FIFOEnable = '0' and iLSR_DR = '1') or - (iFCR_FIFOEnable = '1' and iRXFIFOTrigger = '1') else '0'; - iIIR_PI <= iIIR(0); - iIIR_ID0 <= iIIR(1); - iIIR_ID1 <= iIIR(2); - iIIR_ID2 <= iIIR(3); - iIIR_FIFO64 <= iIIR(5); - iIIR(4) <= '0'; - iIIR(5) <= iFCR_FIFO64E when iFCR_FIFOEnable = '1' else '0'; - iIIR(6) <= iFCR_FIFOEnable; - iIIR(7) <= iFCR_FIFOEnable; - - -- Character timeout indication - UART_CTI: process (CLK, RST) - begin - if (RST = '1') then - iTimeoutCount <= (others => '0'); - iCharTimeout <= '0'; - elsif (CLK'event and CLK = '1') then - if (iRXFIFOEmpty = '1' or iRBRRead = '1' or iRXFIFOWrite = '1') then - iTimeoutCount <= (others => '0'); - elsif (iRXFIFOEmpty = '0' and iBaudtick2x = '1' and iTimeoutCount(5) = '0') then - iTimeoutCount <= iTimeoutCount + 1; - end if; - - -- Timeout indication - if (iFCR_FIFOEnable = '1') then - if (iRBRRead = '1') then - iCharTimeout <= '0'; - elsif (iTimeoutCount(5) = '1') then - iCharTimeout <= '1'; - end if; - else - iCharTimeout <= '0'; - end if; - end if; - end process; - - -- FIFO control register - UART_FCR: process (CLK, RST) - begin - if (RST = '1') then - iFCR_FIFOEnable <= '0'; - iFCR_RXFIFOReset <= '0'; - iFCR_TXFIFOReset <= '0'; - iFCR_DMAMode <= '0'; - iFCR_FIFO64E <= '0'; - iFCR_RXTrigger <= (others => '0'); - elsif (CLK'event and CLK = '1') then - -- FIFO reset pulse only - iFCR_RXFIFOReset <= '0'; - iFCR_TXFIFOReset <= '0'; - - if (iFCRWrite = '1') then - iFCR_FIFOEnable <= iDIN(0); - iFCR_DMAMode <= iDIN(3); - iFCR_RXTrigger <= iDIN(7 downto 6); - - if (iLCR_DLAB = '1') then - iFCR_FIFO64E <= iDIN(5); - end if; - - -- RX FIFO reset control, reset on FIFO enable/disable - if (iDIN(1) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then - iFCR_RXFIFOReset <= '1'; - end if; - -- TX FIFO reset control, reset on FIFO enable/disable - if (iDIN(2) = '1' or (iFCR_FIFOEnable = '0' and iDIN(0) = '1') or (iFCR_FIFOEnable = '1' and iDIN(0) = '0')) then - iFCR_TXFIFOReset <= '1'; - end if; - end if; - end if; - end process; - - iFCR(0) <= iFCR_FIFOEnable; - iFCR(1) <= iFCR_RXFIFOReset; - iFCR(2) <= iFCR_TXFIFOReset; - iFCR(3) <= iFCR_DMAMode; - iFCR(4) <= '0'; - iFCR(5) <= iFCR_FIFO64E; - iFCR(7 downto 6) <= iFCR_RXTrigger; - - -- Line control register - UART_LCR: process (CLK, RST) - begin - if (RST = '1') then - iLCR <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iLCRWrite = '1') then - iLCR <= iDIN; - end if; - end if; - end process; - - iLCR_WLS <= iLCR(1 downto 0); - iLCR_STB <= iLCR(2); - iLCR_PEN <= iLCR(3); - iLCR_EPS <= iLCR(4); - iLCR_SP <= iLCR(5); - iLCR_BC <= iLCR(6); - iLCR_DLAB <= iLCR(7); - - -- Modem control register - UART_MCR: process (CLK, RST) - begin - if (RST = '1') then - iMCR(5 downto 0) <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iMCRWrite = '1') then - iMCR(5 downto 0) <= iDIN(5 downto 0); - end if; - end if; - end process; - - iMCR_DTR <= iMCR(0); - iMCR_RTS <= iMCR(1); - iMCR_OUT1 <= iMCR(2); - iMCR_OUT2 <= iMCR(3); - iMCR_LOOP <= iMCR(4); - iMCR_AFE <= iMCR(5); - iMCR(6) <= '0'; - iMCR(7) <= '0'; - - -- Line status register - UART_LSR: process (CLK, RST) - begin - if (RST = '1') then - iLSR_OE <= '0'; - iLSR_PE <= '0'; - iLSR_FE <= '0'; - iLSR_BI <= '0'; - iFECounter <= 0; - elsif (CLK'event and CLK = '1') then - -- Overrun error - if ((iFCR_FIFOEnable = '0' and iLSR_DR = '1' and iRXFinished = '1') or - (iFCR_FIFOEnable = '1' and iRXFIFOFull = '1' and iRXFinished = '1')) then - iLSR_OE <= '1'; - elsif (iLSRRead = '1') then - iLSR_OE <= '0'; - end if; - -- Parity error - if (iPERE = '1') then - iLSR_PE <= '1'; - elsif (iLSRRead = '1') then - iLSR_PE <= '0'; - end if; - -- Frame error - if (iFERE = '1') then - iLSR_FE <= '1'; - elsif (iLSRRead = '1') then - iLSR_FE <= '0'; - end if; - -- Break interrupt - if (iBIRE = '1') then - iLSR_BI <= '1'; - elsif (iLSRRead = '1') then - iLSR_BI <= '0'; - end if; - - -- FIFO error - -- Datasheet: Cleared by LSR read when no subsequent errors in FIFO - -- Observed: Cleared when no subsequent errors in FIFO - if (iFECounter /= 0) then - iLSR_FIFOERR <= '1'; - --elsif (iLSRRead = '1' and iFECounter = 0 and not (iRXFIFOEmpty = '0' and iRXFIFOQ(10 downto 8) /= "000")) then - elsif (iRXFIFOEmpty = '1' or iRXFIFOQ(10 downto 8) = "000") then - iLSR_FIFOERR <= '0'; - end if; - - -- FIFO error counter - if (iRXFIFOClear = '1') then - iFECounter <= 0; - else - if (iFEIncrement = '1' and iFEDecrement = '0') then - iFECounter <= iFECounter + 1; - elsif (iFEIncrement = '0' and iFEDecrement = '1') then - iFECounter <= iFECounter - 1; - end if; - end if; - end if; - end process; - - iRXFIFOPE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(8) = '1' else '0'; - iRXFIFOFE <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(9) = '1' else '0'; - iRXFIFOBI <= '1' when iRXFIFOEmpty = '0' and iRXFIFOQ(10) = '1' else '0'; - UART_PEDET: slib_edge_detect port map (CLK, RST, iRXFIFOPE, iPERE); - UART_FEDET: slib_edge_detect port map (CLK, RST, iRXFIFOFE, iFERE); - UART_BIDET: slib_edge_detect port map (CLK, RST, iRXFIFOBI, iBIRE); - iFEIncrement <= '1' when iRXFIFOWrite = '1' and iRXFIFOD(10 downto 8) /= "000" else '0'; - iFEDecrement <= '1' when iFECounter /= 0 and iRXFIFOEmpty = '0' and (iPERE = '1' or iFERE = '1' or iBIRE = '1') else '0'; - - iLSR(0) <= iLSR_DR; - iLSR(1) <= iLSR_OE; - iLSR(2) <= iLSR_PE; - iLSR(3) <= iLSR_FE; - iLSR(4) <= iLSR_BI; - iLSR(5) <= iLSR_THRE; - iLSR(6) <= iLSR_TEMT; - iLSR(7) <= '1' when iFCR_FIFOEnable = '1' and iLSR_FIFOERR = '1' else '0'; - iLSR_DR <= '1' when iRXFIFOEmpty = '0' or iRXFIFOWrite = '1' else '0'; - iLSR_THRE <= '1' when iTXFIFOEmpty = '1' else '0'; - iLSR_TEMT <= '1' when iTXRunning = '0' and iLSR_THRE = '1' else '0'; - - -- Modem status register - iMSR_CTS <= '1' when (iMCR_LOOP = '1' and iRTS = '1') or (iMCR_LOOP = '0' and iCTSn = '0') else '0'; - iMSR_DSR <= '1' when (iMCR_LOOP = '1' and iMCR_DTR = '1') or (iMCR_LOOP = '0' and iDSRn = '0') else '0'; - iMSR_RI <= '1' when (iMCR_LOOP = '1' and iMCR_OUT1 = '1') or (iMCR_LOOP = '0' and iRIn = '0') else '0'; - iMSR_DCD <= '1' when (iMCR_LOOP = '1' and iMCR_OUT2 = '1') or (iMCR_LOOP = '0' and iDCDn = '0') else '0'; - - -- Edge detection for CTS, DSR, DCD and RI - UART_ED_CTS: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_CTS, RE => iCTSnRE, FE => iCTSnFE); - UART_ED_DSR: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DSR, RE => iDSRnRE, FE => iDSRnFE); - UART_ED_RI: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_RI, RE => iRInRE, FE => iRInFE); - UART_ED_DCD: slib_edge_detect port map (CLK => CLK, RST => RST, D => iMSR_DCD, RE => iDCDnRE, FE => iDCDnFE); - - UART_MSR: process (CLK, RST) - begin - if (RST = '1') then - iMSR_dCTS <= '0'; - iMSR_dDSR <= '0'; - iMSR_TERI <= '0'; - iMSR_dDCD <= '0'; - elsif (CLK'event and CLK = '1') then - -- Delta CTS - if (iCTSnRE = '1' or iCTSnFE = '1') then - iMSR_dCTS <= '1'; - elsif (iMSRRead = '1') then - iMSR_dCTS <= '0'; - end if; - -- Delta DSR - if (iDSRnRE = '1' or iDSRnFE = '1') then - iMSR_dDSR <= '1'; - elsif (iMSRRead = '1') then - iMSR_dDSR <= '0'; - end if; - -- Trailing edge RI - if (iRInFE = '1') then - iMSR_TERI <= '1'; - elsif (iMSRRead = '1') then - iMSR_TERI <= '0'; - end if; - -- Delta DCD - if (iDCDnRE = '1' or iDCDnFE = '1') then - iMSR_dDCD <= '1'; - elsif (iMSRRead = '1') then - iMSR_dDCD <= '0'; - end if; - end if; - end process; - - iMSR(0) <= iMSR_dCTS; - iMSR(1) <= iMSR_dDSR; - iMSR(2) <= iMSR_TERI; - iMSR(3) <= iMSR_dDCD; - iMSR(4) <= iMSR_CTS; - iMSR(5) <= iMSR_DSR; - iMSR(6) <= iMSR_RI; - iMSR(7) <= iMSR_DCD; - - -- Scratch register - UART_SCR: process (CLK, RST) - begin - if (RST = '1') then - iSCR <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iSCRWrite = '1') then - iSCR <= iDIN; - end if; - end if; - end process; - - - -- Baudrate generator - iBaudgenDiv <= iDLM & iDLL; - UART_BG16: uart_baudgen port map (CLK => CLK, - RST => RST, - CE => BAUDCE, - CLEAR => '0', - DIVIDER => iBaudgenDiv, - BAUDTICK => iBaudtick16x - ); - UART_BG2: slib_clock_div generic map (RATIO => 8) - port map (CLK => CLK, - RST => RST, - CE => iBaudtick16x, - Q => iBaudtick2x - ); - UART_RCLK: slib_edge_detect port map (CLK => CLK, - RST => RST, - D => RCLK, - RE => iRCLK - ); - - -- Transmitter FIFO - UART_TXFF: slib_fifo generic map (WIDTH => 8, SIZE_E => 6) - port map (CLK => CLK, - RST => RST, - CLEAR => iTXFIFOClear, - WRITE => iTXFIFOWrite, - READ => iTXFIFORead, - D => iDIN, - Q => iTXFIFOQ, - EMPTY => iTXFIFOEmpty, - FULL => iTXFIFO64Full, - USAGE => iTXFIFOUsage - ); - -- Transmitter FIFO inputs - iTXFIFO16Full <= iTXFIFOUsage(4); - iTXFIFOFull <= iTXFIFO16Full when iFCR_FIFO64E = '0' else iTXFIFO64Full; - iTXFIFOWrite <= '1' when ((iFCR_FIFOEnable = '0' and iTXFIFOEmpty = '1') or (iFCR_FIFOEnable = '1' and iTXFIFOFull = '0')) and iTHRWrite = '1' else '0'; - iTXFIFOClear <= '1' when iFCR_TXFIFOReset = '1' else '0'; - - -- Receiver FIFO - UART_RXFF: slib_fifo generic map (WIDTH => 11, SIZE_E => 6) - port map (CLK => CLK, - RST => RST, - CLEAR => iRXFIFOClear, - WRITE => iRXFIFOWrite, - READ => iRXFIFORead, - D => iRXFIFOD, - Q => iRXFIFOQ, - EMPTY => iRXFIFOEmpty, - FULL => iRXFIFO64Full, - USAGE => iRXFIFOUsage - ); - -- Receiver FIFO inputs - iRXFIFORead <= '1' when iRBRRead = '1' else '0'; - iRXFIFO16Full <= iRXFIFOUsage(4); - iRXFIFOFull <= iRXFIFO16Full when iFCR_FIFO64E = '0' else iRXFIFO64Full; - - - -- Receiver FIFO outputs - iRBR <= iRXFIFOQ(7 downto 0); - - -- FIFO trigger level: 1, 4, 8, 14 - iRXFIFO16Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or - (iFCR_RXTrigger = "01" and (iRXFIFOUsage(2) = '1' or iRXFIFOUsage(3) = '1')) or - (iFCR_RXTrigger = "10" and iRXFIFOUsage(3) = '1') or - (iFCR_RXTrigger = "11" and iRXFIFOUsage(3) = '1' and iRXFIFOUsage(2) = '1' and iRXFIFOUsage(1) = '1') or - iRXFIFO16Full = '1' else '0'; - -- FIFO 64 trigger level: 1, 16, 32, 56 - iRXFIFO64Trigger <= '1' when (iFCR_RXTrigger = "00" and iRXFIFOEmpty = '0') or - (iFCR_RXTrigger = "01" and (iRXFIFOUsage(4) = '1' or iRXFIFOUsage(5) = '1')) or - (iFCR_RXTrigger = "10" and iRXFIFOUsage(5) = '1') or - (iFCR_RXTrigger = "11" and iRXFIFOUsage(5) = '1' and iRXFIFOUsage(4) = '1' and iRXFIFOUsage(3) = '1') or - iRXFIFO64Full = '1' else '0'; - iRXFIFOTrigger <= iRXFIFO16Trigger when iFCR_FIFO64E = '0' else iRXFIFO64Trigger; - - -- Transmitter - UART_TX: uart_transmitter port map (CLK => CLK, - RST => RST, - TXCLK => iBaudtick2x, - TXSTART => iTXStart, - CLEAR => iTXClear, - WLS => iLCR_WLS, - STB => iLCR_STB, - PEN => iLCR_PEN, - EPS => iLCR_EPS, - SP => iLCR_SP, - BC => iLCR_BC, - DIN => iTSR, - TXFINISHED => iTXFinished, - SOUT => iSOUT - ); - iTXClear <= '0'; - - -- Receiver - UART_RX: uart_receiver port map (CLK => CLK, - RST => RST, - RXCLK => iRCLK, - RXCLEAR => iRXClear, - WLS => iLCR_WLS, - STB => iLCR_STB, - PEN => iLCR_PEN, - EPS => iLCR_EPS, - SP => iLCR_SP, - SIN => iSIN, - PE => iRXPE, - FE => iRXFE, - BI => iRXBI, - DOUT => iRXData, - RXFINISHED => iRXFinished - ); - iRXClear <= '0'; - iSIN <= iSINr when iMCR_LOOP = '0' else iSOUT; - - -- Transmitter enable signal - -- TODO: Use iCTSNs instead of iMSR_CTS? Input filter increases delay for Auto-CTS recognition. - iTXEnable <= '1' when iTXFIFOEmpty = '0' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iMSR_CTS = '1')) else '0'; - - -- Transmitter process - UART_TXPROC: process (CLK, RST) - type state_type is (IDLE, TXSTART, TXRUN, TXEND); - variable State : state_type; - begin - if (RST = '1') then - State := IDLE; - iTSR <= (others => '0'); - iTXStart <= '0'; - iTXFIFORead <= '0'; - iTXRunning <= '0'; - elsif (CLK'event and CLK = '1') then - -- Defaults - iTXStart <= '0'; - iTXFIFORead <= '0'; - iTXRunning <= '0'; - - case State is - when IDLE => if (iTXEnable = '1') then - iTXStart <= '1'; -- Start transmitter - State := TXSTART; - else - State := IDLE; - end if; - when TXSTART => iTSR <= iTXFIFOQ; - iTXStart <= '1'; -- Start transmitter - iTXFIFORead <= '1'; -- Increment TX FIFO read counter - State := TXRUN; - when TXRUN => if (iTXFinished = '1') then -- TX finished - State := TXEND; - else - State := TXRUN; - end if; - iTXRunning <= '1'; - iTXStart <= '1'; - when TXEND => State := IDLE; - when others => State := IDLE; - end case; - end if; - end process; - - -- Receiver process - UART_RXPROC: process (CLK, RST) - type state_type is (IDLE, RXSAVE); - variable State : state_type; - begin - if (RST = '1') then - State := IDLE; - iRXFIFOWrite <= '0'; - iRXFIFOClear <= '0'; - iRXFIFOD <= (others => '0'); - elsif (CLK'event and CLK = '1') then - -- Defaults - iRXFIFOWrite <= '0'; - iRXFIFOClear <= iFCR_RXFIFOReset; - - case State is - when IDLE => if (iRXFinished = '1') then -- Receive finished - iRXFIFOD <= iRXBI & iRXFE & iRXPE & iRXData; - if (iFCR_FIFOEnable = '0') then - iRXFIFOClear <= '1'; -- Non-FIFO mode - end if; - State := RXSAVE; - else - State := IDLE; - end if; - when RXSAVE => if (iFCR_FIFOEnable = '0') then - iRXFIFOWrite <= '1'; -- Non-FIFO mode: Overwrite - elsif (iRXFIFOFull = '0') then - iRXFIFOWrite <= '1'; -- FIFO mode - end if; - State := IDLE; - when others => State := IDLE; - end case; - end if; - end process; - - -- Automatic flow control - UART_AFC: process (CLK, RST) - begin - if (RST = '1') then - iRTS <= '0'; - elsif (CLK'event and CLK = '1') then - if (iMCR_RTS = '0' or (iMCR_AFE = '1' and iRXFIFOTrigger = '1')) then - -- Deassert when MCR_RTS is not set or AFC is enabled and the RX FIFO trigger level is reached - iRTS <= '0'; - elsif (iMCR_RTS = '1' and (iMCR_AFE = '0' or (iMCR_AFE = '1' and iRXFIFOEmpty = '1'))) then - -- Assert when MCR_RTS is set and AFC is disabled or when AFC is enabled and the RX FIFO is empty - iRTS <= '1'; - end if; - end if; - end process; - - -- Output registers - UART_OUTREGS: process (CLK, RST) - begin - if (RST = '1') then - DDIS <= '1'; - BAUDOUTN <= '1'; - OUT1N <= '1'; - OUT2N <= '1'; - RTSN <= '1'; - DTRN <= '1'; - SOUT <= '1'; - elsif (CLK'event and CLK = '1') then - -- Default values - DDIS <= '0'; - BAUDOUTN <= '0'; - OUT1N <= '0'; - OUT2N <= '0'; - RTSN <= '0'; - DTRN <= '0'; - SOUT <= '0'; - - -- DDIS - if (CS = '0' or RD = '0') then - DDIS <= '1'; - end if; - -- BAUDOUTN - if (iBaudtick16x = '0') then - BAUDOUTN <= '1'; - end if; - -- OUT1N - if (iMCR_LOOP = '1' or iMCR_OUT1 = '0') then - OUT1N <= '1'; - end if; - -- OUT2N - if (iMCR_LOOP = '1' or iMCR_OUT2 = '0') then - OUT2N <= '1'; - end if; - -- RTS - if (iMCR_LOOP = '1' or iRTS = '0') then - RTSN <= '1'; - end if; - -- DTR - if (iMCR_LOOP = '1' or iMCR_DTR = '0') then - DTRN <= '1'; - end if; - -- SOUT - if (iMCR_LOOP = '1' or iSOUT = '1') then - SOUT <= '1'; - end if; - end if; - end process; - - - -- UART data output - UART_DOUT: process (A, iLCR_DLAB, iRBR, iDLL, iDLM, iIER, iIIR, iLCR, iMCR, iLSR, iMSR, iSCR) - begin - case A is - when "000" => if (iLCR_DLAB = '0') then - DOUT <= iRBR; - else - DOUT <= iDLL; - end if; - when "001" => if (iLCR_DLAB = '0') then - DOUT <= iIER; - else - DOUT <= iDLM; - end if; - when "010" => DOUT <= iIIR; - when "011" => DOUT <= iLCR; - when "100" => DOUT <= iMCR; - when "101" => DOUT <= iLSR; - when "110" => DOUT <= iMSR; - when "111" => DOUT <= iSCR; - when others => DOUT <= iRBR; - end case; - end process; - -end rtl; - - Index: trunk/uart_16750/slib_input_filter.vhd =================================================================== --- trunk/uart_16750/slib_input_filter.vhd (revision 118) +++ trunk/uart_16750/slib_input_filter.vhd (nonexistent) @@ -1,69 +0,0 @@ --- --- Input filter --- --- Author: Sebastian Witt --- Data: 06.03.2008 --- Version: 1.0 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity slib_input_filter is - generic ( - SIZE : natural := 4 -- Filter counter size - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); -end slib_input_filter; - -architecture rtl of slib_input_filter is - signal iCount : integer range 0 to SIZE; -begin - IF_D: process (RST, CLK) - begin - if (RST = '1') then - iCount <= 0; - Q <= '0'; - elsif (CLK'event and CLK='1') then - -- Input counter - if (CE = '1' ) then - if (D = '1' and iCount /= SIZE) then - iCount <= iCount + 1; - elsif (D = '0' and iCount /= 0) then - iCount <= iCount - 1; - end if; - end if; - - -- Output - if (iCount = SIZE) then - Q <= '1'; - elsif (iCount = 0) then - Q <= '0'; - end if; - end if; - end process; - -end rtl; - Index: trunk/uart_16750/uart_receiver.vhd =================================================================== --- trunk/uart_16750/uart_receiver.vhd (revision 118) +++ trunk/uart_16750/uart_receiver.vhd (nonexistent) @@ -1,311 +0,0 @@ --- --- UART receiver --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.2 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART receiver -entity uart_receiver is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - RXCLK : in std_logic; -- Receiver clock (16x baudrate) - RXCLEAR : in std_logic; -- Reset receiver state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - SIN : in std_logic; -- Receiver input - PE : out std_logic; -- Parity error - FE : out std_logic; -- Framing error - BI : out std_logic; -- Break interrupt - DOUT : out std_logic_vector(7 downto 0); -- Output data - RXFINISHED : out std_logic -- Receiver operation finished - ); -end uart_receiver; - -architecture rtl of uart_receiver is - -- Majority voting logic - component slib_mv_filter is - generic ( - WIDTH : natural := 4; - THRESHOLD : natural := 10 - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - SAMPLE : in std_logic; -- Clock enable for sample process - CLEAR : in std_logic; -- Reset process - D : in std_logic; -- Signal input - Q : out std_logic -- Signal D was at least THRESHOLD samples high - ); - end component; - component slib_input_filter is - generic ( - SIZE : natural := 4 -- Filter counter size - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); - end component; - - -- Counter - component slib_counter is - generic ( - WIDTH : natural := 4 -- Counter width - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear counter register - LOAD : in std_logic; -- Load counter register - ENABLE : in std_logic; -- Enable count operation - DOWN : in std_logic; -- Count direction down - D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input - Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output - OVERFLOW : out std_logic -- Counter overflow - ); - end component; - - -- FSM - type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT); - signal CState, NState : state_type; - - -- Signals - signal iBaudCount : std_logic_vector(3 downto 0); -- Baud counter output - signal iBaudCountClear : std_logic; -- Baud counter clear - signal iBaudStep : std_logic; -- Next symbol pulse - signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock - signal iFilterClear : std_logic; -- Reset input filter - signal iFSIN : std_logic; -- Filtered SIN - signal iFStopBit : std_logic; -- Filtered SIN for stop bit detection - signal iParity : std_logic; -- Data parity - signal iParityReceived : std_logic; -- Parity received - signal iDataCount : integer range 0 to 8; -- Data bit counter - signal iDataCountInit : std_logic; -- Initialize data bit counter to word length - signal iDataCountFinish : std_logic; -- Data bit counter finished - signal iRXFinished : std_logic; -- Word received, output data valid - signal iFE : std_logic; -- Internal frame error - signal iBI : std_logic; -- Internal break interrupt - signal iNoStopReceived : std_logic; -- No valid stop bit received - signal iDOUT : std_logic_vector(7 downto 0); -- Data output - -begin - - -- Baudrate counter: RXCLK/16 - RX_BRC: slib_counter generic map ( - WIDTH => 4 - ) port map ( - CLK => CLK, - RST => RST, - CLEAR => iBaudCountClear, - LOAD => '0', - ENABLE => RXCLK, - DOWN => '0', - D => x"0", - Q => iBaudCount, - OVERFLOW => iBaudStep - ); - - -- Input filter - RX_MVF: slib_mv_filter generic map ( - WIDTH => 4, - THRESHOLD => 10 - ) port map ( - CLK => CLK, - RST => RST, - SAMPLE => RXCLK, - CLEAR => iFilterClear, - D => SIN, - Q => iFSIN - ); - - -- Input filter for the stop bit - RX_IFSB: slib_input_filter generic map ( - SIZE => 4 - ) port map ( - CLK => CLK, - RST => RST, - CE => RXCLK, - D => SIN, - Q => iFStopBit - ); - - -- iBaudStepD - RX_IFC: process (CLK, RST) - begin - if (RST = '1') then - iBaudStepD <= '0'; - elsif (CLK'event and CLK = '1') then - iBaudStepD <= iBaudStep; - end if; - end process; - - iFilterClear <= iBaudStepD or iBaudCountClear; - - -- Parity generation - RX_PAR: process (iDOUT, EPS) - begin - iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS; - end process; - - -- Data bit capture - RX_DATACOUNT: process (CLK, RST) - begin - if (RST = '1') then - iDataCount <= 0; - iDOUT <= (others => '0'); - elsif (CLK'event and CLK = '1') then - if (iDataCountInit = '1') then - iDataCount <= 0; - iDOUT <= (others => '0'); - else - if (iBaudStep = '1' and iDataCountFinish = '0') then - iDOUT(iDataCount) <= iFSIN; - iDataCount <= iDataCount + 1; - end if; - end if; - end if; - end process; - - iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or - (WLS = "01" and iDataCount = 6) or - (WLS = "10" and iDataCount = 7) or - (WLS = "11" and iDataCount = 8) else '0'; - - -- FSM update process - RX_FSMUPDATE: process (CLK, RST) - begin - if (RST = '1') then - CState <= IDLE; - elsif (CLK'event and CLK = '1') then - CState <= NState; - end if; - end process; - - -- RX FSM - RX_FSM: process (CState, SIN, iFSIN, iFStopBit, iBaudStep, iBaudCount, iDataCountFinish, PEN, WLS, STB) - begin - -- Defaults - NState <= IDLE; - iBaudCountClear <= '0'; - iDataCountInit <= '0'; - iRXFinished <= '0'; - - case CState is - when IDLE => if (SIN = '0') then -- Start detected - NState <= START; - end if; - iBaudCountClear <= '1'; - iDataCountInit <= '1'; - when START => iDataCountInit <= '1'; - if (iBaudStep = '1') then -- Wait for start bit end - if (iFSIN = '0') then - NState <= DATA; - end if; - else - NState <= START; - end if; - when DATA => if (iDataCountFinish = '1') then -- Received all data bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= DATA; - end if; - when PAR => if (iBaudStep = '1') then -- Wait for parity bit - NState <= STOP; - else - NState <= PAR; - end if; - when STOP => if (iBaudCount(3) = '1') then -- Wait for stop bit - if (iFStopBit = '0') then -- No stop bit received - iRXFinished <= '1'; - NState <= MWAIT; - else - iRXFinished <= '1'; - NState <= IDLE; -- Stop bit end - end if; - else - NState <= STOP; - end if; - when MWAIT => if (SIN = '0') then -- Wait for mark - NState <= MWAIT; - end if; - when others => null; - end case; - end process; - - -- Check parity - RX_PARCHECK: process (CLK, RST) - begin - if (RST = '1') then - PE <= '0'; - iParityReceived <= '0'; - elsif (CLK'event and CLK = '1') then - if (CState = PAR and iBaudStep = '1') then - iParityReceived <= iFSIN; -- Received parity bit - end if; - - -- Check parity - if (PEN = '1') then -- Parity enabled - PE <= '0'; - if (SP = '1') then -- Sticky parity - if ((EPS xor iParityReceived) = '0') then - PE <= '1'; -- Parity error - end if; - else - if (iParity /= iParityReceived) then - PE <= '1'; -- Parity error - end if; - end if; - else - PE <= '0'; -- Parity disabled - iParityReceived <= '0'; - end if; - end if; - end process; - - -- Framing error and break interrupt - iNoStopReceived <= '1' when iFStopBit = '0' and (CState = STOP) else '0'; - iBI <= '1' when iDOUT = "00000000" and - iParityReceived = '0' and - iNoStopReceived = '1' else '0'; - iFE <= '1' when iNoStopReceived = '1' else '0'; - - -- Output signals - DOUT <= iDOUT; - BI <= iBI; - FE <= iFE; - RXFINISHED <= iRXFinished; - -end rtl; - Index: trunk/uart_16750/slib_mv_filter.vhd =================================================================== --- trunk/uart_16750/slib_mv_filter.vhd (revision 118) +++ trunk/uart_16750/slib_mv_filter.vhd (nonexistent) @@ -1,78 +0,0 @@ --- --- Majority voting filter --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - - -entity slib_mv_filter is - generic ( - WIDTH : natural := 4; - THRESHOLD : natural := 10 - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - SAMPLE : in std_logic; -- Clock enable for sample process - CLEAR : in std_logic; -- Reset process - D : in std_logic; -- Signal input - Q : out std_logic -- Signal D was at least THRESHOLD samples high - ); -end slib_mv_filter; - -architecture rtl of slib_mv_filter is - - -- Signals - signal iCounter : unsigned(WIDTH downto 0); -- Sample counter - signal iQ : std_logic; -- Internal Q - -begin - -- Main process - MV_PROC: process (RST, CLK) - begin - if (RST = '1') then - iCounter <= (others => '0'); - iQ <= '0'; - elsif (CLK'event and CLK='1') then - if (iCounter >= THRESHOLD) then -- Compare with threshold - iQ <= '1'; - else - if (SAMPLE = '1' and D = '1') then -- Take sample - iCounter <= iCounter + 1; - end if; - end if; - - if (CLEAR = '1') then -- Reset logic - iCounter <= (others => '0'); - iQ <= '0'; - end if; - - end if; - end process; - - -- Output signals - Q <= iQ; - -end rtl; - Index: trunk/uart_16750/uart_baudgen.vhd =================================================================== --- trunk/uart_16750/uart_baudgen.vhd (revision 118) +++ trunk/uart_16750/uart_baudgen.vhd (nonexistent) @@ -1,67 +0,0 @@ --- --- UART Baudrate generator --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART baudrate generator -entity uart_baudgen is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable - CLEAR : in std_logic; -- Reset generator (synchronization) - DIVIDER : in std_logic_vector(15 downto 0); -- Clock divider - BAUDTICK : out std_logic -- 16xBaudrate tick - ); -end uart_baudgen; - -architecture rtl of uart_baudgen is - -- Signals - signal iCounter : unsigned(15 downto 0); -begin - -- Baudrate counter - BG_COUNT: process (CLK, RST) - begin - if (RST = '1') then - iCounter <= (others => '0'); - BAUDTICK <= '0'; - elsif (CLK'event and CLK = '1') then - if (CLEAR = '1') then - iCounter <= (others => '0'); - elsif (CE = '1') then - iCounter <= iCounter + 1; - end if; - - BAUDTICK <= '0'; - if (iCounter = unsigned(DIVIDER)) then - iCounter <= (others => '0'); - BAUDTICK <= '1'; - end if; - end if; - end process; - -end rtl; - - Index: trunk/uart_16750/slib_input_sync.vhd =================================================================== --- trunk/uart_16750/slib_input_sync.vhd (revision 118) +++ trunk/uart_16750/slib_input_sync.vhd (nonexistent) @@ -1,54 +0,0 @@ --- --- Input synchronization --- --- Author: Sebastian Witt --- Data: 27.01.2008 --- Version: 1.0 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity slib_input_sync is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - Q : out std_logic -- Signal output - ); -end slib_input_sync; - -architecture rtl of slib_input_sync is - signal iD : std_logic_vector(1 downto 0); -begin - IS_D: process (RST, CLK) - begin - if (RST = '1') then - iD <= (others => '0'); - elsif (CLK'event and CLK='1') then - iD(0) <= D; - iD(1) <= iD(0); - end if; - end process; - - -- Output ports - Q <= iD(1); - -end rtl; - Index: trunk/uart_16750/slib_edge_detect.vhd =================================================================== --- trunk/uart_16750/slib_edge_detect.vhd (revision 118) +++ trunk/uart_16750/slib_edge_detect.vhd (nonexistent) @@ -1,57 +0,0 @@ --- --- Signal edge detect --- --- Author: Sebastian Witt --- Data: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - -entity slib_edge_detect is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - D : in std_logic; -- Signal input - RE : out std_logic; -- Rising edge detected - FE : out std_logic -- Falling edge detected - ); -end slib_edge_detect; - -architecture rtl of slib_edge_detect is - signal iDd : std_logic; -- D register -begin - -- Store D - ED_D: process (RST, CLK) - begin - if (RST = '1') then - iDd <= '0'; - elsif (CLK'event and CLK='1') then - iDd <= D; - end if; - end process; - - -- Output ports - RE <= '1' when iDd = '0' and D = '1' else '0'; - FE <= '1' when iDd = '1' and D = '0' else '0'; - -end rtl; - - Index: trunk/uart_16750/slib_clock_div.vhd =================================================================== --- trunk/uart_16750/slib_clock_div.vhd (revision 118) +++ trunk/uart_16750/slib_clock_div.vhd (nonexistent) @@ -1,70 +0,0 @@ --- --- Clock divider (clock enable generator) --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - - -entity slib_clock_div is - generic ( - RATIO : integer := 4 -- Clock divider ratio - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CE : in std_logic; -- Clock enable input - Q : out std_logic -- New clock enable output - ); -end slib_clock_div; - -architecture rtl of slib_clock_div is - -- Signals - signal iQ : std_logic; -- Internal Q - signal iCounter : integer range 0 to RATIO-1; -- Counter - -begin - -- Main process - CD_PROC: process (RST, CLK) - begin - if (RST = '1') then - iCounter <= 0; - iQ <= '0'; - elsif (CLK'event and CLK='1') then - iQ <= '0'; - if (CE = '1') then - if (iCounter = (RATIO-1)) then - iQ <= '1'; - iCounter <= 0; - else - iCounter <= iCounter + 1; - end if; - end if; - end if; - end process; - - -- Output signals - Q <= iQ; - -end rtl; - Index: trunk/uart_16750/uart_transmitter.vhd =================================================================== --- trunk/uart_16750/uart_transmitter.vhd (revision 118) +++ trunk/uart_16750/uart_transmitter.vhd (nonexistent) @@ -1,216 +0,0 @@ --- --- UART transmitter --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.0 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART transmitter -entity uart_transmitter is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - TXCLK : in std_logic; -- Transmitter clock (2x baudrate) - TXSTART : in std_logic; -- Start transmitter - CLEAR : in std_logic; -- Clear transmitter state - WLS : in std_logic_vector(1 downto 0); -- Word length select - STB : in std_logic; -- Number of stop bits - PEN : in std_logic; -- Parity enable - EPS : in std_logic; -- Even parity select - SP : in std_logic; -- Stick parity - BC : in std_logic; -- Break control - DIN : in std_logic_vector(7 downto 0); -- Input data - TXFINISHED : out std_logic; -- Transmitter operation finished - SOUT : out std_logic -- Transmitter output - ); -end uart_transmitter; - -architecture rtl of uart_transmitter is - -- FSM - type state_type is (IDLE, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PAR, STOP, STOP2); - signal CState, NState : state_type; - - -- Signals - signal iTx2 : std_logic; -- Next TX step - signal iSout : std_logic; -- Transmitter output - signal iParity : std_logic; -- Parity - signal iFinished : std_logic; -- TX finished - -begin - -- Transmitter FSM update process - TX_PROC: process (RST, CLK) - begin - if (RST = '1') then - CState <= IDLE; - iTx2 <= '0'; - elsif (CLK'event and CLK='1') then - if (TXCLK = '1') then -- TX clock - if (iTx2 = '0') then -- Two TX clocks per step - CState <= NState; -- Next step - iTx2 <= '1'; - else - if ((WLS = "00") and (STB = '1') and CState = STOP2) then - CState <= NState; -- 1.5 stop bits for 5 bit word mode - iTx2 <= '1'; - else - CState <= CState; -- First TX clock, wait - iTx2 <= '0'; - end if; - end if; - end if; - end if; - end process; - - -- Transmitter FSM - TX_FSM: process (CState, TXSTART, DIN, WLS, PEN, SP, EPS, STB, iParity) - begin - -- Defaults - NState <= IDLE; - iSout <= '1'; - - case CState is - when IDLE => if (TXSTART = '1') then - NState <= START; - end if; - when START => iSout <= '0'; - NState <= BIT0; - when BIT0 => iSout <= DIN(0); - NState <= BIT1; - when BIT1 => iSout <= DIN(1); - NState <= BIT2; - when BIT2 => iSout <= DIN(2); - NState <= BIT3; - when BIT3 => iSout <= DIN(3); - NState <= BIT4; - when BIT4 => iSout <= DIN(4); - if (WLS = "00") then -- 5 bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= BIT5; - end if; - when BIT5 => iSout <= DIN(5); - if (WLS = "01") then -- 6 bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= BIT6; - end if; - when BIT6 => iSout <= DIN(6); - if (WLS = "10") then -- 7 bits - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - else - NState <= BIT7; - end if; - when BIT7 => iSout <= DIN(7); - if (PEN = '1') then - NState <= PAR; -- Parity enabled - else - NState <= STOP; -- No parity - end if; - when PAR => if (SP = '1') then -- Sticky parity - if (EPS = '1') then - iSout <= '0'; -- Even parity -> cleared - else - iSout <= '1'; -- Odd parity -> set - end if; - else - if (EPS = '1') then - iSout <= iParity; -- Even parity - else - iSout <= not iParity; -- Odd parity - end if; - end if; - NState <= STOP; - when STOP => if (STB = '1') then -- 2 stop bits - NState <= STOP2; - else - if (TXSTART = '1') then -- Next transmission - NState <= START; - end if; - end if; - when STOP2 => if (TXSTART = '1') then -- Next transmission - NState <= START; - end if; - when others => null; - end case; - - - end process; - - - -- Parity generation - TX_PAR: process (DIN, WLS) - variable iP40, iP50, iP60, iP70 : std_logic; - begin - iP40 := DIN(4) xor DIN(3) xor DIN(2) xor DIN(1) xor DIN(0); - iP50 := DIN(5) xor iP40; - iP60 := DIN(6) xor iP50; - iP70 := DIN(7) xor iP60; - - case WLS is - when "00" => iParity <= iP40; - when "01" => iParity <= iP50; - when "10" => iParity <= iP60; - when others => iParity <= iP70; - end case; - end process; - - - -- Signal TX finished on STOP bit transmission - TX_FIN: process (CLK, RST) - variable iLast : std_logic; - begin - if (RST = '1') then - iFinished <= '0'; - iLast := '0'; - elsif (CLK'event and CLK = '1') then - iFinished <= '0'; - if (iLast = '0' and CState = STOP) then - iFinished <= '1'; - end if; - - if (CState = STOP) then - iLast := '1'; - else - iLast := '0'; - end if; - end if; - end process; - - -- Output signals - SOUT <= iSout when BC = '0' else '0'; - TXFINISHED <= iFinished; - -end rtl; - Index: trunk/uart_16750/uart_interrupt.vhd =================================================================== --- trunk/uart_16750/uart_interrupt.vhd (revision 118) +++ trunk/uart_16750/uart_interrupt.vhd (nonexistent) @@ -1,102 +0,0 @@ --- --- UART interrupt control --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.1 --- --- History: 1.0 - Initial version --- 1.1 - Automatic flow control --- --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Serial UART interrupt control -entity uart_interrupt is - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - IER : in std_logic_vector(3 downto 0); -- IER 3:0 - LSR : in std_logic_vector(4 downto 0); -- LSR 4:0 - THI : in std_logic; -- Transmitter holding register empty interrupt - RDA : in std_logic; -- Receiver data available - CTI : in std_logic; -- Character timeout indication - AFE : in std_logic; -- Automatic flow control enable - MSR : in std_logic_vector(3 downto 0); -- MSR 3:0 - IIR : out std_logic_vector(3 downto 0); -- IIR 3:0 - INT : out std_logic -- Interrupt - ); -end uart_interrupt; - -architecture rtl of uart_interrupt is - -- Signals - signal iRLSInterrupt : std_logic; -- Receiver line status interrupt - signal iRDAInterrupt : std_logic; -- Received data available interrupt - signal iCTIInterrupt : std_logic; -- Character timeout indication interrupt - signal iTHRInterrupt : std_logic; -- Transmitter holding register empty interrupt - signal iMSRInterrupt : std_logic; -- Modem status interrupt - signal iIIR : std_logic_vector(3 downto 0); -- IIR register -begin - - -- Priority 1: Receiver line status interrupt on: Overrun error, parity error, framing error or break interrupt - iRLSInterrupt <= IER(2) and (LSR(1) or LSR(2) or LSR(3) or LSR(4)); - - -- Priority 2: Received data available or trigger level reached in FIFO mode - iRDAInterrupt <= IER(0) and RDA; - - -- Priority 2: Character timeout indication - iCTIInterrupt <= IER(0) and CTI; - - -- Priority 3: Transmitter holding register empty - iTHRInterrupt <= IER(1) and THI; - - -- Priority 4: Modem status interrupt: dCTS (when AFC is disabled), dDSR, TERI, dDCD - iMSRInterrupt <= IER(3) and ((MSR(0) and not AFE) or MSR(1) or MSR(2) or MSR(3)); - - -- IIR - IC_IIR: process (CLK, RST) - begin - if (RST = '1') then - iIIR <= "0001"; -- TODO: Invert later - elsif (CLK'event and CLK = '1') then - -- IIR register - if (iRLSInterrupt = '1') then - iIIR <= "0110"; - elsif (iCTIInterrupt = '1') then - iIIR <= "1100"; - elsif (iRDAInterrupt = '1') then - iIIR <= "0100"; - elsif (iTHRInterrupt = '1') then - iIIR <= "0010"; - elsif (iMSRInterrupt = '1') then - iIIR <= "0000"; - else - iIIR <= "0001"; - end if; - end if; - end process; - - -- Outputs - IIR <= iIIR; - INT <= not iIIR(0); - -end rtl; - Index: trunk/uart_16750/slib_counter.vhd =================================================================== --- trunk/uart_16750/slib_counter.vhd (revision 118) +++ trunk/uart_16750/slib_counter.vhd (nonexistent) @@ -1,77 +0,0 @@ --- --- Counter --- --- Author: Sebastian Witt --- Date: 27.01.2008 --- Version: 1.2 --- --- This code is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. --- --- This code is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. --- --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the --- Free Software Foundation, Inc., 59 Temple Place, Suite 330, --- Boston, MA 02111-1307 USA --- - -LIBRARY IEEE; -USE IEEE.std_logic_1164.all; -USE IEEE.numeric_std.all; - --- Counter -entity slib_counter is - generic ( - WIDTH : natural := 4 -- Counter width - ); - port ( - CLK : in std_logic; -- Clock - RST : in std_logic; -- Reset - CLEAR : in std_logic; -- Clear counter register - LOAD : in std_logic; -- Load counter register - ENABLE : in std_logic; -- Enable count operation - DOWN : in std_logic; -- Count direction down - D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input - Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output - OVERFLOW : out std_logic -- Counter overflow - ); -end slib_counter; - -architecture rtl of slib_counter is - signal iCounter : unsigned(WIDTH downto 0); -- Counter register -begin - -- Counter process - COUNT_SHIFT: process (RST, CLK) - begin - if (RST = '1') then - iCounter <= (others => '0'); -- Reset counter register - elsif (CLK'event and CLK='1') then - if (CLEAR = '1') then - iCounter <= (others => '0'); -- Clear counter register - elsif (LOAD = '1') then -- Load counter register - iCounter <= unsigned('0' & D); - elsif (ENABLE = '1') then -- Enable counter - if (DOWN = '0') then -- Count up - iCounter <= iCounter + 1; - else -- Count down - iCounter <= iCounter - 1; - end if; - end if; - if (iCounter(WIDTH) = '1') then -- Clear overflow - iCounter(WIDTH) <= '0'; - end if; - end if; - - end process; - - -- Output ports - Q <= std_logic_vector(iCounter(WIDTH-1 downto 0)); - OVERFLOW <= iCounter(WIDTH); -end rtl; -

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