OpenCores

0,0 → 1,285

segmented_mips.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 3_execution/alu_1bit.vhd =================================================================== --- 3_execution/alu_1bit.vhd (nonexistent) +++ 3_execution/alu_1bit.vhd (revision 2) @@ -0,0 +1,102 @@ +-- +-- ALU de 1 Bit +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.STD_LOGIC_1164.all; + +entity ALU_1BIT is + port( + X : in STD_LOGIC; + Y : in STD_LOGIC; + LESS : in STD_LOGIC; + BINVERT : in STD_LOGIC; + CIN : in STD_LOGIC; + OP1 : in STD_LOGIC; + OP0 : in STD_LOGIC; + RES : out STD_LOGIC; + COUT : out STD_LOGIC; + SET : out STD_LOGIC + ); +end; + +architecture ALU_1BIT_ARC of ALU_1BIT is + +-- Declaración de componentes + component FULL_ADDER is + port( + X : in STD_LOGIC; + Y : in STD_LOGIC; + CIN : in STD_LOGIC; + COUT : out STD_LOGIC; + R : out STD_LOGIC + ); + end component FULL_ADDER; + +-- Declaración de señales + signal NEW_Y : STD_LOGIC; + signal R0,R1,R2,R3 : STD_LOGIC; + signal RES_AUX : STD_LOGIC; + +begin + + MUX_BINV: + process(BINVERT,Y) is + begin + if BINVERT='0' then + NEW_Y <= Y; + else + NEW_Y <= not Y; + end if; + end process MUX_BINV; + + R0 <= X and NEW_Y; + R1 <= X or NEW_Y; + + FULLADDER_ALU: + FULL_ADDER port map( + X => X, + Y => NEW_Y, + CIN => CIN, + COUT => COUT, + R => R2 + ); + + R3 <= LESS; + + MUX_RES_ALU: + process(OP1,OP0,R0,R1,R2,R3) is + begin + if (OP1 = '0' and OP0 = '0') then + RES_AUX <= R0; + elsif (OP1 = '0' and OP0 = '1') then + RES_AUX <= R1; + elsif (OP1 = '1' and OP0 = '0') then + RES_AUX <= R2; + elsif (OP1 = '1' and OP0 = '1') then + RES_AUX <= R3; + end if; + end process MUX_RES_ALU; + + RES <= RES_AUX; + SET <= R2; + +end ALU_1BIT_ARC;

3_execution/alu_1bit.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 3_execution/alu_control.vhd =================================================================== --- 3_execution/alu_control.vhd (nonexistent) +++ 3_execution/alu_control.vhd (revision 2) @@ -0,0 +1,49 @@ +-- +-- Control de la ALU del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.records_pkg.all; + +entity ALU_CONTROL is + port( + --Entradas + CLK : in STD_LOGIC; -- Reloj + FUNCT : in STD_LOGIC_VECTOR(5 downto 0); -- Campo de la instrucción FUNC + ALU_OP_IN : in ALU_OP_INPUT; -- Señal de control de la Unidad de Control + --Salidas + ALU_IN : out ALU_INPUT -- Entrada de la ALU + ); +end ALU_CONTROL; + +architecture ALU_CONTROL_ARC of ALU_CONTROL is +begin + + ALU_IN.Op0 <= ALU_OP_IN.Op1 and ( FUNCT(0) or FUNCT(3) ); + ALU_IN.Op1 <= (not ALU_OP_IN.Op1) or (not FUNCT(2)); + ALU_IN.Op2 <= ALU_OP_IN.Op0 or ( ALU_OP_IN.Op1 and FUNCT(1) ); + ALU_IN.Op3 <= ALU_OP_IN.Op2; + +end ALU_CONTROL_ARC;

3_execution/alu_control.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 3_execution/alu.vhd =================================================================== --- 3_execution/alu.vhd (nonexistent) +++ 3_execution/alu.vhd (revision 2) @@ -0,0 +1,125 @@ +-- +-- ALU del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.STD_LOGIC_1164.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + +entity ALU is + generic (N: NATURAL); + port( + X : in STD_LOGIC_VECTOR(N-1 downto 0); + Y : in STD_LOGIC_VECTOR(N-1 downto 0); + ALU_IN : in ALU_INPUT; + R : out STD_LOGIC_VECTOR(N-1 downto 0); + FLAGS : out ALU_FLAGS + ); +end; + +architecture ALU_ARC of ALU is + +-- Declaración de componentes + component ALU_1BIT is + port( + X : in STD_LOGIC; + Y : in STD_LOGIC; + LESS : in STD_LOGIC; + BINVERT : in STD_LOGIC; + CIN : in STD_LOGIC; + OP1 : in STD_LOGIC; + OP0 : in STD_LOGIC; + RES : out STD_LOGIC; + COUT : out STD_LOGIC; + SET : out STD_LOGIC + ); + end component ALU_1BIT; + +-- Declaración de señales + + signal LESS_AUX : STD_LOGIC; + signal COUT_AUX : STD_LOGIC_VECTOR(N-1 downto 0); + signal R_AUX : STD_LOGIC_VECTOR(N-1 downto 0); + +begin + + BEGIN_ALU1B: + ALU_1BIT port map ( + X => X(0), + Y => Y(0), + LESS => LESS_AUX, + BINVERT => ALU_IN.Op2, + CIN => ALU_IN.Op2, + OP1 => ALU_IN.Op1, + OP0 => ALU_IN.Op0, + RES => R_AUX(0), + COUT => COUT_AUX(0) + ); + + GEN_ALU: + for i in 1 to N-2 generate + NEXT_ALU1B: + ALU_1BIT port map ( + X => X(i), + Y => Y(i), + LESS => '0', + BINVERT => ALU_IN.Op2, + CIN => COUT_AUX(i-1), + OP1 => ALU_IN.Op1, + OP0 => ALU_IN.Op0, + RES => R_AUX(i), + COUT => COUT_AUX(i) + ); + end generate; + + LAST_ALU1B: + ALU_1BIT port map ( + X => X(N-1), + Y => Y(N-1), + LESS => '0', + BINVERT => ALU_IN.Op2, + CIN => COUT_AUX(N-2), + OP1 => ALU_IN.Op1, + OP0 => ALU_IN.Op0, + RES => R_AUX(N-1), + COUT => COUT_AUX(N-1), + SET => LESS_AUX + ); + + FLAGS.Carry <= COUT_AUX(N-1); + FLAGS.Overflow <= COUT_AUX(N-1) xor COUT_AUX(N-2) ; + FLAGS.Negative <= '1' when R_AUX(N-1)='1' else '0'; + FLAGS.Zero <= '1' when R_AUX= ZERO32b else '0'; + + ALU_RES: + process(ALU_IN.Op3,R_AUX,Y) + begin + if ALU_IN.Op3='1' then + R <= Y( ((N/2)-1) downto 0) & ZERO16b; + else + R <= R_AUX; + end if; + end process; + +end ALU_ARC;

3_execution/alu.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 3_execution/ex_mem_registers.vhd =================================================================== --- 3_execution/ex_mem_registers.vhd (nonexistent) +++ 3_execution/ex_mem_registers.vhd (revision 2) @@ -0,0 +1,81 @@ +-- +-- Registros de sincronización entre las etapas EX y MEM del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + +entity EX_MEM_REGISTERS is + port( + --Entradas + CLK : in STD_LOGIC; --Reloj + RESET : in STD_LOGIC; --Reset asincrónico + WB_CR_IN : in WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM_CR_IN : in MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección del PC + ALU_FLAGS_IN : in ALU_FLAGS; --Las flags de la ALU + ALU_RES_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --El resultado generado por la ALU + RT_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Entrará como Write Data en la etapa MEM + RT_RD_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --Se postergará hasta la etapa WB) + + --Salidas + WB_CR_OUT : out WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM_CR_OUT : out MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección del PC + ALU_FLAGS_OUT : out ALU_FLAGS; --Las flags de la ALU + ALU_RES_OUT : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); --El resultado generado por la ALU + RT_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Entrará como Write Data en la etapa MEM + RT_RD_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) --Se postergará hasta la etapa WB) + + ); +end EX_MEM_REGISTERS; + +architecture EX_MEM_REGISTERS_ARC of EX_MEM_REGISTERS is +begin + + SYNC_EX_MEM: + process(CLK,RESET,WB_CR_IN,MEM_CR_IN,NEW_PC_ADDR_IN,ALU_FLAGS_IN,ALU_RES_IN,RT_IN,RT_RD_ADDR_IN) + begin + if RESET = '1' then + WB_CR_OUT <= ('0','0'); + MEM_CR_OUT <= ('0','0','0'); + NEW_PC_ADDR_OUT <= ZERO32b; + ALU_FLAGS_OUT <= ('0','0','0','0'); + ALU_RES_OUT <= ZERO32b; + RT_OUT <= ZERO32b; + RT_RD_ADDR_OUT <= "00000"; + elsif rising_edge(CLK) then + WB_CR_OUT <= WB_CR_IN; + MEM_CR_OUT <= MEM_CR_IN; + NEW_PC_ADDR_OUT <= NEW_PC_ADDR_IN; + ALU_FLAGS_OUT <= ALU_FLAGS_IN; + ALU_RES_OUT <= ALU_RES_IN; + RT_OUT <= RT_IN; + RT_RD_ADDR_OUT <= RT_RD_ADDR_IN; + end if; + end process; + +end EX_MEM_REGISTERS_ARC;

3_execution/ex_mem_registers.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 3_execution/execution.vhd =================================================================== --- 3_execution/execution.vhd (nonexistent) +++ 3_execution/execution.vhd (revision 2) @@ -0,0 +1,203 @@ +-- +-- Etapa Execution (EX) del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + +entity EXECUTION is + port( + --Entradas + CLK : in STD_LOGIC; --Reloj + RESET : in STD_LOGIC; --Reset asincrónico + WB_CR : in WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM_CR : in MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM + EX_CR : in EX_CTRL_REG; --Estas señales se usarán en esta etapa + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección del PC + RS : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Datos leidos de la dir. Rs + RT : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Datos leidos de la dir. Rt + OFFSET : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Offset de la instrucción [15-0] + RT_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --Dirección del registro RT [20-16] + RD_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --Dirección del registro RD [15-11] + + --Salidas + WB_CR_OUT : out WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM_CR_OUT : out MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección del PC + ALU_FLAGS_OUT : out ALU_FLAGS; --Las flags de la ALU + ALU_RES_OUT : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); --El resultado generado por la ALU + RT_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Entrará como Write Data en la etapa MEM + RT_RD_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) --Se postergará hasta la etapa WB + ); +end EXECUTION; + +architecture EXECUTION_ARC of EXECUTION is + +--Declaración de componentes + component ALU_CONTROL is + port( + --Entradas + CLK : in STD_LOGIC; -- Reloj + FUNCT : in STD_LOGIC_VECTOR(5 downto 0); -- Campo de la instrucción FUNC + ALU_OP_IN : in ALU_OP_INPUT; -- Señal de control de la Unidad de Control + --Salidas + ALU_IN : out ALU_INPUT -- Entrada de la ALU + ); + end component ALU_CONTROL; + + component ALU is + generic (N:INTEGER := INST_SIZE); + port( + X : in STD_LOGIC_VECTOR(N-1 downto 0); + Y : in STD_LOGIC_VECTOR(N-1 downto 0); + ALU_IN : in ALU_INPUT; + R : out STD_LOGIC_VECTOR(N-1 downto 0); + FLAGS : out ALU_FLAGS + ); + end component ALU; + + component ADDER is + generic (N:INTEGER := INST_SIZE); + port( + X : in STD_LOGIC_VECTOR(N-1 downto 0); + Y : in STD_LOGIC_VECTOR(N-1 downto 0); + CIN : in STD_LOGIC; + COUT : out STD_LOGIC; + R : out STD_LOGIC_VECTOR(N-1 downto 0) + ); + end component ADDER; + + component EX_MEM_REGISTERS is + port( + --Entradas + CLK : in STD_LOGIC; --Reloj + RESET : in STD_LOGIC; --Reset asincrónico + WB_CR_IN : in WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM_CR_IN : in MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección del PC + ALU_FLAGS_IN : in ALU_FLAGS; --Las flags de la ALU + ALU_RES_IN : in STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); --El resultado generado por la ALU + RT_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Entrará como Write Data en la etapa MEM + RT_RD_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --Se postergará hasta la etapa WB) + + --Salidas + WB_CR_OUT : out WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM_CR_OUT : out MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección del PC + ALU_FLAGS_OUT : out ALU_FLAGS; --Las flags de la ALU + ALU_RES_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --El resultado generado por la ALU + RT_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Entrará como Write Data en la etapa MEM + RT_RD_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) --Se postergará hasta la etapa WB) + + ); + end component EX_MEM_REGISTERS; + +--Declaración de señales + signal CARRY_AUX : STD_LOGIC; + signal ALU_IN_AUX : ALU_INPUT; + signal PC_ADDR_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + signal RT_RD_ADDR_AUX : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); + signal OFFSET_SHIFT2 : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + signal ALU_REG_IN : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + signal ALU_RES_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + signal ALU_FLAGS_AUX : ALU_FLAGS; + +begin + OFFSET_SHIFT2 <= OFFSET(29 downto 0) & "00"; + + --Port maps + ALU_CTRL: + ALU_CONTROL port map( + CLK => CLK, + FUNCT => OFFSET(5 downto 0), + ALU_OP_IN => EX_CR.ALUOp, + ALU_IN => ALU_IN_AUX + ); + + ADDER_MIPS: + ADDER generic map (N => INST_SIZE) + port map( + X => NEW_PC_ADDR_IN, + Y => OFFSET_SHIFT2, + CIN => '0', + COUT => CARRY_AUX, + R => PC_ADDR_AUX + ); + + MUX_RT_RD: + process(EX_CR.RegDst,RT_ADDR,RD_ADDR) is + begin + if( EX_CR.RegDst = '0') then + RT_RD_ADDR_AUX <= RT_ADDR; + else + RT_RD_ADDR_AUX <= RD_ADDR; + end if; + end process MUX_RT_RD; + + MUX_ALU: + process(EX_CR.AluSrc,ALU_REG_IN,RT,OFFSET) + begin + if( EX_CR.AluSrc = '0') then + ALU_REG_IN <= RT; + else + ALU_REG_IN <= OFFSET; + end if; + end process MUX_ALU; + + ALU_MIPS: + ALU generic map (N => INST_SIZE) + port map( + X => RS, + Y => ALU_REG_IN, + ALU_IN => ALU_IN_AUX, + R => ALU_RES_AUX, + FLAGS => ALU_FLAGS_AUX + ); + + EX_MEM_REGS: + EX_MEM_REGISTERS port map( + --Entradas + CLK => CLK, + RESET => RESET, + WB_CR_IN => WB_CR, + MEM_CR_IN => MEM_CR, + NEW_PC_ADDR_IN => PC_ADDR_AUX, + ALU_FLAGS_IN => ALU_FLAGS_AUX, + ALU_RES_IN => ALU_RES_AUX, + RT_IN => RT, + RT_RD_ADDR_IN => RT_RD_ADDR_AUX, + --Salidas + WB_CR_OUT => WB_CR_OUT, + MEM_CR_OUT => MEM_CR_OUT, + NEW_PC_ADDR_OUT => NEW_PC_ADDR_OUT, + ALU_FLAGS_OUT => ALU_FLAGS_OUT, + ALU_RES_OUT => ALU_RES_OUT, + RT_OUT => RT_OUT, + RT_RD_ADDR_OUT => RT_RD_ADDR_OUT + ); + +end EXECUTION_ARC; +

3_execution/execution.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 1_instruction_fetching/if_id_registers.vhd =================================================================== --- 1_instruction_fetching/if_id_registers.vhd (nonexistent) +++ 1_instruction_fetching/if_id_registers.vhd (revision 2) @@ -0,0 +1,55 @@ +-- +-- Registros de sinctonización entre las etapas IF e ID +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.segm_mips_const_pkg.all; + + +entity IF_ID_REGISTERS is + port( + CLK : in STD_LOGIC; -- Reloj + RESET : in STD_LOGIC; -- Reset asincrónico + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); -- Salida del sumador + INST_REG_IN : in STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); -- Salida de la Memoria de Instrucción + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); -- Salida del sumador sincronizada + INST_REG_OUT : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0) -- Salida de la Memoria de Instrucción sincronizada + ); +end IF_ID_REGISTERS; + +architecture IF_ID_REGISTERS_ARC of IF_ID_REGISTERS is +begin + SYNC_IF_ID: + process(CLK,RESET,NEW_PC_ADDR_IN,INST_REG_IN) + begin + if RESET = '1' then + NEW_PC_ADDR_OUT <= (others => '0'); + INST_REG_OUT <= (others => '0'); + elsif rising_edge(CLK) then + NEW_PC_ADDR_OUT <= NEW_PC_ADDR_IN; + INST_REG_OUT<= INST_REG_IN; + end if; + end process; +end IF_ID_REGISTERS_ARC;

1_instruction_fetching/if_id_registers.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 1_instruction_fetching/instruction_fetching.vhd =================================================================== --- 1_instruction_fetching/instruction_fetching.vhd (nonexistent) +++ 1_instruction_fetching/instruction_fetching.vhd (revision 2) @@ -0,0 +1,144 @@ +-- +-- Etapa Instruction Fetching (IF) del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + +entity INSTRUCTION_FETCHING is + port( + --Entradas + CLK : in STD_LOGIC; -- Reloj + RESET : in STD_LOGIC; -- Reset asincrónico + PCSrc : in STD_LOGIC; -- Señal de habilitación del MUX_PC + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); -- Una de las entradas del MUX_PC + --Salidas + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); --Nueva instrucción del PC + INSTRUCTION : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0) --La instrucción encontrada en la Memoria de Instrucción + ); +end INSTRUCTION_FETCHING; + +architecture INSTRUCTION_FETCHING_ARC of INSTRUCTION_FETCHING is + +--Declaración de componentes + + component ADDER is + generic (N:NATURAL := INST_SIZE);-- Tamaño de los valores sumados + port( + X : in STD_LOGIC_VECTOR(N-1 downto 0); + Y : in STD_LOGIC_VECTOR(N-1 downto 0); + CIN : in STD_LOGIC; + COUT : out STD_LOGIC; + R : out STD_LOGIC_VECTOR(N-1 downto 0) + ); + end component ADDER; + + component REG is + generic (N:NATURAL := INST_SIZE); -- N = Tamaño del registro + port( + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + DATA_IN : in STD_LOGIC_VECTOR(N-1 downto 0); + DATA_OUT : out STD_LOGIC_VECTOR(N-1 downto 0) + ); + end component REG; + + component IF_ID_REGISTERS is + port( + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); + INST_REG_IN : in STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); + INST_REG_OUT : out STD_LOGIC_VECTOR(INST_SIZE-1 downto 0) + ); + end component IF_ID_REGISTERS; + + component INSTRUCTION_MEMORY is + port( + RESET : in STD_LOGIC; + READ_ADDR : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + INST : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0) + ); + end component INSTRUCTION_MEMORY; + +--Señales + signal PC_ADDR_AUX1 : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Vieja instrucción de PC + signal PC_ADDR_AUX2 : STD_LOGIC_VECTOR (INST_SIZE downto 0); --Nueva instrucción de PC + Carry out + signal PC_ADDR_AUX3 : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Salida del MUX_PC + signal INST_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Instrucción actual + +begin + + --Port maps + + myADDER : + ADDER generic map (N => INST_SIZE) + port map( + X => PC_ADDR_AUX1, + Y => PC_COUNT, --De a cuanto suma el PC (de a 4 bits) + CIN => '0', + COUT => PC_ADDR_AUX2(INST_SIZE), + R => PC_ADDR_AUX2(INST_SIZE-1 downto 0) + ); + + MUX_PC: + process(PCSrc,PC_ADDR_AUX2,NEW_PC_ADDR_IN) + begin + if( PCSrc = '0') then + PC_ADDR_AUX3 <= PC_ADDR_AUX2(INST_SIZE-1 downto 0); + else + PC_ADDR_AUX3 <= NEW_PC_ADDR_IN; + end if; + end process MUX_PC; + + PC : + REG generic map (N => INST_SIZE) + port map( + CLK => CLK, + RESET => RESET, + DATA_IN => PC_ADDR_AUX3, + DATA_OUT => PC_ADDR_AUX1 + ); + + INST_MEM: + INSTRUCTION_MEMORY port map( + RESET => RESET, + READ_ADDR => PC_ADDR_AUX1, + INST => INST_AUX + ); + + IF_ID_REG: + IF_ID_REGISTERS port map( + CLK => CLK, + RESET => RESET, + NEW_PC_ADDR_IN => PC_ADDR_AUX2(INST_SIZE-1 downto 0), + INST_REG_IN => INST_AUX, + NEW_PC_ADDR_OUT => NEW_PC_ADDR_OUT, + INST_REG_OUT => INSTRUCTION + ); + +end INSTRUCTION_FETCHING_ARC;

1_instruction_fetching/instruction_fetching.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 1_instruction_fetching/instruction_memory.vhd =================================================================== --- 1_instruction_fetching/instruction_memory.vhd (nonexistent) +++ 1_instruction_fetching/instruction_memory.vhd (revision 2) @@ -0,0 +1,150 @@ +-- +-- Memoria de instrucción del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library std; +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.segm_mips_const_pkg.all; + +entity INSTRUCTION_MEMORY is + port( + RESET : in STD_LOGIC; -- Reset asincrónico + READ_ADDR : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); -- Dirección de la instrucción a leer + INST : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0) -- Instrucción leída + ); +end INSTRUCTION_MEMORY; + + +architecture INSTRUCTION_MEMORY_ARC of INSTRUCTION_MEMORY is + +begin + + --Entrego la instrucción almacenada en la dir. dada de forma asincrónica + process (READ_ADDR) + begin + + case READ_ADDR is + when "00000000000000000000000000000000" => + INST <= "00000001010000000010000000100000"; + when "00000000000000000000000000000100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000001000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000001100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000010000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000010100" => + INST <= "00000000100000000001100000100000"; + when "00000000000000000000000000011000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000011100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000100000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000100100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000101000" => + INST <= "00000000011000110010000000100000"; + when "00000000000000000000000000101100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000110000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000110100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000111000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000000111100" => + INST <= "00000000100010110010000000100010"; + when "00000000000000000000000001000000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001000100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001001000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001001100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001010000" => + INST <= "00000000100000000100000000101010"; + when "00000000000000000000000001010100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001011000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001011100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001100000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001100100" => + INST <= "00010001000000010000000000001000"; + when "00000000000000000000000001101000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001101100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001110000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000001110100" => + INST <= "00000001100001010110000000100101"; + when "00000000000000000000000001111000" => + INST <= "00010000000000000000000000000100"; + when "00000000000000000000000001111100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010000000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010000100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010001000" => + INST <= "00000000011000110010000000100000"; + when "00000000000000000000000010001100" => + INST <= "00000000110000010011000000100000"; + when "00000000000000000000000010010000" => + INST <= "00000000101001010010100000100000"; + when "00000000000000000000000010010100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010011000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010011100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010100000" => + INST <= "00000000110001110100000000101010"; + when "00000000000000000000000010100100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010101000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010101100" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010110000" => + INST <= "00000000000000000000000000100010"; + when "00000000000000000000000010110100" => + INST <= "00010001000000011111111111010111"; + when others => + INST <= "11111111111111111111111111111111"; + end case; + + end process; + + +end INSTRUCTION_MEMORY_ARC;

1_instruction_fetching/instruction_memory.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 1_instruction_fetching/reg.vhd =================================================================== --- 1_instruction_fetching/reg.vhd (nonexistent) +++ 1_instruction_fetching/reg.vhd (revision 2) @@ -0,0 +1,49 @@ +-- +-- Registro concencional para implementación del Program Counter (PC) +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + + +entity REG is + generic (N: NATURAL); -- N = tam. dir. + port( + CLK : in STD_LOGIC; -- Reloj + RESET : in STD_LOGIC; -- Reset asincrónico + DATA_IN : in STD_LOGIC_VECTOR(N-1 downto 0); -- Datos de entrada + DATA_OUT : out STD_LOGIC_VECTOR(N-1 downto 0) -- Datos de salida + ); +end REG; + +architecture REG_ARC of REG is +begin + SYNC_REG: + process(CLK,RESET,DATA_IN) + begin + if(RESET = '1') then + DATA_OUT <= (others => '0'); + elsif rising_edge(CLK) then + DATA_OUT <= DATA_IN; + end if; + end process; +end REG_ARC;

1_instruction_fetching/reg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: segmented_mips_tb.vhd =================================================================== --- segmented_mips_tb.vhd (nonexistent) +++ segmented_mips_tb.vhd (revision 2) @@ -0,0 +1,72 @@ +-- +-- Test bench del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +entity SEGMENTED_MIPS_TB is +end SEGMENTED_MIPS_TB; + +architecture SEGMENTED_MIPS_TB_ARC of SEGMENTED_MIPS_TB is + +-- Declaración de componentes + component SEGMENTED_MIPS is + port( + CLK : in STD_LOGIC; + RESET : in STD_LOGIC + ); + end component SEGMENTED_MIPS; + +-- Declaración de señales + signal CLK : STD_LOGIC; + signal RESET : STD_LOGIC; + +begin + MIPS_TB: + SEGMENTED_MIPS port map( + CLK => CLK, + RESET => RESET + ); + + CLK_PROC: + process + begin + while true loop + CLK <= '0'; + wait for 10 ns; + CLK <= '1'; + wait for 10 ns; + end loop; + end process CLK_PROC; + + + RESET_PROC: + process + begin + RESET<='1'; + wait for 40 ns; + RESET<='0'; + wait; + end process RESET_PROC; + +end SEGMENTED_MIPS_TB_ARC;

segmented_mips_tb.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: shared_components/adder.vhd =================================================================== --- shared_components/adder.vhd (nonexistent) +++ shared_components/adder.vhd (revision 2) @@ -0,0 +1,79 @@ +-- +-- Sumador convencional. Usado en las etapas etapas IF y EX. +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; + +entity ADDER is + generic (N: natural); + port( + X : in STD_LOGIC_VECTOR(N-1 downto 0); + Y : in STD_LOGIC_VECTOR(N-1 downto 0); + CIN : in STD_LOGIC; + COUT : out STD_LOGIC; + R : out STD_LOGIC_VECTOR(N-1 downto 0) + ); +end ADDER; + +architecture ADDER_ARC of ADDER is + +--Declaración de componentes + + component FULL_ADDER is + port( + X : in STD_LOGIC; + Y : in STD_LOGIC; + CIN : in STD_LOGIC; + COUT : out STD_LOGIC; + R : out STD_LOGIC + ); + end component FULL_ADDER; + +--Declaración de señales + + signal CAUX : STD_LOGIC_VECTOR (N-1 downto 0); + +begin + + BEGIN_FA: + FULL_ADDER port map ( + X => X(0), + Y => Y(0), + CIN => CIN, + COUT => CAUX(0), + R => R(0) + ); + GEN_ADDER: + for i in 1 to N-1 generate + NEXT_FA: + FULL_ADDER port map ( + X => X(i), + Y => Y(i), + CIN => CAUX(i-1), + COUT=> CAUX(i), + R => R(i) + ); + end generate; + COUT <= CAUX(N-1); + +end ADDER_ARC;

shared_components/adder.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: shared_components/full_adder.vhd =================================================================== --- shared_components/full_adder.vhd (nonexistent) +++ shared_components/full_adder.vhd (revision 2) @@ -0,0 +1,29 @@ +-- +-- full_adder +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity FULL_ADDER is + port( + X : in std_logic; + Y : in std_logic; + CIN : in std_logic; + COUT : out std_logic; + R : out std_logic + ); +end FULL_ADDER; + +architecture FULL_ADDER_ARC of FULL_ADDER is + + +signal G,P,K : std_logic; + +begin + G <= X and Y; + P <= X xor Y; + K <= X nor Y; + COUT <= G or ( P and CIN ); + R <= P xor CIN; +end FULL_ADDER_ARC;

shared_components/full_adder.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: shared_components/records_pkg.vhd =================================================================== --- shared_components/records_pkg.vhd (nonexistent) +++ shared_components/records_pkg.vhd (revision 2) @@ -0,0 +1,82 @@ +-- +-- Registros que agrupan señales de control +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package RECORDS_PKG is + + + --Resgitros que aunan las salidas de la Unidad de Control + + type WB_CTRL_REG is + record + RegWrite : STD_LOGIC; --Señal de habilitación de escritura + MemtoReg : STD_LOGIC; --Señal de habilitación + end record; + + type MEM_CTRL_REG is + record + Branch : STD_LOGIC; --Señal de habilitación + MemRead : STD_LOGIC; --Señal de habilitación + MemWrite : STD_LOGIC; --Señal de habilitación + end record; + + type ALU_OP_INPUT is + record + Op0 : STD_LOGIC; + Op1 : STD_LOGIC; + Op2 : STD_LOGIC; + end record; + + type EX_CTRL_REG is + record + RegDst : STD_LOGIC; --Señal de habilitación + ALUOp : ALU_OP_INPUT; + ALUSrc : STD_LOGIC; --Señal de habilitación + end record; + + + --Registro que auna las entradas de la ALU + + type ALU_INPUT is + record + Op0 : STD_LOGIC; + Op1 : STD_LOGIC; + Op2 : STD_LOGIC; + Op3 : STD_LOGIC; + end record; + + --Registro que auna las flags de la ALU + + type ALU_FLAGS is + record + Carry : STD_LOGIC; + Overflow : STD_LOGIC; + Zero : STD_LOGIC; + Negative : STD_LOGIC; + end record; + + +end RECORDS_PKG;

shared_components/records_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: shared_components/segm_mips_const_pkg.vhd =================================================================== --- shared_components/segm_mips_const_pkg.vhd (nonexistent) +++ shared_components/segm_mips_const_pkg.vhd (revision 2) @@ -0,0 +1,44 @@ +-- +-- Este paquete contiene las constantes que se utilizan en el procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package SEGM_MIPS_CONST_PKG is + + --Constantes + + constant INST_SIZE : INTEGER := 32; -- Tamaño de una instrucción en bits + constant ADDR_SIZE : INTEGER := 5; -- Tamaño de una dirección + constant NUM_REG : INTEGER := 32; -- Cantidad de registros en el banco de registros + --constant NUM_ADDR : INTEGER := 1073741824; -- Cantidad de direcciones de la memoria, cada una de N bits (2 exp 30) + constant NUM_ADDR : INTEGER := 1024; -- Cantidad de direcciones de la memoria, cada una de N bits (reducida) + + constant PC_COUNT : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000100"; --De a cuanto suma el PC (de a 4 bits) + + constant ZERO32b : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000"; + constant ZERO16b : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000"; + constant ONE32b : STD_LOGIC_VECTOR(31 downto 0) := "11111111111111111111111111111111"; + constant ONE16b : STD_LOGIC_VECTOR(15 downto 0) := "1111111111111111"; + +end SEGM_MIPS_CONST_PKG; Index: 4_memory_access/data_memory.vhd =================================================================== --- 4_memory_access/data_memory.vhd (nonexistent) +++ 4_memory_access/data_memory.vhd (revision 2) @@ -0,0 +1,69 @@ +-- +-- Memoria de datos del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library std; +use std.textio.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.segm_mips_const_pkg.all; + + +entity DATA_MEMORY is + generic (N :NATURAL; M :NATURAL); -- N = tam. dir. M = tamaño de la memoria + port( + RESET : in STD_LOGIC; --Reset asincrónico + ADDR : in STD_LOGIC_VECTOR (N-1 downto 0); --Dirección a ser leida o escrita + WRITE_DATA : in STD_LOGIC_VECTOR (N-1 downto 0); --Datos a ser escritos + MemRead : in STD_LOGIC; --Señal de habilitación para lectura + MemWrite : in STD_LOGIC; --Señal de habilitación para escritura + READ_DATA : out STD_LOGIC_VECTOR (N-1 downto 0) --Datos leidos + ); +end DATA_MEMORY; + + +architecture DATA_MEMORY_ARC of DATA_MEMORY is + + type MEM_T is array (M-1 downto 0) of STD_LOGIC_VECTOR (N-1 downto 0); + signal MEM : MEM_T; + +begin + + MEM_PROC: + process(RESET,MemWrite,MemRead,WRITE_DATA,MEM,ADDR) + begin + if (RESET = '1') then -- Reset Asincrónico + for i in 0 to M-1 loop + MEM(i) <= (others => '1'); + end loop; + -- Ejecuto las ordenes de la unidad de control: + elsif MemWrite='1' then -- O bien escribo en la memoria + MEM(to_integer(unsigned( ADDR(9 downto 0) ))) <= WRITE_DATA; + elsif MemRead='1' then -- O bien leo de ella + READ_DATA <= MEM(to_integer(unsigned( ADDR(9 downto 0) ))); + end if; + end process MEM_PROC; + +end DATA_MEMORY_ARC;

4_memory_access/data_memory.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 4_memory_access/memory_access.vhd =================================================================== --- 4_memory_access/memory_access.vhd (nonexistent) +++ 4_memory_access/memory_access.vhd (revision 2) @@ -0,0 +1,136 @@ +-- +-- Etapa Memory Access (MEM) del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + +entity MEMORY_ACCESS is + port( + --Entradas + CLK : in STD_LOGIC; --Reloj + RESET : in STD_LOGIC; --Reset asincrónico + WB_IN : in WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM : in MEM_CTRL_REG; --Estas señales serán usadas en esta etapa + FLAG_ZERO : in STD_LOGIC; --Flag Zero de la ALU + NEW_PC_ADDR : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección de pc hacia la etapa de IF + ADDRESS_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Salida de la ALU (ALU Result), dirección de la memoria de datos + WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Datos a ser escritos en la memoria de datos + WRITE_REG_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --WriteRegister de los registros de la etapa de ID + --Salidas hacia la etapa WB, sincronizadas por registros + WB_OUT : out WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + READ_DATA : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Datos leidos de la memoria de datos + ADDRESS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Resultado de la ALU + WRITE_REG_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --WriteRegister de los registros de la etapa de ID + --Salidas hacia la etapas IF, sin sincronización + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Nueva dirección de pc hacia la etapa de IF + PCSrc : out STD_LOGIC --Señal de habilitación del mux de la etapa de IF + ); +end MEMORY_ACCESS; + +architecture MEMORY_ACCESS_ARC of MEMORY_ACCESS is + +-- Declaración de componentes + + component DATA_MEMORY is + generic (N :NATURAL :=INST_SIZE; M :NATURAL :=NUM_ADDR); -- N = tam. dir. ; M = tamaño de la memoria + port( + RESET : in STD_LOGIC; --Reset asincrónico + ADDR : in STD_LOGIC_VECTOR (N-1 downto 0); --Dirección a ser leida o escrita + WRITE_DATA : in STD_LOGIC_VECTOR (N-1 downto 0); --Datos a ser escritos + MemRead : in STD_LOGIC; --Señal de hailitación para lectura + MemWrite : in STD_LOGIC; --Señal de hailitación para escritura + READ_DATA : out STD_LOGIC_VECTOR (N-1 downto 0) --Datos leidos + + ); + end component DATA_MEMORY; + + component MEM_WB_REGISTERS is + port( + --Entradas + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + WB : in WB_CTRL_REG; + READ_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + ADDRESS : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + WRITE_REG : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); + --Salidas + WB_OUT : out WB_CTRL_REG; + READ_DATA_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + ADDRESS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + WRITE_REG_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) + ); + end component MEM_WB_REGISTERS; + + +--Declaración de señales + signal READ_DATA_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + +begin + + OUT_MEM: + process(RESET,FLAG_ZERO,MEM.Branch,NEW_PC_ADDR) + begin + if( RESET = '1') then + PCSrc <= '0'; + NEW_PC_ADDR_OUT <= ZERO32b; + else + PCSrc <= FLAG_ZERO and MEM.Branch; + NEW_PC_ADDR_OUT <= NEW_PC_ADDR; + end if; + end process OUT_MEM; + + DAT_MEM: + DATA_MEMORY generic map (N=>INST_SIZE, M=>NUM_ADDR) + port map( + RESET => RESET, + ADDR => ADDRESS_IN, + WRITE_DATA => WRITE_DATA, + MemRead => MEM.MemRead, + MemWrite => MEM.MemWrite, + READ_DATA => READ_DATA_AUX + + ); + + MEM_WB_REGS: + MEM_WB_REGISTERS port map( + --Entradas + CLK => CLK, + RESET => RESET, + WB => WB_IN, + READ_DATA => READ_DATA_AUX, + ADDRESS => ADDRESS_IN, + WRITE_REG => WRITE_REG_IN, + --Salidas + WB_OUT => WB_OUT, + READ_DATA_OUT => READ_DATA, + ADDRESS_OUT => ADDRESS_OUT, + WRITE_REG_OUT => WRITE_REG_OUT + ); + + +end MEMORY_ACCESS_ARC;

4_memory_access/memory_access.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 4_memory_access/mem_wb_registers.vhd =================================================================== --- 4_memory_access/mem_wb_registers.vhd (nonexistent) +++ 4_memory_access/mem_wb_registers.vhd (revision 2) @@ -0,0 +1,67 @@ +-- +-- Registros de sincronización entre las etapas MEM y WB del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + + +entity MEM_WB_REGISTERS is + port( + --Entradas + CLK : in STD_LOGIC; + RESET : in STD_LOGIC; + WB : in WB_CTRL_REG; + READ_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + ADDRESS : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + WRITE_REG : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); + --Salidas + WB_OUT : out WB_CTRL_REG; + READ_DATA_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + ADDRESS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + WRITE_REG_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) + ); +end MEM_WB_REGISTERS; + +architecture MEM_WB_REGISTERS_ARC of MEM_WB_REGISTERS is +begin + SYNC_MEM_WB: + process(CLK,RESET,WB,READ_DATA,ADDRESS,WRITE_REG) + begin + if RESET = '1' then + WB_OUT <= ('0','0'); + READ_DATA_OUT <= ZERO32b; + ADDRESS_OUT <= ZERO32b; + WRITE_REG_OUT <= "00000"; + elsif rising_edge(CLK) then + WB_OUT <= WB; + READ_DATA_OUT <= READ_DATA; + ADDRESS_OUT <= ADDRESS; + WRITE_REG_OUT <= WRITE_REG; + end if; + end process; + +end MEM_WB_REGISTERS_ARC;

4_memory_access/mem_wb_registers.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 2_instruction_decoding/id_ex_registers.vhd =================================================================== --- 2_instruction_decoding/id_ex_registers.vhd (nonexistent) +++ 2_instruction_decoding/id_ex_registers.vhd (revision 2) @@ -0,0 +1,97 @@ +-- +-- Registros de sinctonización entre las etapas ID y EX +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + + +entity ID_EX_REGISTERS is + port( + --Entradas + CLK : in STD_LOGIC; -- Reloj + RESET : in STD_LOGIC; -- Reset asincrónico + --Salidas de la etapa de Búsqueda de la Instrucción (IF) + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Nueva dirección del PC + --Salidas generadas a partir de la instrucción + OFFSET_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Offset de la instrucción [15-0] + RT_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RT [20-16] + RD_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RD [15-11] + --Salidas del Banco de Registros + RS_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rs + RT_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rt + --Salidas de la Unidad de Control + WB_IN : in WB_CTRL_REG; -- Señales de control para la etapa WB + M_IN : in MEM_CTRL_REG; -- Señales de control para la etapa MEM + EX_IN : in EX_CTRL_REG; -- Señales de control para la etapa EX + + --Salidas + + --Salidas de la etapa de Búsqueda de la Instrucción (IF) + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Nueva dirección del PC + --Salidas generadas a partir de la instrucción + OFFSET_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Offset de la instrucción [15-0] + RT_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RT [20-16] + RD_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RD [15-11] + --Salidas del Banco de Registros + RS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rs + RT_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rt + --Salidas de la Unidad de Control + WB_OUT : out WB_CTRL_REG; -- Estas señales se postergarán hasta la etapa WB + M_OUT : out MEM_CTRL_REG; -- Estas señales se postergarán hasta la etapa MEM + EX_OUT : out EX_CTRL_REG -- Estas señales se postergarán hasta la etapa EX + ); +end ID_EX_REGISTERS; + +architecture ID_EX_REGISTERS_ARC of ID_EX_REGISTERS is +begin + SYNC_ID_EX: + process(CLK,RESET,NEW_PC_ADDR_IN,OFFSET_IN,RT_ADDR_IN,RD_ADDR_IN,RS_IN,RT_IN,WB_IN,M_IN,EX_IN) + begin + if RESET = '1' then + NEW_PC_ADDR_OUT <= (others => '0'); + OFFSET_OUT <= (others => '0'); + RT_ADDR_OUT <= (others => '0'); + RD_ADDR_OUT <= (others => '0'); + RS_OUT <= (others => '0'); + RT_OUT <= (others => '0'); + WB_OUT <= ('0','0'); + M_OUT <= ('0','0','0'); + EX_OUT <= ('0',('0','0','0'),'0'); + elsif rising_edge(CLK) then + NEW_PC_ADDR_OUT <= NEW_PC_ADDR_IN; + OFFSET_OUT <= OFFSET_IN; + RT_ADDR_OUT <= RT_ADDR_IN; + RD_ADDR_OUT <= RD_ADDR_IN; + RS_OUT <= RS_IN; + RT_OUT <= RT_IN; + WB_OUT <= WB_IN; + M_OUT <= M_IN; + EX_OUT <= EX_IN; + end if; + end process; + +end ID_EX_REGISTERS_ARC;

2_instruction_decoding/id_ex_registers.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 2_instruction_decoding/control_unit.vhd =================================================================== --- 2_instruction_decoding/control_unit.vhd (nonexistent) +++ 2_instruction_decoding/control_unit.vhd (revision 2) @@ -0,0 +1,88 @@ +-- +-- Unidad de control del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.segm_mips_const_pkg.all; + + +entity CONTROL_UNIT is + port( + + OP : in STD_LOGIC_VECTOR (5 downto 0); --Código de operación + + RegWrite : out STD_LOGIC; --Señal de habilitación de escritura (RegWrite) + MemtoReg : out STD_LOGIC; --Señal de habilitación (MemToReg) + Brach : out STD_LOGIC; --Señal de habilitación (Branch) + MemRead : out STD_LOGIC; --Señal de habilitación (MemRead) + MemWrite : out STD_LOGIC; --Señal de habilitación (MemWrite) + RegDst : out STD_LOGIC; --Señal de habilitación (RegDst) + ALUSrc : out STD_LOGIC; --Señal de habilitación (ALUSrc) + ALUOp0 : out STD_LOGIC; --Señal de habilitación (ALUOp0) + ALUOp1 : out STD_LOGIC; --Señal de habilitación (ALUOp1) + ALUOp2 : out STD_LOGIC --Señal de habilitación (ALUOp2) + + ); +end CONTROL_UNIT; + + +architecture CONTROL_UNIT_ARC of CONTROL_UNIT is + +--Decaración de señales + signal R_TYPE : STD_LOGIC; + signal LW : STD_LOGIC; + signal SW : STD_LOGIC; + signal BEQ : STD_LOGIC; + signal LUI : STD_LOGIC; + +begin + + R_TYPE <= not OP(5) and not OP(4) and not OP(3) and + not OP(2) and not OP(1) and not OP(0); + + LW <= OP(5) and not OP(4) and not OP(3) and + not OP(2) and OP(1) and OP(0); + + SW <= OP(5) and not OP(4) and OP(3) and + not OP(2) and OP(1) and OP(0); + + BEQ <= not OP(5) and not OP(4) and not OP(3) and + OP(2) and not OP(1) and not OP(0); + + LUI <= not OP(5) and not OP(4) and OP(3) and + OP(2) and OP(1) and OP(0); + + RegWrite <= R_TYPE or LW or LUI; + MemtoReg <= LW; + Brach <= BEQ; + MemRead <= LW or LUI; + MemWrite <= SW; + RegDst <= R_TYPE; + ALUSrc <= LW or SW or LUI; + ALUOp0 <= BEQ; + ALUOp1 <= R_TYPE; + ALUOp2 <= LUI; + +end CONTROL_UNIT_ARC;

2_instruction_decoding/control_unit.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 2_instruction_decoding/registers.vhd =================================================================== --- 2_instruction_decoding/registers.vhd (nonexistent) +++ 2_instruction_decoding/registers.vhd (revision 2) @@ -0,0 +1,122 @@ +-- +-- Banco de registros del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.segm_mips_const_pkg.all; + + +entity REGISTERS is + port( + --Entradas + CLK : in STD_LOGIC; --Reloj + RESET : in STD_LOGIC; --Reset asincrónico + RW : in STD_LOGIC; --Señal de habilitación de escritura (RegWrite) + RS_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rs + RT_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rt + RD_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rd + WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos a ser escritos + --Salidas + RS : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rs + RT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0) --Datos leidos de la dir. Rt + ); +end REGISTERS; + +architecture REGISTERS_ARC of REGISTERS is + + -- Tipo para almacenar los registros + type REGS_T is array (NUM_REG-1 downto 0) of STD_LOGIC_VECTOR(INST_SIZE-1 downto 0); + + -- Esta es la señal que contiene los registros. El acceso es de la + -- siguiente manera: regs(i) acceso al registro i, donde i es + -- un entero. Para convertir del tipo STD_LOGIC_VECTOR a entero se + -- hace de la siguiente manera: to_integer(unsigned(slv)), donde + -- slv es un elemento de tipo STD_LOGIC_VECTOR + signal REGISTROS : REGS_T; + +begin + + REG_ASIG: + process(CLK,RESET,RW,WRITE_DATA,RD_ADDR) + begin + if RESET='1' then + for i in 0 to NUM_REG-1 loop + REGISTROS(i) <= (others => '0'); + end loop; + --Los resgitros son completados de esta manera para + --la prueba del algoritmo "Restoring", ya que no se + --ha implementado la instrucción LLI + REGISTROS(0) <= "00000000000000000000000000000000"; + REGISTROS(1) <= "00000000000000000000000000000001"; + REGISTROS(2) <= "00000000000000000000000000000010"; + REGISTROS(3) <= "00000000000000000000000000000011"; + REGISTROS(4) <= "00000000000000000000000000000100"; + --REGISTROS(5) <= "00000000000000000000000000000101"; + REGISTROS(5) <= "00000000000000000000000000000001"; + --REGISTROS(6) <= "00000000000000000000000000000110"; + REGISTROS(6) <= "00000000000000000000000000000000"; + --REGISTROS(7) <= "00000000000000000000000000000111"; + REGISTROS(7) <= "00000000000000000000000000100000"; + --REGISTROS(8) <= "00000000000000000000000000001000"; + REGISTROS(8) <= "00000000000000000000000000000000"; + REGISTROS(9) <= "00000000000000000000000000001001"; + --REGISTROS(10) <= "00000000000000000000000000001010"; + REGISTROS(10) <= "00000000000000000000000000010011"; + --REGISTROS(11) <= "00000000000000000000000000001011"; + REGISTROS(11) <= "00000000000000000000000000011010"; + --REGISTROS(12) <= "00000000000000000000000000001100"; + REGISTROS(12) <= "00000000000000000000000000000000"; + REGISTROS(13) <= "00000000000000000000000000001101"; + REGISTROS(14) <= "00000000000000000000000000001110"; + REGISTROS(15) <= "00000000000000000000000000001111"; + REGISTROS(16) <= "00000000000000000000000000010000"; + REGISTROS(17) <= "00000000000000000000000000010001"; + REGISTROS(18) <= "00000000000000000000000000010010"; + REGISTROS(19) <= "00000000000000000000000000010011"; + REGISTROS(20) <= "00000000000000000000000000010100"; + REGISTROS(21) <= "00000000000000000000000000010101"; + REGISTROS(22) <= "00000000000000000000000000010110"; + REGISTROS(23) <= "00000000000000000000000000010111"; + REGISTROS(24) <= "00000000000000000000000000011000"; + REGISTROS(25) <= "00000000000000000000000000011001"; + REGISTROS(26) <= "00000000000000000000000000011010"; + REGISTROS(27) <= "00000000000000000000000000011011"; + REGISTROS(28) <= "00000000000000000000000000011100"; + REGISTROS(29) <= "00000000000000000000000000011101"; + REGISTROS(30) <= "00000000000000000000000000011110"; + REGISTROS(31) <= "00000000000000000000000000011111"; + elsif rising_edge(CLK) then + if RW='1' then + REGISTROS(to_integer(unsigned(RD_ADDR)))<=WRITE_DATA; + end if; + end if; + end process REG_ASIG; + + RS <= (others=>'0') when RS_ADDR="00000" + else REGISTROS(to_integer(unsigned(RS_ADDR))); + RT <= (others=>'0') when RT_ADDR="00000" + else REGISTROS(to_integer(unsigned(RT_ADDR))); + +end REGISTERS_ARC;

2_instruction_decoding/registers.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 2_instruction_decoding/instruction_decoding.vhd =================================================================== --- 2_instruction_decoding/instruction_decoding.vhd (nonexistent) +++ 2_instruction_decoding/instruction_decoding.vhd (revision 2) @@ -0,0 +1,224 @@ +-- +-- Etapa Instruction Decoding (ID) del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + +entity INSTRUCTION_DECODING is + port( + CLK : in STD_LOGIC; --Reloj + RESET : in STD_LOGIC; --Reset asincrónico + --Entradas de la etapa de Búsqueda de la Instrucción (IF) + INSTRUCTION : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Instrucción + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Nueva dirección del PC + --Entradas de la etapa de Post Escritura (WB) + RegWrite : in STD_LOGIC; --Señal de habilitación de escritura (RegWrite) + WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos a ser escritos + WRITE_REG : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rd + --Salidas de la etapa de Búsqueda de la Instrucción (IF) + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Nueva dirección del PC + --Salidas generadas a partir de la instrucción + OFFSET : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Offset de la instrucción [15-0] + RT_ADDR : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro RT [20-16] + RD_ADDR : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro RD [15-11] + --Salidas del Banco de Registros + RS : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rs + RT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rt + --Salidas de la Unidad de Control + WB_CR : out WB_CTRL_REG; --Estas señales se postergarán hasta la etapa WB + MEM_CR : out MEM_CTRL_REG; --Estas señales se postergarán hasta la etapa MEM + EX_CR : out EX_CTRL_REG --Estas señales se postergarán hasta la etapa EX + ); +end INSTRUCTION_DECODING; + +architecture INSTRUCTION_DECODING_ARC of INSTRUCTION_DECODING is + +--Declaración de componentes + + component REGISTERS is + port( + CLK : in STD_LOGIC; --Reloj + RESET : in STD_LOGIC; --Reset asincrónico + RW : in STD_LOGIC; --Señal de habilitación de escritura (RegWrite) + RS_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rs + RT_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rt + RD_ADDR : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);--Dirección del registro Rd + WRITE_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos a ser escritos + RS : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);--Datos leidos de la dir. Rs + RT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0) --Datos leidos de la dir. Rt + ); + end component REGISTERS; + + + component CONTROL_UNIT is + port( + OP : in STD_LOGIC_VECTOR (5 downto 0); --Código de operación + RegWrite : out STD_LOGIC; --Señal de habilitación de escritura (RegWrite) + MemtoReg : out STD_LOGIC; --Señal de habilitación (MemToReg) + Brach : out STD_LOGIC; --Señal de habilitación (Branch) + MemRead : out STD_LOGIC; --Señal de habilitación (MemRead) + MemWrite : out STD_LOGIC; --Señal de habilitación (MemWrite) + RegDst : out STD_LOGIC; --Señal de habilitación (RegDst) + ALUSrc : out STD_LOGIC; --Señal de habilitación (ALUSrc) + ALUOp0 : out STD_LOGIC; --Señal de habilitación (ALUOp) + ALUOp1 : out STD_LOGIC; --Señal de habilitación (ALUOp) + ALUOp2 : out STD_LOGIC --Señal de habilitación (ALUOp2) + ); + end component CONTROL_UNIT; + + + component ID_EX_REGISTERS is + port( + --Entradas + + CLK : in STD_LOGIC; -- Reloj + RESET : in STD_LOGIC; -- Reset asincrónico + --Salidas de la etapa de Búsqueda de la Instrucción (IF) + NEW_PC_ADDR_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Nueva dirección del PC + --Salidas generadas a partir de la instrucción + OFFSET_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Offset de la instrucción [15-0] + RT_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RT [20-16] + RD_ADDR_IN : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RD [15-11] + --Salidas del Banco de Registros + RS_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rs + RT_IN : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rt + --Salidas de la Unidad de Control + WB_IN : in WB_CTRL_REG; -- Señales de control para la etapa WB + M_IN : in MEM_CTRL_REG; -- Señales de control para la etapa MEM + EX_IN : in EX_CTRL_REG; -- Señales de control para la etapa EX + + --Salidas + + --Salidas de la etapa de Búsqueda de la Instrucción (IF) + NEW_PC_ADDR_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Nueva dirección del PC + --Salidas generadas a partir de la instrucción + OFFSET_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Offset de la instrucción [15-0] + RT_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RT [20-16] + RD_ADDR_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0);-- Dirección del registro RD [15-11] + --Salidas del Banco de Registros + RS_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rs + RT_OUT : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0);-- Datos leidos de la dir. Rt + --Salidas de la Unidad de Control + WB_OUT : out WB_CTRL_REG; -- Estas señales se postergarán hasta la etapa WB + M_OUT : out MEM_CTRL_REG; -- Estas señales se postergarán hasta la etapa MEM + EX_OUT : out EX_CTRL_REG -- Estas señales se postergarán hasta la etapa EX + ); + end component ID_EX_REGISTERS; + +--Declaración de señales + + -- Buses de datos auxiliares para comunicar las distintas salidas + -- que los componentes generan y dárselas a los registros de + -- sincronización de etapas. + signal OFFSET_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + signal RS_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + signal RT_AUX : STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); + signal WB_AUX : WB_CTRL_REG; + signal MEM_AUX : MEM_CTRL_REG; + signal EX_AUX : EX_CTRL_REG; + +--Alias + -- Se encuentran comentados debido a que GHDL no soporta su uso. + + --alias OP_A : STD_LOGIC_VECTOR (5 downto 0) is INSTRUCTION(INST_SIZE-1 downto 26); + --alias RS_ADDR_A : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) is INSTRUCTION(25 downto 21); + --alias RT_ADDR_A : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) is INSTRUCTION(20 downto 16); + --alias RD_ADDR_A : STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0) is INSTRUCTION(15 downto 11); + --alias OFFSET_A : STD_LOGIC_VECTOR (15 downto 0) is INSTRUCTION(15 downto 0); + +begin + + --Port maps + REGS: + REGISTERS port map( + CLK => CLK, + RESET => RESET, + RW => RegWrite, + RS_ADDR => INSTRUCTION(25 downto 21),--RS_ADDR_A, + RT_ADDR => INSTRUCTION(20 downto 16),--RT_ADDR_A, + RD_ADDR => WRITE_REG, + WRITE_DATA => WRITE_DATA, + RS => RS_AUX, + RT => RT_AUX + ); + + CTRL : + CONTROL_UNIT port map( + --Entrada + OP => INSTRUCTION(INST_SIZE-1 downto 26),--OP_A, + --Salidas + RegWrite => WB_AUX.RegWrite, + MemtoReg => WB_AUX.MemtoReg, + Brach => MEM_AUX.Branch, + MemRead => MEM_AUX.MemRead, + MemWrite => MEM_AUX.MemWrite, + RegDst => EX_AUX.RegDst, + ALUSrc => EX_AUX.ALUSrc, + ALUOp0 => EX_AUX.ALUOp.Op0, + ALUOp1 => EX_AUX.ALUOp.Op1, + ALUOp2 => EX_AUX.ALUOp.Op2 + ); + + --Se hace una extensión de signo + --OFFSET_AUX <= ZERO16b & OFFSET_A + -- when OFFSET_A(15) = '0' + -- else ONE16b & OFFSET_A; + + + OFFSET_AUX <= ZERO16b & INSTRUCTION(15 downto 0) + when INSTRUCTION(15) = '0' + else ONE16b & INSTRUCTION(15 downto 0); + + + ID_EX_REGS: + ID_EX_REGISTERS port map( + --Entradas + CLK => CLK, + RESET => RESET, + NEW_PC_ADDR_IN => NEW_PC_ADDR_IN, + OFFSET_IN => OFFSET_AUX, + RT_ADDR_IN => INSTRUCTION(20 downto 16),--RT_ADDR_A, + RD_ADDR_IN => INSTRUCTION(15 downto 11),--RD_ADDR_A, + RS_IN => RS_AUX, + RT_IN => RT_AUX, + WB_IN => WB_AUX, + M_IN => MEM_AUX, + EX_IN => EX_AUX, + --Salidas + NEW_PC_ADDR_OUT => NEW_PC_ADDR_OUT, + OFFSET_OUT => OFFSET, + RT_ADDR_OUT => RT_ADDR, + RD_ADDR_OUT => RD_ADDR, + RS_OUT => RS, + RT_OUT => RT, + WB_OUT => WB_CR, + M_OUT => MEM_CR, + EX_OUT => EX_CR + ); + +end INSTRUCTION_DECODING_ARC;

2_instruction_decoding/instruction_decoding.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: 5_write_back/write_back.vhd =================================================================== --- 5_write_back/write_back.vhd (nonexistent) +++ 5_write_back/write_back.vhd (revision 2) @@ -0,0 +1,67 @@ +-- +-- Etapa Write back (WB) del procesador MIPS Segmentado +-- +-- Licencia: Copyright 2008 Emmanuel Luján +-- +-- This program is free software; you can redistribute it and/or +-- modify it under the terms of the GNU General Public License as +-- published by the Free Software Foundation; either version 2 of +-- the License, or (at your option) any later version. This program +-- is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +-- License for more details. You should have received a copy of the +-- GNU General Public License along with this program; if not, write +-- to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, +-- Boston, MA 02110-1301 USA. +-- +-- Autor: Emmanuel Luján +-- Email: info@emmanuellujan.com.ar +-- Versión: 1.0 +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.records_pkg.all; +use work.segm_mips_const_pkg.all; + +entity WRITE_BACK is +port( + --Entradas + RESET : in STD_LOGIC; --Reset + WB : in WB_CTRL_REG; --Señales de control para esta etapa + READ_DATA : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Posible dato a ser escribido en la memoria de registros + ADDRESS : in STD_LOGIC_VECTOR (INST_SIZE-1 downto 0); --Posible dato a ser escribido en la memoria de registros + WRITE_REG : in STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --Dirección del registro a ser escrito en la memoria de registros + --Salidas hacia la etapas ID, sin sincronización + RegWrite : out STD_LOGIC; --WB_OUT.RegWrite + WRITE_REG_OUT : out STD_LOGIC_VECTOR (ADDR_SIZE-1 downto 0); --Dirección del registro a ser escrito en la memoria de registros + WRITE_DATA : out STD_LOGIC_VECTOR (INST_SIZE-1 downto 0) --Este dato representa a READ_DATA o a ADDRESS, según lo decida WB_OUT.MemtoReg +); +end WRITE_BACK; + +architecture WRITE_BACK_ARC of WRITE_BACK is +begin + + MUX_WB: + process(RESET,WB.RegWrite,WRITE_REG,WB.MemtoReg,ADDRESS,READ_DATA) + begin + if( RESET = '1') then + RegWrite <= '0'; + WRITE_REG_OUT <= "00000"; + WRITE_DATA <= ZERO32b; + else + RegWrite <= WB.RegWrite; + WRITE_REG_OUT <= WRITE_REG; + if( WB.MemtoReg = '0') then + WRITE_DATA <= ADDRESS; + else + WRITE_DATA <= READ_DATA; + end if; + end if; + end process MUX_WB; + +end WRITE_BACK_ARC;

5_write_back/write_back.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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