OpenCores
URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

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    /virtex7_pcie_dma/trunk
    from Rev 34 to Rev 35
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Rev 34 → Rev 35

/firmware/sources/pcie/dma_control.vhd
84,30 → 84,33
s_axis_r_cq : out axis_r_type;
fifo_full : in std_logic;
fifo_empty : in std_logic;
dma_interrupt_call : out std_logic_vector(3 downto 0));
dma_interrupt_call : out std_logic_vector(3 downto 0);
pfull_threshold_assert: out std_logic_vector(6 downto 0);
pfull_threshold_negate: out std_logic_vector(6 downto 0));
end entity dma_control;
 
 
architecture rtl of dma_control is
 
type completer_state_type is(IDLE, READ_REGISTER, WRITE_REGISTER_READ, WRITE_REGISTER_MODIFYWRITE, SEND_UNKNOWN_REQUEST);
type completer_state_type is(IDLE, READ_REGISTER, WRITE_REGISTER_READ, WRITE_REGISTER_MODIFYWRITE, WAIT_RW_DONE, SEND_UNKNOWN_REQUEST);
signal completer_state: completer_state_type := IDLE;
signal completer_state_slv: std_logic_vector(2 downto 0);
attribute dont_touch : string;
attribute dont_touch of completer_state_slv : signal is "true";
 
constant IDLE_SLV : std_logic_vector(2 downto 0) := "000";
constant READ_REGISTER_SLV : std_logic_vector(2 downto 0) := "001";
constant WRITE_REGISTER_READ_SLV : std_logic_vector(2 downto 0) := "011";
constant WRITE_REGISTER_MODIFYWRITE_SLV : std_logic_vector(2 downto 0) := "100";
constant WAIT_RW_DONE_SLV : std_logic_vector(2 downto 0) := "101";
constant SEND_UNKNOWN_REQUEST_SLV : std_logic_vector(2 downto 0) := "111";
 
signal dma_descriptors_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_descriptors_40_r_s : dma_descriptors_type(0 to 7);
signal dma_descriptors_40_w_s : dma_descriptors_type(0 to 7);
signal dma_descriptors_w_250_s : dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
 
 
signal dma_status_s : dma_statuses_type(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_status_40_s : dma_statuses_type(0 to 7);
 
114,7 → 117,7
signal int_vector_s : interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
signal int_vector_40_s : interrupt_vectors_type(0 to 7);
signal int_table_en_s : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
 
signal register_address_s : std_logic_vector(63 downto 0);
signal address_type_s : std_logic_vector(1 downto 0);
signal dword_count_s : std_logic_vector(10 downto 0);
133,7 → 136,7
signal register_map_monitor_s : register_map_monitor_type;
signal register_map_control_s : register_map_control_type;
signal tlast_timer_s : std_logic_vector(7 downto 0);
 
signal register_read_address_250_s : std_logic_vector(31 downto 0);
signal register_read_address_40_s : std_logic_vector(31 downto 0);
signal register_read_enable_250_s : std_logic;
171,12 → 174,16
signal last_current_address_s : slv64_arr;
signal last_pc_pointer_s : slv64_arr;
 
signal dma_wait : std_logic_vector(0 to (NUMBER_OF_DESCRIPTORS-1));
signal dma_wait : std_logic_vector(0 to (NUMBER_OF_DESCRIPTORS-1));
signal pfull_threshold_assert_s : std_logic_vector(6 downto 0);
signal pfull_threshold_negate_s : std_logic_vector(6 downto 0);
 
 
begin
 
pfull_threshold_assert <= pfull_threshold_assert_s;
pfull_threshold_negate <= pfull_threshold_negate_s;
 
begin
 
dma_status_s(0 to (NUMBER_OF_DESCRIPTORS-1)) <= dma_status;
 
381,6 → 388,8
byte_count_v := dword_count_v&"00";
completion_status_v := "000";
locked_completion_v := '0';
s_axis_r_cq.tready <= '0';
case(dword_count_v(2 downto 0)) is
when "001" => m_axis_cc.tkeep <= x"0F";
when "010" => m_axis_cc.tkeep <= x"1F";
398,10 → 407,9
m_axis_cc.tvalid <= '1';
--completer state can also be overruled in the case statement below:
if(m_axis_r_cc.tready = '0') then
s_axis_r_cq.tready <= '0';
completer_state <= READ_REGISTER;
else
completer_state <= IDLE;
completer_state <= WAIT_RW_DONE;
end if;
else
register_read_enable_250_s <= '1';
491,23 → 499,22
register_write_data_250_s <= register_data_v;
register_write_address_250_s <= register_address_s(31 downto 4)&"0000";
register_write_enable_250_s <= '1';
 
s_axis_r_cq.tready <= '0'; --only release axi bus if write done goes back to 0 in idle state.
if(register_write_done_250_s = '1') then
if(m_axis_r_cc.tready = '0') then
completer_state <= WRITE_REGISTER_MODIFYWRITE;
m_axis_cc.tlast <= '0';
m_axis_cc.tvalid <= '0';
s_axis_r_cq.tready <= '0';
else
m_axis_cc.tlast <= '1';
m_axis_cc.tvalid <= '1';
completer_state <= IDLE;
completer_state <= WAIT_RW_DONE;
end if;
else
m_axis_cc.tlast <= '0';
m_axis_cc.tvalid <= '0';
completer_state <= WRITE_REGISTER_MODIFYWRITE;
s_axis_r_cq.tready <= '0';
end if;
 
poisoned_completion_v := '0';
517,6 → 524,15
locked_completion_v := '0';
m_axis_cc.tkeep <= x"07";
m_axis_cc.tdata(255 downto 96) <= (others => '0');
when WAIT_RW_DONE =>
completer_state_slv <= WAIT_RW_DONE_SLV;
if(register_read_done_250_s = '1' or register_write_done_250_s = '1') then
s_axis_r_cq.tready <= '0';
completer_state <= WAIT_RW_DONE;
else
s_axis_r_cq.tready <= '1';
completer_state <= IDLE;
end if;
when SEND_UNKNOWN_REQUEST =>
completer_state_slv <= SEND_UNKNOWN_REQUEST_SLV;
poisoned_completion_v := '0';
528,8 → 544,8
m_axis_cc.tlast <= '1';
m_axis_cc.tvalid <= '1';
if(m_axis_r_cc.tready = '0') then
s_axis_r_cq.tready <= '0';
completer_state <= SEND_UNKNOWN_REQUEST;
s_axis_r_cq.tready <= '0';
else
completer_state <= IDLE;
end if;
634,7 → 650,7
end process;
 
regSync250: process(clk)
variable register_write_done_v: std_logic;
variable register_write_done2_v, register_write_done1_v: std_logic;
variable register_read_done1_v, register_read_done2_v,register_read_done3_v,register_read_done4_v: std_logic;
variable register_read_data_v: std_logic_vector(127 downto 0);
variable dma_descriptors_w_v: dma_descriptors_type(0 to 7);
646,7 → 662,7
variable read_interrupt_40_pipe_v : std_logic;
begin
if(rising_edge(clk)) then
register_write_done_250_s <= register_write_done_v;
register_write_done_250_s <= register_write_done2_v;
register_read_done_250_s <= register_read_done2_v;
register_read_data_250_s <= register_read_data_v;
for i in 0 to (NUMBER_OF_DESCRIPTORS - 1) loop
654,7 → 670,8
end loop;
flush_fifo <= flush_fifo_v;
dma_soft_reset <= dma_soft_reset_v;
register_write_done_v := register_write_done_40_s;
register_write_done1_v := register_write_done2_v;
register_write_done2_v := register_write_done_40_s;
register_read_done1_v := register_read_done2_v; --pipeline register_read_done 3 clocks more than the others, so it everything else will be there earlier.
register_read_done2_v := register_read_done3_v;
register_read_done3_v := register_read_done4_v;
694,6 → 711,10
int_vector_40_s(i) <= (int_vec_add => (others => '0'), int_vec_data => (others => '0'),int_vec_ctrl => (others => '0') );
end loop;
int_table_en_s <= (others => '0');
pfull_threshold_assert_s <= "1010000"; --80 decimal
pfull_threshold_negate_s <= "1000110"; --70 decimal
 
------------------------------------------------
---- Application specific registers BEGIN 🂱 ----
------------------------------------------------
711,7 → 732,11
register_map_control_s <= register_map_control_s; --store read (PCIe Write) register map
register_read_done_40_s <= '0';
register_read_data_40_s <= register_read_data_40_s;
 
 
--!
--! generated self clearing "write only" register clear assignment
-- Bar 0
flush_fifo_40_s <= '0';
dma_soft_reset_40_s <= '0';
reset_global_soft_40_s <= '0';
783,47 → 808,47
when REG_STATUS_0 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(0 ).evencycle_pc&
dma_descriptors_40_r_s(0 ).evencycle_dma&
dma_status_40_s(0 ).descriptor_done&
(not dma_descriptors_40_r_s(0 ).enable)&
dma_descriptors_40_r_s(0 ).current_address;
when REG_STATUS_1 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(1 ).evencycle_pc&
dma_descriptors_40_r_s(1 ).evencycle_dma&
dma_status_40_s(1 ).descriptor_done&
(not dma_descriptors_40_r_s(1 ).enable)&
dma_descriptors_40_r_s(1 ).current_address;
when REG_STATUS_2 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(2 ).evencycle_pc&
dma_descriptors_40_r_s(2 ).evencycle_dma&
dma_status_40_s(2 ).descriptor_done&
(not dma_descriptors_40_r_s(2 ).enable)&
dma_descriptors_40_r_s(2 ).current_address;
when REG_STATUS_3 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(3 ).evencycle_pc&
dma_descriptors_40_r_s(3 ).evencycle_dma&
dma_status_40_s(3 ).descriptor_done&
(not dma_descriptors_40_r_s(3 ).enable)&
dma_descriptors_40_r_s(3 ).current_address;
when REG_STATUS_4 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(4 ).evencycle_pc&
dma_descriptors_40_r_s(4 ).evencycle_dma&
dma_status_40_s(4 ).descriptor_done&
(not dma_descriptors_40_r_s(4 ).enable)&
dma_descriptors_40_r_s(4 ).current_address;
when REG_STATUS_5 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(5 ).evencycle_pc&
dma_descriptors_40_r_s(5 ).evencycle_dma&
dma_status_40_s(5 ).descriptor_done&
(not dma_descriptors_40_r_s(5 ).enable)&
dma_descriptors_40_r_s(5 ).current_address;
when REG_STATUS_6 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(6 ).evencycle_pc&
dma_descriptors_40_r_s(6 ).evencycle_dma&
dma_status_40_s(6 ).descriptor_done&
(not dma_descriptors_40_r_s(6 ).enable)&
dma_descriptors_40_r_s(6 ).current_address;
when REG_STATUS_7 => register_read_data_40_s <= x"000000000000000"&"0"&
dma_descriptors_40_r_s(7 ).evencycle_pc&
dma_descriptors_40_r_s(7 ).evencycle_dma&
dma_status_40_s(7 ).descriptor_done&
(not dma_descriptors_40_r_s(7 ).enable)&
dma_descriptors_40_r_s(7 ).current_address;
when REG_BAR0 => register_read_data_40_s <= x"000000000000000000000000"&bar0_40_s;
when REG_BAR1 => register_read_data_40_s <= x"000000000000000000000000"&bar1_40_s;
when REG_BAR2 => register_read_data_40_s <= x"000000000000000000000000"&bar2_40_s;
-- REG_DESCRIPTOR_ENABLE is written at 250 MHz, but read at 40 Mhz.
when REG_BAR2 => register_read_data_40_s <= x"000000000000000000000000"&bar2_40_s;
-- REG_DESCRIPTOR_ENABLE is written at 250 MHz, but read at 40 Mhz.
when REG_DESCRIPTOR_ENABLE => for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
register_read_data_40_s(i) <= dma_descriptors_40_r_s(i).enable;
end loop;
832,39 → 857,42
when REG_DMA_RESET => register_read_data_40_s <= (others => '0');
when REG_SOFT_RESET => register_read_data_40_s <= (others => '0');
when REG_REGISTER_RESET => register_read_data_40_s <= (others => '0');
when others => register_read_data_40_s <= (others => '0');
when REG_FROMHOST_FULL_THRESH => register_read_data_40_s <= x"00000000_00000000" &
x"0000_00"&"0"&pfull_threshold_assert_s&
x"0000_00"&"0"&pfull_threshold_negate_s;
when others => register_read_data_40_s <= (others => '0');
 
 
end case;
--Read registers in BAR1
elsif(register_read_address_40_s(31 downto 20) = bar1_40_s(31 downto 20)) then
case (register_read_address_40_s(19 downto 4)&"0000") is
when REG_INT_VEC_00 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(0).int_vec_add;
when REG_INT_VEC_00 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(0).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(0).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(0).int_vec_ctrl;
when REG_INT_VEC_01 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(1).int_vec_add;
when REG_INT_VEC_01 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(1).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(1).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(1).int_vec_ctrl;
when REG_INT_VEC_02 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(2).int_vec_add;
when REG_INT_VEC_02 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(2).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(2).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(2).int_vec_ctrl;
when REG_INT_VEC_03 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(3).int_vec_add;
when REG_INT_VEC_03 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(3).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(3).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(3).int_vec_ctrl;
when REG_INT_VEC_04 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(4).int_vec_add;
when REG_INT_VEC_04 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(4).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(4).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(4).int_vec_ctrl;
when REG_INT_VEC_05 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(5).int_vec_add;
when REG_INT_VEC_05 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(5).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(5).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(5).int_vec_ctrl;
when REG_INT_VEC_06 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(6).int_vec_add;
when REG_INT_VEC_06 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(6).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(6).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(6).int_vec_ctrl;
when REG_INT_VEC_07 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(7).int_vec_add;
when REG_INT_VEC_07 => register_read_data_40_s(63 downto 0) <= int_vector_40_s(7).int_vec_add;
register_read_data_40_s(95 downto 64) <= int_vector_40_s(7).int_vec_data;
register_read_data_40_s(127 downto 96) <= int_vector_40_s(7).int_vec_ctrl;
when REG_INT_TAB_EN => register_read_data_40_s(NUMBER_OF_INTERRUPTS-1 downto 0) <= int_table_en_s;
when others => register_read_data_40_s <= (others => '0');
when others => register_read_data_40_s <= (others => '0');
end case;
--Read registers in BAR2
elsif(register_read_address_40_s(31 downto 20) = bar2_40_s(31 downto 20)) then
905,13 → 933,13
register_read_data_40_s <= (others => '0');
end if;
end if;
 
register_write_done_40_s <= '0';
if(register_write_enable_40_s = '1') then
register_write_done_40_s <= '1';
--Write registers in BAR0
if(register_write_address_40_s(31 downto 20) = bar0_40_s(31 downto 20)) then
 
case(register_write_address_40_s(19 downto 4)&"0000") is --only check 128 bit addressing
when REG_DESCRIPTOR_0 => dma_descriptors_40_w_s( 0).end_address <= register_write_data_40_s(127 downto 64);
dma_descriptors_40_w_s( 0).start_address <= register_write_data_40_s(63 downto 0);
974,6 → 1002,8
when REG_DMA_RESET => dma_soft_reset_40_s <= '1';
when REG_SOFT_RESET => reset_global_soft_40_s <= '1';
when REG_REGISTER_RESET => reset_register_map_s <= '1';
when REG_FROMHOST_FULL_THRESH => pfull_threshold_assert_s <= register_write_data_40_s(22 downto 16);
pfull_threshold_negate_s <= register_write_data_40_s( 6 downto 0);
when others => --do nothing
 
end case;
1028,17 → 1058,14
---- Application specific registers END 🂱 ----
------------------------------------------------
 
when others =>
when others =>
end case;
end if;
end if;
end if;
end process;
 
end architecture rtl ; -- of dma_control
 
 
 
end architecture rtl ; -- of dma_control
/firmware/sources/pcie/wupper.vhd
65,31 → 65,33
CARD_TYPE : integer := 709;
DEVID : std_logic_vector(15 downto 0) := x"7038");
port (
appreg_clk : out std_logic;
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out STD_LOGIC_VECTOR(7 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
fifo_rd_clk : out std_logic;
fifo_wr_clk : out std_logic;
flush_fifo : out std_logic;
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
lnk_up : out std_logic;
pcie_rxn : in std_logic_vector(7 downto 0);
pcie_rxp : in std_logic_vector(7 downto 0);
pcie_txn : out std_logic_vector(7 downto 0);
pcie_txp : out std_logic_vector(7 downto 0);
pll_locked : out std_logic;
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset_hard : out std_logic;
reset_soft : out std_logic;
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_reset_n : in std_logic;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic);
appreg_clk : out std_logic;
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out std_logic_vector(6 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
fifo_rd_clk : out std_logic;
fifo_wr_clk : out std_logic;
flush_fifo : out std_logic;
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
lnk_up : out std_logic;
pcie_rxn : in std_logic_vector(7 downto 0);
pcie_rxp : in std_logic_vector(7 downto 0);
pcie_txn : out std_logic_vector(7 downto 0);
pcie_txp : out std_logic_vector(7 downto 0);
pfull_threshold_assert : out std_logic_vector(6 downto 0);
pfull_threshold_negate : out std_logic_vector(6 downto 0);
pll_locked : out std_logic;
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset_hard : out std_logic;
reset_soft : out std_logic;
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_reset_n : in std_logic;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic);
end entity wupper;
 
 
120,7 → 122,7
signal cfg_mgmt_read_data : std_logic_vector(31 downto 0);
signal interrupt_table_en : std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
signal clkDiv6 : std_logic;
signal dma_interrupt_call : STD_LOGIC_VECTOR(3 downto 0);
signal dma_interrupt_call : std_logic_vector(3 downto 0);
signal m_axis_cq : axis_type;
signal m_axis_cc : axis_type;
signal m_axis_rc : axis_type;
188,35 → 190,37
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE";
CARD_TYPE : integer := 709);
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clkDiv6 : in std_logic;
dma_interrupt_call : out STD_LOGIC_VECTOR(3 downto 0);
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out STD_LOGIC_VECTOR(7 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
flush_fifo : out std_logic;
interrupt_table_en : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
interrupt_vector : out interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
m_axis_cc : out axis_type;
m_axis_r_cc : in axis_r_type;
m_axis_r_rq : in axis_r_type;
m_axis_rq : out axis_type;
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset : in std_logic;
reset_global_soft : out std_logic;
s_axis_cq : in axis_type;
s_axis_r_cq : out axis_r_type;
s_axis_r_rc : out axis_r_type;
s_axis_rc : in axis_type;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic;
user_lnk_up : in std_logic);
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clkDiv6 : in std_logic;
dma_interrupt_call : out std_logic_vector(3 downto 0);
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out std_logic_vector(6 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
flush_fifo : out std_logic;
interrupt_table_en : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
interrupt_vector : out interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
m_axis_cc : out axis_type;
m_axis_r_cc : in axis_r_type;
m_axis_r_rq : in axis_r_type;
m_axis_rq : out axis_type;
pfull_threshold_assert : out std_logic_vector(6 downto 0);
pfull_threshold_negate : out std_logic_vector(6 downto 0);
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset : in std_logic;
reset_global_soft : out std_logic;
s_axis_cq : in axis_type;
s_axis_r_cq : out axis_r_type;
s_axis_r_rc : out axis_r_type;
s_axis_rc : in axis_type;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic;
user_lnk_up : in std_logic);
end component wupper_core;
 
component intr_ctrl
333,35 → 337,37
BUILD_DATETIME => BUILD_DATETIME,
CARD_TYPE => CARD_TYPE)
port map(
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
clk => clk,
clkDiv6 => clkDiv6,
dma_interrupt_call => dma_interrupt_call,
downfifo_dout => downfifo_dout,
downfifo_empty_thresh => downfifo_empty_thresh,
downfifo_prog_empty => downfifo_prog_empty,
downfifo_re => downfifo_re,
flush_fifo => flush_fifo,
interrupt_table_en => interrupt_table_en,
interrupt_vector => interrupt_vector,
m_axis_cc => m_axis_cc,
m_axis_r_cc => m_axis_r_CNTRL,
m_axis_r_rq => m_axis_r_MM2S,
m_axis_rq => m_axis_rq,
register_map_control => register_map_control,
register_map_monitor => register_map_monitor,
reset => reset,
reset_global_soft => reset_soft,
s_axis_cq => m_axis_cq,
s_axis_r_cq => s_axis_r_STS,
s_axis_r_rc => s_axis_r_S2MM,
s_axis_rc => m_axis_rc,
upfifo_din => upfifo_din,
upfifo_prog_full => upfifo_prog_full,
upfifo_we => upfifo_we,
user_lnk_up => lnk_up_net);
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
clk => clk,
clkDiv6 => clkDiv6,
dma_interrupt_call => dma_interrupt_call,
downfifo_dout => downfifo_dout,
downfifo_empty_thresh => downfifo_empty_thresh,
downfifo_prog_empty => downfifo_prog_empty,
downfifo_re => downfifo_re,
flush_fifo => flush_fifo,
interrupt_table_en => interrupt_table_en,
interrupt_vector => interrupt_vector,
m_axis_cc => m_axis_cc,
m_axis_r_cc => m_axis_r_CNTRL,
m_axis_r_rq => m_axis_r_MM2S,
m_axis_rq => m_axis_rq,
pfull_threshold_assert => pfull_threshold_assert,
pfull_threshold_negate => pfull_threshold_negate,
register_map_control => register_map_control,
register_map_monitor => register_map_monitor,
reset => reset,
reset_global_soft => reset_soft,
s_axis_cq => m_axis_cq,
s_axis_r_cq => s_axis_r_STS,
s_axis_r_rc => s_axis_r_S2MM,
s_axis_rc => m_axis_rc,
upfifo_din => upfifo_din,
upfifo_prog_full => upfifo_prog_full,
upfifo_we => upfifo_we,
user_lnk_up => lnk_up_net);
 
u2: intr_ctrl
generic map(
/firmware/sources/pcie/pcie_init.vhd
114,34 → 114,11
--COMPONENT vio_0
-- PORT (
-- clk : IN STD_LOGIC;
-- probe_in0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- probe_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- probe_in2 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- probe_in3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- probe_in4 : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-- probe_in5 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-- probe_out1 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
-- );
--END COMPONENT;
 
begin
 
--vio_inst : vio_0
-- PORT MAP (
-- clk => clk,
-- probe_in0 => s_cfg_fc_pd,
-- probe_in1 => s_cfg_fc_ph,
-- probe_in2 => s_cfg_fc_npd,
-- probe_in3 => s_cfg_fc_nph,
-- probe_in4 => s_cfg_fc_cpld,
-- probe_in5 => s_cfg_fc_cplh,
-- probe_out0(0) => vio_rst_n,
-- probe_out1 => cfg_fc_sel
-- );
 
 
cfg_fc_sel <= "100";
 
s_cfg_fc_cpld <= cfg_fc_cpld ;
/firmware/sources/pcie/dma_read_write.vhd
65,7 → 65,7
dma_soft_reset : in std_logic;
dma_status : out dma_statuses_type(0 to (NUMBER_OF_DESCRIPTORS-1));
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out std_logic_vector(7 downto 0);
downfifo_empty_thresh : out std_logic_vector(6 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
m_axis_r_rq : in axis_r_type;
114,6 → 114,7
signal s_axis_rc_tlast_pipe, s_axis_rc_tvalid_pipe, upfifo_prog_full_pipe: std_logic;
signal receive_word_count: std_logic_vector(10 downto 0);
signal active_descriptor_s: integer range 0 to (NUMBER_OF_DESCRIPTORS-1);
signal current_dword_count_s: std_logic_vector(10 downto 0);
signal s_m_axis_rq : axis_type;
 
152,9 → 153,9
variable wc: std_logic_vector(10 downto 0);
variable th: std_logic_vector(7 downto 0);
begin
wc := current_descriptor.dword_count-1;
th := wc(10 downto 3)+1;
downfifo_empty_thresh <= th(7 downto 0);
wc := current_dword_count_s-1;
th := wc(10 downto 3);
downfifo_empty_thresh <= th(6 downto 0);
end process;
add_header: process(clk, reset, dma_soft_reset)
173,6 → 174,7
evencycle_pc => '0',
pc_pointer => (others => '0'));
active_descriptor_s <= 0;
current_dword_count_s <= "00001000000"; --256 bytes
for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
descriptor_done_s(i) <= '0'; --clear done flag, controller may load a new descriptor
end loop;
194,8 → 196,14
for i in 0 to (NUMBER_OF_DESCRIPTORS-1) loop
next_active_descriptor_v := active_descriptor_s;
if((i /= active_descriptor_s) and (dma_descriptors(i).enable='1')) then
next_active_descriptor_v := i; --find another active descriptor, else just continue with the current descriptor. 0 has priority above 1 and so on.
exit;
if(((dma_descriptors(i).read_not_write = '0') and (downfifo_prog_empty = '0'))) then
next_active_descriptor_v := i; --find another active descriptor, else just continue with the current descriptor. 0 has priority above 1 and so on.
exit;
end if;
if(((dma_descriptors(i).read_not_write = '1') and (upfifo_prog_full = '0'))) then
next_active_descriptor_v := i; --find another active descriptor, else just continue with the current descriptor. 0 has priority above 1 and so on.
exit;
end if;
end if;
end loop;
case(rw_state) is
202,6 → 210,9
when IDLE =>
rw_state_slv <= IDLE_SLV;
current_descriptor <= dma_descriptors(active_descriptor_s);
if(dma_descriptors(active_descriptor_s).read_not_write = '0' and dma_descriptors(active_descriptor_s).dword_count>0) then
current_dword_count_s <= dma_descriptors(active_descriptor_s).dword_count; --assign dword count to a signal to calculate the prog_empty threshold.
end if;
active_descriptor_s <= next_active_descriptor_v;
if((m_axis_r_rq.tready = '1') and (dma_descriptors(active_descriptor_s).enable = '1')) then
if(((dma_descriptors(active_descriptor_s).read_not_write = '0') and (downfifo_prog_empty = '0'))) then
/firmware/sources/pcie/wupper_core.vhd
64,35 → 64,37
CARD_TYPE : integer := 709;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE");
port (
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clkDiv6 : in std_logic;
dma_interrupt_call : out STD_LOGIC_VECTOR(3 downto 0);
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out STD_LOGIC_VECTOR(7 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
flush_fifo : out std_logic;
interrupt_table_en : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
interrupt_vector : out interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
m_axis_cc : out axis_type;
m_axis_r_cc : in axis_r_type;
m_axis_r_rq : in axis_r_type;
m_axis_rq : out axis_type;
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset : in std_logic;
reset_global_soft : out std_logic;
s_axis_cq : in axis_type;
s_axis_r_cq : out axis_r_type;
s_axis_r_rc : out axis_r_type;
s_axis_rc : in axis_type;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic;
user_lnk_up : in std_logic);
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clkDiv6 : in std_logic;
dma_interrupt_call : out std_logic_vector(3 downto 0);
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out std_logic_vector(6 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
flush_fifo : out std_logic;
interrupt_table_en : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
interrupt_vector : out interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
m_axis_cc : out axis_type;
m_axis_r_cc : in axis_r_type;
m_axis_r_rq : in axis_r_type;
m_axis_rq : out axis_type;
pfull_threshold_assert : out std_logic_vector(6 downto 0);
pfull_threshold_negate : out std_logic_vector(6 downto 0);
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset : in std_logic;
reset_global_soft : out std_logic;
s_axis_cq : in axis_type;
s_axis_r_cq : out axis_r_type;
s_axis_r_rc : out axis_r_type;
s_axis_rc : in axis_type;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic;
user_lnk_up : in std_logic);
end entity wupper_core;
 
 
111,7 → 113,7
dma_soft_reset : in std_logic;
dma_status : out dma_statuses_type(0 to (NUMBER_OF_DESCRIPTORS-1));
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out std_logic_vector(7 downto 0);
downfifo_empty_thresh : out std_logic_vector(6 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
m_axis_r_rq : in axis_r_type;
132,28 → 134,30
CARD_TYPE : integer := 709;
BUILD_DATETIME : std_logic_vector(39 downto 0) := x"0000FE71CE");
port (
bar0 : in STD_LOGIC_VECTOR(31 downto 0);
bar1 : in STD_LOGIC_VECTOR(31 downto 0);
bar2 : in STD_LOGIC_VECTOR(31 downto 0);
clk : in STD_LOGIC;
clkDiv6 : in STD_LOGIC;
dma_descriptors : out dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
dma_soft_reset : out STD_LOGIC;
dma_status : in dma_statuses_type;
flush_fifo : out STD_LOGIC;
interrupt_vector : out interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
m_axis_cc : out axis_type;
m_axis_r_cc : in axis_r_type;
reset : in STD_LOGIC;
reset_global_soft : out STD_LOGIC;
s_axis_cq : in axis_type;
s_axis_r_cq : out axis_r_type;
register_map_monitor : in register_map_monitor_type;
register_map_control : out register_map_control_type;
interrupt_table_en : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
dma_interrupt_call : out STD_LOGIC_VECTOR(3 downto 0);
fifo_empty : in std_logic;
fifo_full : in std_logic);
bar0 : in std_logic_vector(31 downto 0);
bar1 : in std_logic_vector(31 downto 0);
bar2 : in std_logic_vector(31 downto 0);
clk : in std_logic;
clkDiv6 : in std_logic;
dma_descriptors : out dma_descriptors_type(0 to (NUMBER_OF_DESCRIPTORS-1));
dma_soft_reset : out std_logic;
dma_status : in dma_statuses_type;
flush_fifo : out std_logic;
interrupt_vector : out interrupt_vectors_type(0 to (NUMBER_OF_INTERRUPTS-1));
m_axis_cc : out axis_type;
m_axis_r_cc : in axis_r_type;
reset : in std_logic;
reset_global_soft : out std_logic;
s_axis_cq : in axis_type;
s_axis_r_cq : out axis_r_type;
register_map_monitor : in register_map_monitor_type;
register_map_control : out register_map_control_type;
interrupt_table_en : out std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 0);
dma_interrupt_call : out std_logic_vector(3 downto 0);
fifo_empty : in std_logic;
fifo_full : in std_logic;
pfull_threshold_assert : out std_logic_vector(6 downto 0);
pfull_threshold_negate : out std_logic_vector(6 downto 0));
end component dma_control;
 
begin
184,30 → 188,32
NUMBER_OF_DESCRIPTORS => NUMBER_OF_DESCRIPTORS,
NUMBER_OF_INTERRUPTS => NUMBER_OF_INTERRUPTS,
SVN_VERSION => SVN_VERSION,
CARD_TYPE => CARD_TYPE,
BUILD_DATETIME => BUILD_DATETIME)
BUILD_DATETIME => BUILD_DATETIME,
CARD_TYPE => CARD_TYPE)
port map(
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
clk => clk,
clkDiv6 => clkDiv6,
dma_descriptors => u1_dma_descriptors,
dma_soft_reset => dma_soft_reset,
dma_status => dma_status,
flush_fifo => flush_fifo,
interrupt_vector => interrupt_vector,
m_axis_cc => m_axis_cc,
m_axis_r_cc => m_axis_r_cc,
reset => reset,
reset_global_soft => reset_global_soft,
s_axis_cq => s_axis_cq,
s_axis_r_cq => s_axis_r_cq,
register_map_monitor => register_map_monitor,
register_map_control => register_map_control,
interrupt_table_en => interrupt_table_en,
dma_interrupt_call => dma_interrupt_call,
fifo_empty => downfifo_prog_empty,
fifo_full => upfifo_prog_full);
bar0 => bar0,
bar1 => bar1,
bar2 => bar2,
clk => clk,
clkDiv6 => clkDiv6,
dma_descriptors => u1_dma_descriptors,
dma_soft_reset => dma_soft_reset,
dma_status => dma_status,
flush_fifo => flush_fifo,
interrupt_vector => interrupt_vector,
m_axis_cc => m_axis_cc,
m_axis_r_cc => m_axis_r_cc,
reset => reset,
reset_global_soft => reset_global_soft,
s_axis_cq => s_axis_cq,
s_axis_r_cq => s_axis_r_cq,
register_map_monitor => register_map_monitor,
register_map_control => register_map_control,
interrupt_table_en => interrupt_table_en,
dma_interrupt_call => dma_interrupt_call,
fifo_empty => downfifo_prog_empty,
fifo_full => upfifo_prog_full,
pfull_threshold_assert => pfull_threshold_assert,
pfull_threshold_negate => pfull_threshold_negate);
end architecture structure ; -- of wupper_core
 
/firmware/sources/pcie/pcie_ep_wrap.vhd
167,151 → 167,151
 
COMPONENT pcie_x8_gen3_3_0
PORT (
pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pipe_pclk_in : IN STD_LOGIC;
pipe_rxusrclk_in : IN STD_LOGIC;
pipe_rxoutclk_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pipe_dclk_in : IN STD_LOGIC;
pipe_userclk1_in : IN STD_LOGIC;
pipe_userclk2_in : IN STD_LOGIC;
pipe_oobclk_in : IN STD_LOGIC;
pipe_mmcm_lock_in : IN STD_LOGIC;
pipe_txoutclk_out : OUT STD_LOGIC;
pipe_rxoutclk_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pipe_pclk_sel_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pipe_gen3_out : OUT STD_LOGIC;
pipe_mmcm_rst_n : IN STD_LOGIC;
user_clk : OUT STD_LOGIC;
user_reset : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
user_app_rdy : OUT STD_LOGIC;
s_axis_rq_tlast : IN STD_LOGIC;
s_axis_rq_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s_axis_rq_tuser : IN STD_LOGIC_VECTOR(59 DOWNTO 0);
s_axis_rq_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_rq_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rq_tvalid : IN STD_LOGIC;
m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_rc_tuser : OUT STD_LOGIC_VECTOR(74 DOWNTO 0);
m_axis_rc_tlast : OUT STD_LOGIC;
m_axis_rc_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rc_tvalid : OUT STD_LOGIC;
m_axis_rc_tready : IN STD_LOGIC;
m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_cq_tuser : OUT STD_LOGIC_VECTOR(84 DOWNTO 0);
m_axis_cq_tlast : OUT STD_LOGIC;
m_axis_cq_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_cq_tvalid : OUT STD_LOGIC;
m_axis_cq_tready : IN STD_LOGIC;
s_axis_cc_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s_axis_cc_tuser : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
s_axis_cc_tlast : IN STD_LOGIC;
s_axis_cc_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_cc_tvalid : IN STD_LOGIC;
s_axis_cc_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pcie_rq_seq_num : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pcie_rq_seq_num_vld : OUT STD_LOGIC;
pcie_rq_tag : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
pcie_rq_tag_vld : OUT STD_LOGIC;
pcie_tfc_nph_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_tfc_npd_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_cq_np_req : IN STD_LOGIC;
pcie_cq_np_req_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_phy_link_down : OUT STD_LOGIC;
cfg_phy_link_status : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_negotiated_width : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_current_speed : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_max_payload : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_max_read_req : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_function_status : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_function_power_state : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_vf_status : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_vf_power_state : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
cfg_link_power_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
cfg_mgmt_write : IN STD_LOGIC;
cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_mgmt_read : IN STD_LOGIC;
cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_mgmt_read_write_done : OUT STD_LOGIC;
cfg_mgmt_type1_cfg_reg_access : IN STD_LOGIC;
cfg_err_cor_out : OUT STD_LOGIC;
cfg_err_nonfatal_out : OUT STD_LOGIC;
cfg_err_fatal_out : OUT STD_LOGIC;
cfg_ltr_enable : OUT STD_LOGIC;
cfg_ltssm_state : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_rcb_status : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_dpa_substate_change : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_obff_enable : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pl_status_change : OUT STD_LOGIC;
cfg_tph_requester_enable : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_tph_st_mode : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_vf_tph_requester_enable : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_vf_tph_st_mode : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_received_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_msg_received_type : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_msg_transmit : IN STD_LOGIC;
cfg_msg_transmit_type : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_transmit_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_msg_transmit_done : OUT STD_LOGIC;
cfg_fc_ph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_pd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_nph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_npd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_cplh : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_cpld : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_per_func_status_control : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_per_func_status_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_per_function_number : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_per_function_output_request : IN STD_LOGIC;
cfg_per_function_update_done : OUT STD_LOGIC;
cfg_subsys_vend_id : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_dsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_power_state_change_ack : IN STD_LOGIC;
cfg_power_state_change_interrupt : OUT STD_LOGIC;
cfg_err_cor_in : IN STD_LOGIC;
cfg_err_uncor_in : IN STD_LOGIC;
cfg_flr_in_process : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_flr_done : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_vf_flr_in_process : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_vf_flr_done : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_link_training_enable : IN STD_LOGIC;
cfg_ext_read_received : OUT STD_LOGIC;
cfg_ext_write_received : OUT STD_LOGIC;
cfg_ext_register_number : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
cfg_ext_function_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ext_write_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ext_write_byte_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_ext_read_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ext_read_data_valid : IN STD_LOGIC;
cfg_interrupt_int : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_pending : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_interrupt_sent : OUT STD_LOGIC;
cfg_interrupt_msix_enable : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_interrupt_msix_mask : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_interrupt_msix_vf_enable : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_interrupt_msix_vf_mask : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_interrupt_msix_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_interrupt_msix_address : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_interrupt_msix_int : IN STD_LOGIC;
cfg_interrupt_msix_sent : OUT STD_LOGIC;
cfg_interrupt_msix_fail : OUT STD_LOGIC;
cfg_hot_reset_out : OUT STD_LOGIC;
cfg_config_space_enable : IN STD_LOGIC;
cfg_req_pm_transition_l23_ready : IN STD_LOGIC;
cfg_hot_reset_in : IN STD_LOGIC;
cfg_ds_port_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ds_bus_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ds_device_number : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_ds_function_number : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_reset : IN STD_LOGIC
pci_exp_txn : OUT std_logic_vector(7 DOWNTO 0);
pci_exp_txp : OUT std_logic_vector(7 DOWNTO 0);
pci_exp_rxn : IN std_logic_vector(7 DOWNTO 0);
pci_exp_rxp : IN std_logic_vector(7 DOWNTO 0);
pipe_pclk_in : IN std_logic;
pipe_rxusrclk_in : IN std_logic;
pipe_rxoutclk_in : IN std_logic_vector(7 DOWNTO 0);
pipe_dclk_in : IN std_logic;
pipe_userclk1_in : IN std_logic;
pipe_userclk2_in : IN std_logic;
pipe_oobclk_in : IN std_logic;
pipe_mmcm_lock_in : IN std_logic;
pipe_txoutclk_out : OUT std_logic;
pipe_rxoutclk_out : OUT std_logic_vector(7 DOWNTO 0);
pipe_pclk_sel_out : OUT std_logic_vector(7 DOWNTO 0);
pipe_gen3_out : OUT std_logic;
pipe_mmcm_rst_n : IN std_logic;
user_clk : OUT std_logic;
user_reset : OUT std_logic;
user_lnk_up : OUT std_logic;
user_app_rdy : OUT std_logic;
s_axis_rq_tlast : IN std_logic;
s_axis_rq_tdata : IN std_logic_vector(255 DOWNTO 0);
s_axis_rq_tuser : IN std_logic_vector(59 DOWNTO 0);
s_axis_rq_tkeep : IN std_logic_vector(7 DOWNTO 0);
s_axis_rq_tready : OUT std_logic_vector(3 DOWNTO 0);
s_axis_rq_tvalid : IN std_logic;
m_axis_rc_tdata : OUT std_logic_vector(255 DOWNTO 0);
m_axis_rc_tuser : OUT std_logic_vector(74 DOWNTO 0);
m_axis_rc_tlast : OUT std_logic;
m_axis_rc_tkeep : OUT std_logic_vector(7 DOWNTO 0);
m_axis_rc_tvalid : OUT std_logic;
m_axis_rc_tready : IN std_logic;
m_axis_cq_tdata : OUT std_logic_vector(255 DOWNTO 0);
m_axis_cq_tuser : OUT std_logic_vector(84 DOWNTO 0);
m_axis_cq_tlast : OUT std_logic;
m_axis_cq_tkeep : OUT std_logic_vector(7 DOWNTO 0);
m_axis_cq_tvalid : OUT std_logic;
m_axis_cq_tready : IN std_logic;
s_axis_cc_tdata : IN std_logic_vector(255 DOWNTO 0);
s_axis_cc_tuser : IN std_logic_vector(32 DOWNTO 0);
s_axis_cc_tlast : IN std_logic;
s_axis_cc_tkeep : IN std_logic_vector(7 DOWNTO 0);
s_axis_cc_tvalid : IN std_logic;
s_axis_cc_tready : OUT std_logic_vector(3 DOWNTO 0);
pcie_rq_seq_num : OUT std_logic_vector(3 DOWNTO 0);
pcie_rq_seq_num_vld : OUT std_logic;
pcie_rq_tag : OUT std_logic_vector(5 DOWNTO 0);
pcie_rq_tag_vld : OUT std_logic;
pcie_tfc_nph_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_tfc_npd_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_cq_np_req : IN std_logic;
pcie_cq_np_req_count : OUT std_logic_vector(5 DOWNTO 0);
cfg_phy_link_down : OUT std_logic;
cfg_phy_link_status : OUT std_logic_vector(1 DOWNTO 0);
cfg_negotiated_width : OUT std_logic_vector(3 DOWNTO 0);
cfg_current_speed : OUT std_logic_vector(2 DOWNTO 0);
cfg_max_payload : OUT std_logic_vector(2 DOWNTO 0);
cfg_max_read_req : OUT std_logic_vector(2 DOWNTO 0);
cfg_function_status : OUT std_logic_vector(7 DOWNTO 0);
cfg_function_power_state : OUT std_logic_vector(5 DOWNTO 0);
cfg_vf_status : OUT std_logic_vector(11 DOWNTO 0);
cfg_vf_power_state : OUT std_logic_vector(17 DOWNTO 0);
cfg_link_power_state : OUT std_logic_vector(1 DOWNTO 0);
cfg_mgmt_addr : IN std_logic_vector(18 DOWNTO 0);
cfg_mgmt_write : IN std_logic;
cfg_mgmt_write_data : IN std_logic_vector(31 DOWNTO 0);
cfg_mgmt_byte_enable : IN std_logic_vector(3 DOWNTO 0);
cfg_mgmt_read : IN std_logic;
cfg_mgmt_read_data : OUT std_logic_vector(31 DOWNTO 0);
cfg_mgmt_read_write_done : OUT std_logic;
cfg_mgmt_type1_cfg_reg_access : IN std_logic;
cfg_err_cor_out : OUT std_logic;
cfg_err_nonfatal_out : OUT std_logic;
cfg_err_fatal_out : OUT std_logic;
cfg_ltr_enable : OUT std_logic;
cfg_ltssm_state : OUT std_logic_vector(5 DOWNTO 0);
cfg_rcb_status : OUT std_logic_vector(1 DOWNTO 0);
cfg_dpa_substate_change : OUT std_logic_vector(1 DOWNTO 0);
cfg_obff_enable : OUT std_logic_vector(1 DOWNTO 0);
cfg_pl_status_change : OUT std_logic;
cfg_tph_requester_enable : OUT std_logic_vector(1 DOWNTO 0);
cfg_tph_st_mode : OUT std_logic_vector(5 DOWNTO 0);
cfg_vf_tph_requester_enable : OUT std_logic_vector(5 DOWNTO 0);
cfg_vf_tph_st_mode : OUT std_logic_vector(17 DOWNTO 0);
cfg_msg_received : OUT std_logic;
cfg_msg_received_data : OUT std_logic_vector(7 DOWNTO 0);
cfg_msg_received_type : OUT std_logic_vector(4 DOWNTO 0);
cfg_msg_transmit : IN std_logic;
cfg_msg_transmit_type : IN std_logic_vector(2 DOWNTO 0);
cfg_msg_transmit_data : IN std_logic_vector(31 DOWNTO 0);
cfg_msg_transmit_done : OUT std_logic;
cfg_fc_ph : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_pd : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_nph : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_npd : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_cplh : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_cpld : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_sel : IN std_logic_vector(2 DOWNTO 0);
cfg_per_func_status_control : IN std_logic_vector(2 DOWNTO 0);
cfg_per_func_status_data : OUT std_logic_vector(15 DOWNTO 0);
cfg_per_function_number : IN std_logic_vector(2 DOWNTO 0);
cfg_per_function_output_request : IN std_logic;
cfg_per_function_update_done : OUT std_logic;
cfg_subsys_vend_id : IN std_logic_vector(15 DOWNTO 0);
cfg_dsn : IN std_logic_vector(63 DOWNTO 0);
cfg_power_state_change_ack : IN std_logic;
cfg_power_state_change_interrupt : OUT std_logic;
cfg_err_cor_in : IN std_logic;
cfg_err_uncor_in : IN std_logic;
cfg_flr_in_process : OUT std_logic_vector(1 DOWNTO 0);
cfg_flr_done : IN std_logic_vector(1 DOWNTO 0);
cfg_vf_flr_in_process : OUT std_logic_vector(5 DOWNTO 0);
cfg_vf_flr_done : IN std_logic_vector(5 DOWNTO 0);
cfg_link_training_enable : IN std_logic;
cfg_ext_read_received : OUT std_logic;
cfg_ext_write_received : OUT std_logic;
cfg_ext_register_number : OUT std_logic_vector(9 DOWNTO 0);
cfg_ext_function_number : OUT std_logic_vector(7 DOWNTO 0);
cfg_ext_write_data : OUT std_logic_vector(31 DOWNTO 0);
cfg_ext_write_byte_enable : OUT std_logic_vector(3 DOWNTO 0);
cfg_ext_read_data : IN std_logic_vector(31 DOWNTO 0);
cfg_ext_read_data_valid : IN std_logic;
cfg_interrupt_int : IN std_logic_vector(3 DOWNTO 0);
cfg_interrupt_pending : IN std_logic_vector(1 DOWNTO 0);
cfg_interrupt_sent : OUT std_logic;
cfg_interrupt_msix_enable : OUT std_logic_vector(1 DOWNTO 0);
cfg_interrupt_msix_mask : OUT std_logic_vector(1 DOWNTO 0);
cfg_interrupt_msix_vf_enable : OUT std_logic_vector(5 DOWNTO 0);
cfg_interrupt_msix_vf_mask : OUT std_logic_vector(5 DOWNTO 0);
cfg_interrupt_msix_data : IN std_logic_vector(31 DOWNTO 0);
cfg_interrupt_msix_address : IN std_logic_vector(63 DOWNTO 0);
cfg_interrupt_msix_int : IN std_logic;
cfg_interrupt_msix_sent : OUT std_logic;
cfg_interrupt_msix_fail : OUT std_logic;
cfg_hot_reset_out : OUT std_logic;
cfg_config_space_enable : IN std_logic;
cfg_req_pm_transition_l23_ready : IN std_logic;
cfg_hot_reset_in : IN std_logic;
cfg_ds_port_number : IN std_logic_vector(7 DOWNTO 0);
cfg_ds_bus_number : IN std_logic_vector(7 DOWNTO 0);
cfg_ds_device_number : IN std_logic_vector(4 DOWNTO 0);
cfg_ds_function_number : IN std_logic_vector(2 DOWNTO 0);
sys_clk : IN std_logic;
sys_reset : IN std_logic
);
END COMPONENT;
 
319,285 → 319,285
-- UltraScale Architecture Gen3 Integrated Block for PCI Express v4.1
COMPONENT pcie3_ultrascale_7038
PORT (
pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
user_clk : OUT STD_LOGIC;
user_reset : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
s_axis_rq_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s_axis_rq_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_rq_tlast : IN STD_LOGIC;
s_axis_rq_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rq_tuser : IN STD_LOGIC_VECTOR(59 DOWNTO 0);
s_axis_rq_tvalid : IN STD_LOGIC;
m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_rc_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rc_tlast : OUT STD_LOGIC;
m_axis_rc_tready : IN STD_LOGIC;
m_axis_rc_tuser : OUT STD_LOGIC_VECTOR(74 DOWNTO 0);
m_axis_rc_tvalid : OUT STD_LOGIC;
m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_cq_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_cq_tlast : OUT STD_LOGIC;
m_axis_cq_tready : IN STD_LOGIC;
m_axis_cq_tuser : OUT STD_LOGIC_VECTOR(84 DOWNTO 0);
m_axis_cq_tvalid : OUT STD_LOGIC;
s_axis_cc_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s_axis_cc_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_cc_tlast : IN STD_LOGIC;
s_axis_cc_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_cc_tuser : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
s_axis_cc_tvalid : IN STD_LOGIC;
pcie_rq_seq_num : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pcie_rq_seq_num_vld : OUT STD_LOGIC;
pcie_rq_tag : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
pcie_rq_tag_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_rq_tag_vld : OUT STD_LOGIC;
pcie_tfc_nph_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_tfc_npd_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_cq_np_req : IN STD_LOGIC;
pcie_cq_np_req_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_phy_link_down : OUT STD_LOGIC;
cfg_phy_link_status : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_negotiated_width : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_current_speed : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_max_payload : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_max_read_req : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_function_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_function_power_state : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_vf_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_vf_power_state : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
cfg_link_power_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
cfg_mgmt_write : IN STD_LOGIC;
cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_mgmt_read : IN STD_LOGIC;
cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_mgmt_read_write_done : OUT STD_LOGIC;
cfg_mgmt_type1_cfg_reg_access : IN STD_LOGIC;
cfg_err_cor_out : OUT STD_LOGIC;
cfg_err_nonfatal_out : OUT STD_LOGIC;
cfg_err_fatal_out : OUT STD_LOGIC;
cfg_local_error : OUT STD_LOGIC;
cfg_ltr_enable : OUT STD_LOGIC;
cfg_ltssm_state : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_rcb_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_dpa_substate_change : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_obff_enable : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pl_status_change : OUT STD_LOGIC;
cfg_tph_requester_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_tph_st_mode : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_vf_tph_requester_enable : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_vf_tph_st_mode : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_received_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_msg_received_type : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_msg_transmit : IN STD_LOGIC;
cfg_msg_transmit_type : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_transmit_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_msg_transmit_done : OUT STD_LOGIC;
cfg_fc_ph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_pd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_nph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_npd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_cplh : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_cpld : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_per_func_status_control : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_per_func_status_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_per_function_number : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_per_function_output_request : IN STD_LOGIC;
cfg_per_function_update_done : OUT STD_LOGIC;
cfg_dsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_power_state_change_ack : IN STD_LOGIC;
cfg_power_state_change_interrupt : OUT STD_LOGIC;
cfg_err_cor_in : IN STD_LOGIC;
cfg_err_uncor_in : IN STD_LOGIC;
cfg_flr_in_process : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_flr_done : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_vf_flr_in_process : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_vf_flr_done : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_link_training_enable : IN STD_LOGIC;
cfg_ext_read_received : OUT STD_LOGIC;
cfg_ext_write_received : OUT STD_LOGIC;
cfg_ext_register_number : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
cfg_ext_function_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ext_write_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ext_write_byte_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_ext_read_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ext_read_data_valid : IN STD_LOGIC;
cfg_interrupt_int : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_pending : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_sent : OUT STD_LOGIC;
cfg_interrupt_msix_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_msix_mask : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_msix_vf_enable : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_msix_vf_mask : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_msix_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_interrupt_msix_address : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_interrupt_msix_int : IN STD_LOGIC;
cfg_interrupt_msix_sent : OUT STD_LOGIC;
cfg_interrupt_msix_fail : OUT STD_LOGIC;
cfg_hot_reset_out : OUT STD_LOGIC;
cfg_config_space_enable : IN STD_LOGIC;
cfg_req_pm_transition_l23_ready : IN STD_LOGIC;
cfg_hot_reset_in : IN STD_LOGIC;
cfg_ds_port_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ds_bus_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ds_device_number : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_ds_function_number : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_subsys_vend_id : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_clk_gt : IN STD_LOGIC;
sys_reset : IN STD_LOGIC;
int_qpll1lock_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
int_qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
int_qpll1outclk_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
pci_exp_txn : OUT std_logic_vector(7 DOWNTO 0);
pci_exp_txp : OUT std_logic_vector(7 DOWNTO 0);
pci_exp_rxn : IN std_logic_vector(7 DOWNTO 0);
pci_exp_rxp : IN std_logic_vector(7 DOWNTO 0);
user_clk : OUT std_logic;
user_reset : OUT std_logic;
user_lnk_up : OUT std_logic;
s_axis_rq_tdata : IN std_logic_vector(255 DOWNTO 0);
s_axis_rq_tkeep : IN std_logic_vector(7 DOWNTO 0);
s_axis_rq_tlast : IN std_logic;
s_axis_rq_tready : OUT std_logic_vector(3 DOWNTO 0);
s_axis_rq_tuser : IN std_logic_vector(59 DOWNTO 0);
s_axis_rq_tvalid : IN std_logic;
m_axis_rc_tdata : OUT std_logic_vector(255 DOWNTO 0);
m_axis_rc_tkeep : OUT std_logic_vector(7 DOWNTO 0);
m_axis_rc_tlast : OUT std_logic;
m_axis_rc_tready : IN std_logic;
m_axis_rc_tuser : OUT std_logic_vector(74 DOWNTO 0);
m_axis_rc_tvalid : OUT std_logic;
m_axis_cq_tdata : OUT std_logic_vector(255 DOWNTO 0);
m_axis_cq_tkeep : OUT std_logic_vector(7 DOWNTO 0);
m_axis_cq_tlast : OUT std_logic;
m_axis_cq_tready : IN std_logic;
m_axis_cq_tuser : OUT std_logic_vector(84 DOWNTO 0);
m_axis_cq_tvalid : OUT std_logic;
s_axis_cc_tdata : IN std_logic_vector(255 DOWNTO 0);
s_axis_cc_tkeep : IN std_logic_vector(7 DOWNTO 0);
s_axis_cc_tlast : IN std_logic;
s_axis_cc_tready : OUT std_logic_vector(3 DOWNTO 0);
s_axis_cc_tuser : IN std_logic_vector(32 DOWNTO 0);
s_axis_cc_tvalid : IN std_logic;
pcie_rq_seq_num : OUT std_logic_vector(3 DOWNTO 0);
pcie_rq_seq_num_vld : OUT std_logic;
pcie_rq_tag : OUT std_logic_vector(5 DOWNTO 0);
pcie_rq_tag_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_rq_tag_vld : OUT std_logic;
pcie_tfc_nph_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_tfc_npd_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_cq_np_req : IN std_logic;
pcie_cq_np_req_count : OUT std_logic_vector(5 DOWNTO 0);
cfg_phy_link_down : OUT std_logic;
cfg_phy_link_status : OUT std_logic_vector(1 DOWNTO 0);
cfg_negotiated_width : OUT std_logic_vector(3 DOWNTO 0);
cfg_current_speed : OUT std_logic_vector(2 DOWNTO 0);
cfg_max_payload : OUT std_logic_vector(2 DOWNTO 0);
cfg_max_read_req : OUT std_logic_vector(2 DOWNTO 0);
cfg_function_status : OUT std_logic_vector(15 DOWNTO 0);
cfg_function_power_state : OUT std_logic_vector(11 DOWNTO 0);
cfg_vf_status : OUT std_logic_vector(15 DOWNTO 0);
cfg_vf_power_state : OUT std_logic_vector(23 DOWNTO 0);
cfg_link_power_state : OUT std_logic_vector(1 DOWNTO 0);
cfg_mgmt_addr : IN std_logic_vector(18 DOWNTO 0);
cfg_mgmt_write : IN std_logic;
cfg_mgmt_write_data : IN std_logic_vector(31 DOWNTO 0);
cfg_mgmt_byte_enable : IN std_logic_vector(3 DOWNTO 0);
cfg_mgmt_read : IN std_logic;
cfg_mgmt_read_data : OUT std_logic_vector(31 DOWNTO 0);
cfg_mgmt_read_write_done : OUT std_logic;
cfg_mgmt_type1_cfg_reg_access : IN std_logic;
cfg_err_cor_out : OUT std_logic;
cfg_err_nonfatal_out : OUT std_logic;
cfg_err_fatal_out : OUT std_logic;
cfg_local_error : OUT std_logic;
cfg_ltr_enable : OUT std_logic;
cfg_ltssm_state : OUT std_logic_vector(5 DOWNTO 0);
cfg_rcb_status : OUT std_logic_vector(3 DOWNTO 0);
cfg_dpa_substate_change : OUT std_logic_vector(3 DOWNTO 0);
cfg_obff_enable : OUT std_logic_vector(1 DOWNTO 0);
cfg_pl_status_change : OUT std_logic;
cfg_tph_requester_enable : OUT std_logic_vector(3 DOWNTO 0);
cfg_tph_st_mode : OUT std_logic_vector(11 DOWNTO 0);
cfg_vf_tph_requester_enable : OUT std_logic_vector(7 DOWNTO 0);
cfg_vf_tph_st_mode : OUT std_logic_vector(23 DOWNTO 0);
cfg_msg_received : OUT std_logic;
cfg_msg_received_data : OUT std_logic_vector(7 DOWNTO 0);
cfg_msg_received_type : OUT std_logic_vector(4 DOWNTO 0);
cfg_msg_transmit : IN std_logic;
cfg_msg_transmit_type : IN std_logic_vector(2 DOWNTO 0);
cfg_msg_transmit_data : IN std_logic_vector(31 DOWNTO 0);
cfg_msg_transmit_done : OUT std_logic;
cfg_fc_ph : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_pd : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_nph : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_npd : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_cplh : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_cpld : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_sel : IN std_logic_vector(2 DOWNTO 0);
cfg_per_func_status_control : IN std_logic_vector(2 DOWNTO 0);
cfg_per_func_status_data : OUT std_logic_vector(15 DOWNTO 0);
cfg_per_function_number : IN std_logic_vector(3 DOWNTO 0);
cfg_per_function_output_request : IN std_logic;
cfg_per_function_update_done : OUT std_logic;
cfg_dsn : IN std_logic_vector(63 DOWNTO 0);
cfg_power_state_change_ack : IN std_logic;
cfg_power_state_change_interrupt : OUT std_logic;
cfg_err_cor_in : IN std_logic;
cfg_err_uncor_in : IN std_logic;
cfg_flr_in_process : OUT std_logic_vector(3 DOWNTO 0);
cfg_flr_done : IN std_logic_vector(3 DOWNTO 0);
cfg_vf_flr_in_process : OUT std_logic_vector(7 DOWNTO 0);
cfg_vf_flr_done : IN std_logic_vector(7 DOWNTO 0);
cfg_link_training_enable : IN std_logic;
cfg_ext_read_received : OUT std_logic;
cfg_ext_write_received : OUT std_logic;
cfg_ext_register_number : OUT std_logic_vector(9 DOWNTO 0);
cfg_ext_function_number : OUT std_logic_vector(7 DOWNTO 0);
cfg_ext_write_data : OUT std_logic_vector(31 DOWNTO 0);
cfg_ext_write_byte_enable : OUT std_logic_vector(3 DOWNTO 0);
cfg_ext_read_data : IN std_logic_vector(31 DOWNTO 0);
cfg_ext_read_data_valid : IN std_logic;
cfg_interrupt_int : IN std_logic_vector(3 DOWNTO 0);
cfg_interrupt_pending : IN std_logic_vector(3 DOWNTO 0);
cfg_interrupt_sent : OUT std_logic;
cfg_interrupt_msix_enable : OUT std_logic_vector(3 DOWNTO 0);
cfg_interrupt_msix_mask : OUT std_logic_vector(3 DOWNTO 0);
cfg_interrupt_msix_vf_enable : OUT std_logic_vector(7 DOWNTO 0);
cfg_interrupt_msix_vf_mask : OUT std_logic_vector(7 DOWNTO 0);
cfg_interrupt_msix_data : IN std_logic_vector(31 DOWNTO 0);
cfg_interrupt_msix_address : IN std_logic_vector(63 DOWNTO 0);
cfg_interrupt_msix_int : IN std_logic;
cfg_interrupt_msix_sent : OUT std_logic;
cfg_interrupt_msix_fail : OUT std_logic;
cfg_hot_reset_out : OUT std_logic;
cfg_config_space_enable : IN std_logic;
cfg_req_pm_transition_l23_ready : IN std_logic;
cfg_hot_reset_in : IN std_logic;
cfg_ds_port_number : IN std_logic_vector(7 DOWNTO 0);
cfg_ds_bus_number : IN std_logic_vector(7 DOWNTO 0);
cfg_ds_device_number : IN std_logic_vector(4 DOWNTO 0);
cfg_ds_function_number : IN std_logic_vector(2 DOWNTO 0);
cfg_subsys_vend_id : IN std_logic_vector(15 DOWNTO 0);
sys_clk : IN std_logic;
sys_clk_gt : IN std_logic;
sys_reset : IN std_logic;
int_qpll1lock_out : OUT std_logic_vector(1 DOWNTO 0);
int_qpll1outrefclk_out : OUT std_logic_vector(1 DOWNTO 0);
int_qpll1outclk_out : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
COMPONENT pcie3_ultrascale_7039
PORT (
pci_exp_txn : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_txp : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_rxn : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pci_exp_rxp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
user_clk : OUT STD_LOGIC;
user_reset : OUT STD_LOGIC;
user_lnk_up : OUT STD_LOGIC;
s_axis_rq_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s_axis_rq_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_rq_tlast : IN STD_LOGIC;
s_axis_rq_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_rq_tuser : IN STD_LOGIC_VECTOR(59 DOWNTO 0);
s_axis_rq_tvalid : IN STD_LOGIC;
m_axis_rc_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_rc_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_rc_tlast : OUT STD_LOGIC;
m_axis_rc_tready : IN STD_LOGIC;
m_axis_rc_tuser : OUT STD_LOGIC_VECTOR(74 DOWNTO 0);
m_axis_rc_tvalid : OUT STD_LOGIC;
m_axis_cq_tdata : OUT STD_LOGIC_VECTOR(255 DOWNTO 0);
m_axis_cq_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_cq_tlast : OUT STD_LOGIC;
m_axis_cq_tready : IN STD_LOGIC;
m_axis_cq_tuser : OUT STD_LOGIC_VECTOR(84 DOWNTO 0);
m_axis_cq_tvalid : OUT STD_LOGIC;
s_axis_cc_tdata : IN STD_LOGIC_VECTOR(255 DOWNTO 0);
s_axis_cc_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_cc_tlast : IN STD_LOGIC;
s_axis_cc_tready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_cc_tuser : IN STD_LOGIC_VECTOR(32 DOWNTO 0);
s_axis_cc_tvalid : IN STD_LOGIC;
pcie_rq_seq_num : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
pcie_rq_seq_num_vld : OUT STD_LOGIC;
pcie_rq_tag : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
pcie_rq_tag_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_rq_tag_vld : OUT STD_LOGIC;
pcie_tfc_nph_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_tfc_npd_av : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
pcie_cq_np_req : IN STD_LOGIC;
pcie_cq_np_req_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_phy_link_down : OUT STD_LOGIC;
cfg_phy_link_status : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_negotiated_width : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_current_speed : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_max_payload : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_max_read_req : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_function_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_function_power_state : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_vf_status : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_vf_power_state : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
cfg_link_power_state : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_mgmt_addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
cfg_mgmt_write : IN STD_LOGIC;
cfg_mgmt_write_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_mgmt_byte_enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_mgmt_read : IN STD_LOGIC;
cfg_mgmt_read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_mgmt_read_write_done : OUT STD_LOGIC;
cfg_mgmt_type1_cfg_reg_access : IN STD_LOGIC;
cfg_err_cor_out : OUT STD_LOGIC;
cfg_err_nonfatal_out : OUT STD_LOGIC;
cfg_err_fatal_out : OUT STD_LOGIC;
cfg_local_error : OUT STD_LOGIC;
cfg_ltr_enable : OUT STD_LOGIC;
cfg_ltssm_state : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
cfg_rcb_status : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_dpa_substate_change : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_obff_enable : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
cfg_pl_status_change : OUT STD_LOGIC;
cfg_tph_requester_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_tph_st_mode : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_vf_tph_requester_enable : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_vf_tph_st_mode : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
cfg_msg_received : OUT STD_LOGIC;
cfg_msg_received_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_msg_received_type : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_msg_transmit : IN STD_LOGIC;
cfg_msg_transmit_type : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_msg_transmit_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_msg_transmit_done : OUT STD_LOGIC;
cfg_fc_ph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_pd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_nph : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_npd : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_cplh : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_fc_cpld : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
cfg_fc_sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_per_func_status_control : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_per_func_status_data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
cfg_per_function_number : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_per_function_output_request : IN STD_LOGIC;
cfg_per_function_update_done : OUT STD_LOGIC;
cfg_dsn : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_power_state_change_ack : IN STD_LOGIC;
cfg_power_state_change_interrupt : OUT STD_LOGIC;
cfg_err_cor_in : IN STD_LOGIC;
cfg_err_uncor_in : IN STD_LOGIC;
cfg_flr_in_process : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_flr_done : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_vf_flr_in_process : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_vf_flr_done : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_link_training_enable : IN STD_LOGIC;
cfg_ext_read_received : OUT STD_LOGIC;
cfg_ext_write_received : OUT STD_LOGIC;
cfg_ext_register_number : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
cfg_ext_function_number : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ext_write_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ext_write_byte_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_ext_read_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_ext_read_data_valid : IN STD_LOGIC;
cfg_interrupt_int : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_pending : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_sent : OUT STD_LOGIC;
cfg_interrupt_msix_enable : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_msix_mask : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cfg_interrupt_msix_vf_enable : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_msix_vf_mask : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_interrupt_msix_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cfg_interrupt_msix_address : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
cfg_interrupt_msix_int : IN STD_LOGIC;
cfg_interrupt_msix_sent : OUT STD_LOGIC;
cfg_interrupt_msix_fail : OUT STD_LOGIC;
cfg_hot_reset_out : OUT STD_LOGIC;
cfg_config_space_enable : IN STD_LOGIC;
cfg_req_pm_transition_l23_ready : IN STD_LOGIC;
cfg_hot_reset_in : IN STD_LOGIC;
cfg_ds_port_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ds_bus_number : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
cfg_ds_device_number : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
cfg_ds_function_number : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
cfg_subsys_vend_id : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
sys_clk : IN STD_LOGIC;
sys_clk_gt : IN STD_LOGIC;
sys_reset : IN STD_LOGIC;
int_qpll1lock_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
int_qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
int_qpll1outclk_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
pci_exp_txn : OUT std_logic_vector(7 DOWNTO 0);
pci_exp_txp : OUT std_logic_vector(7 DOWNTO 0);
pci_exp_rxn : IN std_logic_vector(7 DOWNTO 0);
pci_exp_rxp : IN std_logic_vector(7 DOWNTO 0);
user_clk : OUT std_logic;
user_reset : OUT std_logic;
user_lnk_up : OUT std_logic;
s_axis_rq_tdata : IN std_logic_vector(255 DOWNTO 0);
s_axis_rq_tkeep : IN std_logic_vector(7 DOWNTO 0);
s_axis_rq_tlast : IN std_logic;
s_axis_rq_tready : OUT std_logic_vector(3 DOWNTO 0);
s_axis_rq_tuser : IN std_logic_vector(59 DOWNTO 0);
s_axis_rq_tvalid : IN std_logic;
m_axis_rc_tdata : OUT std_logic_vector(255 DOWNTO 0);
m_axis_rc_tkeep : OUT std_logic_vector(7 DOWNTO 0);
m_axis_rc_tlast : OUT std_logic;
m_axis_rc_tready : IN std_logic;
m_axis_rc_tuser : OUT std_logic_vector(74 DOWNTO 0);
m_axis_rc_tvalid : OUT std_logic;
m_axis_cq_tdata : OUT std_logic_vector(255 DOWNTO 0);
m_axis_cq_tkeep : OUT std_logic_vector(7 DOWNTO 0);
m_axis_cq_tlast : OUT std_logic;
m_axis_cq_tready : IN std_logic;
m_axis_cq_tuser : OUT std_logic_vector(84 DOWNTO 0);
m_axis_cq_tvalid : OUT std_logic;
s_axis_cc_tdata : IN std_logic_vector(255 DOWNTO 0);
s_axis_cc_tkeep : IN std_logic_vector(7 DOWNTO 0);
s_axis_cc_tlast : IN std_logic;
s_axis_cc_tready : OUT std_logic_vector(3 DOWNTO 0);
s_axis_cc_tuser : IN std_logic_vector(32 DOWNTO 0);
s_axis_cc_tvalid : IN std_logic;
pcie_rq_seq_num : OUT std_logic_vector(3 DOWNTO 0);
pcie_rq_seq_num_vld : OUT std_logic;
pcie_rq_tag : OUT std_logic_vector(5 DOWNTO 0);
pcie_rq_tag_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_rq_tag_vld : OUT std_logic;
pcie_tfc_nph_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_tfc_npd_av : OUT std_logic_vector(1 DOWNTO 0);
pcie_cq_np_req : IN std_logic;
pcie_cq_np_req_count : OUT std_logic_vector(5 DOWNTO 0);
cfg_phy_link_down : OUT std_logic;
cfg_phy_link_status : OUT std_logic_vector(1 DOWNTO 0);
cfg_negotiated_width : OUT std_logic_vector(3 DOWNTO 0);
cfg_current_speed : OUT std_logic_vector(2 DOWNTO 0);
cfg_max_payload : OUT std_logic_vector(2 DOWNTO 0);
cfg_max_read_req : OUT std_logic_vector(2 DOWNTO 0);
cfg_function_status : OUT std_logic_vector(15 DOWNTO 0);
cfg_function_power_state : OUT std_logic_vector(11 DOWNTO 0);
cfg_vf_status : OUT std_logic_vector(15 DOWNTO 0);
cfg_vf_power_state : OUT std_logic_vector(23 DOWNTO 0);
cfg_link_power_state : OUT std_logic_vector(1 DOWNTO 0);
cfg_mgmt_addr : IN std_logic_vector(18 DOWNTO 0);
cfg_mgmt_write : IN std_logic;
cfg_mgmt_write_data : IN std_logic_vector(31 DOWNTO 0);
cfg_mgmt_byte_enable : IN std_logic_vector(3 DOWNTO 0);
cfg_mgmt_read : IN std_logic;
cfg_mgmt_read_data : OUT std_logic_vector(31 DOWNTO 0);
cfg_mgmt_read_write_done : OUT std_logic;
cfg_mgmt_type1_cfg_reg_access : IN std_logic;
cfg_err_cor_out : OUT std_logic;
cfg_err_nonfatal_out : OUT std_logic;
cfg_err_fatal_out : OUT std_logic;
cfg_local_error : OUT std_logic;
cfg_ltr_enable : OUT std_logic;
cfg_ltssm_state : OUT std_logic_vector(5 DOWNTO 0);
cfg_rcb_status : OUT std_logic_vector(3 DOWNTO 0);
cfg_dpa_substate_change : OUT std_logic_vector(3 DOWNTO 0);
cfg_obff_enable : OUT std_logic_vector(1 DOWNTO 0);
cfg_pl_status_change : OUT std_logic;
cfg_tph_requester_enable : OUT std_logic_vector(3 DOWNTO 0);
cfg_tph_st_mode : OUT std_logic_vector(11 DOWNTO 0);
cfg_vf_tph_requester_enable : OUT std_logic_vector(7 DOWNTO 0);
cfg_vf_tph_st_mode : OUT std_logic_vector(23 DOWNTO 0);
cfg_msg_received : OUT std_logic;
cfg_msg_received_data : OUT std_logic_vector(7 DOWNTO 0);
cfg_msg_received_type : OUT std_logic_vector(4 DOWNTO 0);
cfg_msg_transmit : IN std_logic;
cfg_msg_transmit_type : IN std_logic_vector(2 DOWNTO 0);
cfg_msg_transmit_data : IN std_logic_vector(31 DOWNTO 0);
cfg_msg_transmit_done : OUT std_logic;
cfg_fc_ph : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_pd : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_nph : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_npd : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_cplh : OUT std_logic_vector(7 DOWNTO 0);
cfg_fc_cpld : OUT std_logic_vector(11 DOWNTO 0);
cfg_fc_sel : IN std_logic_vector(2 DOWNTO 0);
cfg_per_func_status_control : IN std_logic_vector(2 DOWNTO 0);
cfg_per_func_status_data : OUT std_logic_vector(15 DOWNTO 0);
cfg_per_function_number : IN std_logic_vector(3 DOWNTO 0);
cfg_per_function_output_request : IN std_logic;
cfg_per_function_update_done : OUT std_logic;
cfg_dsn : IN std_logic_vector(63 DOWNTO 0);
cfg_power_state_change_ack : IN std_logic;
cfg_power_state_change_interrupt : OUT std_logic;
cfg_err_cor_in : IN std_logic;
cfg_err_uncor_in : IN std_logic;
cfg_flr_in_process : OUT std_logic_vector(3 DOWNTO 0);
cfg_flr_done : IN std_logic_vector(3 DOWNTO 0);
cfg_vf_flr_in_process : OUT std_logic_vector(7 DOWNTO 0);
cfg_vf_flr_done : IN std_logic_vector(7 DOWNTO 0);
cfg_link_training_enable : IN std_logic;
cfg_ext_read_received : OUT std_logic;
cfg_ext_write_received : OUT std_logic;
cfg_ext_register_number : OUT std_logic_vector(9 DOWNTO 0);
cfg_ext_function_number : OUT std_logic_vector(7 DOWNTO 0);
cfg_ext_write_data : OUT std_logic_vector(31 DOWNTO 0);
cfg_ext_write_byte_enable : OUT std_logic_vector(3 DOWNTO 0);
cfg_ext_read_data : IN std_logic_vector(31 DOWNTO 0);
cfg_ext_read_data_valid : IN std_logic;
cfg_interrupt_int : IN std_logic_vector(3 DOWNTO 0);
cfg_interrupt_pending : IN std_logic_vector(3 DOWNTO 0);
cfg_interrupt_sent : OUT std_logic;
cfg_interrupt_msix_enable : OUT std_logic_vector(3 DOWNTO 0);
cfg_interrupt_msix_mask : OUT std_logic_vector(3 DOWNTO 0);
cfg_interrupt_msix_vf_enable : OUT std_logic_vector(7 DOWNTO 0);
cfg_interrupt_msix_vf_mask : OUT std_logic_vector(7 DOWNTO 0);
cfg_interrupt_msix_data : IN std_logic_vector(31 DOWNTO 0);
cfg_interrupt_msix_address : IN std_logic_vector(63 DOWNTO 0);
cfg_interrupt_msix_int : IN std_logic;
cfg_interrupt_msix_sent : OUT std_logic;
cfg_interrupt_msix_fail : OUT std_logic;
cfg_hot_reset_out : OUT std_logic;
cfg_config_space_enable : IN std_logic;
cfg_req_pm_transition_l23_ready : IN std_logic;
cfg_hot_reset_in : IN std_logic;
cfg_ds_port_number : IN std_logic_vector(7 DOWNTO 0);
cfg_ds_bus_number : IN std_logic_vector(7 DOWNTO 0);
cfg_ds_device_number : IN std_logic_vector(4 DOWNTO 0);
cfg_ds_function_number : IN std_logic_vector(2 DOWNTO 0);
cfg_subsys_vend_id : IN std_logic_vector(15 DOWNTO 0);
sys_clk : IN std_logic;
sys_clk_gt : IN std_logic;
sys_reset : IN std_logic;
int_qpll1lock_out : OUT std_logic_vector(1 DOWNTO 0);
int_qpll1outrefclk_out : OUT std_logic_vector(1 DOWNTO 0);
int_qpll1outclk_out : OUT std_logic_vector(1 DOWNTO 0)
);
END COMPONENT;
 
/firmware/sources/application/application.vhd
71,8 → 71,8
upfifo_din : in std_logic_vector(255 downto 0);
downfifo_dout : out std_logic_vector(255 downto 0);
downfifo_prog_empty : out std_logic;
downfifo_empty_thresh: in STD_LOGIC_VECTOR(7 downto 0);
upfifo_prog_full : out std_logic;
downfifo_empty_thresh: in std_logic_vector(6 downto 0);
upfifo_prog_full : out std_logic;
fifo_rd_clk : in std_logic;
downfifo_re : in std_logic;
upfifo_we : in std_logic;
252,7 → 252,7
empty => open,
prog_full => s_downfifo_prog_full,
prog_empty => downfifo_prog_empty,
prog_empty_thresh => downfifo_empty_thresh
prog_empty_thresh => "0"&downfifo_empty_thresh
);
 
/firmware/sources/shared/wupper_oc_top.vhd
97,8 → 97,7
signal u1_pll_locked : std_logic;
signal reset_soft : std_logic;
signal reset_hard : std_logic;
signal downfifo_empty_thresh : STD_LOGIC_VECTOR(7 downto 0);
signal sys_reset_n_c : std_logic;
signal downfifo_empty_thresh : std_logic_vector(6 downto 0);
 
component wupper
generic(
109,31 → 108,33
CARD_TYPE : integer := 709;
DEVID : std_logic_vector(15 downto 0) := x"7038");
port (
appreg_clk : out std_logic;
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out STD_LOGIC_VECTOR(7 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
fifo_rd_clk : out std_logic;
fifo_wr_clk : out std_logic;
flush_fifo : out std_logic;
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
lnk_up : out std_logic;
pcie_rxn : in std_logic_vector(7 downto 0);
pcie_rxp : in std_logic_vector(7 downto 0);
pcie_txn : out std_logic_vector(7 downto 0);
pcie_txp : out std_logic_vector(7 downto 0);
pll_locked : out std_logic;
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset_hard : out std_logic;
reset_soft : out std_logic;
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_reset_n : in std_logic;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic);
appreg_clk : out std_logic;
downfifo_dout : in std_logic_vector(255 downto 0);
downfifo_empty_thresh : out std_logic_vector(6 downto 0);
downfifo_prog_empty : in std_logic;
downfifo_re : out std_logic;
fifo_rd_clk : out std_logic;
fifo_wr_clk : out std_logic;
flush_fifo : out std_logic;
interrupt_call : in std_logic_vector(NUMBER_OF_INTERRUPTS-1 downto 4);
lnk_up : out std_logic;
pcie_rxn : in std_logic_vector(7 downto 0);
pcie_rxp : in std_logic_vector(7 downto 0);
pcie_txn : out std_logic_vector(7 downto 0);
pcie_txp : out std_logic_vector(7 downto 0);
pfull_threshold_assert : out std_logic_vector(6 downto 0);
pfull_threshold_negate : out std_logic_vector(6 downto 0);
pll_locked : out std_logic;
register_map_control : out register_map_control_type;
register_map_monitor : in register_map_monitor_type;
reset_hard : out std_logic;
reset_soft : out std_logic;
sys_clk_n : in std_logic;
sys_clk_p : in std_logic;
sys_reset_n : in std_logic;
upfifo_din : out std_logic_vector(255 downto 0);
upfifo_prog_full : in std_logic;
upfifo_we : out std_logic);
end component wupper;
 
component application
143,7 → 144,7
port (
appreg_clk : in std_logic;
downfifo_dout : out std_logic_vector(255 downto 0);
downfifo_empty_thresh : in STD_LOGIC_VECTOR(7 downto 0);
downfifo_empty_thresh : in std_logic_vector(6 downto 0);
downfifo_prog_empty : out std_logic;
downfifo_re : in std_logic;
fifo_rd_clk : in std_logic;
163,16 → 164,8
 
begin
emcclk_out <= emcclk;
-- This seems to be needed for ultrascale
ib1: IBUF
port map (
I => sys_reset_n,
O => sys_reset_n_c);
 
 
 
--! Instantiation of the actual PCI express core. Please note the 40MHz
--! clock required by the core, the 250MHz clock (fifo_rd_clk and fifo_wr_clk)
--! are generated from sys_clk_p and _n
185,31 → 178,33
SVN_VERSION => SVN_VERSION,
DEVID => x"7038")
port map(
appreg_clk => appreg_clk,
downfifo_dout => downfifo_dout,
downfifo_empty_thresh => downfifo_empty_thresh,
downfifo_prog_empty => downfifo_prog_empty,
downfifo_re => downfifo_re,
fifo_rd_clk => fifo_rd_clk,
fifo_wr_clk => fifo_wr_clk,
flush_fifo => flush_fifo,
interrupt_call => interrupt_call,
lnk_up => open,
pcie_rxn => pcie_rxn,
pcie_rxp => pcie_rxp,
pcie_txn => pcie_txn,
pcie_txp => pcie_txp,
pll_locked => u1_pll_locked,
register_map_control => register_map_control,
register_map_monitor => register_map_monitor,
reset_hard => reset_hard,
reset_soft => reset_soft,
sys_clk_n => sys_clk_n,
sys_clk_p => sys_clk_p,
sys_reset_n => sys_reset_n_c,
upfifo_din => upfifo_din,
upfifo_prog_full => upfifo_prog_full,
upfifo_we => upfifo_we);
appreg_clk => appreg_clk,
downfifo_dout => downfifo_dout,
downfifo_empty_thresh => downfifo_empty_thresh,
downfifo_prog_empty => downfifo_prog_empty,
downfifo_re => downfifo_re,
fifo_rd_clk => fifo_rd_clk,
fifo_wr_clk => fifo_wr_clk,
flush_fifo => flush_fifo,
interrupt_call => interrupt_call,
lnk_up => open,
pcie_rxn => pcie_rxn,
pcie_rxp => pcie_rxp,
pcie_txn => pcie_txn,
pcie_txp => pcie_txp,
pfull_threshold_assert => open,
pfull_threshold_negate => open,
pll_locked => u1_pll_locked,
register_map_control => register_map_control,
register_map_monitor => register_map_monitor,
reset_hard => reset_hard,
reset_soft => reset_soft,
sys_clk_n => sys_clk_n,
sys_clk_p => sys_clk_p,
sys_reset_n => sys_reset_n,
upfifo_din => upfifo_din,
upfifo_prog_full => upfifo_prog_full,
upfifo_we => upfifo_we);
 
 
--! The example application only instantiates one fifo (PC=>PCIe).
/firmware/sources/packages/pcie_package.vhd
69,7 → 69,7
end record;
 
--
-- PCIe DMA core: descriptors
-- PCIe DMA core: descriptors
type dma_descriptor_type is record
start_address : std_logic_vector(63 downto 0);
current_address : std_logic_vector(63 downto 0);
80,7 → 80,7
wrap_around : std_logic; --1 means when end is reached, keep enabled and start over
evencycle_dma : std_logic; --For every time the current_address overflows, this bit toggles
evencycle_pc : std_logic; --For every time the pc pointer overflows, this bit toggles.
pc_pointer : std_logic_vector(63 downto 0); --Last address that the PC has read / written. For write: overflow and read until this cycle.
pc_pointer : std_logic_vector(63 downto 0); --Last address that the PC has read / written. For write: overflow and read until this cycle.
end record;
 
type dma_descriptors_type is array (natural range <>) of dma_descriptor_type;
92,7 → 92,7
type dma_statuses_type is array(natural range <>) of dma_status_type;
 
--
-- PCIe DMA core: Interrupt Vectors
-- PCIe DMA core: Interrupt Vectors
type interrupt_vector_type is record
int_vec_add : std_logic_vector(63 downto 0);
int_vec_data : std_logic_vector(31 downto 0);
99,10 → 99,10
int_vec_ctrl : std_logic_vector(31 downto 0);
end record;
 
type interrupt_vectors_type is array (natural range <>) of interrupt_vector_type;
type interrupt_vectors_type is array (natural range <>) of interrupt_vector_type;
 
--! Address Offset assignment
--! --> BAR0 User Application Registers Addresses
--! --> BAR0 User Application Registers Addresses
-- ### BAR0 registers: start
constant REG_DESCRIPTOR_0 : std_logic_vector(19 downto 0) := x"00000";
constant REG_DESCRIPTOR_0a : std_logic_vector(19 downto 0) := x"00010";
154,16 → 154,17
constant REG_STATUS_15 : std_logic_vector(19 downto 0) := x"002F0";
constant REG_BAR0 : std_logic_vector(19 downto 0) := x"00300";
constant REG_BAR1 : std_logic_vector(19 downto 0) := x"00310";
constant REG_BAR2 : std_logic_vector(19 downto 0) := x"00320";
constant REG_BAR2 : std_logic_vector(19 downto 0) := x"00320";
constant REG_DESCRIPTOR_ENABLE : std_logic_vector(19 downto 0) := x"00400";
constant REG_FIFO_FLUSH : std_logic_vector(19 downto 0) := x"00410";
constant REG_DMA_RESET : std_logic_vector(19 downto 0) := x"00420";
constant REG_SOFT_RESET : std_logic_vector(19 downto 0) := x"00430";
constant REG_REGISTER_RESET : std_logic_vector(19 downto 0) := x"00440";
constant REG_FROMHOST_FULL_THRESH: std_logic_vector(19 downto 0) := x"00450";
-- BAR0 registers: end
 
--! Address Offset assignment
--! --> BAR1 User Application Registers Addresses
--! --> BAR1 User Application Registers Addresses
-- ### BAR1 registers: start
-- interrupt vectors
constant REG_INT_VEC_00 : std_logic_vector(19 downto 0) := x"00000";
176,8 → 177,8
constant REG_INT_VEC_07 : std_logic_vector(19 downto 0) := x"00070";
constant REG_INT_TAB_EN : std_logic_vector(19 downto 0) := x"00100";
-- BAR1 registers: end
 
 
--! Address Offset assignment
--! --> BAR2 User Application Registers Addresses
--! -- leave 16x8 = 128 bits space per register

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