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URL https://opencores.org/ocsvn/vspi/vspi/trunk

Subversion Repositories vspi

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  • This comparison shows the changes necessary to convert path 
    /vspi/trunk
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/test/spi_base/spiifc_tb.v
0,0 → 1,98
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:46:21 10/18/2011
// Design Name: spiifc
// Module Name: C:/workspace/robobees/hbp/fpga/spiifc/spiifc_tb.v
// Project Name: spiifc
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spiifc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module spiifc_tb;
 
// Inputs
reg Reset;
reg SPI_CLK;
reg SPI_MOSI;
reg SPI_SS;
reg [7:0] MemData;
 
// Outputs
wire SPI_MISO;
wire [11:0] MemAddr;
 
// Memory
reg [7:0] Mem [0:4095];
integer i;
// Instantiate the Unit Under Test (UUT)
spiifc uut (
.Reset(Reset),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.MemAddr(MemAddr),
.MemData(MemData)
);
 
always @(posedge SPI_CLK) begin
MemData <= Mem[MemAddr];
end
 
always @(*) begin
#50;
SPI_CLK <= ~SPI_CLK;
end
 
initial begin
// Initialize memory
for (i = 0; i < 4096; i = i + 2) begin
// Mem[i] <= i[7:0];
Mem[i] <= 8'hFF;
Mem[i+1] <= 8'h00;
end
// Initialize Inputs
Reset = 0;
SPI_CLK = 0;
SPI_MOSI = 0;
SPI_SS = 1;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Reset <= 1'b1;
#100;
Reset <= 1'b0;
#100;
SPI_SS <= 1'b0;
#4000;
SPI_SS <= 1'b1;
#400;
$finish;
 
end
endmodule
 
/test/spi_base/rc-bytes.txt
0,0 → 1,10
01
FF
F0
33
55
12
34
56
78
9A
/test/spi_base/spiifc_tb2.v
0,0 → 1,134
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:08:12 02/15/2012
// Design Name: spiifc
// Module Name: C:/workspace/robobees/hbp/fpga/spitest/pcores/spi_v1_00_a/hdl/verilog/spiifc_tb2.v
// Project Name: spi
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spiifc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module spiifc_tb2;
 
// Inputs
reg Reset;
reg SysClk;
reg SPI_CLK;
reg SPI_MOSI;
reg SPI_SS;
reg [7:0] txMemData;
 
// Outputs
wire SPI_MISO;
wire [11:0] txMemAddr;
wire [11:0] rcMemAddr;
wire [7:0] rcMemData;
wire rcMemWE;
wire [7:0] debug_out;
 
// Instantiate the Unit Under Test (UUT)
spiifc uut (
.Reset(Reset),
.SysClk(SysClk),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.txMemAddr(txMemAddr),
.txMemData(txMemData),
.rcMemAddr(rcMemAddr),
.rcMemData(rcMemData),
.rcMemWE(rcMemWE),
.debug_out(debug_out)
);
 
task recvByte;
input [7:0] rcByte;
integer rcBitIndex;
begin
$display("%g - spiifc receiving byte '0x%h'", $time, rcByte);
for (rcBitIndex = 0; rcBitIndex < 8; rcBitIndex = rcBitIndex + 1) begin
SPI_MOSI = rcByte[7 - rcBitIndex];
#100;
end
end
endtask
 
always begin
#20 SysClk = ~SysClk;
end
 
reg SPI_CLK_en;
initial begin
#310
SPI_CLK_en = 1;
end
always begin
#10
if (SPI_CLK_en) begin
#40 SPI_CLK = ~SPI_CLK;
end
end
 
integer fdRcBytes;
integer dummy;
integer currRcByte;
integer rcBytesNotEmpty;
reg [8*10:1] rcBytesStr;
initial begin
// Initialize Inputs
Reset = 0;
SysClk = 0;
SPI_CLK = 0;
SPI_CLK_en = 0;
SPI_MOSI = 0;
SPI_SS = 1;
txMemData = 0;
 
// Wait 100 ns for global reset to finish
#100;
Reset = 1;
#100;
Reset = 0;
#100;
// Add stimulus here
SPI_SS = 0;
// For each byte, transmit its bits
fdRcBytes = $fopen("rc-bytes.txt", "r");
rcBytesNotEmpty = 1;
while (rcBytesNotEmpty) begin
rcBytesNotEmpty = $fgets(rcBytesStr, fdRcBytes);
if (rcBytesNotEmpty) begin
dummy = $sscanf(rcBytesStr, "%x", currRcByte);
recvByte(currRcByte);
end
end
// Wrap it up.
SPI_SS = 1;
#1000;
$finish;
end
endmodule
 
/src/spi_base/spiifc_tb.v File deleted
/src/spi_base/spiifc_tb2.v File deleted
/src/spi_base/spiifc.v
38,6 → 38,14
//
parameter AddrBits = 12;
// Defines
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
//
// Input/Output defs
//
68,6 → 76,9
reg rcStarted;
reg [ 2: 0] rcBitIndexReg;
reg [11: 0] rcMemAddrReg;
reg [11: 0] rcMemAddrNext;
reg [ 7: 0] rcMemDataReg;
reg rcMemWEReg;
reg ssPrev;
77,6 → 88,9
reg ssTurnOnReg;
reg ssTurnOnHandled;
reg [ 7: 0] cmd;
reg [ 7: 0] stateReg;
//
// Wires
//
89,6 → 103,8
wire ssFastToggle;
wire [ 7: 0] state;
//
// Output assigns
//
98,8 → 114,8
assign txMemAddr = 0;
assign rcMemAddr = rcMemAddrReg;
assign rcMemData = rcByte;
assign rcMemWE = rcByteValid;
assign rcMemData = rcMemDataReg;
assign rcMemWE = rcMemWEReg;
assign ssFastToggle =
(ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg);
112,8 → 128,8
assign rcStarting = ssTurnOn;
assign rcBitIndex = (rcStarting ? 3'd7 : rcBitIndexReg);
//assign ssTurnOn = ~ssTurnOnHandled & (ssTurnOnReg | (ssPrev & (~SPI_SS)));
assign ssTurnOn = ssSlowToggle ^ ssFastToggle;
assign state = (rcStarting ? `STATE_GET_CMD : stateReg);
initial begin
ssSlowToggle <= 0;
140,6 → 156,7
always @(posedge SPI_CLK) begin
ssSlowToggle <= ssFastToggle;
 
if (Reset) begin
// Resetting
152,6 → 169,8
end else begin
// Not resetting
ssTurnOnHandled <= ssTurnOn;
stateReg <= state;
rcMemAddrReg <= rcMemAddrNext;
if (~SPI_SS) begin
rcByteReg[rcBitIndex] <= SPI_MOSI;
161,11 → 180,32
// We've just received a byte (well, currently receiving the last bit)
if (rcByteValid) begin
// For now, just display on LEDs
debug_reg <= rcByte;
end
if (rcByteValid) begin
// For now, just display on LEDs
debug_reg <= rcByte;
if (`STATE_GET_CMD == state) begin
cmd <= rcByte; // Will take effect next cycle
if (`CMD_READ_START == rcByte) begin
rcMemAddrNext <= 0;
stateReg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
stateReg <= `STATE_READING;
end
end else if (`STATE_READING == state) begin
rcMemDataReg <= rcByte;
rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1;
end
end else begin
// Not a valid byte
rcMemWEReg <= 0;
end // valid/valid' byte
end // Reset/Reset'
end
/src/spi_base/spiwrap.v
32,6 → 32,7
 
wire [11:0] spi_addr;
wire [ 7:0] spi_data;
wire [31:0] rcMem_douta;
 
reg initMem;
reg [ 9:0] initMemAddr;
82,8 → 83,8
.clka(SysClk),
.ena(1'b1),
.wea(1'b0),
.addra(10'h000),
.douta(debug_out),
.addra(10'h001),
.douta(rcMem_douta),
.clkb(spi_clk),
.enb(1'b1),
.web(spi_rcMem_we),
104,11 → 105,11
.rcMemAddr(spi_rcMem_addr),
.rcMemData(spi_rcMem_data),
.rcMemWE(spi_rcMem_we),
.debug_out(leds)
.debug_out(debug_out)
);
 
 
 
//assign leds = debug_out;
assign leds = rcMem_douta[31:24];
 
endmodule

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