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URL https://opencores.org/ocsvn/vspi/vspi/trunk

Subversion Repositories vspi

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  • This comparison shows the changes necessary to convert path 
    /vspi/trunk
    from Rev 8 to Rev 9
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Rev 8 → Rev 9

/src/spi_base/spiifc_tb.v
0,0 → 1,98
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:46:21 10/18/2011
// Design Name: spiifc
// Module Name: C:/workspace/robobees/hbp/fpga/spiifc/spiifc_tb.v
// Project Name: spiifc
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spiifc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module spiifc_tb;
 
// Inputs
reg Reset;
reg SPI_CLK;
reg SPI_MOSI;
reg SPI_SS;
reg [7:0] MemData;
 
// Outputs
wire SPI_MISO;
wire [11:0] MemAddr;
 
// Memory
reg [7:0] Mem [0:4095];
integer i;
// Instantiate the Unit Under Test (UUT)
spiifc uut (
.Reset(Reset),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.MemAddr(MemAddr),
.MemData(MemData)
);
 
always @(posedge SPI_CLK) begin
MemData <= Mem[MemAddr];
end
 
always @(*) begin
#50;
SPI_CLK <= ~SPI_CLK;
end
 
initial begin
// Initialize memory
for (i = 0; i < 4096; i = i + 2) begin
// Mem[i] <= i[7:0];
Mem[i] <= 8'hFF;
Mem[i+1] <= 8'h00;
end
// Initialize Inputs
Reset = 0;
SPI_CLK = 0;
SPI_MOSI = 0;
SPI_SS = 1;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Reset <= 1'b1;
#100;
Reset <= 1'b0;
#100;
SPI_SS <= 1'b0;
#4000;
SPI_SS <= 1'b1;
#400;
$finish;
 
end
endmodule
 
/src/spi_base/spiifc_tb2.v
0,0 → 1,117
`timescale 1ns / 1ps
 
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:08:12 02/15/2012
// Design Name: spiifc
// Module Name: C:/workspace/robobees/hbp/fpga/spitest/pcores/spi_v1_00_a/hdl/verilog/spiifc_tb2.v
// Project Name: spi
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spiifc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
 
module spiifc_tb2;
 
// Inputs
reg Reset;
reg SysClk;
reg SPI_CLK;
reg SPI_MOSI;
reg SPI_SS;
reg [7:0] txMemData;
 
// Outputs
wire SPI_MISO;
wire [11:0] txMemAddr;
wire [11:0] rcMemAddr;
wire [7:0] rcMemData;
wire rcMemWE;
 
// Instantiate the Unit Under Test (UUT)
spiifc uut (
.Reset(Reset),
.SysClk(SysClk),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.txMemAddr(txMemAddr),
.txMemData(txMemData),
.rcMemAddr(rcMemAddr),
.rcMemData(rcMemData),
.rcMemWE(rcMemWE)
);
 
task recvByte;
input [7:0] rcByte;
integer rcBitIndex;
begin
$display("%g - spiifc receiving byte '0x%h'", $time, rcByte);
for (rcBitIndex = 0; rcBitIndex < 8; rcBitIndex = rcBitIndex + 1) begin
SPI_MOSI = rcByte[7 - rcBitIndex];
#100;
end
end
endtask
 
always begin
#20 SysClk = ~SysClk;
end
 
always begin
#50 SPI_CLK = ~SPI_CLK;
end
 
integer fdRcBytes;
integer dummy;
integer currRcByte;
integer rcBytesNotEmpty;
reg [8*10:1] rcBytesStr;
initial begin
// Initialize Inputs
Reset = 0;
SysClk = 0;
SPI_CLK = 0;
SPI_MOSI = 0;
SPI_SS = 1;
txMemData = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
SPI_SS = 0;
// For each byte, transmit its bits
fdRcBytes = $fopen("rc-bytes.txt", "r");
rcBytesNotEmpty = 1;
while (rcBytesNotEmpty) begin
rcBytesNotEmpty = $fgets(rcBytesStr, fdRcBytes);
if (rcBytesNotEmpty) begin
dummy = $sscanf(rcBytesStr, "%x", currRcByte);
recvByte(currRcByte);
end
end
// Wrap it up.
SPI_SS = 1;
#1000;
$finish;
end
endmodule
 

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