OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

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  • This comparison shows the changes necessary to convert path 
    /w11
    from Rev 7 to Rev 8
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  •

Rev 7 → Rev 8

/trunk/tools/bin/tmuconv
1,5 → 1,5
#!/usr/bin/perl -w
# $Id: tmuconv 314 2010-07-09 17:38:41Z mueller $
# $Id: tmuconv 334 2010-10-23 08:24:24Z mueller $
#
# Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
14,6 → 14,7
#
# Revision History:
# Date Rev Version Comment
# 2010-10-22 334 1.0.9 adapt to ibus V2 signals: req,we,dip->aval,re,we,rmw
# 2010-06-26 309 1.0.8 add ibimres.cacc/racc handling
# 2010-04-26 284 1.0.7 add error check for GetOptions
# 2009-09-19 240 1.0.6 add more VFETCH addr defs; add 2nd DL11 defs
40,11 → 41,12
# dp.gpr_mode:o
# dp.gpr_bytop:b
# dp.gpr_we:b
# vm.ibmreq.req:b
# vm.ibmreq.aval:b
# vm.ibmreq.re:b
# vm.ibmreq.we:b
# vm.ibmreq.rmw:b
# vm.ibmreq.be0:b
# vm.ibmreq.be1:b
# vm.ibmreq.dip:b
# vm.ibmreq.cacc:b
# vm.ibmreq.racc:b
# vm.ibmreq.addr:o
108,8 → 110,10
my $ind_dp_gpr_bytop;
my $ind_dp_gpr_we;
 
my $ind_vm_ibmreq_req;
my $ind_vm_ibmreq_aval;
my $ind_vm_ibmreq_re;
my $ind_vm_ibmreq_we;
my $ind_vm_ibmreq_rmw;
my $ind_vm_ibmreq_be0;
my $ind_vm_ibmreq_be1;
my $ind_vm_ibmreq_cacc;
463,8 → 467,10
$ind_dp_gpr_bytop = $name{'dp.gpr_bytop'}->{ind};
$ind_dp_gpr_we = $name{'dp.gpr_we'}->{ind};
 
$ind_vm_ibmreq_req = $name{'vm.ibmreq.req'}->{ind};
$ind_vm_ibmreq_aval = $name{'vm.ibmreq.aval'}->{ind};
$ind_vm_ibmreq_re = $name{'vm.ibmreq.re'}->{ind};
$ind_vm_ibmreq_we = $name{'vm.ibmreq.we'}->{ind};
$ind_vm_ibmreq_rmw = $name{'vm.ibmreq.rmw'}->{ind};
$ind_vm_ibmreq_be0 = $name{'vm.ibmreq.be0'}->{ind};
$ind_vm_ibmreq_be1 = $name{'vm.ibmreq.be1'}->{ind};
$ind_vm_ibmreq_cacc = $name{'vm.ibmreq.cacc'}->{ind};
685,19 → 691,20
}
#
# handle t_ib
# uses cycles with sy_ibmreq_req = '1'
# uses cycles with sy_ibmreq_re = '1' or sy_ibmreq_we = '1'
# sy_ibsres_ack = '1'
# vm_ibsres_busy '1' -> '0' transition
#
if (exists $opts{t_ib}) {
if ($val_curr[$ind_vm_ibmreq_req]) {
if ($val_curr[$ind_vm_ibmreq_re] || $val_curr[$ind_vm_ibmreq_we]) {
my $addr_str = sprintf "%6.6o", $val_curr[$ind_vm_ibmreq_addr];
$ibreq_cyc = $cyc_curr;
$ibreq_typ = sprintf "%s%s",
($val_curr[$ind_vm_ibmreq_cacc] ? "c" : "-"),
($val_curr[$ind_vm_ibmreq_racc] ? "r" : "-");
$ibreq_str = sprintf "%s %s%s %s",
($val_curr[$ind_vm_ibmreq_we] ? "w" : "r"),
$ibreq_str = sprintf "%s%s%s%s %s",
($val_curr[$ind_vm_ibmreq_we] ? "w" : "r"),
($val_curr[$ind_vm_ibmreq_rmw] ? "m" : " "),
$val_curr[$ind_vm_ibmreq_be1],
$val_curr[$ind_vm_ibmreq_be0],
$addr_str;
/trunk/tools/bin/xilinx_ghdl_unisim
1,5 → 1,5
#!/bin/sh
# $Id: xilinx_ghdl_unisim 311 2010-06-30 17:52:37Z mueller $
# $Id: xilinx_ghdl_unisim 248 2009-11-08 22:51:38Z mueller $
#
# Revision History:
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
/trunk/tools/bin/set_ftdi_lat
1,5 → 1,5
#!/bin/sh
# $Id: set_ftdi_lat 311 2010-06-30 17:52:37Z mueller $
# $Id: set_ftdi_lat 282 2010-04-24 12:08:32Z mueller $
#
# Usage: sudo $HOME/other/retro/trunk/bin/set_ftdi_lat USB0 1
#
/trunk/tools/bin/rm_dep
1,5 → 1,5
#!/bin/sh
# $Id: rm_dep 311 2010-06-30 17:52:37Z mueller $
# $Id: rm_dep 284 2010-04-26 20:55:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
/trunk/tools/bin/xilinx_vhdl_memcolltype_fix
1,5 → 1,5
#!/bin/sh
# $Id: xilinx_vhdl_memcolltype_fix 311 2010-06-30 17:52:37Z mueller $
# $Id: xilinx_vhdl_memcolltype_fix 93 2007-10-28 21:24:44Z mueller $
#
# remove the lines
#
/trunk/tools/bin/xilinx_ghdl_simprim
1,5 → 1,5
#!/bin/sh
# $Id: xilinx_ghdl_simprim 311 2010-06-30 17:52:37Z mueller $
# $Id: xilinx_ghdl_simprim 248 2009-11-08 22:51:38Z mueller $
#
# Revision History:
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
/trunk/rtl/ibus/ib_sres_or_mon.vhd
0,0 → 1,99
-- $Id: ib_sres_or_mon.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_mon - sim
-- Description: ibus result or monitor
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.iblib.all;
 
-- ----------------------------------------------------------------------------
 
entity ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end ib_sres_or_mon;
 
architecture sim of ib_sres_or_mon is
begin
 
proc_comb : process (IB_SRES_1, IB_SRES_2, IB_SRES_3, IB_SRES_4)
constant dzero : slv16 := (others=>'0');
variable oline : line;
variable nack : integer := 0;
variable nbusy : integer := 0;
variable ndout : integer := 0;
begin
 
nack := 0;
nbusy := 0;
ndout := 0;
if IB_SRES_1.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_2.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_3.ack /= '0' then nack := nack + 1; end if;
if IB_SRES_4.ack /= '0' then nack := nack + 1; end if;
 
if IB_SRES_1.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_2.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_3.busy /= '0' then nbusy := nbusy + 1; end if;
if IB_SRES_4.busy /= '0' then nbusy := nbusy + 1; end if;
 
if IB_SRES_1.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_2.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if IB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
 
if now > 0 ns and (nack>1 or nbusy>1 or ndout>1) then
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
write(oline, nack);
end if;
if nbusy > 1 then
write(oline, string'(" #busy="));
write(oline, nbusy);
end if;
if ndout > 1 then
write(oline, string'(" #dout="));
write(oline, ndout);
end if;
write(oline, string'(" FAIL in "));
write(oline, ib_sres_or_mon'path_name);
writeline(output, oline);
end if;
end process proc_comb;
end sim;
/trunk/rtl/ibus/ibdr_dl11.vhd
1,4 → 1,4
-- $Id: ibdr_dl11.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibdr_dl11.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,15 → 18,18
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
55,7 → 58,7
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
84,6 → 87,7
constant xbuf_ibf_rrdy : integer := 9;
 
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
100,6 → 104,7
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- rrlim
'0','0', -- rdone, rie
(others=>'0'), -- rbuf
126,7 → 131,7
R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter
end if;
else
else
R_REGS <= N_REGS;
end if;
end if;
135,8 → 140,8
proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
148,9 → 153,9
r := R_REGS;
n := R_REGS;
 
ibsel := '0';
idout := (others=>'0');
ibrd := not IB_MREQ.we;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
157,12 → 162,14
rdlystart := '0';
-- ibus address decoder
if IB_MREQ.req='1' and IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
ibsel := '1';
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
 
-- ibus transactions
if ibsel = '1' then
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
 
when ibaddr_rcsr => -- RCSR -- receive control status ----
328,10 → 335,10
N_REGS <= n;
 
IB_SRES.dout <= idout;
IB_SRES.ack <= ibsel;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
 
RRI_LAM <= ilam;
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
/trunk/rtl/ibus/ibdr_pc11.vhd
1,4 → 1,4
-- $Id: ibdr_pc11.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibdr_pc11.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,14 → 18,17
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
-- causes interrupt, if enabled; validated with zpcae0
46,7 → 49,7
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
79,6 → 82,7
constant pbuf_ibf_rbusy : integer := 9;
 
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
93,6 → 97,7
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
'0','0','0', -- rbusy,rdone,rie
(others=>'0'), -- rbuf
118,7 → 123,7
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
end if;
else
else
R_REGS <= N_REGS;
end if;
end if;
127,8 → 132,8
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
138,21 → 143,22
r := R_REGS;
n := R_REGS;
 
ibsel := '0';
idout := (others=>'0');
ibrd := not IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
if IB_MREQ.req='1' and
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
ibsel := '1';
n.ibsel := '1';
end if;
 
-- ibus transactions
if ibsel = '1' then
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
 
when ibaddr_rcsr => -- RCSR -- reader control status -----
301,10 → 307,10
N_REGS <= n;
 
IB_SRES.dout <= idout;
IB_SRES.ack <= ibsel;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
 
RRI_LAM <= ilam;
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
/trunk/rtl/ibus/ib_sres_or_2.vhd
1,6 → 1,6
-- $Id: ib_sres_or_2.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ib_sres_or_2.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,9 → 18,11
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
58,4 → 60,14
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => ib_sres_init,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
 
end syn;
/trunk/rtl/ibus/ib_sres_or_3.vhd
1,6 → 1,6
-- $Id: ib_sres_or_3.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ib_sres_or_3.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,9 → 18,11
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
61,5 → 63,15
IB_SRES_3.dout;
end process proc_comb;
 
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
end syn;
/trunk/rtl/ibus/ib_sres_or_4.vhd
1,6 → 1,6
-- $Id: ib_sres_or_4.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ib_sres_or_4.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,9 → 18,11
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
65,5 → 67,15
IB_SRES_4.dout;
end process proc_comb;
 
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => IB_SRES_3,
IB_SRES_4 => IB_SRES_4
);
-- synthesis translate_on
end syn;
/trunk/rtl/ibus/ibdr_lp11.vhd
1,4 → 1,4
-- $Id: ibdr_lp11.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibdr_lp11.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,14 → 18,17
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 12 35 0 24 s 5.6
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 11 30 0 19 s 5.8
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-21 228 1.0.1 generate interrupt locally when err=1
-- 2009-05-30 220 1.0 Initial version
51,7 → 54,7
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
72,6 → 75,7
constant buf_ibf_val : integer := 8;
 
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
err : slbit; -- csr: error flag
done : slbit; -- csr: done flag
ie : slbit; -- csr: interrupt enable
80,6 → 84,7
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- err !! is set !!
'1', -- done !! is set !!
'0', -- ie
100,7 → 105,7
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.err <= N_REGS.err; -- don't reset ERR flag
end if;
else
else
R_REGS <= N_REGS;
end if;
end if;
109,8 → 114,8
proc_next : process (R_REGS, IB_MREQ, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ilam : slbit := '0';
119,20 → 124,21
r := R_REGS;
n := R_REGS;
 
ibsel := '0';
idout := (others=>'0');
ibrd := not IB_MREQ.we;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ilam := '0';
-- ibus address decoder
if IB_MREQ.req='1' and
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_lp11(12 downto 2) then
ibsel := '1';
n.ibsel := '1';
end if;
 
-- ibus transactions
if ibsel = '1' then
if r.ibsel = '1' then
case IB_MREQ.addr(1 downto 1) is
 
when ibaddr_csr => -- CSR -- control status -------------
193,11 → 199,11
N_REGS <= n;
 
IB_SRES.dout <= idout;
IB_SRES.ack <= ibsel;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
 
RRI_LAM <= ilam;
EI_REQ <= r.intreq;
RB_LAM <= ilam;
EI_REQ <= r.intreq;
end process proc_next;
 
/trunk/rtl/ibus/ibd_kw11l.vhd
1,6 → 1,6
-- $Id: ibd_kw11l.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibd_kw11l.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2008-2009 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,14 → 18,16
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 9 23 0 14 s 5.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 8 25 0 15 s 5.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2009-06-01 221 1.0.5 BUGFIX: add RESET; don't clear tcnt on ibus reset
-- 2008-08-22 161 1.0.4 use iblib; add EI_ACK to proc_next sens. list
-- 2008-05-09 144 1.0.3 use intreq flop, use EI_ACK
67,6 → 69,7
constant tdivide : natural := 20;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
ie : slbit; -- interrupt enable
moni : slbit; -- monitor bit
intreq : slbit; -- interrupt request
74,6 → 77,7
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- ibsel
'0', -- ie
'1', -- moni (set on reset !!)
'0', -- intreq
93,7 → 97,7
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.tcnt <= N_REGS.tcnt; -- don't clear msec tick counter
end if;
else
else
R_REGS <= N_REGS;
end if;
end if;
102,29 → 106,33
proc_next : process (R_REGS, IB_MREQ, CE_MSEC, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
ibsel := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
-- ibus address decoder
if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
ibsel := '1';
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_kw11l(12 downto 1) then
n.ibsel := '1';
end if;
 
-- ibus output driver
if ibsel = '1' then
if r.ibsel = '1' then
idout(lks_ibf_ie) := R_REGS.ie;
idout(lks_ibf_moni) := R_REGS.moni;
end if;
 
-- ibus write transactions
if ibsel='1' and IB_MREQ.we='1' and IB_MREQ.be0='1' then
if r.ibsel='1' and ibw0='1' then
n.ie := IB_MREQ.din(lks_ibf_ie);
n.moni := IB_MREQ.din(lks_ibf_moni);
if IB_MREQ.din(lks_ibf_ie)='0' or IB_MREQ.din(lks_ibf_moni)='0' then
151,7 → 159,7
N_REGS <= n;
 
IB_SRES.dout <= idout;
IB_SRES.ack <= ibsel;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
EI_REQ <= r.intreq;
/trunk/rtl/ibus/ibdr_rk11.vhd
1,4 → 1,4
-- $Id: ibdr_rk11.vhd 317 2010-07-22 19:36:56Z mueller $
-- $Id: ibdr_rk11.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,15 → 18,18
-- Dependencies: ram_1swar_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 46 248 16 137 s 7.2
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 46 249 16 148 s 7.1
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 36 189 16 111 s 6.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-05-24 219 1.0.9 add CE_MSEC input; inc sector counter every msec
-- BUGFIX: sector counter now counts 000,...,013.
58,7 → 61,7
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
113,6 → 116,7
);
 
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
state : state_type; -- state
id : slv3; -- rkds: drive id of search done
sc : slv4; -- rkds: sector counter
134,7 → 138,8
end record regs_type;
 
constant regs_init : regs_type := (
s_init, --
'0', -- ibsel
s_init, -- state
(others=>'0'), -- id
(others=>'0'), -- sc
'0','0', -- cse, wce
200,12 → 205,12
proc_next : process (R_REGS, CE_MSEC, IB_MREQ, MEM_DOUT, EI_ACK)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel : slbit := '0';
variable ibbusy : slbit := '0';
variable ibhold : slbit := '0';
variable icrip : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibrem : slbit := '0';
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibrem : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ibwrem : slbit := '0';
223,12 → 228,12
r := R_REGS;
n := R_REGS;
 
ibsel := '0';
ibbusy := '0';
ibhold := '0';
icrip := '0';
idout := (others=>'0');
ibrd := not IB_MREQ.we;
ibrem := IB_MREQ.racc or r.maint;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ibwrem := IB_MREQ.we and ibrem;
243,9 → 248,10
imem_din := IB_MREQ.din;
-- ibus address decoder
if IB_MREQ.req = '1' and
n.ibsel := '0';
if IB_MREQ.aval = '1' and
IB_MREQ.addr(12 downto 4)=ibaddr_rk11(12 downto 4) then
ibsel := '1';
n.ibsel := '1';
end if;
 
-- internal state machine (for control reset)
254,8 → 260,7
null;
 
when s_init =>
ibbusy := ibsel; -- keep req pending if selected
ibsel := '0'; -- but don't process selection
ibhold := r.ibsel; -- hold ibus when controller busy
icrip := '1';
n.icnt := unsigned(r.icnt) + 1;
if unsigned(r.icnt) = 7 then
267,7 → 272,8
 
-- ibus transactions
if ibsel = '1' then
if r.ibsel='1' and ibhold='0' then -- selected and not holding
idout := MEM_DOUT;
imem_we0 := ibw0;
imem_we1 := ibw1;
462,11 → 468,11
MEM_DIN <= imem_din;
IB_SRES.dout <= idout;
IB_SRES.ack <= ibsel;
IB_SRES.busy <= ibbusy;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
 
RRI_LAM <= ilam;
EI_REQ <= iei_req;
RB_LAM <= ilam;
EI_REQ <= iei_req;
end process proc_next;
 
/trunk/rtl/ibus/ib_sel.vbom
0,0 → 1,6
# libs
../vlib/slvtypes.vhd
iblib.vhd
# components
# design
ib_sel.vhd
/trunk/rtl/ibus/iblib.vhd
1,4 → 1,4
-- $Id: iblib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: iblib.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,9 → 16,11
-- Description: Definitions for ibus interface and bus entities
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon
-- 2010-10-17 333 2.0 ibus V2 interface: use aval,re,we,rmw
-- 2010-06-11 303 1.1 added racc,cacc signals to ib_mreq_type
-- 2009-06-01 221 1.0.1 added dip signal to ib_mreq_type
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
33,11 → 35,12
package iblib is
 
type ib_mreq_type is record -- ibus - master request
req : slbit; -- request
aval : slbit; -- address valid
re : slbit; -- read enable
we : slbit; -- write enable
rmw : slbit; -- read-modify-write
be0 : slbit; -- byte enable low
be1 : slbit; -- byte enable high
dip : slbit; -- data in pause: rmw cycle 1st part
cacc : slbit; -- console access
racc : slbit; -- remote access
addr : slv13_1; -- address bit(12:1)
45,8 → 48,8
end record ib_mreq_type;
 
constant ib_mreq_init : ib_mreq_type :=
('0','0','0','0', -- req, we, be0, be1,
'0','0','0', -- dip, cacc, racc
('0','0','0','0', -- aval, re, we, rmw
'0','0','0','0', -- be0, be1, cacc, racc
(others=>'0'), -- addr
(others=>'0')); -- din
 
65,6 → 68,17
subtype ibf_byte1 is integer range 15 downto 8;
subtype ibf_byte0 is integer range 7 downto 0;
 
component ib_sel is -- ibus address select logic
generic (
IB_ADDR : slv16; -- ibus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
IB_MREQ : in ib_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end component;
 
component ib_sres_or_2 is -- ibus result or, 2 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
99,6 → 113,15
);
end component;
 
component ib_sres_or_mon is -- ibus result or monitor
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_3 : in ib_sres_type := ib_sres_init; -- ib_sres input 3
IB_SRES_4 : in ib_sres_type := ib_sres_init -- ib_sres input 4
);
end component;
 
type intmap_type is record -- interrupt map entry type
vec : integer; -- vector address
pri : integer; -- priority
/trunk/rtl/ibus/ib_sres_or_mon.vbom
0,0 → 1,5
# libs
../vlib/slvtypes.vhd
iblib.vhd
# design
ib_sres_or_mon.vhd
/trunk/rtl/ibus/ibdlib.vhd
1,4 → 1,4
-- $Id: ibdlib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibdlib.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,9 → 16,10
-- Description: Definitions for ibus devices
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys
-- 2009-06-07 224 1.0.4 add iist_mreq and iist_sreq;
120,7 → 121,7
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
134,7 → 135,7
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
147,7 → 148,7
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
162,7 → 163,7
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
180,7 → 181,7
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
196,7 → 197,7
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
212,7 → 213,7
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
238,7 → 239,7
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slv16_1; -- remote attention vector
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
255,7 → 256,7
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slv16_1; -- remote attention vector
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
/trunk/rtl/ibus/ibd_iist.vhd
1,6 → 1,6
-- $Id: ibd_iist.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibd_iist.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2009- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,15 → 18,18
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 112 510 0 291 s 15.8
-- 2010-10-17 314 12.1 M53 xc3s1000-4 111 504 0 290 s 15.6
-- 2009-06-01 223 10.1.03 K39 xc3s1000-4 111 439 0 256 s 9.8
-- 2009-06-01 221 10.1.03 K39 xc3s1000-4 111 449 0 258 s 13.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-17 333 0.8 use ibus V2 interface
-- 2009-06-07 224 0.7 send inverted stc_stp; remove pgc_err; honor msk_im
-- also for dcf_dcf and exc_rte; add iist_mreq and
-- iist_sreq, boot and lock interfaces
142,6 → 145,7
);
 
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
acr_ac : slv4; -- acr: ac
pge_pbe : slv4; -- pge: pg boot ena
pge_pie : slv4; -- pge: pg int ena
185,6 → 189,7
end record regs_type;
 
constant regs_init : regs_type := (
'0', -- ibsel
"0000", -- acr_ac
"0000","0000", -- pge_pbe, pge_pie
'0', -- pgc_grj
227,7 → 232,7
R_REGS.stf_sbf <= N_REGS.stf_sbf; -- don't reset st boot flags
R_REGS.tcnt256 <= N_REGS.tcnt256; -- don't reset st clock divider
end if;
else
else
R_REGS <= N_REGS;
end if;
end if;
238,9 → 243,9
IIST_SRES)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel : slbit := '0';
variable ibbusy : slbit := '0';
variable ibhold : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
258,10 → 263,10
r := R_REGS;
n := R_REGS;
 
ibsel := '0';
ibbusy := '0';
ibhold := '0';
idout := (others=>'0');
ibrd := not IB_MREQ.we;
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
 
300,9 → 305,10
iout := iist_line_init; -- default state of out line
-- ibus address decoder
if IB_MREQ.req='1' and
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 2)=ibaddr_iist(12 downto 2) then
ibsel := '1';
n.ibsel := '1';
end if;
 
-- internal state machine
316,8 → 322,7
end if;
when s_clear => -- handle acr clr
ibbusy := ibsel; -- keep req pending if selected
ibsel := '0'; -- but don't process selection
ibhold := r.ibsel; -- keep req pending if selected
-- r.req_clear is set when in this state and cause a reset in prog_regs
-- --> n.req_clear := '0';
-- --> n.state := s_idle;
355,7 → 360,7
end if;
-- ibus transactions
if ibsel = '1' then
if r.ibsel = '1' and ibhold='0' then
 
if IB_MREQ.addr(1 downto 1) = "0" then -- ACR -- access control reg -----
 
553,7 → 558,7
end case;
 
if unsigned(r.acr_ac) <= unsigned(ac_exc) then -- if ac 0,..,10
if IB_MREQ.dip = '0' then -- if not 1st part of rmw
if IB_MREQ.rmw = '0' then -- if not 1st part of rmw
n.acr_ac := unsigned(r.acr_ac) + 1; -- autoincrement
end if;
end if;
658,8 → 663,8
N_REGS <= n;
 
IB_SRES.dout <= idout;
IB_SRES.ack <= ibsel;
IB_SRES.busy <= ibbusy;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= ibhold and ibreq;
 
EI_REQ <= r.pgc_ie and int_or;
 
/trunk/rtl/ibus/ib_sres_or_2.vbom
1,5 → 1,7
# libs
../vlib/slvtypes.vhd
iblib.vhd
# components
[ghdl,isim]ib_sres_or_mon.vbom
# design
ib_sres_or_2.vhd
/trunk/rtl/ibus/ib_sres_or_4.vbom
1,5 → 1,7
# libs
../vlib/slvtypes.vhd
iblib.vhd
# components
[ghdl,isim]ib_sres_or_mon.vbom
# design
ib_sres_or_4.vhd
/trunk/rtl/ibus/ibdr_minisys.vhd
1,4 → 1,4
-- $Id: ibdr_minisys.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibdr_minisys.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
23,9 → 23,16
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 128 469 16 265 s 7.8
-- 2010-10-17 314 12.1 M53 xc3s1000-4 122 472 16 269 s 7.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.7 reorder ports, add CE_USEC; add RESET and CE_USEC
-- to _dl11
65,7 → 72,7
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slv16_1; -- remote attention vector
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
96,8 → 103,8
intmap_init -- line 0
);
 
signal RRI_LAM_DL11 : slbit := '0';
signal RRI_LAM_RK11 : slbit := '0';
signal RB_LAM_DL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
 
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11L : ib_sres_type := ib_sres_init;
146,7 → 153,7
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RRI_LAM => RRI_LAM_DL11,
RB_LAM => RB_LAM_DL11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11,
EI_REQ_RX => EI_REQ_DL11RX,
160,7 → 167,7
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RRI_LAM => RRI_LAM_RK11,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
197,10 → 204,10
EI_ACK_DL11RX <= EI_ACK(2);
EI_ACK_DL11TX <= EI_ACK(1);
 
RRI_LAM(1) <= RRI_LAM_DL11;
RRI_LAM(2) <= '0'; -- for 2nd DL11
RRI_LAM(3) <= '0'; -- for DZ11
RRI_LAM(4) <= RRI_LAM_RK11;
RRI_LAM(15 downto 5) <= (others=>'0');
RB_LAM(1) <= RB_LAM_DL11;
RB_LAM(2) <= '0'; -- for 2nd DL11
RB_LAM(3) <= '0'; -- for DZ11
RB_LAM(4) <= RB_LAM_RK11;
RB_LAM(15 downto 5) <= (others=>'0');
end syn;
/trunk/rtl/ibus/ibdr_maxisys.vhd
1,4 → 1,4
-- $Id: ibdr_maxisys.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibdr_maxisys.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
27,9 → 27,16
-- ib_intmap
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 312 1058 16 617 s 10.3
-- 2010-10-17 314 12.1 M53 xc3s1000-4 300 1094 16 626 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.4 reorder ports; add RESET, CE_USEC to _dl11
-- 2009-06-20 227 1.0.3 rename generate labels.
79,7 → 86,7
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RRI_LAM : out slv16_1; -- remote attention vector
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
110,16 → 117,16
intmap_init -- line 0
);
 
signal RRI_LAM_DENUA : slbit := '0';
signal RRI_LAM_RP06 : slbit := '0';
signal RRI_LAM_RL11 : slbit := '0';
signal RRI_LAM_RK11 : slbit := '0';
signal RRI_LAM_TM11 : slbit := '0';
signal RRI_LAM_DZ11 : slbit := '0';
signal RRI_LAM_DL11_0 : slbit := '0';
signal RRI_LAM_DL11_1 : slbit := '0';
signal RRI_LAM_PC11 : slbit := '0';
signal RRI_LAM_LP11 : slbit := '0';
signal RB_LAM_DENUA : slbit := '0';
signal RB_LAM_RP06 : slbit := '0';
signal RB_LAM_RL11 : slbit := '0';
signal RB_LAM_RK11 : slbit := '0';
signal RB_LAM_TM11 : slbit := '0';
signal RB_LAM_DZ11 : slbit := '0';
signal RB_LAM_DL11_0 : slbit := '0';
signal RB_LAM_DL11_1 : slbit := '0';
signal RB_LAM_PC11 : slbit := '0';
signal RB_LAM_LP11 : slbit := '0';
 
signal IB_SRES_IIST : ib_sres_type := ib_sres_init;
signal IB_SRES_KW11P : ib_sres_type := ib_sres_init;
231,7 → 238,7
CLK => CLK,
CE_MSEC => CE_MSEC,
BRESET => BRESET,
RRI_LAM => RRI_LAM_RK11,
RB_LAM => RB_LAM_RK11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_RK11,
EI_REQ => EI_REQ_RK11,
245,7 → 252,7
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RRI_LAM => RRI_LAM_DL11_0,
RB_LAM => RB_LAM_DL11_0,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_0,
EI_REQ_RX => EI_REQ_DL11RX_0,
264,7 → 271,7
CE_USEC => CE_USEC,
RESET => RESET,
BRESET => BRESET,
RRI_LAM => RRI_LAM_DL11_1,
RB_LAM => RB_LAM_DL11_1,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_DL11_1,
EI_REQ_RX => EI_REQ_DL11RX_1,
281,7 → 288,7
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RRI_LAM => RRI_LAM_PC11,
RB_LAM => RB_LAM_PC11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_PC11,
EI_REQ_PTR => EI_REQ_PC11PTR,
298,7 → 305,7
CLK => CLK,
RESET => RESET,
BRESET => BRESET,
RRI_LAM => RRI_LAM_LP11,
RB_LAM => RB_LAM_LP11,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_LP11,
EI_REQ => EI_REQ_LP11,
399,16 → 406,16
EI_ACK_PC11PTP <= EI_ACK( 2);
EI_ACK_LP11 <= EI_ACK( 1);
 
RRI_LAM(15 downto 11) <= (others=>'0');
RRI_LAM(10) <= RRI_LAM_PC11;
RRI_LAM( 9) <= RRI_LAM_DENUA;
RRI_LAM( 8) <= RRI_LAM_LP11;
RRI_LAM( 7) <= RRI_LAM_TM11;
RRI_LAM( 6) <= RRI_LAM_RP06;
RRI_LAM( 5) <= RRI_LAM_RL11;
RRI_LAM( 4) <= RRI_LAM_RK11;
RRI_LAM( 3) <= RRI_LAM_DZ11;
RRI_LAM( 2) <= RRI_LAM_DL11_1;
RRI_LAM( 1) <= RRI_LAM_DL11_0;
RB_LAM(15 downto 11) <= (others=>'0');
RB_LAM(10) <= RB_LAM_PC11;
RB_LAM( 9) <= RB_LAM_DENUA;
RB_LAM( 8) <= RB_LAM_LP11;
RB_LAM( 7) <= RB_LAM_TM11;
RB_LAM( 6) <= RB_LAM_RP06;
RB_LAM( 5) <= RB_LAM_RL11;
RB_LAM( 4) <= RB_LAM_RK11;
RB_LAM( 3) <= RB_LAM_DZ11;
RB_LAM( 2) <= RB_LAM_DL11_1;
RB_LAM( 1) <= RB_LAM_DL11_0;
end syn;
/trunk/rtl/ibus/ibdr_sdreg.vhd
1,4 → 1,4
-- $Id: ibdr_sdreg.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: ibdr_sdreg.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,14 → 18,16
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53 xc3s1000-4 34 40 0 30 s 4.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 32 39 0 29 s 2.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2008-08-22 161 1.0.4 use iblib
-- 2008-04-18 136 1.0.3 use RESET. Switch/Display not cleared by console
60,13 → 62,15
constant ibaddr_sdreg : slv16 := conv_std_logic_vector(8#177570#,16);
 
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
sreg : slv16; -- switch register
dreg : slv16; -- display register
end record regs_type;
 
constant regs_init : regs_type := (
(others=>'0'),
(others=>'0')
'0', -- ibsel
(others=>'0'), -- sreg
(others=>'0') -- dreg
);
 
signal R_REGS : regs_type := regs_init;
79,7 → 83,7
if CLK'event and CLK='1' then
if RESET = '1' then
R_REGS <= regs_init;
else
else
R_REGS <= N_REGS;
end if;
end if;
88,23 → 92,25
proc_next : process (R_REGS, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
begin
 
r := R_REGS;
n := R_REGS;
 
ibsel := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
 
-- ibus address decoder
if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_sdreg(12 downto 1) then
ibsel := '1';
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr=ibaddr_sdreg(12 downto 1) then
n.ibsel := '1';
end if;
 
-- ibus output driver
if ibsel = '1' then
if r.ibsel = '1' then
if IB_MREQ.racc = '0' then
idout := r.sreg; -- cpu will read switch register
else
113,7 → 119,7
end if;
 
-- ibus write transactions
if ibsel='1' and IB_MREQ.we='1' then
if r.ibsel='1' and IB_MREQ.we='1' then
if IB_MREQ.racc = '0' then -- cpu will write display register
if IB_MREQ.be1 = '1' then
n.dreg(ibf_byte1) := IB_MREQ.din(ibf_byte1);
129,7 → 135,7
N_REGS <= n;
 
IB_SRES.dout <= idout;
IB_SRES.ack <= ibsel;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
DISPREG <= r.dreg;
/trunk/rtl/ibus/ib_sres_or_3.vbom
1,5 → 1,7
# libs
../vlib/slvtypes.vhd
iblib.vhd
# components
[ghdl,isim]ib_sres_or_mon.vbom
# design
ib_sres_or_3.vhd
/trunk/rtl/ibus/ib_sel.vhd
0,0 → 1,69
-- $Id: ib_sel.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sel - syn
-- Description: ibus: address select logic
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.0 Initial version (derived from rritb_sres_or_mon)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
use work.iblib.all;
 
-- ----------------------------------------------------------------------------
 
entity ib_sel is -- ibus address select logic
generic (
IB_ADDR : slv16; -- ibus address base
SAWIDTH : natural := 0); -- device subaddress space width
port (
CLK : in slbit; -- clock
IB_MREQ : in ib_mreq_type; -- ibus request
SEL : out slbit -- select state bit
);
end ib_sel;
 
architecture syn of ib_sel is
signal R_SEL : slbit := '0';
begin
 
assert SAWIDTH<=10 -- at most 1k words devices
report "assert(SAWIDTH<=10)" severity failure;
proc_regs: process (CLK)
variable isel : slbit := '0';
begin
if CLK'event and CLK='1' then
isel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto SAWIDTH+1)=IB_ADDR(12 downto SAWIDTH+1) then
isel := '1';
end if;
R_SEL <= isel;
end if;
end process proc_regs;
 
SEL <= R_SEL;
end syn;
/trunk/rtl/sys_gen/w11a/tb/dorri
1,5 → 1,5
#!/usr/bin/perl -w
# $Id: dorri 311 2010-06-30 17:52:37Z mueller $
# $Id: dorri 296 2010-05-29 21:45:09Z mueller $
#
# Revision History:
# Date Rev Version Comment
/trunk/rtl/sys_gen/w11a/nexys2/sys_conf.vhd
1,4 → 1,4
-- $Id: sys_conf.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: sys_conf.vhd 341 2010-11-27 23:05:43Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-05 295 1.0 Initial version (derived from _s3 version)
------------------------------------------------------------------------------
 
27,10 → 28,24
 
use work.slvtypes.all;
 
-- valid system clock / delay combinations:
-- div mul clksys read0 read1 write
-- 1 1 50.0 2 2 3
-- 25 27 54.0 3 3 3
-- 25 29 58.0 3 3 4
 
package sys_conf is
 
constant sys_conf_clkfx_divide : positive := 25;
constant sys_conf_clkfx_multiply : positive := 29; -- ==> 58 MHz
 
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
 
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
 
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_ser2rri_cdinit : integer := 434-1; -- 50000000/115200
 
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
43,6 → 58,15
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
 
-- derived constants
 
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
 
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.ucf_cpp
1,14 → 1,15
## $Id: sys_w11a_n2.ucf_cpp 311 2010-06-30 17:52:37Z mueller $
## $Id: sys_w11a_n2.ucf_cpp 336 2010-11-06 18:28:27Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
## 2010-05-26 295 1.0 Initial version
##
 
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "CLK";
OFFSET = OUT 20 ns AFTER "CLK";
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
 
## std board
##
/trunk/rtl/sys_gen/w11a/nexys2/tb/tbw.dat
1,4 → 1,4
# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tbw.dat 295 2010-05-29 16:58:01Z mueller $
#
[tb_w11a_n2]
tb_rriext_fifo_rx = <fifo>
/trunk/rtl/sys_gen/w11a/nexys2/tb/sys_conf_sim.vhd
1,4 → 1,4
-- $Id: sys_conf_sim.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: sys_conf_sim.vhd 341 2010-11-27 23:05:43Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Tool versions: xst 11.4; ghdl 0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-28 295 1.0 Initial version (cloned from _s3)
------------------------------------------------------------------------------
 
29,9 → 30,17
 
package sys_conf is
 
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_clkfx_divide : positive := 25;
constant sys_conf_clkfx_multiply : positive := 29; -- ==> 58 MHz
 
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
 
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
43,6 → 52,12
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
 
-- derived constants
 
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
 
end package sys_conf;
 
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
1,4 → 1,4
-- $Id: sys_w11a_n2.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: sys_w11a_n2.vhd 341 2010-11-27 23:05:43Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,7 → 15,8
-- Module Name: sys_w11a_n2 - syn
-- Description: w11a test design for nexys2
--
-- Dependencies: vlib/genlib/clkdivce
-- Dependencies: vlib/xlib/dcm_sp_sfs
-- vlib/genlib/clkdivce
-- bplib/s3board/s3_rs232_iob_int_ext
-- bplib/s3board/s3_humanio_rri
-- vlib/rri/rri_core_serport
35,11 → 36,15
-- Test bench: tb/tb_s3board_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26 - 0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+I
-- 2010-11-06 336 12.1 M53d xc3s1200e-4 1357 4304* 242 2618 ok: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1200e-4 1357 4546 242 2618 ok: LP+PC+DL+II
-- 2010-10-17 333 12.1 M53d xc3s1200e-4 1350 4541 242 2617 ok: LP+PC+DL+II
-- 2010-10-16 332 12.1 M53d xc3s1200e-4 1338 4545 242 2629 ok: LP+PC+DL+II
-- 2010-06-27 310 12.1 M53d xc3s1200e-4 1337 4307 242 2630 ok: LP+PC+DL+II
-- 2010-06-26 309 11.4 L68 xc3s1200e-4 1318 4293 242 2612 ok: LP+PC+DL+II
-- 2010-06-18 306 12.1 M53d xc3s1200e-4 1319 4300 242 2624 ok: LP+PC+DL+II
-- " 306 11.4 L68 xc3s1200e-4 1319 4286 242 2618 ok: LP+PC+DL+II
52,9 → 57,14
-- 2010-06-03 300 11.4 L68 xc3s1200e-4 1318 4181 242 2572 ok: LP+PC+DL+II
-- 2010-06-03 299 11.4 L68 xc3s1200e-4 1250 4071 224 2489 ok: LP+PC+DL+II
-- 2010-05-26 296 11.4 L68 xc3s1200e-4 1284 4079 224 2492 ok: LP+PC+DL+II
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-27 341 1.1.8 add DCM; new sys_conf consts for mem and clkdiv
-- 2010-11-13 338 1.1.7 add O_CLKSYS (for DCM derived system clock)
-- 2010-11-06 336 1.1.6 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.1.5 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.1.4 use constants for rbus addresses (rbaddr_...)
-- BUGFIX: resolve rbus address clash hio<->ibr
-- 2010-06-18 306 1.1.3 change proc_led sensitivity list to avoid xst warn;
100,6 → 110,7
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.rrilib.all;
use work.s3boardlib.all;
114,7 → 125,8
entity sys_w11a_n2 is -- top level
-- implements nexys2_fusp_aif
port (
CLK : in slbit; -- clock
I_CLK50 : in slbit; -- 50 MHz clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
142,6 → 154,8
 
architecture syn of sys_w11a_n2 is
 
signal CLK : slbit := '0';
 
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
218,10 → 232,27
 
begin
 
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sp_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 20.0)
port map (
CLKIN => I_CLK50,
CLKFX => CLK,
LOCKED => open
);
 
O_CLKSYS <= CLK;
 
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
USECDIV => 50,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
307,7 → 338,7
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RRI_LAM => RB_LAM(0),
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
420,9 → 451,9
 
SRAM_CTL: n2_cram_memctl_as
generic map (
READ0DELAY => 2,
READ1DELAY => 2,
WRITEDELAY => 3)
READ0DELAY => sys_conf_memctl_read0delay,
READ1DELAY => sys_conf_memctl_read1delay,
WRITEDELAY => sys_conf_memctl_writedelay)
port map (
CLK => CLK,
RESET => CPU_RESET,
468,7 → 499,7
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RRI_LAM => RB_LAM(15 downto 1),
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
487,7 → 518,7
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RRI_LAM => RB_LAM(15 downto 1),
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
548,6 → 579,6
DM_STAT_CO => DM_STAT_CO,
DM_STAT_SY => DM_STAT_SY
);
 
-- synthesis translate_on
end syn;
/trunk/rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vbom
1,5 → 1,6
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/rri/rrilib.vhd
../../../bplib/s3board/s3boardlib.vbom
9,6 → 10,8
../../../w11a/pdp11.vhd
sys_conf = sys_conf.vhd
# components
[xst,isim]../../../vlib/xlib/dcm_sp_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/dcm_sp_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/s3board/s3_rs232_iob_int_ext.vbom
../../../bplib/s3board/s3_humanio_rri.vbom
/trunk/rtl/sys_gen/w11a/nexys2/balanced.opt
0,0 → 1,96
FLOWTYPE = FPGA;
###############################################################
## Filename: balanced.opt
##
## Option File For Xilinx FPGA Implementation Flow
##
## Version: 8.1.1
## $Header: /devl/xcs/repo/env/Jobs/Xflow/data/optionfiles/virtex_fpga_balanced.opt,v 1.14 2004/10/01 22:29:20 rvklair Exp $
###############################################################
#
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
#-bm <design>.bmm # Block RAM memory map file
<userdesign>; # User design - pick from xflow command line
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
 
#
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
# -fp <design>.mfp; # Floorplan file
# -gm incremental; # Guide mode
# -timing; # Perform Timing-Driven Packing and Placement
# -ol med; # Map Effort Levels. -ol [std|med|high]
# Note: If -timing is not specified, -ol switch is ignored.
# Device families supported: Virtex2, Virtex2P
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
 
#
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-xml <design>_map.twx; # Output XML version of the timing report
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
#-o <design>_map.twr; # Output trace report file
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
#-fastpaths; # Report minimum paths in verbose mode
#-nodatasheet; # Do not create the datasheet section of the report
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
 
#
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
-xe n; # extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
# -gm incremental; # Guide mode
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
 
#
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
#-o <design>.twr; # Output trace report file
#-tsi <design>.tsi; # Produce Timing Specification Interaction report
#-fastpaths; # Report minimum paths in verbose mode
#-nodatasheet; # Do not create the datasheet section of the report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce
 
 
/trunk/rtl/sys_gen/w11a/s3board/tb/tbw.dat
1,4 → 1,4
# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tbw.dat 295 2010-05-29 16:58:01Z mueller $
#
[tb_w11a_s3]
tb_rriext_fifo_rx = <fifo>
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.ucf_cpp
1,16 → 1,17
## $Id: sys_w11a_s3.ucf_cpp 311 2010-06-30 17:52:37Z mueller $
## $Id: sys_w11a_s3.ucf_cpp 336 2010-11-06 18:28:27Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2010-11-06 336 2.0.1 rename input pin CLK -> I_CLK50
## 2010-05-02 287 2.0 added defs for pm1 rs232
## 2007-12-16 101 1.1 converted to ucf_cpp, factor out std pins
## 2007-12-09 100 1.0 Initial version
##
 
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "CLK";
OFFSET = OUT 20 ns AFTER "CLK";
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
 
## std board
##
/trunk/rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
1,4 → 1,4
-- $Id: sys_w11a_s3.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: sys_w11a_s3.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
35,10 → 35,12
-- Test bench: tb/tb_s3board_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 10.1, 11.4, 12.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-11-06 336 12.1 M53d xc3s1000-4 1284 4253* 242 2575 OK: LP+PC+DL+II
-- 2010-10-24 335 12.1 M53d xc3s1000-4 1284 4495 242 2575 OK: LP+PC+DL+II
-- 2010-05-01 285 11.4 L68 xc3s1000-4 1239 4086 224 2471 OK: LP+PC+DL+II
-- 2010-04-26 283 11.4 L68 xc3s1000-4 1245 4083 224 2474 OK: LP+PC+DL+II
-- 2009-07-12 233 11.2 L46 xc3s1000-4 1245 4078 224 2472 OK: LP+PC+DL+II
64,9 → 66,12
-- 2008-01-06 111 8.2.03 I34 xc3s1000-4 971 2898 182 1831 m+p; TIME OK
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2719 137 1515 s 18.8
-- 2007-12-30 107 8.2.03 I34 xc3s1000-4 891 2661 137 1654 m+p; TIME OK
-- Note: till 2010-10-24 lutm included 'route-thru', after only logic
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.3.7 rename input pin CLK -> I_CLK50
-- 2010-10-23 335 1.3.3 rename RRI_LAM->RB_LAM;
-- 2010-06-26 309 1.3.2 use constants for rbus addresses (rbaddr_...)
-- 2010-06-18 306 1.3.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- remove pdp11_ibdr_rri
136,7 → 141,7
entity sys_w11a_s3 is -- top level
-- implements s3board_fusp_aif
port (
CLK : in slbit; -- clock
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
159,6 → 164,8
 
architecture syn of sys_w11a_s3 is
 
signal CLK : slbit := '0';
 
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
230,6 → 237,8
 
begin
 
CLK <= I_CLK50; -- use 50MHz as system clock
 
CLKDIV : clkdivce
generic map (
CDUWIDTH => 6,
315,7 → 324,7
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RRI_LAM => RB_LAM(0),
RB_LAM => RB_LAM(0),
CPU_RESET => CPU_RESET,
CP_CNTL => CP_CNTL,
CP_ADDR => CP_ADDR,
459,7 → 468,7
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RRI_LAM => RB_LAM(15 downto 1),
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
477,7 → 486,7
CE_MSEC => CE_MSEC,
RESET => CPU_RESET,
BRESET => BRESET,
RRI_LAM => RB_LAM(15 downto 1),
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
/trunk/rtl/bplib/nexys2/nexys2lib.vhd
1,4 → 1,4
-- $Id: nexys2lib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: nexys2lib.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,9 → 16,12
-- Description: Nexys 2 components
--
-- Dependencies: -
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
-- 2010-05-23 294 1.0.2 add n2_cram_dummy;
-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl
34,7 → 37,8
 
component nexys2_aif is -- NEXYS 2, abstract iface, base
port (
CLK : in slbit; -- clock
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
58,7 → 62,8
 
component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
port (
CLK : in slbit; -- clock
I_CLK50 : in slbit; -- 50 MHz board clock
O_CLKSYS : out slbit; -- DCM derived system clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
/trunk/rtl/bplib/nexys2/n2_cram_memctl_as.vhd
1,4 → 1,4
-- $Id: n2_cram_memctl_as.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: n2_cram_memctl_as.vhd 340 2010-11-27 13:00:57Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
31,6 → 31,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
-- cycle;
-- 2010-05-30 297 1.0.2 use READ(0|1)DELAY generic
54,6 → 55,23
-- some dekal. FPGA_OE goes 0->1 in the next cycle at s_wrinit->s_wrwait0.
-- Again no clash due to the 1 cycle delay.
--
-- Nominal timings:
-- READ0/1 = N_rd_cycle - 2
-- WRITE = N_wr_cycle - 1
--
-- from notes_nexys2.txt (Rev 339):
-- clksys RD WR < use for > Test case
-- MHz div mul
-- <51.20 2 3 <-- 50 50 1 1
-- 51.20- 54.80 3 3 <-- 52,54 54 25 27
-- 54.80- 64.10 3 4 <-- 55,56,58,60,62,64 64 25 32
-- 64.10- 68.50 4 4 <-- 65 65 10 13
-- 68.50- 76.92 4 5 <-- 70,75 75 2 3
-- 76.92- 82.19 5 5 <-- 80 80 5 8
-- 82.19- 89.74 5 6 <-- 85 85 10 17
-- 89.74- 95.89 6 6 <-- 90,95 95 10 19
-- 95.89-102.56 6 7 <-- 100 100 1 2
--
-- Timing of some signals:
--
-- single read request:
154,7 → 172,7
ackr : slbit; -- signal ack_r
addr0 : slbit; -- current addr0
be2nd : slv2; -- be's of 2nd write cycle
cntdly : slv2; -- wait delay counter
cntdly : slv3; -- wait delay counter
cntce : slv7; -- ce counter
fidle : slbit; -- force idle flag
memdo0 : slv16; -- mem data out, low word
197,6 → 215,12
 
begin
 
assert READ0DELAY<=2**R_REGS.cntdly'length and
READ1DELAY<=2**R_REGS.cntdly'length and
WRITEDELAY<=2**R_REGS.cntdly'length
report "assert(READ0,READ1,WRITEDELAY <= 2**cntdly'length)"
severity failure;
 
CLK_180 <= not CLK;
IOB_MEM_CE : iob_reg_o
/trunk/rtl/bplib/nexys2/tb/tbw.dat
1,4 → 1,4
# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tbw.dat 297 2010-05-30 20:10:16Z mueller $
#
[tb_n2_cram_memctl_as]
tb_n2_cram_memctl_stim = tb_n2_cram_memctl_stim.dat
/trunk/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
1,4 → 1,4
-- $Id: tb_nexys2_fusp.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tb_nexys2_fusp.vhd 339 2010-11-22 21:20:51Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,7 → 15,7
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: vlib/rri/tb/rritb_core
-- Dependencies: vlib/rri/tb/rritb_core_dcm
-- tb_nexys2_core
-- vlib/serport/serport_uart_rxtx
-- nexys2_fusp_aif [UUT]
23,9 → 23,12
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
------------------------------------------------------------------------------
 
48,7 → 51,8
 
architecture sim of tb_nexys2_fusp is
signal CLK : slbit := '0';
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
 
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
97,21 → 101,22
 
constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
 
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant clockosc_period : time := 20 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
constant c2out_time : time := 9 ns;
 
begin
TBCORE : rritb_core
TBCORE : rritb_core_dcm
generic map (
CLK_PERIOD => clock_period,
CLK_OFFSET => clock_offset,
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLK => CLK,
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
140,7 → 145,8
 
UUT : nexys2_fusp_aif
port map (
CLK => CLK,
I_CLK50 => CLKOSC,
O_CLKSYS => CLKSYS,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
169,7 → 175,7
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
CLK => CLKSYS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
208,7 → 214,7
begin
loop
wait until CLK'event and CLK='1';
wait until CLKSYS'event and CLKSYS='1';
wait for c2out_time;
 
if RXERR = '1' then
/trunk/rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
11,7 → 11,7
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/rri/tb/rritb_core.vbom
../../../vlib/rri/tb/rritb_core_dcm.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
nexys2_fusp_aif : nexys2_fusp_dummy.vbom
/trunk/rtl/bplib/nexys2/nexys2_pins_pmb0_rs232.ucf
1,4 → 1,4
## $Id: nexys2_pins_pmb0_rs232.ucf 311 2010-06-30 17:52:37Z mueller $
## $Id: nexys2_pins_pmb0_rs232.ucf 297 2010-05-30 20:10:16Z mueller $
##
## Revision History:
## Date Rev Version Comment
/trunk/rtl/bplib/nexys2/nexys2_pins.ucf
1,4 → 1,4
## $Id: nexys2_pins.ucf 311 2010-06-30 17:52:37Z mueller $
## $Id: nexys2_pins.ucf 338 2010-11-13 22:19:25Z mueller $
##
## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
## internal RS232
7,6 → 7,8
##
## Revision History:
## Date Rev Version Comment
## 2010-11-13 338 1.0.3 add O_CLKSYS (for DCM derived system clock)
## 2010-11-06 336 1.0.2 Rename CLK -> I_CLK50
## 2010-05-23 294 1.0.1 use ADV_N rather ADV
## 2010-05-16 291 1.0 Initial version
##
13,8 → 15,12
## Note: default is DRIVE=12 | SLEW=SLOW
##
## clocks --------------------------------------------------------------------
NET "CLK" LOC = "b8" | IOSTANDARD=LVCMOS33;
NET "I_CLK50" LOC = "b8" | IOSTANDARD=LVCMOS33;
##
## system clock on FX2 connector ---------------------------------------------
## (use FX2_CLKIO pin; currently only used to make test benches happy !!)
NET "O_CLKSYS" LOC = "m9" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
##
## RS232 interface -----------------------------------------------------------
NET "I_RXD" LOC = "u6" | IOSTANDARD=LVCMOS33;
NET "O_TXD" LOC = "p9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
/trunk/rtl/bplib/s3board/s3board_pins.ucf
1,4 → 1,4
## $Id: s3board_pins.ucf 311 2010-06-30 17:52:37Z mueller $
## $Id: s3board_pins.ucf 336 2010-11-06 18:28:27Z mueller $
##
## Pin locks for S3BOARD core functionality:
## internal RS232
7,6 → 7,7
##
## Revision History:
## Date Rev Version Comment
## 2010-11-06 336 1.1.1 Rename CLK -> I_CLK50
## 2008-05-25 150 1.1 Use DRIVE=6|SLEW=SLOW|KEEPER for memory data lines
## 2008-02-17 101 1.0 Initial version
##
13,7 → 14,7
## Note: default is DRIVE=12 | SLEW=SLOW
##
## clocks --------------------------------------------------------------------
NET "CLK" LOC = "t9" | IOSTANDARD=LVCMOS33;
NET "I_CLK50" LOC = "t9" | IOSTANDARD=LVCMOS33;
##
## RS232 interface -----------------------------------------------------------
NET "I_RXD" LOC = "t13" | IOSTANDARD=LVCMOS33;
/trunk/rtl/bplib/s3board/s3board_a2_pm1_rs232.ucf
1,4 → 1,4
## $Id: s3board_a2_pm1_rs232.ucf 311 2010-06-30 17:52:37Z mueller $
## $Id: s3board_a2_pm1_rs232.ucf 295 2010-05-29 16:58:01Z mueller $
##
## Revision History:
## Date Rev Version Comment
/trunk/rtl/bplib/s3board/s3boardlib.vhd
1,4 → 1,4
-- $Id: s3boardlib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: s3boardlib.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.3.1 rename input pin CLK -> I_CLK50
-- 2010-06-03 300 1.3 add s3_humanio_rri (now needs rrilib)
-- 2010-05-21 292 1.2.2 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.2.1 rename memctl_s3sram -> s3_sram_memctl; _usp->_fusp
45,7 → 46,7
 
component s3board_aif is -- S3BOARD, abstract iface, base
port (
CLK : in slbit; -- clock
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
64,7 → 65,7
 
component s3board_fusp_aif is -- S3BOARD, abstract iface, base+fusp
port (
CLK : in slbit; -- clock
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- s3 switches
/trunk/rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
1,4 → 1,4
-- $Id: tb_s3board_fusp.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tb_s3board_fusp.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
26,6 → 26,7
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
-- 2010-05-16 291 1.0.2 rename tb_s3board_usp->tb_s3board_fusp
-- 2010-05-02 287 1.0.1 add sbaddr_portsel def, now sbus addr 8
133,7 → 134,7
 
UUT : s3board_fusp_aif
port map (
CLK => CLK,
I_CLK50 => CLK,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
/trunk/rtl/bplib/s3board/tb/tbw.dat
1,4 → 1,4
# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tbw.dat 290 2010-05-16 08:44:36Z mueller $
#
[tb_s3board_dummy]
tb_rriext_fifo_rx = <fifo>
/trunk/rtl/w11a/pdp11_abox.vbom File deleted
/trunk/rtl/w11a/pdp11_dbox.vbom File deleted
/trunk/rtl/w11a/pdp11_mbox.vbom File deleted
/trunk/rtl/w11a/pdp11_lbox.vbom File deleted
/trunk/rtl/w11a/pdp11_abox.vhd File deleted
/trunk/rtl/w11a/pdp11_dbox.vhd File deleted
/trunk/rtl/w11a/pdp11_mbox.vhd File deleted
/trunk/rtl/w11a/pdp11_lbox.vhd File deleted
/trunk/rtl/w11a/pdp11_irq.vhd
1,6 → 1,6
-- $Id: pdp11_irq.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_irq.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
15,12 → 15,15
-- Module Name: pdp11_irq - syn
-- Description: pdp11: interrupt requester
--
-- Dependencies: -
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2008-08-22 161 1.1.4 use iblib
-- 2008-04-25 138 1.1.3 use BRESET to clear pirq
-- 2008-01-06 111 1.1.2 rename signal EI_ACK->EI_ACKM (master ack)
73,29 → 76,28
begin
 
proc_ibsel: process (IB_MREQ)
variable ipirq : slbit := '0';
begin
ipirq := '0';
if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_pirq(12 downto 1) then
ipirq := '1';
end if;
IBSEL_PIRQ <= ipirq;
IB_SRES.ack <= ipirq;
IB_SRES.busy <= '0';
end process proc_ibsel;
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_pirq)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PIRQ
);
 
proc_ibdout : process (IBSEL_PIRQ, R_PIRQ, PI_PRI)
variable pirqout : slv16 := (others=>'0');
proc_ibres : process (IBSEL_PIRQ, IB_MREQ, R_PIRQ, PI_PRI)
variable idout : slv16 := (others=>'0');
begin
pirqout := (others=>'0');
idout := (others=>'0');
if IBSEL_PIRQ = '1' then
pirqout(pirq_ubf_pir) := R_PIRQ;
pirqout(pirq_ubf_pia_h) := PI_PRI;
pirqout(pirq_ubf_pia_l) := PI_PRI;
idout(pirq_ubf_pir) := R_PIRQ;
idout(pirq_ubf_pia_h) := PI_PRI;
idout(pirq_ubf_pia_l) := PI_PRI;
end if;
IB_SRES.dout <= pirqout;
end process proc_ibdout;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PIRQ and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_pirq : process (CLK)
begin
/trunk/rtl/w11a/pdp11_dpath.vhd
1,4 → 1,4
-- $Id: pdp11_dpath.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_dpath.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
17,10 → 17,10
--
-- Dependencies: pdp11_gpr
-- pdp11_psr
-- pdp11_abox
-- pdp11_dbox
-- pdp11_lbox
-- pdp11_mbox
-- pdp11_ounit
-- pdp11_aunit
-- pdp11_lunit
-- pdp11_munit
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
27,6 → 27,7
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.2.1 rename (adlm)box->(oalm)unit
-- 2010-06-13 305 1.2 rename CPDIN -> CP_DIN; add CP_DOUT out port;
-- remove CPADDR out port; drop R_CPADDR, proc_cpaddr;
-- added R_CPDOUT, proc_cpdout
92,16 → 93,16
signal DRES : slv16 := (others=>'0'); -- result bus
signal DRESE : slv16 := (others=>'0'); -- result bus extra
 
signal ABOX_DOUT : slv16 := (others=>'0'); -- result abox
signal DBOX_DOUT : slv16 := (others=>'0'); -- result dbox
signal LBOX_DOUT : slv16 := (others=>'0'); -- result lbox
signal MBOX_DOUT : slv16 := (others=>'0'); -- result mbox
signal OUNIT_DOUT : slv16 := (others=>'0'); -- result ounit
signal AUNIT_DOUT : slv16 := (others=>'0'); -- result aunit
signal LUNIT_DOUT : slv16 := (others=>'0'); -- result lunit
signal MUNIT_DOUT : slv16 := (others=>'0'); -- result munit
 
signal ABOX_NZOUT : slv2 := (others=>'0'); -- nz flags abox
signal ABOX_CCOUT : slv4 := (others=>'0'); -- cc flags abox
signal DBOX_CCOUT : slv4 := (others=>'0'); -- cc flags dbox
signal LBOX_CCOUT : slv4 := (others=>'0'); -- cc flags lbox
signal MBOX_CCOUT : slv4 := (others=>'0'); -- cc flags mbox
signal OUNIT_NZOUT : slv2 := (others=>'0'); -- nz flags ounit
signal OUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags ounit
signal AUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags aunit
signal LUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags lunit
signal MUNIT_CCOUT : slv4 := (others=>'0'); -- cc flags munit
 
subtype lal_ibf_addr is integer range 15 downto 1;
subtype lah_ibf_addr is integer range 5 downto 0;
138,82 → 139,82
IB_SRES => IB_SRES
);
ABOX : pdp11_abox port map (
OUNIT : pdp11_ounit port map (
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
PC => GPR_PC,
ASEL => CNTL.abox_asel,
AZERO => CNTL.abox_azero,
ASEL => CNTL.ounit_asel,
AZERO => CNTL.ounit_azero,
IREG8 => R_IREG(7 downto 0),
VMDOUT => VM_DOUT,
CONST => CNTL.abox_const,
BSEL => CNTL.abox_bsel,
OPSUB => CNTL.abox_opsub,
DOUT => ABOX_DOUT,
NZOUT => ABOX_NZOUT
CONST => CNTL.ounit_const,
BSEL => CNTL.ounit_bsel,
OPSUB => CNTL.ounit_opsub,
DOUT => OUNIT_DOUT,
NZOUT => OUNIT_NZOUT
);
DBOX : pdp11_dbox port map (
AUNIT : pdp11_aunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CI => CCIN(0),
SRCMOD => CNTL.dbox_srcmod,
DSTMOD => CNTL.dbox_dstmod,
CIMOD => CNTL.dbox_cimod,
CC1OP => CNTL.dbox_cc1op,
CCMODE => CNTL.dbox_ccmode,
BYTOP => CNTL.dbox_bytop,
DOUT => DBOX_DOUT,
CCOUT => DBOX_CCOUT
SRCMOD => CNTL.aunit_srcmod,
DSTMOD => CNTL.aunit_dstmod,
CIMOD => CNTL.aunit_cimod,
CC1OP => CNTL.aunit_cc1op,
CCMODE => CNTL.aunit_ccmode,
BYTOP => CNTL.aunit_bytop,
DOUT => AUNIT_DOUT,
CCOUT => AUNIT_CCOUT
);
 
LBOX : pdp11_lbox port map (
LUNIT : pdp11_lunit port map (
DSRC => R_DSRC,
DDST => R_DDST,
CCIN => CCIN,
FUNC => CNTL.lbox_func,
BYTOP => CNTL.lbox_bytop,
DOUT => LBOX_DOUT,
CCOUT => LBOX_CCOUT
FUNC => CNTL.lunit_func,
BYTOP => CNTL.lunit_bytop,
DOUT => LUNIT_DOUT,
CCOUT => LUNIT_CCOUT
);
MBOX : pdp11_mbox port map (
MUNIT : pdp11_munit port map (
CLK => CLK,
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
GPR_DSRC => GPR_DSRC,
FUNC => CNTL.mbox_func,
S_DIV => CNTL.mbox_s_div,
S_DIV_CN => CNTL.mbox_s_div_cn,
S_DIV_CR => CNTL.mbox_s_div_cr,
S_ASH => CNTL.mbox_s_ash,
S_ASH_CN => CNTL.mbox_s_ash_cn,
S_ASHC => CNTL.mbox_s_ashc,
S_ASHC_CN => CNTL.mbox_s_ashc_cn,
FUNC => CNTL.munit_func,
S_DIV => CNTL.munit_s_div,
S_DIV_CN => CNTL.munit_s_div_cn,
S_DIV_CR => CNTL.munit_s_div_cr,
S_ASH => CNTL.munit_s_ash,
S_ASH_CN => CNTL.munit_s_ash_cn,
S_ASHC => CNTL.munit_s_ashc,
S_ASHC_CN => CNTL.munit_s_ashc_cn,
SHC_TC => STAT.shc_tc,
DIV_CR => STAT.div_cr,
DIV_CQ => STAT.div_cq,
DIV_ZERO => STAT.div_zero,
DIV_OVFL => STAT.div_ovfl,
DOUT => MBOX_DOUT,
DOUT => MUNIT_DOUT,
DOUTE => DRESE,
CCOUT => MBOX_CCOUT
CCOUT => MUNIT_CCOUT
);
 
CCIN <= PSW.cc;
 
ABOX_CCOUT <= ABOX_NZOUT & "0" & CCIN(0); -- clear v, keep c
OUNIT_CCOUT <= OUNIT_NZOUT & "0" & CCIN(0); -- clear v, keep c
proc_dres_sel: process (ABOX_DOUT, DBOX_DOUT, LBOX_DOUT, MBOX_DOUT,
proc_dres_sel: process (OUNIT_DOUT, AUNIT_DOUT, LUNIT_DOUT, MUNIT_DOUT,
VM_DOUT, R_IREG, CP_DIN, CNTL)
begin
case CNTL.dres_sel is
when c_dpath_res_abox => DRES <= ABOX_DOUT;
when c_dpath_res_dbox => DRES <= DBOX_DOUT;
when c_dpath_res_lbox => DRES <= LBOX_DOUT;
when c_dpath_res_mbox => DRES <= MBOX_DOUT;
when c_dpath_res_ounit => DRES <= OUNIT_DOUT;
when c_dpath_res_aunit => DRES <= AUNIT_DOUT;
when c_dpath_res_lunit => DRES <= LUNIT_DOUT;
when c_dpath_res_munit => DRES <= MUNIT_DOUT;
when c_dpath_res_vmdout => DRES <= VM_DOUT;
when c_dpath_res_fpdout => DRES <= (others=>'0');
when c_dpath_res_ireg => DRES <= R_IREG;
222,14 → 223,14
end case;
end process proc_dres_sel;
 
proc_cres_sel: process (ABOX_CCOUT, DBOX_CCOUT, LBOX_CCOUT, MBOX_CCOUT,
proc_cres_sel: process (OUNIT_CCOUT, AUNIT_CCOUT, LUNIT_CCOUT, MUNIT_CCOUT,
CCIN, CNTL)
begin
case CNTL.cres_sel is
when c_dpath_res_abox => CCOUT <= ABOX_CCOUT;
when c_dpath_res_dbox => CCOUT <= DBOX_CCOUT;
when c_dpath_res_lbox => CCOUT <= LBOX_CCOUT;
when c_dpath_res_mbox => CCOUT <= MBOX_CCOUT;
when c_dpath_res_ounit => CCOUT <= OUNIT_CCOUT;
when c_dpath_res_aunit => CCOUT <= AUNIT_CCOUT;
when c_dpath_res_lunit => CCOUT <= LUNIT_CCOUT;
when c_dpath_res_munit => CCOUT <= MUNIT_CCOUT;
when c_dpath_res_vmdout => CCOUT <= CCIN;
when c_dpath_res_fpdout => CCOUT <= "0000";
when c_dpath_res_ireg => CCOUT <= CCIN;
/trunk/rtl/w11a/pdp11_mmu_sadr.vhd
1,6 → 1,6
-- $Id: pdp11_mmu_sadr.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_mmu_sadr.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
19,9 → 19,12
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.3.1 change proc_eaddr logic, shorten logic path
-- 2010-10-17 333 1.3 use ibus V2 interface
-- 2008-08-22 161 1.2.2 rename ubf_ -> ibf_; use iblib
-- 2008-01-05 110 1.2.1 rename _mmu_regs -> _mmu_sadr
-- rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
89,13 → 92,13
signal SDR_AIB_WE : slbit := '0'; -- ...
signal SDR_LOW_WE : slbit := '0'; -- ...
 
signal IBSEL_DR : slbit := '0';
signal IBSEL_AR : slbit := '0';
signal R_IBSEL_DR : slbit := '0'; -- DR's selected from ibus
signal R_IBSEL_AR : slbit := '0'; -- AR's selected from ibus
 
signal SAF : slv16 := (others=>'0'); -- current SAF
signal SLF : slv7 := (others=>'0'); -- current SLF
signal AIB : slv2 := "00"; -- current AIB flags
signal NEXT_AIB : slv2 := "00"; -- next AIB flags
signal N_AIB : slv2 := "00"; -- next AIB flags
signal ED_ACF : slv4 := "0000"; -- current ED & ACF
begin
141,7 → 144,7
CLK => CLK,
WE => SDR_AIB_WE,
ADDR => SADR_ADDR,
DI => NEXT_AIB,
DI => N_AIB,
DO => AIB);
SDR_LOW : ram_1swar_gen
155,54 → 158,43
DI => IB_MREQ.din(sdr_ibf_acf),
DO => ED_ACF);
 
-- determibe IBSEL's and the address for accessing the SADR's
proc_ibsel: process (IB_MREQ, MODE, ASN)
variable iaddr : slv6 := (others=>'0');
variable idr : slbit := '0';
variable iar : slbit := '0';
-- determine IBSEL's and the address for accessing the SADR's
 
proc_ibsel: process (CLK)
variable ibsel_dr : slbit := '0';
variable ibsel_ar : slbit := '0';
begin
iaddr := MODE & ASN;
idr := '0';
iar := '0';
if IB_MREQ.req = '1' then
iaddr(5) := IB_MREQ.addr(8);
iaddr(4) := not IB_MREQ.addr(6);
iaddr(3 downto 0) := IB_MREQ.addr(4 downto 1);
if IB_MREQ.addr(12 downto 6)=ibaddr_kmdar(12 downto 6) or
IB_MREQ.addr(12 downto 6)=ibaddr_smdar(12 downto 6) or
IB_MREQ.addr(12 downto 6)=ibaddr_umdar(12 downto 6) then
if IB_MREQ.addr(5) = '0' then
idr := '1';
else
iar := '1';
if CLK'event and CLK='1' then
ibsel_dr := '0';
ibsel_ar := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr(12 downto 6)=ibaddr_kmdar(12 downto 6) or
IB_MREQ.addr(12 downto 6)=ibaddr_smdar(12 downto 6) or
IB_MREQ.addr(12 downto 6)=ibaddr_umdar(12 downto 6) then
if IB_MREQ.addr(5) = '0' then
ibsel_dr := '1';
else
ibsel_ar := '1';
end if;
end if;
end if;
R_IBSEL_DR <= ibsel_dr;
R_IBSEL_AR <= ibsel_ar;
end if;
SADR_ADDR <= iaddr;
-- SADR_ADDR <= iaddr(3) & iaddr(5 downto 4) & iaddr(2 downto 0);
IBSEL_DR <= idr;
IBSEL_AR <= iar;
IB_SRES.ack <= idr or iar;
IB_SRES.busy <= '0';
end process proc_ibsel;
 
proc_ubdout : process (IBSEL_DR, IBSEL_AR, SAF, SLF, AIB, ED_ACF)
proc_ibres : process (R_IBSEL_DR, R_IBSEL_AR, IB_MREQ, SAF, SLF, AIB, ED_ACF)
variable sarout : slv16 := (others=>'0'); -- IB sar out
variable sdrout : slv16 := (others=>'0'); -- IB sdr out
begin
 
sarout := (others=>'0');
if IBSEL_AR = '1' then
if R_IBSEL_AR = '1' then
sarout := SAF;
end if;
sdrout := (others=>'0');
if IBSEL_DR = '1' then
if R_IBSEL_DR = '1' then
sdrout(sdr_ibf_slf) := SLF;
sdrout(sdr_ibf_aib) := AIB;
sdrout(sdr_ibf_acf) := ED_ACF;
209,14 → 201,43
end if;
 
IB_SRES.dout <= sarout or sdrout;
IB_SRES.ack <= (R_IBSEL_DR or R_IBSEL_AR) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
 
end process proc_ubdout;
end process proc_ibres;
 
proc_comb : process (IBSEL_AR, IBSEL_DR, IB_MREQ, AIB_WE, AIB_SETA, AIB_SETW,
-- the eaddr select should be done as early as possible, it is in the
-- mmu paadr logic path. Currently it's derived from 4 flops. If that's
-- to slow just use IB_MREQ.we or IB_MREQ.we, that should be sufficient
-- and reduce the eaddr mux to a 4-input LUT. Last resort is a 2 cycle ibus
-- access with a state flop marking the 2nd cycle of a re/we transaction.
proc_eaddr: process (IB_MREQ, MODE, ASN)
variable eaddr : slv6 := (others=>'0');
variable idr : slbit := '0';
variable iar : slbit := '0';
begin
eaddr := MODE & ASN;
if (R_IBSEL_DR='1' or R_IBSEL_AR='1') and
(IB_MREQ.re='1' or IB_MREQ.we='1') then
eaddr(5) := IB_MREQ.addr(8);
eaddr(4) := not IB_MREQ.addr(6);
eaddr(3 downto 0) := IB_MREQ.addr(4 downto 1);
end if;
SADR_ADDR <= eaddr;
 
end process proc_eaddr;
 
proc_comb : process (R_IBSEL_AR, R_IBSEL_DR, IB_MREQ, AIB_WE,
AIB_SETA, AIB_SETW,
SAF, SLF, AIB, ED_ACF)
begin
 
NEXT_AIB <= "00";
N_AIB <= "00";
SAR_HIGH_WE <= '0';
SAR_LOW_WE <= '0';
SDR_SLF_WE <= '0';
224,7 → 245,7
SDR_LOW_WE <= '0';
if IB_MREQ.we = '1' then
if IBSEL_AR = '1' then
if R_IBSEL_AR = '1' then
if IB_MREQ.be1 = '1' then
SAR_HIGH_WE <= '1';
end if;
233,7 → 254,7
end if;
end if;
 
if IBSEL_DR = '1' then
if R_IBSEL_DR = '1' then
if IB_MREQ.be1 = '1' then
SDR_SLF_WE <= '1';
end if;
242,15 → 263,15
end if;
end if;
 
if (IBSEL_AR or IBSEL_DR)='1' then
NEXT_AIB <= "00";
if (R_IBSEL_AR or R_IBSEL_DR)='1' then
N_AIB <= "00";
SDR_AIB_WE <= '1';
end if;
end if;
 
if AIB_WE = '1' then
NEXT_AIB(0) <= AIB(0) or AIB_SETW;
NEXT_AIB(1) <= AIB(1) or AIB_SETA;
N_AIB(0) <= AIB(0) or AIB_SETW;
N_AIB(1) <= AIB(1) or AIB_SETA;
SDR_AIB_WE <= '1';
end if;
 
/trunk/rtl/w11a/pdp11_vmbox.vbom
8,5 → 8,6
pdp11_ubmap.vbom
../ibus/ib_sres_or_4.vbom
../ibus/ib_sres_or_2.vbom
../ibus/ib_sel.vbom
# design
pdp11_vmbox.vhd
/trunk/rtl/w11a/pdp11_lunit.vbom
0,0 → 1,5
# libs
../vlib/slvtypes.vhd
pdp11.vbom
# design
pdp11_lunit.vhd
/trunk/rtl/w11a/tb/tbw.dat
1,4 → 1,4
# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tbw.dat 81 2007-09-09 20:50:42Z mueller $
#
[tb_rritba_pdp11core]
tb_rritba_stim = tb_rritba_pdp11core_stim.dat
/trunk/rtl/w11a/tb/tb_pdp11_core_stim.dat
1,4 → 1,4
# $Id: tb_pdp11_core_stim.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tb_pdp11_core_stim.dat 309 2010-06-26 18:49:06Z mueller $
#
# Revision History:
# Date Rev Version Comment
/trunk/rtl/w11a/tb/tbd_pdp11_core.vhd
1,4 → 1,4
-- $Id: tbd_pdp11_core.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tbd_pdp11_core.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
41,6 → 41,7
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.4.2 rename RRI_LAM->RB_LAM;
-- 2010-06-20 307 1.4.1 add CP_ADDR_racc, CP_ADDR_be port
-- 2010-06-13 305 1.4 add CP_ADDR_... in ports; add CP_CNTL_rnum in port
-- 2010-06-11 303 1.3.9 use IB_MREQ.racc instead of RRI_REQ
191,7 → 192,7
CE_MSEC => CE_USEC, -- !! in test benches msec = usec !!
RESET => RESET,
BRESET => BRESET,
RRI_LAM => open,
RB_LAM => open,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_M,
EI_ACKM => EI_ACKM,
/trunk/rtl/w11a/pdp11_aunit.vhd
0,0 → 1,244
-- $Id: pdp11_aunit.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_aunit - syn
-- Description: pdp11: arithmetic unit for data (aunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
use work.slvtypes.all;
use work.pdp11.all;
 
-- ----------------------------------------------------------------------------
 
-- arithmetic unit for data, usage:
-- ADD: SRC + DST + 0 (dst+src)
-- SUB: ~SRC + DST + 1 (dst-src)
-- ADC: 0 + DST + CI (dst+ci)
-- SBC: ~0 + DST + ~CI (dst-ci)
-- CMP: SRC + ~DST + 1 (src-dst)
-- COM: 0 + ~DST + 0 (~dst)
-- NEG: 0 + ~DST + 1 (-dst)
-- INC: 0 + DST + 1 (dst+1)
-- DEC: ~0 + DST + 0 (dst-1)
-- CLR: 0 + 0 + 0 (0)
-- SOB: SRC + ~0 + 0 (src-1)
 
entity pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_aunit;
 
architecture syn of pdp11_aunit is
 
-- --------------------------------------
 
begin
 
process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
 
variable msrc : slv16 := (others=>'0'); -- effective src data
variable mdst : slv16 := (others=>'0'); -- effective dst data
variable mci : slbit := '0'; -- effective ci
variable sum : slv16 := (others=>'0'); -- sum
variable co8 : slbit := '0'; -- co 8 bit
variable co16 : slbit := '0'; -- co 16 bit
 
variable nno : slbit := '0'; -- local no
variable nzo : slbit := '0'; -- local zo
variable nvo : slbit := '0'; -- local vo
variable nco : slbit := '0'; -- local co
 
variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
 
alias NO : slbit is CCOUT(3);
alias ZO : slbit is CCOUT(2);
alias VO : slbit is CCOUT(1);
alias CO : slbit is CCOUT(0);
-- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
-- implemented following the recommended pattern for XST ISE V8.1
procedure do_add8_ci_co (
variable a : in slv8; -- input a
variable b : in slv8; -- input b
variable ci : in slbit; -- carry in
variable sum : out slv8; -- sum out
variable co : out slbit -- carry out
) is
variable tmp: slv9;
 
begin
 
tmp := conv_std_logic_vector((conv_integer(a) + conv_integer(b) +
conv_integer(ci)),9);
sum := tmp(7 downto 0);
co := tmp(8);
end procedure do_add8_ci_co;
 
begin
 
case SRCMOD is
when c_aunit_mod_pass => msrc := DSRC;
when c_aunit_mod_inv => msrc := not DSRC;
when c_aunit_mod_zero => msrc := (others=>'0');
when c_aunit_mod_one => msrc := (others=>'1');
when others => null;
end case;
 
case DSTMOD is
when c_aunit_mod_pass => mdst := DDST;
when c_aunit_mod_inv => mdst := not DDST;
when c_aunit_mod_zero => mdst := (others=>'0');
when c_aunit_mod_one => mdst := (others=>'1');
when others => null;
end case;
 
case CIMOD is
when c_aunit_mod_pass => mci := CI;
when c_aunit_mod_inv => mci := not CI;
when c_aunit_mod_zero => mci := '0';
when c_aunit_mod_one => mci := '1';
when others => null;
end case;
 
do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
sum(7 downto 0), co8);
do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
sum(15 downto 8), co16);
 
DOUT <= sum;
 
-- V ('overflow) bit set if
-- ADD : both operants of same sign but has result opposite sign
-- SUB : both operants of opposide sign and sign source equals sign result
-- CMP : both operants of opposide sign and sign dest. equals sign result
nno := '0';
nzo := '0';
nvo := '0';
nco := '0';
 
if BYTOP = '1' then
nno := sum(7);
if unsigned(sum(7 downto 0)) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co8;
 
src_msb := DSRC(7);
dst_msb := DDST(7);
sum_msb := sum(7);
else
nno := sum(15);
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co16;
 
src_msb := DSRC(15);
dst_msb := DDST(15);
sum_msb := sum(15);
end if;
 
-- the logic for 2 operand V+C is ugly. It is reverse engineered from
-- the MOD's the operation type.
if CC1OP = '0' then -- 2 operand cases
if unsigned(CIMOD) = unsigned(c_aunit_mod_zero) then -- case ADD
nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
else
if unsigned(SRCMOD) = unsigned(c_aunit_mod_inv) then -- case SUB
nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
else -- case CMP
nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
end if;
nco := not nco; -- invert C for SUB and CMP
end if;
else -- 1 operand cases
case CCMODE is
when c_aunit_ccmode_clr|c_aunit_ccmode_tst =>
nvo := '0'; -- force v=0 for tst and clr
nco := '0'; -- force c=0 for tst and clr
when c_aunit_ccmode_com =>
nvo := '0'; -- force v=0 for com
nco := '1'; -- force c=1 for com
when c_aunit_ccmode_inc =>
nvo := sum_msb and not dst_msb;
nco := CI; -- C not affected for INC
 
when c_aunit_ccmode_dec =>
nvo := not sum_msb and dst_msb;
nco := CI; -- C not affected for DEC
 
when c_aunit_ccmode_neg =>
nvo := sum_msb and dst_msb;
nco := not nzo;
when c_aunit_ccmode_adc =>
nvo := sum_msb and not dst_msb;
 
when c_aunit_ccmode_sbc =>
nvo := not sum_msb and dst_msb;
nco := not nco;
 
when others => null;
end case;
end if;
NO <= nno;
ZO <= nzo;
VO <= nvo;
CO <= nco;
end process;
end syn;
/trunk/rtl/w11a/pdp11_dpath.vbom
5,9 → 5,9
# components
pdp11_gpr.vbom
pdp11_psr.vbom
pdp11_abox.vbom
pdp11_dbox.vbom
pdp11_lbox.vbom
pdp11_mbox.vbom
pdp11_ounit.vbom
pdp11_aunit.vbom
pdp11_lunit.vbom
pdp11_munit.vbom
# design
pdp11_dpath.vhd
/trunk/rtl/w11a/pdp11_decode.vhd
1,4 → 1,4
-- $Id: pdp11_decode.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_decode.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
21,6 → 21,7
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.0.5 rename (adlm)box->(oalm)unit
-- 2008-11-30 174 1.0.4 BUGFIX: add updt_dstadsrc; set for MFP(I/D)
-- 2008-05-03 143 1.0.3 get fork_srcr,fork_dstr,fork_dsta assign out of if
-- 2008-04-27 139 1.0.2 BUGFIX: mtp now via do_fork_op; is_dsta logic mods
103,14 → 104,14
nstat.force_srcsp := '0';
nstat.updt_dstadsrc := '0';
nstat.dbox_srcmod := c_dbox_mod_pass;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_pass;
nstat.dbox_cc1op := '0';
nstat.dbox_ccmode := IREG(8 downto 6); -- STATIC
nstat.lbox_func := (others=>'0');
nstat.mbox_func := (others=>'0');
nstat.res_sel := c_dpath_res_abox;
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
nstat.aunit_cc1op := '0';
nstat.aunit_ccmode := IREG(8 downto 6); -- STATIC
nstat.lunit_func := (others=>'0');
nstat.munit_func := (others=>'0');
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_op := (others=>'0');
nstat.fork_srcr := (others=>'0');
231,8 → 232,8
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lbox_func := c_lbox_func_swap;
nstat.res_sel := c_dpath_res_lbox;
nstat.lunit_func := c_lunit_func_swap;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if; -- OPBYTE='0' and OPEXT1="000"
265,54 → 266,54
if OPEXT1 = "101" then -- CLR(B),...,TST(B)
nstat.is_res := '0';
nstat.res_sel := c_dpath_res_dbox;
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
 
nstat.dbox_cc1op := '1';
nstat.aunit_cc1op := '1';
case OPEXT2 is
when "000" => -- CLR: 0 + 0 + 0 (0)
is_dstw := '1';
nstat.dbox_srcmod := c_dbox_mod_zero;
nstat.dbox_dstmod := c_dbox_mod_zero;
nstat.dbox_cimod := c_dbox_mod_zero;
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_zero;
nstat.aunit_cimod := c_aunit_mod_zero;
when "001" => -- COM: 0 + ~DST + 0 (~dst)
is_dstm := '1';
nstat.dbox_srcmod := c_dbox_mod_zero;
nstat.dbox_dstmod := c_dbox_mod_inv;
nstat.dbox_cimod := c_dbox_mod_zero;
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_zero;
when "010" => -- INC: 0 + DST + 1 (dst+1)
is_dstm := '1';
nstat.dbox_srcmod := c_dbox_mod_zero;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_one;
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
when "011" => -- DEC: ~0 + DST + 0 (dst-1)
is_dstm := '1';
nstat.dbox_srcmod := c_dbox_mod_one;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_zero;
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when "100" => -- NEG: 0 + ~DST + 1 (-dst)
is_dstm := '1';
nstat.dbox_srcmod := c_dbox_mod_zero;
nstat.dbox_dstmod := c_dbox_mod_inv;
nstat.dbox_cimod := c_dbox_mod_one;
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
when "101" => -- ADC: 0 + DST + CI (dst+ci)
is_dstm := '1';
nstat.dbox_srcmod := c_dbox_mod_zero;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_pass;
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_pass;
when "110" => -- SBC: ~0 + DST + ~CI (dst-ci)
is_dstm := '1';
nstat.dbox_srcmod := c_dbox_mod_one;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_inv;
nstat.aunit_srcmod := c_aunit_mod_one;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_inv;
when "111" => -- TST: 0 + DST + 0 (dst)
is_dstr := '1';
nstat.dbox_srcmod := c_dbox_mod_zero;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_zero;
nstat.aunit_srcmod := c_aunit_mod_zero;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
when others => null;
end case;
 
332,16 → 333,16
if OPBYTE = '1' then
nstat.is_bytop := '1';
end if;
nstat.res_sel := c_dpath_res_lbox;
nstat.res_sel := c_dpath_res_lunit;
case OPEXT2(1 downto 0) is
when "00" => -- ROR
nstat.lbox_func := c_lbox_func_ror;
nstat.lunit_func := c_lunit_func_ror;
when "01" => -- ROL
nstat.lbox_func := c_lbox_func_rol;
nstat.lunit_func := c_lunit_func_rol;
when "10" => -- ASR
nstat.lbox_func := c_lbox_func_asr;
nstat.lunit_func := c_lunit_func_asr;
when "11" => -- ASL
nstat.lbox_func := c_lbox_func_asl;
nstat.lunit_func := c_lunit_func_asl;
when others => null;
end case;
end if;
358,7 → 359,7
if DSTREG = c_gpr_sp then -- is dst reg == sp ?
nstat.updt_dstadsrc := '1'; -- ensure DSRC update in dsta flow
end if;
nstat.res_sel := c_dpath_res_abox;
nstat.res_sel := c_dpath_res_ounit;
if nstat.is_dstmode0 = '1' then
nstat.fork_opa := c_fork_opa_mfp_reg;
else
370,7 → 371,7
if OPEXT2 = "110" then -- MTP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
nstat.res_sel := c_dpath_res_abox;
nstat.res_sel := c_dpath_res_ounit;
nstat.fork_opa := c_fork_opa_mtp;
nstat.fork_op := c_fork_op_mtp;
nstat.do_fork_op := '1';
382,8 → 383,8
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
nstat.lbox_func := c_lbox_func_sxt;
nstat.res_sel := c_dpath_res_lbox;
nstat.lunit_func := c_lunit_func_sxt;
nstat.res_sel := c_dpath_res_lunit;
end if;
end if;
 
396,47 → 397,47
is_srcr := '1';
is_dstw := '1';
nstat.op_mov := '1';
nstat.lbox_func := c_lbox_func_mov;
nstat.res_sel := c_dpath_res_lbox;
nstat.lunit_func := c_lunit_func_mov;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "010" => -- CMP
is_srcr := '1';
is_dstr := '1';
nstat.res_sel := c_dpath_res_dbox;
nstat.dbox_srcmod := c_dbox_mod_pass;
nstat.dbox_dstmod := c_dbox_mod_inv;
nstat.dbox_cimod := c_dbox_mod_one;
nstat.res_sel := c_dpath_res_aunit;
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_inv;
nstat.aunit_cimod := c_aunit_mod_one;
nstat.is_bytop := OPBYTE;
when "011" => -- BIT
is_srcr := '1';
is_dstr := '1';
nstat.lbox_func := c_lbox_func_bit;
nstat.res_sel := c_dpath_res_lbox;
nstat.lunit_func := c_lunit_func_bit;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "100" => -- BIC
is_srcr := '1';
is_dstm := '1';
nstat.lbox_func := c_lbox_func_bic;
nstat.res_sel := c_dpath_res_lbox;
nstat.lunit_func := c_lunit_func_bic;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "101" => -- BIS
is_srcr := '1';
is_dstm := '1';
nstat.lbox_func := c_lbox_func_bis;
nstat.res_sel := c_dpath_res_lbox;
nstat.lunit_func := c_lunit_func_bis;
nstat.res_sel := c_dpath_res_lunit;
nstat.is_bytop := OPBYTE;
when "110" =>
is_srcr := '1';
is_dstm := '1';
nstat.res_sel := c_dpath_res_dbox;
nstat.res_sel := c_dpath_res_aunit;
if OPBYTE = '0' then -- ADD
nstat.dbox_srcmod := c_dbox_mod_pass;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_zero;
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_zero;
else -- SUB
nstat.dbox_srcmod := c_dbox_mod_inv;
nstat.dbox_dstmod := c_dbox_mod_pass;
nstat.dbox_cimod := c_dbox_mod_one;
nstat.aunit_srcmod := c_aunit_mod_inv;
nstat.aunit_dstmod := c_aunit_mod_pass;
nstat.aunit_cimod := c_aunit_mod_one;
end if;
when others => null;
end case;
452,45 → 453,45
when "000" => -- MUL
nstat.is_res := '0';
is_dstr := '1';
nstat.mbox_func := c_mbox_func_mul;
nstat.res_sel := c_dpath_res_mbox;
nstat.munit_func := c_munit_func_mul;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_mul;
nstat.do_fork_opg := '1';
when "001" => -- DIV
nstat.is_res := '0';
is_dstr := '1';
nstat.mbox_func := c_mbox_func_div;
nstat.res_sel := c_dpath_res_mbox;
nstat.munit_func := c_munit_func_div;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_div;
nstat.do_fork_opg := '1';
when "010" => -- ASH
nstat.is_res := '0';
is_dstr := '1';
nstat.mbox_func := c_mbox_func_ash;
nstat.res_sel := c_dpath_res_mbox;
nstat.munit_func := c_munit_func_ash;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ash;
nstat.do_fork_opg := '1';
when "011" => -- ASHC
nstat.is_res := '0';
is_dstr := '1';
nstat.mbox_func := c_mbox_func_ashc;
nstat.res_sel := c_dpath_res_mbox;
nstat.munit_func := c_munit_func_ashc;
nstat.res_sel := c_dpath_res_munit;
nstat.fork_opg := c_fork_opg_ashc;
nstat.do_fork_opg := '1';
when "100" => -- XOR
nstat.is_res := '0';
is_dstm := '1';
nstat.lbox_func := c_lbox_func_xor;
nstat.res_sel := c_dpath_res_lbox;
nstat.lunit_func := c_lunit_func_xor;
nstat.res_sel := c_dpath_res_lunit;
nstat.fork_opg := c_fork_opg_gen;
nstat.do_fork_opg := '1';
nstat.do_pref_dec := is_dstmode0notpc;
when "111" => -- SOB: SRC + ~0 + 0 (src-1)
nstat.is_res := '0';
nstat.dbox_srcmod := c_dbox_mod_pass;
nstat.dbox_dstmod := c_dbox_mod_one;
nstat.dbox_cimod := c_dbox_mod_zero;
nstat.res_sel := c_dpath_res_dbox;
nstat.aunit_srcmod := c_aunit_mod_pass;
nstat.aunit_dstmod := c_aunit_mod_one;
nstat.aunit_cimod := c_aunit_mod_zero;
nstat.res_sel := c_dpath_res_aunit;
nstat.fork_op := c_fork_op_sob;
nstat.do_fork_op := '1';
when others => null;
/trunk/rtl/w11a/pdp11_mem70.vhd
1,6 → 1,6
-- $Id: pdp11_mem70.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_mem70.vhd 333 2010-10-17 21:18:33Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,9 → 18,11
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.2 rename ubf_ -> ibf_; use iblib
-- 2008-02-23 118 1.0.1 use sys_conf_mem_losize; rename CACHE_ENA->_FMISS
-- 2008-01-27 115 1.0 Initial version
66,6 → 68,10
constant cntl_ibf_distrap : integer := 0;
 
type regs_type is record -- state registers
ibsel_cr : slbit; -- ibus select cntl
ibsel_hm : slbit; -- ibus select hitmiss
ibsel_ls : slbit; -- ibus select losize
ibsel_nn : slbit; -- ibus select others
hm_data : slv6; -- hit/miss: data
cr_frep : slv2; -- cntl: force replacement bits
cr_fmiss : slv2; -- cntl: force miss bits
74,6 → 80,7
end record regs_type;
 
constant regs_init : regs_type := (
'0','0','0','0', -- ibsel_*
(others=>'0'), -- hm_data
"00","00", -- cr_freq,_fmiss
'0','0' -- dis(u)trap
98,33 → 105,32
proc_next: process (R_REGS, HM_ENA, HM_VAL, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel_cr : slbit := '0'; -- control reg
variable ibsel_hm : slbit := '0'; -- hit/miss reg
variable ibsel_ls : slbit := '0'; -- low size reg
variable ibsel_nn : slbit := '0'; -- all other
variable ibsel : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
 
ibsel_cr := '0';
ibsel_hm := '0';
ibsel_ls := '0';
ibsel_nn := '0';
ibsel := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
 
if IB_MREQ.req = '1' then
-- ibus address decoder
n.ibsel_cr := '0';
n.ibsel_hm := '0';
n.ibsel_ls := '0';
n.ibsel_nn := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_cntl(12 downto 1) then
ibsel_cr := '1';
n.ibsel_cr := '1';
end if;
if IB_MREQ.addr = ibaddr_hm(12 downto 1) then
ibsel_hm := '1';
n.ibsel_hm := '1';
end if;
if IB_MREQ.addr = ibaddr_losize(12 downto 1) then
ibsel_ls := '1';
n.ibsel_ls := '1';
end if;
if IB_MREQ.addr=ibaddr_loaddr(12 downto 1) or
IB_MREQ.addr=ibaddr_hiaddr(12 downto 1) or
131,26 → 137,25
IB_MREQ.addr=ibaddr_syserr(12 downto 1) or
IB_MREQ.addr=ibaddr_maint(12 downto 1) or
IB_MREQ.addr=ibaddr_hisize(12 downto 1) then
ibsel_nn := '1';
n.ibsel_nn := '1';
end if;
end if;
 
ibsel := ibsel_cr or ibsel_hm or ibsel_ls or ibsel_nn;
if ibsel_cr = '1' then
-- ibus transactions
if r.ibsel_cr = '1' then
idout(cntl_ibf_frep) := r.cr_frep;
idout(cntl_ibf_fmiss) := r.cr_fmiss;
idout(cntl_ibf_disutrap) := r.cr_disutrap;
idout(cntl_ibf_distrap) := r.cr_distrap;
end if;
if ibsel_hm = '1' then
if r.ibsel_hm = '1' then
idout(r.hm_data'range) := r.hm_data;
end if;
if ibsel_ls = '1' then
if r.ibsel_ls = '1' then
idout := conv_std_logic_vector(sys_conf_mem_losize,16);
end if;
 
if ibsel_cr='1' and IB_MREQ.we='1' and IB_MREQ.be0='1' then
if r.ibsel_cr='1' and ibw0='1' then
n.cr_frep := IB_MREQ.din(cntl_ibf_frep);
n.cr_fmiss := IB_MREQ.din(cntl_ibf_fmiss);
n.cr_disutrap := IB_MREQ.din(cntl_ibf_disutrap);
163,9 → 168,10
 
N_REGS <= n;
 
IB_SRES.ack <= ibsel;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_cr or r.ibsel_hm or
r.ibsel_ls or r.ibsel_nn) and ibreq;
IB_SRES.busy <= '0';
IB_SRES.dout <= idout;
 
end process proc_next;
 
/trunk/rtl/w11a/pdp11_mmu_ssr12.vhd
1,6 → 1,6
-- $Id: pdp11_mmu_ssr12.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_mmu_ssr12.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2006-2009 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
15,13 → 15,15
-- Module Name: pdp11_mmu_ssr12 - syn
-- Description: pdp11: mmu register ssr1 and ssr2
--
-- Dependencies: -
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
66,28 → 68,29
signal IBSEL_SSR2 : slbit := '0';
signal R_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
signal R_SSR2 : slv16 := (others=>'0');
signal NEXT_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
signal NEXT_SSR2 : slv16 := (others=>'0');
signal N_SSR1 : mmu_ssr1_type := mmu_ssr1_init;
signal N_SSR2 : slv16 := (others=>'0');
 
begin
 
proc_ibsel: process (IB_MREQ)
variable issr1 : slbit := '0';
variable issr2 : slbit := '0';
begin
issr1 := '0';
issr2 := '0';
if IB_MREQ.req = '1' then
if IB_MREQ.addr = ibaddr_ssr1(12 downto 1) then issr1 := '1'; end if;
if IB_MREQ.addr = ibaddr_ssr2(12 downto 1) then issr2 := '1'; end if;
end if;
IBSEL_SSR1 <= issr1;
IBSEL_SSR2 <= issr2;
IB_SRES.ack <= issr1 or issr2;
IB_SRES.busy <= '0';
end process proc_ibsel;
SEL_SSR1 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr1)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR1
);
SEL_SSR2 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr2)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR2
);
 
proc_ubdout : process (IBSEL_SSR1, IBSEL_SSR2, R_SSR1, R_SSR2)
proc_ibres : process (IBSEL_SSR1, IBSEL_SSR2, IB_MREQ, R_SSR1, R_SSR2)
variable ssr1out : slv16 := (others=>'0');
variable ssr2out : slv16 := (others=>'0');
begin
106,14 → 109,17
end if;
IB_SRES.dout <= ssr1out or ssr2out;
IB_SRES.ack <= (IBSEL_SSR1 or IBSEL_SSR2) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
 
end process proc_ubdout;
end process proc_ibres;
 
proc_regs : process (CLK)
begin
if CLK'event and CLK='1' then
R_SSR1 <= NEXT_SSR1;
R_SSR2 <= NEXT_SSR2;
R_SSR1 <= N_SSR1;
R_SSR2 <= N_SSR2;
end if;
end process proc_regs;
 
177,8 → 183,8
 
end if;
 
NEXT_SSR1 <= nssr1;
NEXT_SSR2 <= nssr2;
N_SSR1 <= nssr1;
N_SSR2 <= nssr2;
 
end process proc_comb;
 
/trunk/rtl/w11a/pdp11_sequencer.vhd
1,4 → 1,4
-- $Id: pdp11_sequencer.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_sequencer.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
15,12 → 15,16
-- Module Name: pdp11_sequencer - syn
-- Description: pdp11: CPU sequencer
--
-- Dependencies: -
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-09-18 300 1.3.2 rename (adlm)box->(oalm)unit
-- 2010-06-20 307 1.3.1 rename cpacc to cacc in vm_cntl_type
-- 2010-06-13 305 1.3 remove CPDIN_WE, CPDOUT_WE out ports; set
-- CNTL.cpdout_we instead of CPDOUT_WE
244,32 → 248,31
 
begin
 
proc_ibsel: process (IB_MREQ)
variable icpuerr : slbit := '0';
begin
icpuerr := '0';
if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_cpuerr(12 downto 1) then
icpuerr := '1';
end if;
IBSEL_CPUERR <= icpuerr;
IB_SRES.ack <= icpuerr;
IB_SRES.busy <= '0';
end process proc_ibsel;
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_cpuerr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_CPUERR
);
 
proc_ibdout : process (IBSEL_CPUERR, R_CPUERR)
variable cpuerrout : slv16 := (others=>'0');
proc_ibres : process (IBSEL_CPUERR, IB_MREQ, R_CPUERR)
variable idout : slv16 := (others=>'0');
begin
cpuerrout := (others=>'0');
idout := (others=>'0');
if IBSEL_CPUERR = '1' then
cpuerrout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
cpuerrout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
cpuerrout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
cpuerrout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
cpuerrout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
cpuerrout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
idout(cpuerr_ibf_rsv) := R_CPUERR.rsv;
end if;
IB_SRES.dout <= cpuerrout;
end process proc_ibdout;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_CPUERR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
 
proc_status: process (CLK)
begin
373,10 → 376,10
nmmumoni : inout mmu_moni_type;
updt_sp : in slbit := '0') is
begin
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_const := "000000010"; -- ABOX const=2
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
if updt_sp = '1' then
427,9 → 430,9
begin
if bytop='0' or isdef='1' or
regnum=c_gpr_pc or regnum=c_gpr_sp then
ndpcntl.abox_const := "000000010";
ndpcntl.ounit_const := "000000010";
else
ndpcntl.abox_const := "000000001";
ndpcntl.ounit_const := "000000001";
end if;
end procedure do_const_opsize;
 
522,10 → 525,10
begin
ndpcntl.dtmp_sel := c_dpath_dtmp_psw; -- DTMP = PSW
ndpcntl.dtmp_we := '1';
ndpcntl.abox_azero := '1'; -- ABOX A = 0
ndpcntl.abox_const := vector & "00"; -- vector
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(vector)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := vector & "00"; -- vector
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- DSRC = vector
nstate := s_int_getpc;
545,7 → 548,7
nidstat := R_IDSTAT;
 
if IB_MREQ.we='1' and IBSEL_CPUERR='1' then -- write to CPUERR clears it !!
if IBSEL_CPUERR='1' and IB_MREQ.we='1' then -- write to CPUERR clears it !
ncpuerr := cpuerr_init;
end if;
 
603,28 → 606,28
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '0';
 
ndpcntl.abox_asel := c_abox_asel_ddst;
ndpcntl.abox_azero := '0'; -- DEFAULT
ndpcntl.abox_const := (others=>'0'); -- DEFAULT
ndpcntl.abox_bsel := c_abox_bsel_const;
ndpcntl.abox_opsub := '0'; -- DEFAULT
ndpcntl.ounit_asel := c_ounit_asel_ddst;
ndpcntl.ounit_azero := '0'; -- DEFAULT
ndpcntl.ounit_const := (others=>'0'); -- DEFAULT
ndpcntl.ounit_bsel := c_ounit_bsel_const;
ndpcntl.ounit_opsub := '0'; -- DEFAULT
 
ndpcntl.dbox_srcmod := R_IDSTAT.dbox_srcmod; -- STATIC
ndpcntl.dbox_dstmod := R_IDSTAT.dbox_dstmod; -- STATIC
ndpcntl.dbox_cimod := R_IDSTAT.dbox_cimod; -- STATIC
ndpcntl.dbox_cc1op := R_IDSTAT.dbox_cc1op; -- STATIC
ndpcntl.dbox_ccmode := R_IDSTAT.dbox_ccmode; -- STATIC
ndpcntl.dbox_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.aunit_srcmod := R_IDSTAT.aunit_srcmod; -- STATIC
ndpcntl.aunit_dstmod := R_IDSTAT.aunit_dstmod; -- STATIC
ndpcntl.aunit_cimod := R_IDSTAT.aunit_cimod; -- STATIC
ndpcntl.aunit_cc1op := R_IDSTAT.aunit_cc1op; -- STATIC
ndpcntl.aunit_ccmode := R_IDSTAT.aunit_ccmode; -- STATIC
ndpcntl.aunit_bytop := R_IDSTAT.is_bytop; -- STATIC
 
ndpcntl.lbox_func := R_IDSTAT.lbox_func; -- STATIC
ndpcntl.lbox_bytop := R_IDSTAT.is_bytop; -- STATIC
ndpcntl.lunit_func := R_IDSTAT.lunit_func; -- STATIC
ndpcntl.lunit_bytop := R_IDSTAT.is_bytop; -- STATIC
 
ndpcntl.mbox_func := R_IDSTAT.mbox_func; -- STATIC
ndpcntl.munit_func := R_IDSTAT.munit_func; -- STATIC
 
ndpcntl.ireg_we := '0';
 
ndpcntl.cres_sel := R_IDSTAT.res_sel; -- DEFAULT
ndpcntl.dres_sel := c_dpath_res_abox;
ndpcntl.dres_sel := c_dpath_res_ounit;
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc;
 
if CP_CNTL.req='1' and R_STATUS.cmdbusy='0' then
766,16 → 769,16
end if;
 
when s_cp_regread =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A = DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B = const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
when s_cp_rps =>
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A = DTMP
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B = const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
nstatus.cmdack := '1';
nstate := s_idle;
 
941,10 → 944,10
end if;
 
when s_srcr_inc =>
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
977,11 → 980,11
end if;
when s_srcr_dec =>
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := SRCREG;
1005,12 → 1008,12
when s_srcr_ind1_w =>
nstate := s_srcr_ind1_w;
if R_IDSTAT.is_srcpc = '0' then
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A = DSRC
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A = DSRC
else
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A = PC (for nn(pc))
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.abox_bsel := c_abox_bsel_vmdout; -- ABOX B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout; -- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = R(DST)
do_memcheck(nstate, nstatus, imemok);
1101,10 → 1104,10
end if;
 
when s_dstr_inc =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
1130,11 → 1133,11
end if;
when s_dstr_dec =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
1156,12 → 1159,12
when s_dstr_ind1_w =>
nstate := s_dstr_ind1_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A = DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A = PC (for nn(pc))
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.abox_bsel := c_abox_bsel_vmdout; -- ABOX B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
1249,9 → 1252,9
when s_dstw_inc =>
ndpcntl.psr_ccwe := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST (for else)
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST (for else)
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG); --(...)
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const (for else)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (for else)
if DSTDEF = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
nvmcntl.kstack := is_dstkstack1246;
1258,7 → 1261,7
do_memwrite(nstate, nvmcntl, s_dstw_inc_w);
nstatus.do_gprwe := '1';
else
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
1269,10 → 1272,10
when s_dstw_inc_w =>
nstate := s_dstw_inc_w;
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
if R_STATUS.do_gprwe = '1' then
nmmumoni.regmod := '1';
1298,11 → 1301,11
 
when s_dstw_dec =>
ndpcntl.psr_ccwe := '1';
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
1328,12 → 1331,12
when s_dstw_ind_w =>
nstate := s_dstw_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A = DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A = PC (for nn(pc))
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.abox_bsel := c_abox_bsel_vmdout; -- ABOX B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
1378,10 → 1381,10
-- -> do_fork_opa
 
when s_dsta_inc =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_const := "000000010";
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(2)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
nmmumoni.regmod := '1';
1409,11 → 1412,11
end if;
when s_dsta_dec =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_const := "000000010";
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(2)
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
1440,12 → 1443,12
when s_dsta_ind_w =>
nstate := s_dsta_ind_w;
if R_IDSTAT.is_dstpc = '0' then
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A = DDST
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
else
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A = PC (for nn(pc))
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC (for nn(pc))
end if;
ndpcntl.abox_bsel := c_abox_bsel_vmdout; -- ABOX B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_bsel := c_ounit_bsel_vmdout;-- OUNIT B = VMDOUT
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
do_memcheck(nstate, nstatus, imemok);
if imemok then
1492,9 → 1495,9
nstate := s_idle;
when s_op_rts => -- RTS
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with reg(dst)
nstate := s_op_rts_pop;
1534,9 → 1537,9
when s_op_br => -- BR
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A = PC
ndpcntl.abox_bsel := c_abox_bsel_ireg8; -- ABOX B = IREG8
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg8;-- OUNIT B = IREG8
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
-- note: cc are NZVC
case brcode(3 downto 1) is
when "000" => -- BR
1567,9 → 1570,9
end if;
when s_op_mark => -- MARK
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A = PC
ndpcntl.abox_bsel := c_abox_bsel_ireg6; -- ABOX B = IREG6
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
ndpcntl.gpr_adst := c_gpr_r5; -- fetch r5
1578,9 → 1581,9
nstate := s_op_mark1;
 
when s_op_mark1 =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A = DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B = const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with r5
nstate := s_op_mark_pop;
1615,10 → 1618,10
end if;
when s_op_sob1 => -- SOB (br)
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A = PC
ndpcntl.abox_bsel := c_abox_bsel_ireg6; -- ABOX B = IREG6
ndpcntl.abox_opsub := '1'; -- ABOX = A - B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A = PC
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
1677,9 → 1680,9
nstate := s_opg_mul1;
when s_opg_mul1 => -- MUL (write odd reg)
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A = DTMP
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B = const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
1686,7 → 1689,7
do_fork_next(nstate, nstatus, nmmumoni);
when s_opg_div => -- DIV (load dd_low)
ndpcntl.mbox_s_div := '1';
ndpcntl.munit_s_div := '1';
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
1693,7 → 1696,7
nstate := s_opg_div_cn;
 
when s_opg_div_cn => -- DIV (1st...16th cycle)
ndpcntl.mbox_s_div_cn := '1';
ndpcntl.munit_s_div_cn := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
1709,7 → 1712,7
end if;
 
when s_opg_div_cr => -- DIV (reminder correction)
ndpcntl.mbox_s_div_cr := '1';
ndpcntl.munit_s_div_cr := '1';
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := DP_STAT.div_cr; -- update DSRC
1716,10 → 1719,10
nstate := s_opg_div_sq;
when s_opg_div_sq => -- DIV (store quotient)
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A=DTMP
ndpcntl.abox_const := "00000000"&DP_STAT.div_cq;-- ABOX const = Q corr.
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const (q cor)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.gpr_we := '1';
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
1727,9 → 1730,9
nstate := s_opg_div_sr;
 
when s_opg_div_sr => -- DIV (store reminder)
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const (0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
1740,16 → 1743,16
do_fork_next(nstate, nstatus, nmmumoni);
 
when s_opg_ash => -- ASH (load shc)
ndpcntl.mbox_s_ash := '1';
ndpcntl.munit_s_ash := '1';
nstate := s_opg_ash_cn;
 
when s_opg_ash_cn => -- ASH (shift cycles)
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.mbox_s_ash_cn := '1';
ndpcntl.munit_s_ash_cn := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nstate := s_opg_ash_cn;
if DP_STAT.shc_tc = '0' then
1756,7 → 1759,7
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.dsrc_we := '1'; -- update DSRC
else
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
1766,16 → 1769,16
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
ndpcntl.mbox_s_ashc := '1';
ndpcntl.munit_s_ashc := '1';
nstate := s_opg_ashc_cn;
 
when s_opg_ashc_cn => -- ASHC (shift cycles)
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.mbox_s_ashc_cn := '1';
ndpcntl.munit_s_ashc_cn := '1';
nstate := s_opg_ashc_cn;
if DP_STAT.shc_tc = '0' then
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
1782,7 → 1785,7
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.dtmp_we := '1'; -- update DTMP
else
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.psr_ccwe := '1';
nstate := s_opg_ashc_wl;
1789,9 → 1792,9
end if;
 
when s_opg_ashc_wl => -- ASHC (write low)
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A = DTMP
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B = const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
1813,11 → 1816,11
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
ndpcntl.dtmp_we := '1';
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_const := "000000010";
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(2)
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
ndpcntl.dsrc_we := '1'; -- update DDST
ndpcntl.gpr_adst := c_gpr_sp;
1827,9 → 1830,9
nstate := s_opa_jsr_push;
 
when s_opa_jsr_push =>
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A=DTMP
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
1839,9 → 1842,9
 
when s_opa_jsr_push_w =>
nstate := s_opa_jsr_push_w;
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A=PC
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
1850,17 → 1853,17
end if;
 
when s_opa_jsr2 =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with dsta
do_fork_next(nstate, nstatus, nmmumoni);
 
when s_opa_jmp =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_trap_10; -- trap 10 like 11/70
1896,19 → 1899,19
ndpcntl.ddst_we := '1'; -- update DDST (needed for sp)
 
when s_opa_mtp_reg =>
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A = DTMP
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B = const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.psr_ccwe := '1'; -- set cc (from abox too)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.gpr_mode := PSW.pmode; -- load reg in pmode
ndpcntl.gpr_we := '1';
do_fork_next(nstate, nstatus, nmmumoni);
 
when s_opa_mtp_mem =>
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A = DTMP
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B = const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.psr_ccwe := '1'; -- set cc (from abox too)
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst;-- VA = DDST
nvmcntl.dspace := IREG(15); -- msb indicates I/D: 0->I, 1->D
nvmcntl.mode := PSW.pmode;
1952,11 → 1955,11
end if;
 
when s_opa_mfp_dec =>
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_const := "000000010";
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(2)
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
1966,10 → 1969,10
nstate := s_opa_mfp_push;
 
when s_opa_mfp_push =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.psr_ccwe := '1'; -- set cc (from abox too)
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.dspace := '1';
nvmcntl.kstack := is_kmode;
2056,11 → 2059,11
nstate := s_int_decsp;
 
when s_int_decsp =>
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_const := "000000010"; -- ABOX const=2
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
2068,9 → 2071,9
nstate := s_int_pushps;
 
when s_int_pushps =>
ndpcntl.abox_asel := c_abox_asel_dtmp; -- ABOX A=DTMP (old PS)
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const (0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A=DTMP (old PS)
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
2079,11 → 2082,11
nstate := s_int_pushps_w;
 
when s_int_pushps_w =>
ndpcntl.abox_asel := c_abox_asel_dsrc; -- ABOX A=DSRC
ndpcntl.abox_const := "000000010"; -- ABOX const=2
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const
ndpcntl.abox_opsub := '1'; -- ABOX = A-B
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_const := "000000010"; -- OUNIT const=2
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.gpr_adst := c_gpr_sp;
 
2096,9 → 2099,9
end if;
when s_int_pushpc =>
ndpcntl.abox_asel := c_abox_asel_pc; -- ABOX A=PC
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const (0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
nvmcntl.wacc := '1'; -- write mem
nvmcntl.dspace := '1';
2107,9 → 2110,9
nstate := s_int_pushpc_w;
 
when s_int_pushpc_w =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const (0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
 
nstate := s_int_pushpc_w;
2155,14 → 2158,14
end if;
 
when s_rti_newpc =>
ndpcntl.abox_asel := c_abox_asel_ddst; -- ABOX A=DDST
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const (0)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load new PC
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
nstate := s_ifetch; -- force fetch
else -- otherwise RTI
ndpcntl.gpr_we := '1'; -- load new PC
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
nstate := s_ifetch; -- force fetch
else -- otherwise RTI
do_fork_next(nstate, nstatus, nmmumoni);
end if;
 
2172,22 → 2175,22
nstate := s_cpufail;
 
-- setup for R_VMSTAT.err_rsv='1'
ndpcntl.abox_azero := '1'; -- ABOX A = 0
ndpcntl.abox_const := "000000100"; -- emergency stack pointer
ndpcntl.abox_bsel := c_abox_bsel_const; -- ABOX B=const(vector)
ndpcntl.dres_sel := c_dpath_res_abox; -- DRES = ABOX
ndpcntl.gpr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.ounit_azero := '1'; -- OUNIT A = 0
ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gpr_adst := c_gpr_sp;
nstatus.trap_mmu :='0'; -- drop pending mmu trap
nstatus.trap_mmu :='0'; -- drop pending mmu trap
 
if R_VMSTAT.fail = '1' then -- vmbox failure
nstatus.cpugo := '0'; -- halt cpu
if R_VMSTAT.fail = '1' then -- vmbox failure
nstatus.cpugo := '0'; -- halt cpu
nstatus.cpurust := c_cpurust_vfail;
nstate := s_idle;
 
elsif R_STATUS.do_intrsv = '1' then -- double error
nstatus.cpugo := '0'; -- give up, HALT cpu
elsif R_STATUS.do_intrsv = '1' then -- double error
nstatus.cpugo := '0'; -- give up, HALT cpu
nstatus.cpurust := c_cpurust_recrsv;
nstate := s_idle;
2251,7 → 2254,7
VM_CNTL <= nvmcntl;
 
nmmumoni.regnum := ndpcntl.gpr_adst;
nmmumoni.delta := ndpcntl.abox_const(3 downto 0);
nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
MMU_MONI <= nmmumoni;
end process proc_next;
/trunk/rtl/w11a/pdp11_lunit.vhd
0,0 → 1,232
-- $Id: pdp11_lunit.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_lunit - syn
-- Description: pdp11: logic unit for data (lunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.1 renamed from lbox
-- 2008-03-30 131 1.0.2 BUGFIX: SXT clears V condition code
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.pdp11.all;
 
-- ----------------------------------------------------------------------------
 
entity pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CCIN : in slv4; -- condition codes in
FUNC : in slv4; -- function
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_lunit;
 
architecture syn of pdp11_lunit is
 
-- --------------------------------------
 
begin
 
process (DSRC, DDST, CCIN, FUNC, BYTOP)
variable iout : slv16 := (others=>'0');
variable inzstd : slbit := '0';
variable ino : slbit := '0';
variable izo : slbit := '0';
variable ivo : slbit := '0';
variable ico : slbit := '0';
 
alias DSRC_L : slv8 is DSRC(7 downto 0);
alias DSRC_H : slv8 is DSRC(15 downto 8);
alias DDST_L : slv8 is DDST(7 downto 0);
alias DDST_H : slv8 is DDST(15 downto 8);
alias NI : slbit is CCIN(3);
alias ZI : slbit is CCIN(2);
alias VI : slbit is CCIN(1);
alias CI : slbit is CCIN(0);
alias iout_l : slv8 is iout(7 downto 0);
alias iout_h : slv8 is iout(15 downto 8);
 
begin
 
iout := (others=>'0');
inzstd := '1'; -- use standard logic by default
ino := '0';
izo := '0';
ivo := '0';
ico := '0';
 
--
-- the decoding of FUNC is done "manually" to get a structure based on
-- a 8->1 pattern. This matches the opcode structure and seems most
-- efficient.
--
if FUNC(3) = '0' then
if BYTOP = '0' then
 
case FUNC(2 downto 0) is
when "000" => -- ASR
iout := DDST(15) & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
 
when "001" => -- ASL
iout := DDST(14 downto 0) & '0';
ico := DDST(15);
ivo := iout(15) xor ico;
 
when "010" => -- ROR
iout := CI & DDST(15 downto 1);
ico := DDST(0);
ivo := iout(15) xor ico;
 
when "011" => -- ROL
iout := DDST(14 downto 0) & CI;
ico := DDST(15);
ivo := iout(15) xor ico;
 
when "100" => -- BIS
iout := DDST or DSRC;
ico := CI;
 
when "101" => -- BIC
iout := DDST and not DSRC;
ico := CI;
 
when "110" => -- BIT
iout := DDST and DSRC;
ico := CI;
 
when "111" => -- MOV
iout := DSRC;
ico := CI;
when others => null;
end case;
 
else
 
case FUNC(2 downto 0) is
when "000" => -- ASRB
iout_l := DDST_L(7) & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
 
when "001" => -- ASLB
iout_l := DDST(6 downto 0) & '0';
ico := DDST(7);
ivo := iout_l(7) xor ico;
 
when "010" => -- RORB
iout_l := CI & DDST_L(7 downto 1);
ico := DDST_L(0);
ivo := iout_l(7) xor ico;
 
when "011" => -- ROLB
iout_l := DDST_L(6 downto 0) & CI;
ico := DDST_L(7);
ivo := iout_l(7) xor ico;
 
when "100" => -- BISB
iout_l := DDST_L or DSRC_L;
ico := CI;
 
when "101" => -- BICB
iout_l := DDST_L and not DSRC_L;
ico := CI;
 
when "110" => -- BITB
iout_l := DDST_L and DSRC_L;
ico := CI;
 
when "111" => -- MOVB
iout_l := DSRC_L;
iout_h := (others=>DSRC_L(7));
ico := CI;
when others => null;
end case;
end if;
 
else
case FUNC(2 downto 0) is
when "000" => -- SXT
iout := (others=>NI);
inzstd := '0';
ino := NI;
izo := not NI;
ivo := '0';
ico := CI;
when "001" => -- SWAP
iout := DDST_L & DDST_H;
inzstd := '0';
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
 
when "010" => -- XOR
iout := DDST xor DSRC;
ico := CI;
 
when others => null;
 
end case;
end if;
DOUT <= iout;
 
if inzstd = '1' then
if BYTOP = '1' then
ino := iout(7);
if unsigned(iout(7 downto 0)) = 0 then
izo := '1';
else
izo := '0';
end if;
else
ino := iout(15);
if unsigned(iout) = 0 then
izo := '1';
else
izo := '0';
end if;
end if;
end if;
 
CCOUT(3) <= ino;
CCOUT(2) <= izo;
CCOUT(1) <= ivo;
CCOUT(0) <= ico;
end process;
end syn;
/trunk/rtl/w11a/pdp11_vmbox.vhd
1,4 → 1,4
-- $Id: pdp11_vmbox.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_vmbox.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,12 → 19,17
-- pdp11_ubmap
-- ibus/ib_sres_or_4
-- ibus/ib_sres_or_2
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.6.2 add r.paddr_iopage, use ib_sel
-- 2010-10-22 334 1.6.1 deassert ibus be's at end-cycle; fix rmw logic
-- 2010-10-17 333 1.6 implement ibus V2 interface
-- 2010-06-27 310 1.5 redo ibus driver logic, now ibus driven from flops
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 for cpacc: set cacc in ib_mreq, forward racc,be
118,14 → 123,14
trap_mmu : slbit; -- mmu trace trap requested
mdin : slv16; -- data input (memory order)
paddr : slv22; -- physical address register
paddr_iopage : slv9; -- iopage base (upper 9 bits of paddr)
atocnt : slv(atowidth-1 downto 0); -- access timeout counter
ibreq : slbit; -- ibus req signal
ibre : slbit; -- ibus re signal
ibwe : slbit; -- ibus we signal
ibbe : slv2; -- ibus be0,be1 signals
ibdip : slbit; -- ibus dip signal
ibrmw : slbit; -- ibus rmw signal
ibcacc : slbit; -- ibus cacc signal
ibracc : slbit; -- ibus racc signal
ibaddr : slv13_1; -- ibus addr signal
ibdout : slv16; -- ibus dout register
end record regs_type;
 
136,10 → 141,10
'0','0','0','0', -- kstack,ysv,vaok,trap_mmu
(others=>'0'), -- mdin
(others=>'0'), -- paddr
(others=>'0'), -- paddr_iopage
atocnt_init, -- atocnt
'0','0',"00", -- ibreq,ibwe,ibbe
'0','0','0', -- ibdip,ibcacc,ibracc
(others=>'0'), -- ibaddr
'0','0',"00", -- ibre,ibwe,ibbe
'0','0','0', -- ibrmw,ibcacc,ibracc
(others=>'0') -- ibdout
);
 
190,7 → 195,7
IB_SRES => IB_SRES_UBMAP
);
 
IB_SRES_OR_INT : ib_sres_or_4
SRES_OR_INT : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_CPU,
IB_SRES_2 => IB_SRES_SLIM,
199,7 → 204,7
IB_SRES_OR => IB_SRES_INT
);
 
IB_SRES_OR_ALL : ib_sres_or_2
SRES_OR_ALL : ib_sres_or_2
port map (
IB_SRES_1 => IB_SRES_INT,
IB_SRES_2 => IB_SRES_EXT,
206,27 → 211,26
IB_SRES_OR => IB_SRES
);
 
proc_ibsel: process (IB_MREQ)
variable islim : slbit := '0';
begin
islim := '0';
if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_slim(12 downto 1) then
islim := '1';
end if;
IBSEL_SLIM <= islim;
IB_SRES_SLIM.ack <= islim;
IB_SRES_SLIM.busy <= '0';
end process proc_ibsel;
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_slim)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SLIM
);
 
proc_ibdout : process (IBSEL_SLIM, R_SLIM)
variable slimout : slv16 := (others=>'0');
proc_ibres : process (IBSEL_SLIM, IB_MREQ, R_SLIM)
variable idout : slv16 := (others=>'0');
begin
slimout := (others=>'0');
idout := (others=>'0');
if IBSEL_SLIM = '1' then
slimout(ibf_byte1) := R_SLIM;
idout(ibf_byte1) := R_SLIM;
end if;
IB_SRES_SLIM.dout <= slimout;
end process proc_ibdout;
IB_SRES_SLIM.dout <= idout;
IB_SRES_SLIM.ack <= IBSEL_SLIM and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SLIM.busy <= '0';
end process proc_ibres;
 
proc_slim: process (CLK)
begin
233,7 → 237,7
if CLK'event and CLK='1' then
if BRESET = '1' then
R_SLIM <= (others=>'0');
elsif IB_MREQ.we='1' and IBSEL_SLIM='1' then
elsif IBSEL_SLIM='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
R_SLIM <= IB_MREQ.din(ibf_byte1);
end if;
261,9 → 265,13
 
variable ivm_stat : vm_stat_type := vm_stat_init;
variable ivm_dout : slv16 := (others=>'0');
variable ipaddr : slv22 := (others=>'0');
variable iem_mreq : em_mreq_type := em_mreq_init;
variable immu_cntl : mmu_cntl_type := mmu_cntl_init;
 
variable ipaddr : slv22 := (others=>'0');
variable ipaddr_iopage : slv9 := (others=>'0');
 
variable iib_aval : slbit := '0';
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
279,7 → 287,6
constant c_paddr_sel_cacc : slv2 := "10";
constant c_paddr_sel_ubmap : slv2 := "11";
 
variable paddr_iopage : slv9 := (others=>'0');
begin
292,6 → 299,8
ivm_dout := EM_SRES.dout;
immu_cntl := mmu_cntl_init;
 
iib_aval := '0';
iem_mreq := em_mreq_init;
iem_mreq.din := VM_DIN;
 
323,17 → 332,22
end if;
end if;
 
paddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if r.cacc = '1' then
-- the iopage base is determined based on mmu regs and request type
-- r.paddr_iopage is updated during s_idle. This way the iopage base
-- address is determined in parallel to paddr and latched at end of s_idle.
-- Note: is VM_CNTL.cacc here, the status in s_idle is relevant !
ipaddr_iopage := "111111111"; -- iopage match pattern (for 22 bit)
if VM_CNTL.cacc = '1' then
if CP_ADDR.ena_22bit = '0' then
paddr_iopage := "000000111"; -- 16 bit cacc
ipaddr_iopage := "000000111"; -- 16 bit cacc
end if;
else
if MMU_STAT.ena_mmu = '0' then
paddr_iopage := "000000111"; -- 16 bit mode
ipaddr_iopage := "000000111"; -- 16 bit mode
else
if MMU_STAT.ena_22bit = '0' then
paddr_iopage := "000011111"; -- 18 bit mode
ipaddr_iopage := "000011111"; -- 18 bit mode
end if;
end if;
end if;
418,10 → 432,11
n.state := s_idle;
 
else
if r.paddr(21 downto 13) = paddr_iopage then
if r.paddr(21 downto 13) = r.paddr_iopage then
-- I/O page decoded
iem_mreq.cancel := '1'; -- cancel pending mem request
n.ibreq := '1'; -- setup ibus request
iib_aval := '1'; -- declare ibus addr valid
n.ibre := not r.wacc;
n.ibwe := r.wacc;
n.ibcacc := r.cacc;
n.ibracc := r.cacc and CP_ADDR.racc;
437,8 → 452,7
end if;
end if;
end if;
n.ibdip := r.macc;
n.ibaddr := r.paddr(12 downto 1);
n.ibrmw := r.macc;
n.state := s_ib_w;
 
else
471,19 → 485,35
when s_ib_w => -- s_ib_w: wait for ibus -------------
ato_go := '1'; -- activate timeout counter
 
n.ibreq := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
iib_aval := '1'; -- declare ibus addr valid
 
n.ibre := '0'; -- end cycle, unless busy seen
n.ibwe := '0';
n.ibrmw := '0';
n.ibbe := "00";
n.ibcacc := '0';
n.ibracc := '0';
if IB_SRES.ack='1' and IB_SRES.busy='0' then -- ibus cycle finished
if r.wacc = '1' then
n.state := s_ib_wend;
else
if r.macc = '1' then -- if first part of rmw
n.ibrmw := r.macc; -- keep rmw
n.ibbe := r.ibbe; -- keep be's
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
end if;
n.ibdout := IB_SRES.dout;
n.state := s_ib_rend;
end if;
elsif IB_SRES.busy='1' and ato_end='0' then
n.ibreq := r.ibreq; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibre := r.ibre; -- continue ibus cycle
n.ibwe := r.ibwe;
n.ibrmw := r.ibrmw;
n.ibbe := r.ibbe;
n.ibcacc := r.ibcacc;
n.ibracc := r.ibracc;
n.state := s_ib_w;
else
n.state := s_errib;
496,7 → 526,8
when s_ib_rend => -- s_ib_rend: ibus read completion ---
ivm_stat.ack := '1';
ivm_dout := r.ibdout;
if r.macc='1' and r.wacc='0' then -- first part of read-mod-write
if r.macc='1' then -- first part of read-mod-write
iib_aval := '1'; -- keep ibus addr valid
n.state := s_idle_mw_ib;
else
n.state := s_idle;
504,6 → 535,7
 
when s_idle_mw_ib => -- s_idle_mw_ib: wait macc write (ibus)
n.state := s_idle_mw_ib;
iib_aval := '1'; -- keep ibus addr valid
if r.ibbe = "10" then
iem_mreq.din(ibf_byte1) := VM_DIN(ibf_byte0);
end if;
514,7 → 546,6
if VM_CNTL.wacc='0' or VM_CNTL.macc='0' then
n.state := s_fail;
else
n.ibreq := '1'; -- start ibus write cycle
n.ibwe := '1'; -- Note: all other ibus drivers
-- already set in 1st part
n.state := s_ib_w;
614,7 → 645,8
end if;
 
if r.state = s_idle then
n.paddr := ipaddr;
n.paddr := ipaddr;
n.paddr_iopage := ipaddr_iopage;
end if;
iem_mreq.addr := ipaddr(21 downto 1);
623,14 → 655,15
 
UBMAP_MREQ <= iubmap_mreq;
 
IB_MREQ.req <= r.ibreq;
IB_MREQ.aval <= iib_aval;
IB_MREQ.re <= r.ibre;
IB_MREQ.we <= r.ibwe;
IB_MREQ.be0 <= r.ibbe(0);
IB_MREQ.be1 <= r.ibbe(1);
IB_MREQ.dip <= r.ibdip;
IB_MREQ.rmw <= r.ibrmw;
IB_MREQ.cacc <= r.ibcacc;
IB_MREQ.racc <= r.ibracc;
IB_MREQ.addr <= r.ibaddr;
IB_MREQ.addr <= r.paddr(12 downto 1);
IB_MREQ.din <= r.mdin;
VM_DOUT <= ivm_dout;
/trunk/rtl/w11a/pdp11_munit.vhd
0,0 → 1,396
-- $Id: pdp11_munit.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_munit - syn
-- Description: pdp11: mul/div unit for data (munit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.1 renamed from mbox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.pdp11.all;
 
-- ----------------------------------------------------------------------------
 
entity pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state
S_DIV_CN : in slbit; -- s_opg_div_cn state
S_DIV_CR : in slbit; -- s_opg_div_cr state
S_ASH : in slbit; -- s_opg_ash state
S_ASH_CN : in slbit; -- s_opg_ash_cn state
S_ASHC : in slbit; -- s_opg_ashc state
S_ASHC_CN : in slbit; -- s_opg_ashc_cn state
SHC_TC : out slbit; -- last shc cycle (shc==0)
DIV_CR : out slbit; -- division: reminder correction needed
DIV_CQ : out slbit; -- division: quotient correction needed
DIV_ZERO : out slbit; -- division: divident or divisor zero
DIV_OVFL : out slbit; -- division: overflow
DOUT : out slv16; -- data output
DOUTE : out slv16; -- data output extra
CCOUT : out slv4 -- condition codes out
);
end pdp11_munit;
 
architecture syn of pdp11_munit is
 
signal R_DD_L : slv16 := (others=>'0'); -- divident, low order part
signal R_DDO_LT : slbit := '0'; -- original sign bit of divident
signal R_DIV_V : slbit := '0'; -- V flag for division
signal R_SHC : slv6 := (others=>'0'); -- shift counter for div and ash/c
signal R_C1 : slbit := '0'; -- first cycle indicator
signal R_MSBO : slbit := '0'; -- original sign bit for ash/c
signal R_ASH_V : slbit := '0'; -- V flag for ash/c
signal R_ASH_C : slbit := '0'; -- C flag for ash/c
 
signal NEXT_DD_L : slv16 := (others=>'0');
signal NEXT_DDO_LT : slbit := '0';
signal NEXT_DIV_V : slbit := '0';
signal NEXT_SHC : slv6 := (others=>'0');
signal NEXT_C1 : slbit := '0';
signal NEXT_MSBO : slbit := '0';
signal NEXT_ASH_V : slbit := '0';
signal NEXT_ASH_C : slbit := '0';
 
signal SHC_TC_L : slbit := '0';
 
signal DDST_ZERO : slbit := '0';
signal DSRC_ZERO : slbit := '0';
signal DSRC_ONES : slbit := '0';
signal DTMP_ZERO : slbit := '0';
 
signal DOUT_DIV : slv16 := (others=>'0');
signal DOUTE_DIV : slv16 := (others=>'0');
 
alias DR : slv16 is DDST; -- divisor (in DDST)
alias DD_H : slv16 is DSRC; -- divident, high order part (in DSRC)
alias Q : slv16 is DTMP; -- quotient (accumulated in DTMP)
 
begin
 
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
R_DD_L <= NEXT_DD_L;
R_DDO_LT <= NEXT_DDO_LT;
R_DIV_V <= NEXT_DIV_V;
R_SHC <= NEXT_SHC;
R_C1 <= NEXT_C1;
R_MSBO <= NEXT_MSBO;
R_ASH_V <= NEXT_ASH_V;
R_ASH_C <= NEXT_ASH_C;
end if;
end process proc_regs;
proc_comm: process (DDST, DSRC, DTMP)
begin
DDST_ZERO <= '0';
DSRC_ZERO <= '0';
DSRC_ONES <= '0';
DTMP_ZERO <= '0';
 
if unsigned(DDST) = 0 then
DDST_ZERO <= '1';
end if;
if unsigned(DSRC) = 0 then
DSRC_ZERO <= '1';
end if;
if signed(DSRC) = -1 then
DSRC_ONES <= '1';
end if;
if unsigned(DTMP) = 0 then
DTMP_ZERO <= '1';
end if;
end process proc_comm;
proc_shc: process (DDST, R_SHC, R_C1,
S_DIV, S_DIV_CN, S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN)
begin
NEXT_SHC <= R_SHC;
NEXT_C1 <= R_C1;
 
if S_ASH='1' or S_ASHC='1' then
NEXT_SHC <= DDST(5 downto 0);
NEXT_C1 <= '1';
end if;
if S_DIV = '1' then
NEXT_SHC <= "001111";
NEXT_C1 <= '1';
end if;
 
if S_DIV_CN='1' or S_ASH_CN='1' or S_ASHC_CN='1' then
if R_SHC(5) = '0' then
NEXT_SHC <= unsigned(R_SHC) - 1;
else
NEXT_SHC <= unsigned(R_SHC) + 1;
end if;
NEXT_C1 <= '0';
end if;
 
SHC_TC_L <= '0';
if unsigned(R_SHC) = 0 then
SHC_TC_L <= '1';
end if;
end process proc_shc;
proc_div: process (DDST, DSRC, DTMP, GPR_DSRC, DR, DD_H, Q,
R_DD_L, R_DDO_LT, R_DIV_V, R_SHC, R_C1,
S_DIV, S_DIV_CN, S_DIV_CR,
DDST_ZERO, DSRC_ZERO, DTMP_ZERO)
variable shftdd : slbit := '0';
variable subadd : slbit := '0';
 
variable dd_gt : slbit := '0';
variable qbit : slbit := '0';
variable qbit_1 : slbit := '0';
variable qbit_n : slbit := '0';
 
variable dd_h_old : slv16 := (others=>'0'); -- dd_h before add/sub
variable dd_h_new : slv16 := (others=>'0'); -- dd_h after add/sub
begin
NEXT_DD_L <= R_DD_L;
NEXT_DDO_LT <= R_DDO_LT;
NEXT_DIV_V <= R_DIV_V;
 
DIV_ZERO <= '0';
DIV_OVFL <= '0';
 
qbit_1 := not (DR(15) xor DD_H(15)); -- !(dr<0 ^ dd_h<0)
shftdd := not S_DIV_CR;
if shftdd = '1' then
dd_h_old := DD_H(14 downto 0) & R_DD_L(15);
else
dd_h_old := DD_H(15 downto 0);
end if;
if R_C1 = '1' then
subadd := qbit_1;
DIV_ZERO <= DDST_ZERO or
(DSRC_ZERO and DTMP_ZERO); -- note: DTMP here still dd_low !
else
subadd := Q(0);
end if;
if subadd = '0' then
dd_h_new := signed(dd_h_old) + signed(DR);
else
dd_h_new := signed(dd_h_old) - signed(DR);
end if;
 
dd_gt := '0';
if dd_h_new(15) = '0' and
(unsigned(dd_h_new(14 downto 0))/=0 or
unsigned(R_DD_L(14 downto 0))/=0)
then
dd_gt := '1'; -- set if dd_new > 0
end if;
if R_DDO_LT = '0' then
qbit_n := DR(15) xor not dd_h_new(15); -- b_dr_lt ^ !b_dd_lt
else
qbit_n := DR(15) xor dd_gt; -- b_dr_lt ^ b_dd_gt
end if;
if S_DIV = '1' then
NEXT_DDO_LT <= DD_H(15);
NEXT_DD_L <= GPR_DSRC;
end if;
if R_C1 = '1' then
NEXT_DIV_V <= (DD_H(15) xor DD_H(14)) or
(DD_H(15) xor (DR(15) xor qbit_n));
DIV_OVFL <= (DD_H(15) xor DD_H(14)) or --??? cleanup
(DD_H(15) xor (DR(15) xor qbit_n)); --??? cleanup
end if;
 
if S_DIV_CN = '1' then
NEXT_DD_L <= R_DD_L(14 downto 0) & '0';
end if;
 
if S_DIV_CN = '1' then
qbit := qbit_n;
else
qbit := qbit_1;
end if;
 
DIV_CR <= not (R_DDO_LT xor
(DR(15) xor Q(0))); --!(b_ddo_lt ^ (b_dr_lt ^ b_qbit));
DIV_CQ <= R_DDO_LT xor DR(15); -- b_ddo_lt ^ b_dr_lt;
DOUT_DIV <= dd_h_new;
DOUTE_DIV <= Q(14 downto 0) & qbit;
 
end process proc_div;
proc_ash: process (R_MSBO, R_ASH_V, R_ASH_C, R_SHC, DSRC, DTMP, FUNC,
S_ASH, S_ASH_CN, S_ASHC, S_ASHC_CN, SHC_TC_L)
begin
NEXT_MSBO <= R_MSBO;
NEXT_ASH_V <= R_ASH_V;
NEXT_ASH_C <= R_ASH_C;
 
if S_ASH='1' or S_ASHC='1' then
NEXT_MSBO <= DSRC(15);
NEXT_ASH_V <= '0';
NEXT_ASH_C <= '0';
end if;
if (S_ASH_CN='1' or S_ASHC_CN='1') and SHC_TC_L='0' then
if R_SHC(5) = '0' then -- left shift
if (R_MSBO xor DSRC(14))='1' then
NEXT_ASH_V <= '1';
end if;
NEXT_ASH_C <= DSRC(15);
else -- right shift
if FUNC = c_munit_func_ash then
NEXT_ASH_C <= DSRC(0);
else
NEXT_ASH_C <= DTMP(0);
end if;
end if;
end if;
end process proc_ash;
 
proc_omux: process (DSRC, DDST, DTMP, FUNC,
R_ASH_V, R_ASH_C, R_SHC, R_DIV_V,
DOUT_DIV, DOUTE_DIV,
DSRC_ZERO, DSRC_ONES, DTMP_ZERO, DDST_ZERO)
variable prod : slv32 := (others=>'0');
variable omux_sel : slv2 := "00";
variable ash_dout0 : slbit := '0';
 
variable mul_c : slbit := '0';
 
begin
 
prod := signed(DSRC) * signed(DDST);
 
case FUNC is
when c_munit_func_mul =>
omux_sel := "00";
when c_munit_func_div =>
omux_sel := "01";
when c_munit_func_ash |c_munit_func_ashc =>
if R_SHC(5) = '0' then
omux_sel := "10";
else
omux_sel := "11";
end if;
when others => null;
end case;
 
if FUNC = c_munit_func_ash then
ash_dout0 := '0';
else
ash_dout0 := DTMP(15);
end if;
 
case omux_sel is
when "00" => -- MUL
DOUT <= prod(31 downto 16);
DOUTE <= prod(15 downto 0);
when "01" => -- DIV
DOUT <= DOUT_DIV;
DOUTE <= DOUTE_DIV;
when "10" => -- shift left
DOUT <= DSRC(14 downto 0) & ash_dout0;
DOUTE <= DTMP(14 downto 0) & "0";
when "11" => -- shift right
DOUT <= DSRC(15) & DSRC(15 downto 1);
DOUTE <= DSRC(0) & DTMP(15 downto 1);
when others => null;
end case;
mul_c := '0'; -- MUL C codes is set if
if DSRC(15) = '0' then
if DSRC_ZERO='0' or DTMP(15)='1' then -- for positive results when
mul_c := '1'; -- product > 2^15-1
end if;
else -- for negative results when
if DSRC_ONES='0' or DTMP(15)='0' then
mul_c := '1'; -- product < -2^15
end if;
end if;
case FUNC is
when c_munit_func_mul =>
CCOUT(3) <= DSRC(15); -- N
CCOUT(2) <= DSRC_ZERO and DTMP_ZERO;-- Z
CCOUT(1) <= '0'; -- V=0
CCOUT(0) <= mul_c; -- C
 
when c_munit_func_div =>
if DDST_ZERO = '1' then
CCOUT(3) <= '0'; -- N=0 if div/0
CCOUT(2) <= '1'; -- Z=1 if div/0
elsif R_DIV_V = '1' then
CCOUT(3) <= DSRC(15) xor DDST(15); -- N (from unchanged reg)
CCOUT(2) <= '0'; -- Z (from unchanged reg) ??? veri
else
CCOUT(3) <= DTMP(15); -- N (from Q (DTMP))
CCOUT(2) <= DTMP_ZERO; -- Z (from Q (DTMP)) ??? verify
end if;
CCOUT(1) <= R_DIV_V or DDST_ZERO; -- V
CCOUT(0) <= DDST_ZERO; -- C (dst=0)
 
when c_munit_func_ash =>
CCOUT(3) <= DSRC(15); -- N
CCOUT(2) <= DSRC_ZERO; -- Z
CCOUT(1) <= R_ASH_V; -- V
CCOUT(0) <= R_ASH_C; -- C
 
when c_munit_func_ashc =>
CCOUT(3) <= DSRC(15); -- N
CCOUT(2) <= DSRC_ZERO and DTMP_ZERO;-- Z
CCOUT(1) <= R_ASH_V; -- V
CCOUT(0) <= R_ASH_C; -- C
 
when others => null;
end case;
end process proc_omux;
 
SHC_TC <= SHC_TC_L;
end syn;
/trunk/rtl/w11a/pdp11_ounit.vhd
0,0 → 1,113
-- $Id: pdp11_ounit.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_ounit - syn
-- Description: pdp11: arithmetic unit for addresses (ounit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
use work.slvtypes.all;
use work.pdp11.all;
 
-- ----------------------------------------------------------------------------
 
entity pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
DTMP : in slv16; -- 'tmp' data for port A
PC : in slv16; -- PC data for port A
ASEL : in slv2; -- selector for port A
AZERO : in slbit; -- force zero for port A
IREG8 : in slv8; -- 'ireg' data for port B
VMDOUT : in slv16; -- virt. memory data for port B
CONST : in slv9; -- sequencer const data for port B
BSEL : in slv2; -- selector for port B
OPSUB : in slbit; -- operation: 0 add, 1 sub
DOUT : out slv16; -- data output
NZOUT : out slv2 -- NZ condition codes out
);
end pdp11_ounit;
 
architecture syn of pdp11_ounit is
 
-- --------------------------------------
 
begin
 
process (DSRC, DDST, DTMP, PC, ASEL, AZERO,
IREG8, VMDOUT, CONST, BSEL, OPSUB)
 
variable ma : slv16 := (others=>'0'); -- effective port a data
variable mb : slv16 := (others=>'0'); -- effective port b data
variable sum : slv16 := (others=>'0'); -- sum
variable nzo : slbit := '0';
begin
 
if AZERO = '0' then
case ASEL is
when c_ounit_asel_dsrc => ma := DSRC;
when c_ounit_asel_ddst => ma := DDST;
when c_ounit_asel_dtmp => ma := DTMP;
when c_ounit_asel_pc => ma := PC;
when others => null;
end case;
else
ma := (others=>'0');
end if;
 
case BSEL is
when c_ounit_bsel_ireg6 => mb := "000000000" & IREG8(5 downto 0) & "0";
when c_ounit_bsel_ireg8 => mb := IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8(7) & IREG8(7) &
IREG8(7) & IREG8 & "0";
when c_ounit_bsel_vmdout => mb := VMDOUT;
when c_ounit_bsel_const => mb := "0000000" & CONST;
when others => null;
end case;
 
if OPSUB = '0' then
sum := unsigned(ma) + unsigned(mb);
else
sum := unsigned(ma) - unsigned(mb);
end if;
 
nzo := '0';
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
DOUT <= sum;
NZOUT(1) <= sum(15);
NZOUT(0) <= nzo;
end process;
end syn;
/trunk/rtl/w11a/pdp11_mmu.vhd
1,4 → 1,4
-- $Id: pdp11_mmu.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_mmu.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
18,12 → 18,16
-- Dependencies: pdp11_mmu_sadr
-- pdp11_mmu_ssr12
-- ibus/ib_sres_or_3
-- ibus/ib_sel
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
-- 2010-06-20 307 1.3.7 rename cpacc to cacc in mmu_cntl_type
-- 2009-05-30 220 1.3.6 final removal of snoopers (were already commented)
-- 2009-05-09 213 1.3.5 BUGFIX: tie inst_compl permanentely '0'
133,7 → 137,7
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_SSR12);
 
IB_SRES_OR : ib_sres_or_3
SRES_OR : ib_sres_or_3
port map (
IB_SRES_1 => IB_SRES_SADR,
IB_SRES_2 => IB_SRES_SSR12,
140,23 → 144,24
IB_SRES_3 => IB_SRES_SSR03,
IB_SRES_OR => IB_SRES);
 
proc_ibsel: process (IB_MREQ)
variable issr0 : slbit := '0';
variable issr3 : slbit := '0';
begin
issr0 := '0';
issr3 := '0';
if IB_MREQ.req = '1' then
if IB_MREQ.addr = ibaddr_ssr0(12 downto 1) then issr0 := '1'; end if;
if IB_MREQ.addr = ibaddr_ssr3(12 downto 1) then issr3 := '1'; end if;
end if;
IBSEL_SSR0 <= issr0;
IBSEL_SSR3 <= issr3;
IB_SRES_SSR03.ack <= issr0 or issr3;
IB_SRES_SSR03.busy <= '0';
end process proc_ibsel;
SEL_SSR0 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr0)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR0
);
SEL_SSR3 : ib_sel
generic map (
IB_ADDR => ibaddr_ssr3)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_SSR3
);
 
proc_ibdout : process (IBSEL_SSR0, IBSEL_SSR3, R_SSR0, R_SSR3)
proc_ibres : process (IBSEL_SSR0, IBSEL_SSR3, IB_MREQ, R_SSR0, R_SSR3)
 
variable ssr0out : slv16 := (others=>'0');
variable ssr3out : slv16 := (others=>'0');
187,8 → 192,11
end if;
IB_SRES_SSR03.dout <= ssr0out or ssr3out;
IB_SRES_SSR03.ack <= (IBSEL_SSR0 or IBSEL_SSR3) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES_SSR03.busy <= '0';
 
end process proc_ibdout;
end process proc_ibres;
 
proc_ssr0 : process (CLK)
begin
206,7 → 214,7
if CLK'event and CLK='1' then
if BRESET = '1' then
R_SSR3 <= mmu_ssr3_init;
elsif IB_MREQ.we='1' and IBSEL_SSR3='1' then
elsif IBSEL_SSR3='1' and IB_MREQ.we='1' then
if IB_MREQ.be0 = '1' then
R_SSR3.ena_ubmap <= IB_MREQ.din(ssr3_ibf_ena_ubmap);
R_SSR3.ena_22bit <= IB_MREQ.din(ssr3_ibf_ena_22bit);
324,7 → 332,7
abo_nonres := '1';
end case;
 
if IB_MREQ.we='1' and IBSEL_SSR0='1' then
if IBSEL_SSR0='1' and IB_MREQ.we='1' then
 
if IB_MREQ.be1 = '1' then
nssr0.abo_nonres := IB_MREQ.din(ssr0_ibf_abo_nonres);
/trunk/rtl/w11a/pdp11_aunit.vbom
0,0 → 1,5
# libs
../vlib/slvtypes.vhd
pdp11.vbom
# design
pdp11_aunit.vhd
/trunk/rtl/w11a/pdp11_core_rri.vhd
1,4 → 1,4
-- $Id: pdp11_core_rri.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_core_rri.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
21,9 → 21,10
-- tb/tb_rriext_pdp11core
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.26
-- Revision History: -
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.3 rename RRI_LAM->RB_LAM;
-- 2010-06-20 308 1.2.2 use c_ibrb_ibf_ def's
-- 2010-06-18 306 1.2.1 rename RB_ADDR->RB_ADDR_CORE, add RB_ADDR_IBUS;
-- add ibrb register and ibr window logic
96,7 → 97,7
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
382,7 → 383,7
RB_STAT(1) <= CP_STAT.cpuhalt or CP_STAT.cpurust(CP_STAT.cpurust'left);
RB_STAT(2) <= CP_STAT.cmderr or CP_STAT.cmdmerr;
 
RRI_LAM <= irb_lam;
RB_LAM <= irb_lam;
 
CPU_RESET <= icpureset;
/trunk/rtl/w11a/pdp11_psr.vhd
1,6 → 1,6
-- $Id: pdp11_psr.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_psr.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2006-2009 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
15,12 → 15,15
-- Module Name: pdp11_psr - syn
-- Description: pdp11: processor status word register
--
-- Dependencies: -
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
64,32 → 67,31
 
begin
proc_ibsel: process (IB_MREQ)
variable ipsr : slbit := '0';
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_psr)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_PSR
);
 
proc_ibres: process (IBSEL_PSR, IB_MREQ, R_PSW)
variable idout : slv16 := (others=>'0');
begin
ipsr := '0';
if IB_MREQ.req='1' and IB_MREQ.addr=ibaddr_psr(12 downto 1) then
ipsr := '1';
idout := (others=>'0');
if IBSEL_PSR = '1' then
idout(psw_ibf_cmode) := R_PSW.cmode;
idout(psw_ibf_pmode) := R_PSW.pmode;
idout(psw_ibf_rset) := R_PSW.rset;
idout(psw_ibf_pri) := R_PSW.pri;
idout(psw_ibf_tflag) := R_PSW.tflag;
idout(psw_ibf_cc) := R_PSW.cc;
end if;
IBSEL_PSR <= ipsr;
IB_SRES.ack <= ipsr;
IB_SRES.dout <= idout;
IB_SRES.ack <= IBSEL_PSR and (IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibsel;
proc_ibdout: process (IBSEL_PSR, R_PSW)
variable pswout : slv16 := (others=>'0');
begin
pswout := (others=>'0');
if IBSEL_PSR = '1' then
pswout(psw_ibf_cmode) := R_PSW.cmode;
pswout(psw_ibf_pmode) := R_PSW.pmode;
pswout(psw_ibf_rset) := R_PSW.rset;
pswout(psw_ibf_pri) := R_PSW.pri;
pswout(psw_ibf_tflag) := R_PSW.tflag;
pswout(psw_ibf_cc) := R_PSW.cc;
end if;
IB_SRES.dout <= pswout;
end process proc_ibdout;
end process proc_ibres;
proc_psw : process (CLK)
begin
120,26 → 122,26
when c_psr_func_wint => -- wint (interupt handling)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.cmode; -- save current mode
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
R_PSW.cc <= DIN(psw_ibf_cc);
when c_psr_func_wrti => -- wrti (rti/rtt in non-kernel mode)
R_PSW.cmode <= R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.pmode <= R_PSW.pmode or DIN(psw_ibf_pmode) or
R_PSW.cmode or DIN(psw_ibf_cmode);
R_PSW.rset <= R_PSW.rset or DIN(psw_ibf_rset);
R_PSW.rset <= R_PSW.rset or DIN(psw_ibf_rset);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
R_PSW.cc <= DIN(psw_ibf_cc);
 
when c_psr_func_wall => -- wall (rti/rtt kernel mode)
R_PSW.cmode <= DIN(psw_ibf_cmode);
R_PSW.pmode <= DIN(psw_ibf_pmode);
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.rset <= DIN(psw_ibf_rset);
R_PSW.pri <= DIN(psw_ibf_pri);
R_PSW.tflag <= DIN(psw_ibf_tflag);
R_PSW.cc <= DIN(psw_ibf_cc);
R_PSW.cc <= DIN(psw_ibf_cc);
when others => null;
end case;
150,11 → 152,11
if IB_MREQ.be1 = '1' then
R_PSW.cmode <= IB_MREQ.din(psw_ibf_cmode);
R_PSW.pmode <= IB_MREQ.din(psw_ibf_pmode);
R_PSW.rset <= IB_MREQ.din(psw_ibf_rset);
R_PSW.rset <= IB_MREQ.din(psw_ibf_rset);
end if;
if IB_MREQ.be0 = '1' then
R_PSW.pri <= IB_MREQ.din(psw_ibf_pri);
R_PSW.cc <= IB_MREQ.din(psw_ibf_cc);
R_PSW.cc <= IB_MREQ.din(psw_ibf_cc);
end if;
end if;
/trunk/rtl/w11a/pdp11_ubmap.vhd
1,6 → 1,6
-- $Id: pdp11_ubmap.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_ubmap.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
15,12 → 15,16
-- Module Name: pdp11_ubmap - syn
-- Description: pdp11: 11/70 unibus mapper
--
-- Dependencies: -
-- Dependencies: memlib/ram_1swar_gen
-- ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1.1 use ib_sel
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.1 use iblib
-- 2008-01-27 115 1.0 Initial version
------------------------------------------------------------------------------
51,6 → 55,8
constant ibaddr_ubmap : slv16 := conv_std_logic_vector(8#170200#,16);
 
signal IBSEL_UBMAP : slbit := '0';
 
signal MAP_2_WE : slbit := '0';
signal MAP_1_WE : slbit := '0';
signal MAP_0_WE : slbit := '0';
92,8 → 98,17
DI => IB_MREQ.din(7 downto 1),
DO => MAP_DOUT(7 downto 1));
 
proc_comb: process (MREQ, ADDR_UB, IB_MREQ, MAP_DOUT)
variable ibsel : slbit := '0';
SEL : ib_sel
generic map (
IB_ADDR => ibaddr_ubmap,
SAWIDTH => 6) -- 2^6 = 64 = 2*32 words
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_UBMAP
);
 
proc_comb: process (MREQ, ADDR_UB, IBSEL_UBMAP, IB_MREQ, MAP_DOUT)
variable ibusy : slbit := '0';
variable idout : slv16 := (others=>'0');
variable iwe2 : slbit := '0';
102,7 → 117,6
variable iaddr : slv5 := (others=>'0');
begin
ibsel := '0';
ibusy := '0';
idout := (others=>'0');
iwe2 := '0';
110,12 → 124,7
iwe0 := '0';
iaddr := (others=>'0');
 
if IB_MREQ.req = '1' and
IB_MREQ.addr(12 downto 7)=ibaddr_ubmap(12 downto 7) then
ibsel := '1';
end if;
if ibsel = '1' then
if IBSEL_UBMAP = '1' then
if IB_MREQ.addr(1) = '1' then
idout(5 downto 0) := MAP_DOUT(21 downto 16);
else
126,7 → 135,7
end if;
end if;
 
if ibsel='1' and IB_MREQ.we='1' then
if IBSEL_UBMAP='1' and IB_MREQ.we='1' then
if IB_MREQ.addr(1)='1' then
if IB_MREQ.be0 = '1' then
iwe2 := '1';
154,7 → 163,7
 
ADDR_PM <= unsigned(MAP_DOUT) + unsigned("000000000"&ADDR_UB(12 downto 1));
 
IB_SRES.ack <= ibsel;
IB_SRES.ack <= IBSEL_UBMAP and (IB_MREQ.re or IB_MREQ.we);
IB_SRES.busy <= ibusy;
IB_SRES.dout <= idout;
 
/trunk/rtl/w11a/pdp11_tmu.vhd
1,4 → 1,4
-- $Id: pdp11_tmu.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_tmu.vhd 333 2010-10-17 21:18:33Z mueller $
--
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
20,8 → 20,10
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.25
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-17 333 1.0.6 use ibus V2 interface
-- 2010-06-26 309 1.0.5 add ibmreq.dip,.cacc,.racc to trace
-- 2009-05-10 214 1.0.4 add ENA signal (trace enable)
-- 2008-12-14 177 1.0.3 write gpr_* of DM_STAT_DP and dp_ireg_we_last
95,11 → 97,12
write(oline, string'(" dp.gpr_bytop:b"));
write(oline, string'(" dp.gpr_we:b"));
 
write(oline, string'(" vm.ibmreq.req:b"));
write(oline, string'(" vm.ibmreq.aval:b"));
write(oline, string'(" vm.ibmreq.re:b"));
write(oline, string'(" vm.ibmreq.we:b"));
write(oline, string'(" vm.ibmreq.rmw:b"));
write(oline, string'(" vm.ibmreq.be0:b"));
write(oline, string'(" vm.ibmreq.be1:b"));
write(oline, string'(" vm.ibmreq.dip:b"));
write(oline, string'(" vm.ibmreq.cacc:b"));
write(oline, string'(" vm.ibmreq.racc:b"));
write(oline, string'(" vm.ibmreq.addr:o"));
146,7 → 149,8
DM_STAT_SY.emsres.ack_r='1' or
DM_STAT_SY.emsres.ack_w='1' or
DM_STAT_SY.emmreq.cancel='1' or
DM_STAT_VM.ibmreq.req='1' or
DM_STAT_VM.ibmreq.re='1' or
DM_STAT_VM.ibmreq.we='1' or
DM_STAT_VM.ibsres.ack='1'
then
wcycle := true;
179,11 → 183,12
write(oline, DM_STAT_DP.gpr_bytop, right, 2);
write(oline, DM_STAT_DP.gpr_we, right, 2);
 
write(oline, DM_STAT_VM.ibmreq.req, right, 2);
write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
write(oline, DM_STAT_VM.ibmreq.re, right, 2);
write(oline, DM_STAT_VM.ibmreq.we, right, 2);
write(oline, DM_STAT_VM.ibmreq.rmw, right, 2);
write(oline, DM_STAT_VM.ibmreq.be0, right, 2);
write(oline, DM_STAT_VM.ibmreq.be1, right, 2);
write(oline, DM_STAT_VM.ibmreq.dip, right, 2);
write(oline, DM_STAT_VM.ibmreq.cacc, right, 2);
write(oline, DM_STAT_VM.ibmreq.racc, right, 2);
writeoct(oline, ibaddr, right, 7);
/trunk/rtl/w11a/pdp11_mmu_ssr12.vbom
2,5 → 2,7
../vlib/slvtypes.vhd
../ibus/iblib.vhd
pdp11.vbom
# components
../ibus/ib_sel.vbom
# design
pdp11_mmu_ssr12.vhd
/trunk/rtl/w11a/pdp11_sequencer.vbom
2,5 → 2,7
../vlib/slvtypes.vhd
../ibus/iblib.vhd
pdp11.vbom
# components
../ibus/ib_sel.vbom
# design
pdp11_sequencer.vhd
/trunk/rtl/w11a/pdp11_irq.vbom
2,5 → 2,7
../vlib/slvtypes.vhd
../ibus/iblib.vhd
pdp11.vbom
# components
../ibus/ib_sel.vbom
# design
pdp11_irq.vhd
/trunk/rtl/w11a/pdp11_munit.vbom
0,0 → 1,5
# libs
../vlib/slvtypes.vhd
pdp11.vbom
# design
pdp11_munit.vhd
/trunk/rtl/w11a/pdp11_mmu.vbom
6,5 → 6,6
pdp11_mmu_sadr.vbom
pdp11_mmu_ssr12.vbom
../ibus/ib_sres_or_3.vbom
../ibus/ib_sel.vbom
# design
pdp11_mmu.vhd
/trunk/rtl/w11a/pdp11.vhd
1,4 → 1,4
-- $Id: pdp11.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,9
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.4.6 rename RRI_LAM->RB_LAM;
-- 2010-10-16 332 1.4.5 renames of pdp11_du_drv port names
-- 2010-09-18 330 1.4.4 rename (adlm)box->(oalm)unit
-- 2010-06-20 308 1.4.3 add c_ibrb_ibf_ def's
-- 2010-06-20 307 1.4.2 rename cpacc to cacc in vm_cntl_type, mmu_cntl_type
-- 2010-06-18 306 1.4.1 add racc, be to cp_addr_type; rm pdp11_ibdr_rri
140,27 → 143,27
ddst_we : slbit; -- dst data register write enable
dtmp_sel : slv2; -- tmp data register source select
dtmp_we : slbit; -- tmp data register write enable
abox_asel : slv2; -- abox a port selector
abox_azero : slbit; -- abox a port force zero
abox_const : slv9; -- abox b port const
abox_bsel : slv2; -- abox b port selector
abox_opsub : slbit; -- abox operation
dbox_srcmod : slv2; -- dbox src port modifier
dbox_dstmod : slv2; -- dbox dst port modifier
dbox_cimod : slv2; -- dbox ci port modifier
dbox_cc1op : slbit; -- dbox use cc modes (1 op instruction)
dbox_ccmode : slv3; -- dbox cc port mode
dbox_bytop : slbit; -- dbox byte operation
lbox_func : slv4; -- lbox function
lbox_bytop : slbit; -- lbox byte operation
mbox_func : slv2; -- mbox function
mbox_s_div : slbit; -- mbox s_opg_div state
mbox_s_div_cn : slbit; -- mbox s_opg_div_cn state
mbox_s_div_cr : slbit; -- mbox s_opg_div_cr state
mbox_s_ash : slbit; -- mbox s_opg_ash state
mbox_s_ash_cn : slbit; -- mbox s_opg_ash_cn state
mbox_s_ashc : slbit; -- mbox s_opg_ashc state
mbox_s_ashc_cn : slbit; -- mbox s_opg_ashc_cn state
ounit_asel : slv2; -- ounit a port selector
ounit_azero : slbit; -- ounit a port force zero
ounit_const : slv9; -- ounit b port const
ounit_bsel : slv2; -- ounit b port selector
ounit_opsub : slbit; -- ounit operation
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
aunit_bytop : slbit; -- aunit byte operation
lunit_func : slv4; -- lunit function
lunit_bytop : slbit; -- lunit byte operation
munit_func : slv2; -- munit function
munit_s_div : slbit; -- munit s_opg_div state
munit_s_div_cn : slbit; -- munit s_opg_div_cn state
munit_s_div_cr : slbit; -- munit s_opg_div_cr state
munit_s_ash : slbit; -- munit s_opg_ash state
munit_s_ash_cn : slbit; -- munit s_opg_ash_cn state
munit_s_ashc : slbit; -- munit s_opg_ashc state
munit_s_ashc_cn : slbit; -- munit s_opg_ashc_cn state
ireg_we : slbit; -- ireg register write enable
cres_sel : slv3; -- result bus (cres) select
dres_sel : slv3; -- result bus (dres) select
172,10 → 175,10
"000","000","00",'0','0','0','0', -- gpr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- abox
"00","00","00",'0',"000",'0', -- dbox
"0000",'0', -- lbox
"00",'0','0','0','0','0','0','0', -- mbox
"00",'0',"000000000","00",'0', -- ounit
"00","00","00",'0',"000",'0', -- aunit
"0000",'0', -- lunit
"00",'0','0','0','0','0','0','0', -- munit
'0',"000","000","00",'0' -- rest
);
189,10 → 192,10
constant c_dpath_dtmp_dres : slv2 := "10"; -- DTMP = DRES
constant c_dpath_dtmp_drese : slv2 := "11"; -- DTMP = DRESE
 
constant c_dpath_res_abox : slv3 := "000"; -- D/CRES = ABOX
constant c_dpath_res_dbox : slv3 := "001"; -- D/CRES = DBOX
constant c_dpath_res_lbox : slv3 := "010"; -- D/CRES = LBOX
constant c_dpath_res_mbox : slv3 := "011"; -- D/CRES = MBOX
constant c_dpath_res_ounit : slv3 := "000"; -- D/CRES = OUNIT
constant c_dpath_res_aunit : slv3 := "001"; -- D/CRES = AUNIT
constant c_dpath_res_lunit : slv3 := "010"; -- D/CRES = LUNIT
constant c_dpath_res_munit : slv3 := "011"; -- D/CRES = MUNIT
constant c_dpath_res_vmdout : slv3 := "100"; -- D/CRES = VMDOUT
constant c_dpath_res_fpdout : slv3 := "101"; -- D/CRES = FPDOUT
constant c_dpath_res_ireg : slv3 := "110"; -- D/CRES = IREG
229,13 → 232,13
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
updt_dstadsrc : slbit; -- update dsrc in dsta flow
dbox_srcmod : slv2; -- dbox src port modifier
dbox_dstmod : slv2; -- dbox dst port modifier
dbox_cimod : slv2; -- dbox ci port modifier
dbox_cc1op : slbit; -- dbox use cc modes (1 op instruction)
dbox_ccmode : slv3; -- dbox cc port mode
lbox_func : slv4; -- lbox function
mbox_func : slv2; -- mbox function
aunit_srcmod : slv2; -- aunit src port modifier
aunit_dstmod : slv2; -- aunit dst port modifier
aunit_cimod : slv2; -- aunit ci port modifier
aunit_cc1op : slbit; -- aunit use cc modes (1 op instruction)
aunit_ccmode : slv3; -- aunit cc port mode
lunit_func : slv4; -- lunit function
munit_func : slv2; -- munit function
res_sel : slv3; -- result bus (cres/dres) select
fork_op : slv4; -- op fork after idecode state
fork_srcr : slv2; -- src-read fork after idecode state
254,8 → 257,8
constant decode_stat_init : decode_stat_type := (
'0','0','0','0','0','0','0','0','0', -- is_
'0','0',"000",'0','0', -- op_, trap_, force_, updt_
"00","00","00",'0',"000", -- dbox_
"0000","00","000", -- lbox_, mbox_, res_
"00","00","00",'0',"000", -- aunit_
"0000","00","000", -- lunit_, munit_, res_
"0000","00","00","00","0000","000", -- fork_
'0','0','0','0','0', -- do_fork_
'0' -- do_pref_
694,7 → 697,7
constant c_psr_func_wrti : slv3 := "011"; -- rti mode: protect modes
constant c_psr_func_wall : slv3 := "100"; -- write all fields
 
component pdp11_abox is -- arithmetic unit for addresses (abox)
component pdp11_ounit is -- offset adder for addresses (ounit)
port (
DSRC : in slv16; -- 'src' data for port A
DDST : in slv16; -- 'dst' data for port A
712,17 → 715,17
);
end component;
 
constant c_abox_asel_ddst : slv2 := "00"; -- A = DDST
constant c_abox_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_abox_asel_pc : slv2 := "10"; -- A = PC
constant c_abox_asel_dtmp : slv2 := "11"; -- A = DTMP
constant c_ounit_asel_ddst : slv2 := "00"; -- A = DDST
constant c_ounit_asel_dsrc : slv2 := "01"; -- A = DSRC
constant c_ounit_asel_pc : slv2 := "10"; -- A = PC
constant c_ounit_asel_dtmp : slv2 := "11"; -- A = DTMP
 
constant c_abox_bsel_const : slv2 := "00"; -- B = CONST
constant c_abox_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_abox_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_abox_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
constant c_ounit_bsel_const : slv2 := "00"; -- B = CONST
constant c_ounit_bsel_vmdout : slv2 := "01"; -- B = VMDOUT
constant c_ounit_bsel_ireg6 : slv2 := "10"; -- B = 2*IREG(6bit)
constant c_ounit_bsel_ireg8 : slv2 := "11"; -- B = 2*IREG(8bit,sign-extend)
 
component pdp11_dbox is -- arithmetic unit for data (dbox)
component pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
738,22 → 741,22
);
end component;
 
constant c_dbox_mod_pass : slv2 := "00"; -- pass data
constant c_dbox_mod_inv : slv2 := "01"; -- invert data
constant c_dbox_mod_zero : slv2 := "10"; -- set to 0
constant c_dbox_mod_one : slv2 := "11"; -- set to 1
constant c_aunit_mod_pass : slv2 := "00"; -- pass data
constant c_aunit_mod_inv : slv2 := "01"; -- invert data
constant c_aunit_mod_zero : slv2 := "10"; -- set to 0
constant c_aunit_mod_one : slv2 := "11"; -- set to 1
 
-- the c_dbox_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_dbox_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_dbox_ccmode_com : slv3 := "001"; -- do com instruction
constant c_dbox_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_dbox_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_dbox_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_dbox_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_dbox_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_dbox_ccmode_tst : slv3 := "111"; -- do tst instruction
-- the c_aunit_ccmode codes follow exactly the opcode format (bit 8:6)
constant c_aunit_ccmode_clr : slv3 := "000"; -- do clr instruction
constant c_aunit_ccmode_com : slv3 := "001"; -- do com instruction
constant c_aunit_ccmode_inc : slv3 := "010"; -- do inc instruction
constant c_aunit_ccmode_dec : slv3 := "011"; -- do dec instruction
constant c_aunit_ccmode_neg : slv3 := "100"; -- do neg instruction
constant c_aunit_ccmode_adc : slv3 := "101"; -- do adc instruction
constant c_aunit_ccmode_sbc : slv3 := "110"; -- do sbc instruction
constant c_aunit_ccmode_tst : slv3 := "111"; -- do tst instruction
component pdp11_lbox is -- logic unit for data (lbox)
component pdp11_lunit is -- logic unit for data (lunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
765,19 → 768,19
);
end component;
 
constant c_lbox_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lbox_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lbox_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lbox_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lbox_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lbox_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lbox_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lbox_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lbox_func_sxt : slv4 := "1000"; -- SXT
constant c_lbox_func_swap : slv4 := "1001"; -- SWAB
constant c_lbox_func_xor : slv4 := "1010"; -- XOR
constant c_lunit_func_asr : slv4 := "0000"; -- ASR/ASRB ??? recheck coding !!
constant c_lunit_func_asl : slv4 := "0001"; -- ASL/ASLB
constant c_lunit_func_ror : slv4 := "0010"; -- ROR/RORB
constant c_lunit_func_rol : slv4 := "0011"; -- ROL/ROLB
constant c_lunit_func_bis : slv4 := "0100"; -- BIS/BISB
constant c_lunit_func_bic : slv4 := "0101"; -- BIC/BICB
constant c_lunit_func_bit : slv4 := "0110"; -- BIT/BITB
constant c_lunit_func_mov : slv4 := "0111"; -- MOV/MOVB
constant c_lunit_func_sxt : slv4 := "1000"; -- SXT
constant c_lunit_func_swap : slv4 := "1001"; -- SWAB
constant c_lunit_func_xor : slv4 := "1010"; -- XOR
 
component pdp11_mbox is -- mul/div unit for data (mbox)
component pdp11_munit is -- mul/div unit for data (munit)
port (
CLK : in slbit; -- clock
DSRC : in slv16; -- 'src' data in
803,10 → 806,10
);
end component;
 
constant c_mbox_func_mul : slv2 := "00"; -- MUL
constant c_mbox_func_div : slv2 := "01"; -- DIV
constant c_mbox_func_ash : slv2 := "10"; -- ASH
constant c_mbox_func_ashc : slv2 := "11"; -- ASHC
constant c_munit_func_mul : slv2 := "00"; -- MUL
constant c_munit_func_div : slv2 := "01"; -- DIV
constant c_munit_func_ash : slv2 := "10"; -- ASH
constant c_munit_func_ashc : slv2 := "11"; -- ASHC
 
component pdp11_mmu_sadr is -- mmu SAR/SDR register set
port (
1046,8 → 1049,8
ROW3 : in slv10; -- led row 3 (10 leds, bottom)
SWOPT : out slv8; -- option pattern from du
SWOPT_RDY : out slbit; -- marks update of swopt
DU_CLK : out slbit; -- DU: clk
DU_FRAME : out slbit; -- DU: frame
DU_SCLK : out slbit; -- DU: sclk
DU_SS_N : out slbit; -- DU: ss_n
DU_MOSI : out slbit; -- DU: mosi (master out, slave in)
DU_MISO : in slbit -- DU: miso (master in, slave out)
);
1074,7 → 1077,7
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RB_STAT : out slv3; -- rbus: status flags
RRI_LAM : out slbit; -- remote attention
RB_LAM : out slbit; -- remote attention
CPU_RESET : out slbit; -- cpu master reset
CP_CNTL : out cp_cntl_type; -- console control port
CP_ADDR : out cp_addr_type; -- console address port
/trunk/rtl/w11a/pdp11_ounit.vbom
0,0 → 1,5
# libs
../vlib/slvtypes.vhd
pdp11.vbom
# design
pdp11_ounit.vhd
/trunk/rtl/w11a/pdp11_sys70.vhd
1,6 → 1,6
-- $Id: pdp11_sys70.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: pdp11_sys70.vhd 333 2010-10-17 21:18:33Z mueller $
--
-- Copyright 2008- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,9 → 18,11
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-17 333 1.1 use ibus V2 interface
-- 2008-08-22 161 1.0.1 use iblib
-- 2008-04-20 137 1.0 Initial version
------------------------------------------------------------------------------
51,10 → 53,13
constant ibaddr_sysid : slv16 := conv_std_logic_vector(8#177764#,16);
 
type regs_type is record -- state registers
ibsel_mbrk : slbit; -- ibus select mbrk
ibsel_sysid : slbit; -- ibus select sysid
mbrk : slv8; -- status of mbrk register
end record regs_type;
 
constant regs_init : regs_type := (
'0','0', -- ibsel_*
mbrk=>(others=>'0') -- mbrk
);
 
77,47 → 82,47
proc_next: process (R_REGS, IB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibsel_mbrk : slbit := '0'; -- mbrk
variable ibsel_sysid : slbit := '0'; -- sysid
variable ibsel : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibw0 : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
 
ibsel_mbrk := '0';
ibsel_sysid := '0';
ibsel := '0';
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
 
if IB_MREQ.req = '1' then
-- ibus address decoder
n.ibsel_mbrk := '0';
n.ibsel_sysid := '0';
if IB_MREQ.aval = '1' then
if IB_MREQ.addr = ibaddr_mbrk(12 downto 1) then
ibsel_mbrk := '1';
n.ibsel_mbrk := '1';
end if;
if IB_MREQ.addr = ibaddr_sysid(12 downto 1) then
ibsel_sysid := '1';
n.ibsel_sysid := '1';
end if;
end if;
 
ibsel := ibsel_mbrk or ibsel_sysid;
end if;
if ibsel_mbrk = '1' then
-- ibus transactions
if r.ibsel_mbrk = '1' then
idout(r.mbrk'range) := r.mbrk;
end if;
if ibsel_sysid = '1' then
if r.ibsel_sysid = '1' then
idout := conv_std_logic_vector(8#123456#,16);
end if;
 
if ibsel_mbrk='1' and IB_MREQ.we='1' and IB_MREQ.be0='1' then
if r.ibsel_mbrk='1' and ibw0='1' then
n.mbrk := IB_MREQ.din(n.mbrk'range);
end if;
 
N_REGS <= n;
 
IB_SRES.ack <= ibsel;
IB_SRES.dout <= idout;
IB_SRES.ack <= (r.ibsel_mbrk or r.ibsel_sysid) and ibreq;
IB_SRES.busy <= '0';
IB_SRES.dout <= idout;
 
end process proc_next;
/trunk/rtl/w11a/pdp11_psr.vbom
2,5 → 2,7
../vlib/slvtypes.vhd
../ibus/iblib.vhd
pdp11.vbom
# components
../ibus/ib_sel.vbom
# design
pdp11_psr.vhd
/trunk/rtl/w11a/pdp11_ubmap.vbom
6,5 → 6,6
# components
[ghdl,isim]../vlib/memlib/ram_1swar_gen.vbom
[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom
../ibus/ib_sel.vbom
# design
pdp11_ubmap.vhd
/trunk/rtl/vlib/simlib/simlib.vhd
1,6 → 1,6
-- $Id: simlib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: simlib.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2006-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,9 → 18,11
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-13 338 1.3.6 add simclkcnt; xx.x ns time in writetimestamp()
-- 2008-03-24 129 1.3.5 CLK_CYCLE now 31 bits
-- 2008-03-02 121 1.3.4 added readempty (to discard rest of line)
-- 2007-12-27 106 1.3.3 added simclk2v
220,6 → 222,13
);
end component;
 
component simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out slv31 -- clock cycle number
);
end component;
 
end package simlib;
 
-- ----------------------------------------------------------------------------
1049,9 → 1058,22
clkcyc: in slv31;
str: in string := null_string) is
 
variable t_nsec : integer := 0;
variable t_psec : integer := 0;
variable t_dnsec : integer := 0;
 
begin
 
write(L, now, right, 12);
t_nsec := now / 1 ns;
t_psec := (now - t_nsec * 1 ns) / 1 ps;
t_dnsec := t_psec/100;
-- write(L, now, right, 12);
write(L, t_nsec, right, 8);
write(L,'.');
write(L, t_dnsec, right, 1);
write(L, string'(" ns"));
write(L, conv_integer(unsigned(clkcyc)), right, 7);
if str /= null_string then
write(L, str);
/trunk/rtl/vlib/simlib/simclk.vhd
1,4 → 1,4
-- $Id: simclk.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: simclk.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
19,6 → 19,7
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
--
-- Revision History:
-- Date Rev Version Comment
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
45,7 → 46,7
architecture sim of simclk is
begin
 
clk_proc: process
proc_clk: process
constant clock_halfperiod : time := PERIOD/2;
variable icycle : slv31 := (others=>'0');
begin
73,6 → 74,6
wait; -- endless wait, simulator will stop
end process;
end process proc_clk;
 
end sim;
/trunk/rtl/vlib/simlib/simclkcnt.vhd
0,0 → 1,55
-- $Id: simclkcnt.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simclkcnt - sim
-- Description: test bench system clock cycle counter
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-13 72 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
 
entity simclkcnt is -- test bench system clock cycle counter
port (
CLK : in slbit; -- clock
CLK_CYCLE : out slv31 -- clock cycle number
);
end entity simclkcnt;
 
architecture sim of simclkcnt is
signal R_CLKCNT : slv31 := (others=>'0');
begin
 
proc_clk: process (CLK)
begin
 
if CLK'event and CLK='1' then
R_CLKCNT <= unsigned(R_CLKCNT) + 1;
end if;
end process proc_clk;
 
CLK_CYCLE <= R_CLKCNT;
end sim;
/trunk/rtl/vlib/simlib/simclkcnt.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
# components
# design
simclkcnt.vhd
/trunk/rtl/vlib/genlib/clkdivce.vhd
1,6 → 1,6
-- $Id: clkdivce.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: clkdivce.vhd 341 2010-11-27 23:05:43Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
18,7 → 18,7
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2008-01-20 112 1.0.2 rename clkgen->clkdivce; remove SYS_CLK port
/trunk/rtl/vlib/Makefile.ghdl
1,4 → 1,4
# $Id: Makefile.ghdl 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile.ghdl 284 2010-04-26 20:55:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
/trunk/rtl/vlib/Makefile.xflow
1,7 → 1,8
# $Id: Makefile.xflow 317 2010-07-22 19:36:56Z mueller $
# $Id: Makefile.xflow 341 2010-11-27 23:05:43Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2010-11-26 340 1.5.8 fix path for .opt defaults (now rtl/vlib)
# 2010-05-06 289 1.5.7 add xilinx_tsim_xon support
# 2010-04-24 282 1.5.6 add %.impact rule to run impact_wrapper
# 2010-04-17 278 1.4.5 add '|| true' after grep in diag summary to prevent
69,8 → 70,8
(cd ./ise; vbomconv --xst_prj ../$< > $*.prj)
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${RETROBASE}/vlib/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/vlib/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${RETROBASE}/rtl/vlib/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/vlib/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
89,8 → 90,8
(cd ./ise; vbomconv --xst_prj ../$< > $*.prj)
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${RETROBASE}/vlib/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/vlib/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${RETROBASE}/rtl/vlib/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/vlib/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
117,8 → 118,8
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
if [ -r $*.ucf ]; then cp -p $*.ucf ./ise; fi
if [ -r ${RETROBASE}/vlib/${XFLOWOPT_IMP} ]; then \
cp ${RETROBASE}/vlib/${XFLOWOPT_IMP} ./ise; fi
if [ -r ${RETROBASE}/rtl/vlib/${XFLOWOPT_IMP} ]; then \
cp ${RETROBASE}/rtl/vlib/${XFLOWOPT_IMP} ./ise; fi
if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi
${XFLOW} -wd ise -implement ${XFLOWOPT_IMP} $<
(cd ./ise; chmod -x *.* )
/trunk/rtl/vlib/rri/tb/rritb_core_dcm.vbom
0,0 → 1,13
# libs
../../slvtypes.vhd
../../simlib/simlib.vhd
../../simlib/simbus.vhd
rritblib.vhd
vhpi_rriext.vhd
# components
../../simlib/simclk.vbom
../../simlib/simclkcnt.vbom
# vhpi
cext_rriext.c
# design
rritb_core_dcm.vhd
/trunk/rtl/vlib/rri/tb/tb_rri_stim.dat
1,4 → 1,4
# $Id: tb_rri_stim.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tb_rri_stim.dat 303 2010-06-12 06:12:45Z mueller $
#
# Revision History:
# Date Rev Version Comment
/trunk/rtl/vlib/rri/tb/rritblib.vhd
1,4 → 1,4
-- $Id: rritblib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: rritblib.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
16,9 → 16,10
-- Description: Remote Register Interface test environment components
--
-- Dependencies: -
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.29
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-13 338 2.5.2 add rritb_core_dcm
-- 2010-06-26 309 2.5.1 add rritb_sres_or_mon
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-05 301 2.1.2 renamed _rpmon -> _rbmon
134,6 → 135,23
);
end component;
 
component rritb_core_dcm is -- dcm aware core of rri/cext based tb's
generic (
CLKOSC_PERIOD : time := 20 ns; -- clock osc period
CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLKOSC : out slbit; -- clock osc
CLKSYS : in slbit; -- DCM derived system clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end component;
 
component rricp_rp is -- rri comm->reg port aif forwarder
-- implements rricp_aif, uses rrirp_aif
port (
/trunk/rtl/vlib/rri/tb/tbw.dat
1,4 → 1,4
# $Id: tbw.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tbw.dat 81 2007-09-09 20:50:42Z mueller $
#
[tb_rri_core]
tb_rri_stim = tb_rri_stim.dat
/trunk/rtl/vlib/rri/tb/rritb_core_dcm.vhd
0,0 → 1,283
-- $Id: rritb_core_dcm.vhd 339 2010-11-22 21:20:51Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rritb_core_dcm - sim
-- Description: DCM aware core for a rri and cext based test bench
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
--
-- To test: generic, any rri/cext based target
--
-- Target Devices: generic
-- Tool versions: 11.4-12.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-13 338 1.1 First DCM aware version, cloned from rritb_core
-- 2010-06-05 301 1.1.2 renamed .rpmon -> .rbmon
-- 2010-05-02 287 1.1.1 rename config command .sdata -> .sinit;
-- use sbcntl_sbf_(cp|rp)mon defs, use rritblib;
-- 2010-04-25 283 1.1 new clk handling in proc_stim, wait period-setup
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use std.textio.all;
 
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.rritblib.all;
use work.vhpi_rriext.all;
 
entity rritb_core_dcm is -- dcm aware core of rri/cext based tb's
generic (
CLKOSC_PERIOD : time := 20 ns; -- clock osc period
CLKOSC_OFFSET : time := 200 ns; -- clock osc offset (time to start clk)
SETUP_TIME : time := 5 ns; -- setup time
C2OUT_TIME : time := 10 ns); -- clock to output time
port (
CLKOSC : out slbit; -- clock osc
CLKSYS : in slbit; -- DCM derived system clock
RX_DATA : out slv8; -- read data (data ext->tb)
RX_VAL : out slbit; -- read data valid (data ext->tb)
RX_HOLD : in slbit; -- read data hold (data ext->tb)
TX_DATA : in slv8; -- write data (data tb->ext)
TX_ENA : in slbit -- write data enable (data tb->ext)
);
end rritb_core_dcm;
 
architecture sim of rritb_core_dcm is
 
signal CLK_STOP : slbit := '0';
begin
 
CLKGEN : simclk
generic map (
PERIOD => CLKOSC_PERIOD,
OFFSET => CLKOSC_OFFSET)
port map (
CLK => CLKOSC,
CLK_CYCLE => open,
CLK_STOP => CLK_STOP
);
 
CLKCNT : simclkcnt
port map (
CLK => CLKSYS,
CLK_CYCLE => SB_CLKCYCLE
);
proc_conf: process
file fconf : text open read_mode is "tb_rriext_conf";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable ien : slbit := '0';
variable ibit : integer := 0;
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
SB_CNTL <= (others=>'L');
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
file_loop: while not endfile(fconf) loop
readline (fconf, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
 
when ".scntl" => -- .scntl
read_ea(iline, ibit);
read_ea(iline, ien);
assert (ibit>=SB_CNTL'low and ibit<=SB_CNTL'high)
report "assert bit number in range of SB_CNTL"
severity failure;
if ien = '1' then
SB_CNTL(ibit) <= 'H';
else
SB_CNTL(ibit) <= 'L';
end if;
 
when ".cpmon" => -- .cpmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_cpmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_cpmon) <= 'L';
end if;
 
when ".rbmon" => -- .rbmon
read_ea(iline, ien);
if ien = '1' then
SB_CNTL(sbcntl_sbf_rbmon) <= 'H';
else
SB_CNTL(sbcntl_sbf_rbmon) <= 'L';
end if;
 
when ".sinit" => -- .sinit
readgen_ea(iline, iaddr, 8);
readgen_ea(iline, idata, 8);
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= 'H';
wait for 0 ns;
SB_VAL <= 'L';
SB_ADDR <= (others=>'L');
SB_DATA <= (others=>'L');
wait for 0 ns;
 
when others => -- bad command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
 
testempty_ea(iline);
end loop; -- file_loop:
 
wait; -- halt process here
end process proc_conf;
proc_stim: process
variable t_lastclksys : time := 0 ns;
variable clksys_period : time := 0 ns;
variable icycle : integer := 0;
variable irxint : integer := 0;
variable irxslv : slv24 := (others=>'0');
variable ibit : integer := 0;
variable oline : line;
variable r_sb_cntl : slv16 := (others=>'Z');
variable iaddr : slv8 := (others=>'0');
variable idata : slv16 := (others=>'0');
begin
 
-- just wait for 10 CLKSYS cycles
for i in 1 to 10 loop
wait until CLKSYS'event and CLKSYS='1';
clksys_period := now - t_lastclksys;
t_lastclksys := now;
end loop; -- i
stim_loop: loop
wait until CLKSYS'event and CLKSYS='1';
clksys_period := now - t_lastclksys;
t_lastclksys := now;
wait for clksys_period-SETUP_TIME;
 
SB_ADDR <= (others=>'Z');
SB_DATA <= (others=>'Z');
 
icycle := conv_integer(unsigned(SB_CLKCYCLE));
RX_VAL <= '0';
 
if RX_HOLD = '0' then
irxint := cext_getbyte(icycle);
if irxint >= 0 then
if irxint <= 16#ff# then -- normal data byte
RX_DATA <= conv_std_logic_vector(irxint, 8);
RX_VAL <= '1';
elsif irxint >= 16#1000000# then -- out-of-band message
irxslv := conv_std_logic_vector(irxint, 24);
iaddr := irxslv(23 downto 16);
idata := irxslv(15 downto 0);
writetimestamp(oline, SB_CLKCYCLE, ": OOB-MSG");
write(oline, irxslv(23 downto 16), right, 9);
write(oline, irxslv(15 downto 8), right, 9);
write(oline, irxslv( 7 downto 0), right, 9);
write(oline, string'(" : "));
writeoct(oline, iaddr, right, 3);
writeoct(oline, idata, right, 7);
writeline(output, oline);
if unsigned(iaddr) = 0 then
ibit := conv_integer(unsigned(idata(15 downto 8)));
r_sb_cntl(ibit) := idata(0);
else
SB_ADDR <= iaddr;
SB_DATA <= idata;
SB_VAL <= '1';
wait for 0 ns;
SB_VAL <= 'Z';
wait for 0 ns;
end if;
end if;
elsif irxint = -1 then -- end-of-file seen
exit stim_loop;
else
report "cext_getbyte error: " & integer'image(-irxint)
severity failure;
end if;
end if;
SB_CNTL <= r_sb_cntl;
end loop;
-- just wait for 50 CLKSYS cycles
for i in 1 to 50 loop
wait until CLKSYS'event and CLKSYS='1';
end loop; -- i
CLK_STOP <= '1';
writetimestamp(oline, SB_CLKCYCLE, ": DONE ");
writeline(output, oline);
 
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
 
end process proc_stim;
 
proc_moni: process
variable itxdata : integer := 0;
variable itxrc : integer := 0;
variable oline : line;
begin
loop
wait until CLKSYS'event and CLKSYS='1';
wait for C2OUT_TIME;
if TX_ENA = '1' then
itxdata := conv_integer(unsigned(TX_DATA));
itxrc := cext_putbyte(itxdata);
assert itxrc=0
report "cext_putbyte error: " & integer'image(itxrc)
severity failure;
end if;
 
end loop;
end process proc_moni;
 
end sim;
/trunk/rtl/vlib/rri/tb/rritb_sres_or_mon.vhd
1,4 → 1,4
-- $Id: rritb_sres_or_mon.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: rritb_sres_or_mon.vhd 336 2010-11-06 18:28:27Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
20,6 → 20,7
-- Tool versions: ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-28 336 1.0.1 log errors only if now>0ns (drop startup glitches)
-- 2010-06-26 309 1.0 Initial version
------------------------------------------------------------------------------
 
80,7 → 81,7
if RB_SRES_3.dout /= dzero then ndout := ndout + 1; end if;
if RB_SRES_4.dout /= dzero then ndout := ndout + 1; end if;
 
if nack>1 or nbusy>1 or nerr>1 or ndout>1 then
if now > 0 ns and (nack>1 or nbusy>1 or nerr>1 or ndout>1) then
write(oline, now, right, 12);
if nack > 1 then
write(oline, string'(" #ack="));
/trunk/rtl/vlib/Makefile
1,4 → 1,4
# $Id: Makefile 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile 52 2007-06-10 17:14:53Z mueller $
#
#
include Makefile.xflow
/trunk/rtl/vlib/Makefile.isim
1,4 → 1,4
# $Id: Makefile.isim 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile.isim 284 2010-04-26 20:55:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
/trunk/rtl/vlib/Makefile.xflow_cpld
1,4 → 1,4
# $Id: Makefile.xflow_cpld 311 2010-06-30 17:52:37Z mueller $
# $Id: Makefile.xflow_cpld 268 2010-03-14 22:41:18Z mueller $
#
# Revision History:
# Date Rev Version Comment
/trunk/rtl/vlib/serport/tb/tb_serport_uart_rx_stim.dat
1,4 → 1,4
# $Id: tb_serport_uart_rx_stim.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tb_serport_uart_rx_stim.dat 91 2007-10-21 18:59:14Z mueller $
#
#
C setting rate=1 -> CLKDIV=0 ------------------------------------------------
/trunk/rtl/vlib/serport/tb/tb_serport_uart_rxtx_stim.dat
1,4 → 1,4
# $Id: tb_serport_uart_rxtx_stim.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tb_serport_uart_rxtx_stim.dat 91 2007-10-21 18:59:14Z mueller $
#
#
C ----------------------------------------------------------------------------
/trunk/rtl/vlib/serport/tb/tb_serport_autobaud_stim.dat
1,4 → 1,4
# $Id: tb_serport_autobaud_stim.dat 311 2010-06-30 17:52:37Z mueller $
# $Id: tb_serport_autobaud_stim.dat 91 2007-10-21 18:59:14Z mueller $
#
#
C ----------------------------------------------------------------------------
/trunk/rtl/vlib/xlib/dcm_sp_sfs_gsim.vhd
0,0 → 1,118
-- $Id: dcm_sp_sfs_gsim.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: dcm_sp_sfs - sim
-- Description: DCM_SP as 'simple freq. synthesis'
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-12 338 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.slvtypes.all;
 
entity dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis'
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sp_sfs;
 
 
architecture sim of dcm_sp_sfs is
 
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
 
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
 
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * CLKFX_DIVIDE) / CLKFX_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "dcm_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := CLKFX_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
 
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
 
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
 
loop
wait until CLK_DIVPULSE = '1';
 
for i in 1 to CLKFX_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= CLKFX_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
 
end loop;
end process proc_clkout;
 
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;
/trunk/rtl/vlib/xlib/dcm_sp_sfs_unisim.vhd
0,0 → 1,84
-- $Id: dcm_sp_sfs_unisim.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: dcm_sp_sfs - syn
-- Description: DCM_SP as 'simple freq. synthesis'
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-12 338 1.0.1 drop SB_CLK generic; allow DIV=1,MUL=1 without DCM
-- 2010-11-07 337 1.0 Initial version
------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.ALL;
 
use work.slvtypes.all;
 
entity dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis'
generic (
CLKFX_DIVIDE : positive := 1; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 1; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end dcm_sp_sfs;
 
 
architecture syn of dcm_sp_sfs is
 
begin
 
assert (CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1) or CLKFX_MULTIPLY>=2
report "assert((FX_DIV=1 and FX_MULT)=1 or FX_MULT>=2"
severity failure;
 
DCM0: if CLKFX_DIVIDE=1 and CLKFX_MULTIPLY=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate DCM0;
 
DCM1: if CLKFX_MULTIPLY >= 2 generate
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => CLKFX_DIVIDE,
CLKFX_MULTIPLY => CLKFX_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE")
port map (
CLKIN => CLKIN,
CLKFX => CLKFX,
LOCKED => LOCKED
);
 
end generate DCM1;
end syn;
/trunk/rtl/vlib/xlib/dcm_sp_sfs_gsim.vbom
0,0 → 1,4
# libs
../slvtypes.vhd
# design
dcm_sp_sfs_gsim.vhd
/trunk/rtl/vlib/xlib/dcm_sp_sfs_unisim.vbom
0,0 → 1,5
# libs
../slvtypes.vhd
@lib:unisim
# design
dcm_sp_sfs_unisim.vhd
/trunk/rtl/vlib/xlib/xlib.vhd
1,6 → 1,6
-- $Id: xlib.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: xlib.vhd 338 2010-11-13 22:19:25Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
19,6 → 19,7
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2010-11-07 337 1.0.5 add dcm_sp_sfs
-- 2008-05-23 149 1.0.4 add iob_io(_gen)
-- 2008-05-22 148 1.0.3 add iob_keeper(_gen);
-- 2008-05-18 147 1.0.2 add PULL generic to iob_reg_io(_gen)
151,4 → 152,16
);
end component;
 
component dcm_sp_sfs is -- DCM_SP as 'simple freq. synthesis'
generic (
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock divide (2-32)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- dcm locked
);
end component;
 
end xlib;
/trunk/doc/README.txt
1,4 → 1,4
# $Id: README.txt 318 2010-07-23 18:28:40Z mueller $
# $Id: README.txt 341 2010-11-27 23:05:43Z mueller $
 
Release notes for w11a
 
48,10 → 48,38
 
3. Change Log -------------------------------------------------------------
 
- trunk (current development snapshot) -----------------------
- trunk (2010-11-28: svn rev 8(oc) 341(wfjm); untagged w11a_V0.51)
 
indentical to w11a_V0.5
- Changes
- module renames:
- in future 'box' is used for large autonomous blocks, therefore use
the term unit for purely sequential logic modules:
pdp11_abox -> pdp11_ounit
pdp11_dbox -> pdp11_aunit
pdp11_lbox -> pdp11_lunit
pdp11_mbox -> pdp11_munit
 
- signal renames:
- renamed RRI_LAM -> RB_LAM in all ibus devices
- renamed CLK -> I_CLK50 in all top level nexys2 and s3board designs
 
- migrate to ibus protocol verion 2
- in ib_mreq use now aval,re,we,rmw instead of req,we,dip
- basic ibus transaction now takes 2 cycles, one for address select, one
for data exchange. This avoids too long logic paths in ibus sector.
 
- New features
- ibus
- added ib_sres_or_mon to check for miss-behaving ibus devices
- added ib_sel to encapsulate address select logic
- nexys2 systems
- now DCM derived system clock supported
- sys_gen/w11a/nexys2
- sys_w11a_n2 now runs with 58 MHz clksys
 
- Bug fixes
- rtl/vlib/Makefile.xflow: use default .opt files under rtl/vlib again.
 
- w11a_V0.5 (2010-07-23) -------------------------------------
 
Initial release with
/trunk/doc/man/man5/vbom.5
0,0 → 1,107
.\" -*- nroff -*-
.\" $Id: vbom.5 320 2010-07-30 19:35:01Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH VBOM 2010-07-25 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbom \- 'vhdl bill of material' file format
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
These files describe the sources needed to build a
.I vhdl
module. The source files are either given directly in case of libraries
or via other
.IR vbom 's
in case of instantiated components. They are used by
.BR vbomconv (1)
to build project descriptions for synthesis and simulation tools.
 
The format has four types of lines:
.
.\" ----------------------------------------------
.TP
.B comments
each line starting with
.B #
is treated as comment and ignored.
.
.\" ----------------------------------------------
.TP
.B file names
either source files with a
.I '.vhd'
file type or nested
.IR vbom 's
with a
.I '.vbom'
file type. The must be given as relative path name
from the directory the
.I vbom
file is located in. Absolute path names are not allowed, nor is expansion of
environment variables.
.
.\" ----------------------------------------------
.TP
.B logical names
A logical name can be defined with
.EX
<lname> = <filename>
.EE
The first definition of a logical name encountered in the traversal of the
.IR vbom 's
by
.BR vbomconv (1)
is taken, all later definitions are ignored.
 
A logical name can be used with
.EX
<lname> : <filename>
.EE
If it wasn't
 
 
Again, the filenames, either of type
.I vhd
or
.IR vbom ,
must be given as relative path name from the directory the
.I vbom
file is located in.
 
The definition clause just sets up the logical name for later usage.
The usage clause
 
.\" ----------------------------------------------
.TP
.B directives
 
 
 
The format is simple, essentially a list of file names, either
source files with a
.I '.vhd'
file type or nested
.IR vbom 's
with a
.I '.vbom'
file type. Lines starting with
.B #
are treated as comments.
 
 
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR vbomconv (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/trunk/doc/man/man1/set_ftdi_lat.1
0,0 → 1,70
.\" -*- nroff -*-
.\" $Id: set_ftdi_lat.1 321 2010-08-01 19:43:39Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH SET_FTDI_LAT 1 2010-07-24 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
set_ftdi_lat \- set latency timer in FTDI USB UART or FIFO
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY set_ftdi_lat
.RI [ dev ]
.RI [ time ]
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
FTDI USB UART or FIFO adapters of type FT232, FT245, and other similar
models have a latency timer which controls the maximal time between reception
of a byte by the UART or FIFO and the emission of a USB frame. The default
is 16 msec and can lead to unsatisfactory response times.
The
.B set_ftdi_lat
script allows to set this latency timer via a node in the
.I /sys
virtual file system, specifically
.IP "" 4
.I /sys/bus/usb-serial/devices/ttyUSBn/latency_timer
.
.PP
The first optional argument
.I dev
allows to specify the device name in the form
.I USBn
with the default
.IR USB0 .
The second optional argument
.I
time
allows to specify the new value of the latency timer, given in msec.
Default is 1 msec.
.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If device
.RI tty dev
is not found or the entry in
.I /sys
is not writable an exit status 1 is returned.
 
.\" ------------------------------------------------------------------
.SH EXAMPLES
In general the command is given via
.BR sudo ,
like
.EX
sudo set_ftdi_lat USB0 1
.EE
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR sudo (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/trunk/doc/man/man1/rm_dep.1
0,0 → 1,43
.\" -*- nroff -*-
.\" $Id: rm_dep.1 321 2010-08-01 19:43:39Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH RM_DEP 1 2010-07-24 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
rm_dep \- remove vbomconv generated dependency files in a directory tree
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY rm_dep
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.B rm_dep
removes all
.B vbomconv
generated dependency rule files from the whole directory tree starting
at the current working directory. Specifically, it removes
.PP
.EX
*.dep_ghdl
*.dep_isim
*.dep_xst
*.dep_ucf_cpp
.EE
.PP
The script produces a log to
.I stdout
indicating all removed files, the messages are generated by '\fIrm -v\fP'.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR vbomconv (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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