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URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

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    /wb2axip
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Rev 2 → Rev 3

/trunk/rtl/wbm2axisp.v
28,7 → 28,7
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
57,7 → 57,8
// This is an int between 1-16
parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
parameter AW = 28, // Wishbone address width
parameter DW = 128 // Wishbone data width
parameter DW = 32, // Wishbone data width
parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
) (
input i_clk, // System clock
input i_reset,// Wishbone reset signal
77,8 → 78,8
// AXI write data channel signals
input i_axi_wd_wready, // Write data ready
output wire [C_AXI_ID_WIDTH-1:0] o_axi_wd_wid, // Write ID tag
output reg [DW-1:0] o_axi_wd_data, // Write data
output reg [DW/8-1:0] o_axi_wd_strb, // Write strobes
output reg [C_AXI_DATA_WIDTH-1:0] o_axi_wd_data, // Write data
output reg [C_AXI_DATA_WIDTH/8-1:0] o_axi_wd_strb, // Write strobes
output wire o_axi_wd_last, // Last write transaction
output reg o_axi_wd_valid, // Write valid
104,18 → 105,21
input [C_AXI_ID_WIDTH-1:0] i_axi_rd_bid, // Response ID
input [1:0] i_axi_rd_rresp, // Read response
input i_axi_rd_rvalid, // Read reponse valid
input [DW-1:0] i_axi_rd_data, // Read data
input [C_AXI_DATA_WIDTH-1:0] i_axi_rd_data, // Read data
input i_axi_rd_last, // Read last
output wire o_axi_rd_rready, // Read Response ready
 
// We'll share the clock and the reset
input i_wb_cyc, i_wb_stb, i_wb_we;
input [AW-1:0] i_wb_addr;
input [DW-1:0] i_wb_data;
output reg o_wb_ack;
output wire o_wb_stall;
output reg [DW-1:0] o_wb_data;
output reg o_wb_err;
input i_wb_cyc,
input i_wb_stb,
input i_wb_we,
input [AW-1:0] i_wb_addr,
input [DW-1:0] i_wb_data,
input [3:0] i_wb_sel,
output reg o_wb_ack,
output wire o_wb_stall,
output reg [DW-1:0] o_wb_data,
output reg o_wb_err
);
 
//*****************************************************************************
203,7 → 207,7
assign o_axi_wd_wid = transaction_id;
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wbdata };
o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
always @(posedge i_clk)
if (!o_wb_stall)
case(i_wb_addr[1:0])
230,9 → 234,23
localparam LGFIFOLN = C_AXI_ID_WIDTH;
localparam FIFOLN = (1<<LGFIFOLN);
// FIFO reorder buffer
reg [(DW-1):0] reorder_fifo_data [0:(FIFOLN-1)];
reg reorder_fifo_valid[0:(FIFOLN-1)];
reg reorder_fifo_err [0:(FIFOLN-1)];
reg [(LGFIFOLN-1):0] fifo_tail;
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
reg [(FIFOLN-1):0] reorder_fifo_valid;
reg [(FIFOLN-1):0] reorder_fifo_err;
reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
 
 
reg [1:0] low_addr;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
low_addr <= i_wb_addr[1:0];
always @(posedge i_clk)
if ((o_axi_rvalid)&&(i_axi_rready))
reorder_fifo_addr[o_axi_rid] <= low_addr;
 
 
wire [(LGFIFOLN-1):0] fifo_head;
assign fifo_head = transaction_id;
 
// Let's do some math to figure out where the FIFO head will
249,15 → 267,21
if ((i_axi_rd_rvalid)&&(o_axi_rd_rready))
begin
reorder_fifo_valid[i_axi_rd_bid] <= 1'b1;
reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_resp[1];
reorder_fifo_err[i_axi_rd_bid] <= i_axi_rd_rresp[1];
end
if ((i_axi_wd_bvalid)&&(o_axi_wd_bready))
begin
reorder_fifo_valid[i_axi_wd_bid] = 1'b1;
reorder_fifo_err[i_axi_wd_bid] = i_axi_wd_bresp[1];
reorder_fifo_valid[i_axi_wd_bid] <= 1'b1;
reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
end
 
o_wb_data <= reorder_fifo_data[fifo_tail];
case(reorder_fifo_addr[1:0])
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
endcase
 
if (reorder_fifo_valid[fifo_tail])
begin
o_wb_ack <= 1'b1;
280,6 → 304,7
end
end
 
reg r_fifo_full;
always @(posedge i_clk)
begin
if (!i_wb_cyc)
296,7 → 321,7
end
assign w_fifo_full = r_fifo_full;
end else begin
w_fifo_full = 1'b0;
assign w_fifo_full = 1'b0;
always @(posedge i_clk)
o_wb_data <= i_axi_rd_data;
always @(posedge i_clk)
304,9 → 329,9
||((i_axi_wd_bvalid)&&(o_axi_wd_bready));
always @(posedge i_clk)
o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
||((i_axi_rd_rvalid)&&(i_axi_rd_resp[1]))
||((i_axi_rd_rvalid)&&(i_axi_rd_rresp[1]))
||((i_axi_wd_bvalid)&&(i_axi_wd_bresp[1])));
end
end endgenerate
 
// Now, the difficult signal ... the stall signal
315,6 → 340,6
assign o_wb_stall = (i_wb_cyc)&&(
(w_fifo_full)
||((o_axi_wvalid)&&(!i_axi_wready))
||((o_axi_wd_valid)&&(!i_axi_wd_bready))
||((o_axi_wd_valid)&&(!i_axi_wd_wready))
||((o_axi_rvalid)&&(!i_axi_rready)));
endmodule
/trunk/rtl/Makefile
0,0 → 1,69
################################################################################
##
## Filename: Makefile
##
## Project: Pipelined Wishbone to AXI converter
##
## Purpose: To describe how to build the Verilator libraries from the
## RTL, for the purposes of trying to discover if they work.
## Any actual testing will be done from the code within the bench/cpp
## directory.
##
## Targets: The default target, all, builds the target test, which includes
## the libraries necessary for Verilator testing.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
##
all: test
YYMMDD=`date +%Y%m%d`
CXX := g++
FBDIR := .
VDIRFB:= $(FBDIR)/obj_dir
 
.PHONY: test
test: $(VDIRFB)/Vwbm2axisp__ALL.a
# test: $(VDIRFB)/Vaxim2wbsp__ALL.a
 
$(VDIRFB)/Vwbm2axisp__ALL.a: $(VDIRFB)/Vwbm2axisp.h $(VDIRFB)/Vwbm2axisp.cpp
$(VDIRFB)/Vwbm2axisp__ALL.a: $(VDIRFB)/Vwbm2axisp.mk
$(VDIRFB)/Vwbm2axisp.h $(VDIRFB)/Vwbm2axisp.cpp $(VDIRFB)/Vwbm2axisp.mk: wbm2axisp.v
 
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator -cc $*.v
 
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
cd $(VDIRFB); make -f V$*.mk
 
.PHONY: clean
clean:
rm -rf $(VDIRFB)/*.mk
rm -rf $(VDIRFB)/*.cpp
rm -rf $(VDIRFB)/*.h
rm -rf $(VDIRFB)/
 
/trunk/Makefile
0,0 → 1,65
################################################################################
##
## Filename: Makefile
##
## Project: Pipelined Wishbone to AXI converter
##
## Purpose: A master project makefile. It tries to build all targets
## within the project, mostly by directing subdirectory makes.
##
## Targets:
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http:##www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
.PHONY: all
all: archive rtl bench
# all: verilated sw bench bit
#
# Could also depend upon load, if desired, but not necessary
BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
NOTES := `find . -name "*.txt"` `find . -name "*.html"`
YYMMDD:=`date +%Y%m%d`
 
.PHONY: archive
archive:
tar --transform s,^,$(YYMMDD)-wb2axi/, -chjf $(YYMMDD)-wb2axi.tjz $(BENCH) $(RTL) $(NOTES)
 
.PHONY: verilated
verilated:
cd rtl ; $(MAKE) --no-print-directory
 
.PHONY: rtl
rtl: verilated
 
.PHONY: bench
bench: rtl
cd bench/cpp ; $(MAKE) --no-print-directory
 
.PHONY: doc
doc:
cd doc ; $(MAKE) --no-print-directory
 
 

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