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URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

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    from Rev 3 to Rev 4
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Rev 3 → Rev 4

/trunk/rtl/wbm2axisp.v
57,7 → 57,7
// This is an int between 1-16
parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
parameter AW = 28, // Wishbone address width
parameter DW = 32, // Wishbone data width
parameter DW = 128, // Wishbone data width
parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
) (
input i_clk, // System clock
115,7 → 115,7
input i_wb_we,
input [AW-1:0] i_wb_addr,
input [DW-1:0] i_wb_data,
input [3:0] i_wb_sel,
input [(DW/8-1):0] i_wb_sel,
output reg o_wb_ack,
output wire o_wb_stall,
output reg [DW-1:0] o_wb_data,
205,17 → 205,31
 
// Write data logic
assign o_axi_wd_wid = transaction_id;
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
always @(posedge i_clk)
if (!o_wb_stall)
case(i_wb_addr[1:0])
2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
endcase
 
generate
if (DW == 32)
begin
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wd_data <= { i_wb_data, i_wb_data, i_wb_data, i_wb_data };
always @(posedge i_clk)
if (!o_wb_stall)
case(i_wb_addr[1:0])
2'b00:o_axi_wd_strb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
2'b01:o_axi_wd_strb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
2'b10:o_axi_wd_strb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
2'b11:o_axi_wd_strb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
endcase
end else if (DW == 128)
begin
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wd_data <= i_wb_data;
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_wd_strb <= i_wb_sel;
end endgenerate
 
assign o_axi_wd_last = 1'b1;
always @(posedge i_clk)
o_axi_wd_valid <= ((!o_wb_stall)&&(i_wb_stb)&&(i_wb_we))
238,18 → 252,35
reg [(C_AXI_DATA_WIDTH-1):0] reorder_fifo_data [0:(FIFOLN-1)];
reg [(FIFOLN-1):0] reorder_fifo_valid;
reg [(FIFOLN-1):0] reorder_fifo_err;
reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
 
if (DW == 32)
begin
reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
 
reg [1:0] low_addr;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
low_addr <= i_wb_addr[1:0];
always @(posedge i_clk)
if ((o_axi_rvalid)&&(i_axi_rready))
reorder_fifo_addr[o_axi_rid] <= low_addr;
 
reg [1:0] low_addr;
always @(posedge i_clk)
if ((i_wb_stb)&&(!o_wb_stall))
low_addr <= i_wb_addr[1:0];
always @(posedge i_clk)
if ((o_axi_rvalid)&&(i_axi_rready))
reorder_fifo_addr[o_axi_rid] <= low_addr;
 
always @(posedge i_clk)
case(reorder_fifo_addr[1:0])
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
endcase
 
end else if (DW == 128)
begin
always @(posedge i_clk)
o_wb_data <= reorder_fifo_data[fifo_tail];
end
 
 
wire [(LGFIFOLN-1):0] fifo_head;
assign fifo_head = transaction_id;
 
275,13 → 306,6
reorder_fifo_err[i_axi_wd_bid] <= i_axi_wd_bresp[1];
end
 
case(reorder_fifo_addr[1:0])
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
2'b11: o_wb_data <=reorder_fifo_data[fifo_tail][127:96];
endcase
 
if (reorder_fifo_valid[fifo_tail])
begin
o_wb_ack <= 1'b1;

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