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URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

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    /wb2axip
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/rtl/wbm2axisp.v
56,21 → 56,22
parameter C_AXI_ID_WIDTH = 6, // The AXI id width used for R&W
// This is an int between 1-16
parameter C_AXI_DATA_WIDTH = 128,// Width of the AXI R&W data
parameter AW = 28, // Wishbone address width
parameter DW = 128, // Wishbone data width
parameter C_AXI_ADDR_WIDTH = 28, // AXI Address width
parameter DW = 32, // Wishbone data width
parameter AW = 26, // Wishbone address width
parameter STRICT_ORDER = 0 // Reorder, or not? 0 -> Reorder
) (
input i_clk, // System clock
input i_reset,// Wishbone reset signal
// input i_reset,// Wishbone reset signal--unused
 
// AXI write address channel signals
input i_axi_awready, // Slave is ready to accept
output wire [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID
output reg [AW-1:0] o_axi_awaddr, // Write address
output reg [C_AXI_ID_WIDTH-1:0] o_axi_awid, // Write ID
output reg [C_AXI_ADDR_WIDTH-1:0] o_axi_awaddr, // Write address
output wire [7:0] o_axi_awlen, // Write Burst Length
output wire [2:0] o_axi_awsize, // Write Burst size
output wire [1:0] o_axi_awburst, // Write Burst type
output wire [1:0] o_axi_awlock, // Write lock type
output wire [0:0] o_axi_awlock, // Write lock type
output wire [3:0] o_axi_awcache, // Write Cache type
output wire [2:0] o_axi_awprot, // Write Protection type
output wire [3:0] o_axi_awqos, // Write Quality of Svc
92,11 → 93,11
// AXI read address channel signals
input i_axi_arready, // Read address ready
output wire [C_AXI_ID_WIDTH-1:0] o_axi_arid, // Read ID
output wire [AW-1:0] o_axi_araddr, // Read address
output wire [C_AXI_ADDR_WIDTH-1:0] o_axi_araddr, // Read address
output wire [7:0] o_axi_arlen, // Read Burst Length
output wire [2:0] o_axi_arsize, // Read Burst size
output wire [1:0] o_axi_arburst, // Read Burst type
output wire [1:0] o_axi_arlock, // Read lock type
output wire [0:0] o_axi_arlock, // Read lock type
output wire [3:0] o_axi_arcache, // Read Cache type
output wire [2:0] o_axi_arprot, // Read Protection type
output wire [3:0] o_axi_arqos, // Read Protection type
114,12 → 115,12
input i_wb_cyc,
input i_wb_stb,
input i_wb_we,
input [AW-1:0] i_wb_addr,
input [DW-1:0] i_wb_data,
input [(AW-1):0] i_wb_addr,
input [(DW-1):0] i_wb_data,
input [(DW/8-1):0] i_wb_sel,
output reg o_wb_ack,
output wire o_wb_stall,
output reg [DW-1:0] o_wb_data,
output reg [(DW-1):0] o_wb_data,
output reg o_wb_err
);
 
135,44 → 136,17
// Internal register and wire declarations
//*****************************************************************************
 
wire cmd_en;
wire [2:0] cmd;
wire [7:0] blen;
wire [31:0] addr;
wire [CTL_SIG_WIDTH-1:0] ctl;
wire cmd_ack;
 
// User interface write ports
wire wrdata_vld;
wire [C_AXI_DATA_WIDTH-1:0] wrdata;
wire [C_AXI_DATA_WIDTH/8-1:0] wrdata_bvld;
wire wrdata_cmptd;
wire wrdata_rdy;
wire wrdata_sts_vld;
wire [WR_STS_WIDTH-1:0] wrdata_sts;
 
// User interface read ports
wire rddata_rdy;
wire rddata_vld;
wire [C_AXI_DATA_WIDTH-1:0] rddata;
wire [C_AXI_DATA_WIDTH/8-1:0] rddata_bvld;
wire rddata_cmptd;
wire [RD_STS_WIDTH-1:0] rddata_sts;
reg cmptd_one_wr;
reg cmptd_one_rd;
 
 
// Things we're not changing ...
assign o_axi_awlen = 8'h0; // Burst length is one
assign o_axi_awsize = 3'b101; // maximum bytes per burst is 32
assign o_axi_awburst = 2'b01; // Incrementing address (ignored)
assign o_axi_arburst = 2'b01; // Incrementing address (ignored)
assign o_axi_awlock = 2'b00; // Normal signaling
assign o_axi_arlock = 2'b00; // Normal signaling
assign o_axi_awlock = 1'b0; // Normal signaling
assign o_axi_arlock = 1'b0; // Normal signaling
assign o_axi_awcache = 4'h2; // Normal: no cache, no buffer
assign o_axi_arcache = 4'h2; // Normal: no cache, no buffer
assign o_axi_awprot = 3'h010; // Unpriviledged, unsecure, data access
assign o_axi_arprot = 3'h010; // Unpriviledged, unsecure, data access
assign o_axi_awprot = 3'b010; // Unpriviledged, unsecure, data access
assign o_axi_arprot = 3'b010; // Unpriviledged, unsecure, data access
assign o_axi_awqos = 4'h0; // Lowest quality of service (unused)
assign o_axi_arqos = 4'h0; // Lowest quality of service (unused)
 
182,10 → 156,20
always @(posedge i_clk)
o_axi_awvalid <= (!o_wb_stall)&&(i_wb_stb)&&(i_wb_we)
||(o_wb_stall)&&(o_axi_awvalid)&&(!i_axi_awready);
always @(posedge i_clk)
if (!o_wb_stall)
o_axi_awaddr <= { i_wb_addr[AW-1:2], 2'b00 }; // 28 bits
 
generate
if (DW == 32)
begin
always @(posedge i_clk)
if (!o_wb_stall) // 26 bit address becomes 28 bit ...
o_axi_awaddr <= { i_wb_addr[AW-1:2], 4'b00 };
end else if (DW == 128)
begin
always @(posedge i_clk)
if (!o_wb_stall) // 28 bit address ...
o_axi_awaddr <= { i_wb_addr[AW-1:0], 4'b00 };
end endgenerate
 
reg [5:0] transaction_id;
always @(posedge i_clk)
if (!i_wb_cyc)
192,10 → 176,12
transaction_id <= 6'h00;
else if ((i_wb_stb)&&(~o_wb_stall))
transaction_id <= transaction_id + 6'h01;
assign o_axi_awid = transaction_id;
always @(posedge i_clk)
if ((i_wb_stb)&&(~o_wb_stall))
o_axi_awid <= transaction_id;
 
// Read address logic
assign o_axi_arid = transaction_id;
assign o_axi_arid = o_axi_awid;
assign o_axi_araddr = o_axi_awaddr;
assign o_axi_arlen = o_axi_awlen;
assign o_axi_arsize = 3'b101; // maximum bytes per burst is 32
214,10 → 200,10
always @(posedge i_clk)
if (!o_wb_stall)
case(i_wb_addr[1:0])
2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0, i_wb_sel };
2'b01:o_axi_wstrb<={ 4'h0, 4'h0, i_wb_sel, 4'h0 };
2'b10:o_axi_wstrb<={ 4'h0, i_wb_sel, 4'h0, 4'h0 };
2'b11:o_axi_wstrb<={ i_wb_sel, 4'h0, 4'h0, 4'h0 };
2'b00:o_axi_wstrb<={ 4'h0, 4'h0, 4'h0,i_wb_sel};
2'b01:o_axi_wstrb<={ 4'h0, 4'h0,i_wb_sel, 4'h0};
2'b10:o_axi_wstrb<={ 4'h0,i_wb_sel, 4'h0, 4'h0};
2'b11:o_axi_wstrb<={i_wb_sel, 4'h0, 4'h0, 4'h0};
endcase
end else if (DW == 128)
begin
252,6 → 238,9
reg [(FIFOLN-1):0] reorder_fifo_valid;
reg [(FIFOLN-1):0] reorder_fifo_err;
 
initial reorder_fifo_valid = 0;
initial reorder_fifo_err = 0;
 
if (DW == 32)
begin
reg [1:0] reorder_fifo_addr [0:(FIFOLN-1)];
266,7 → 255,7
reorder_fifo_addr[o_axi_arid] <= low_addr;
 
always @(posedge i_clk)
case(reorder_fifo_addr[1:0])
case(reorder_fifo_addr[fifo_tail][1:0])
2'b00: o_wb_data <=reorder_fifo_data[fifo_tail][ 31: 0];
2'b01: o_wb_data <=reorder_fifo_data[fifo_tail][ 63:32];
2'b10: o_wb_data <=reorder_fifo_data[fifo_tail][ 95:64];
289,6 → 278,7
// calculation below.
wire [(LGFIFOLN-1):0] n_fifo_head, nn_fifo_head;
assign n_fifo_head = fifo_head+1'b1;
assign nn_fifo_head = { fifo_head[(LGFIFOLN-1):1]+1'b1, fifo_head[0] };
 
always @(posedge i_clk)
begin
344,14 → 334,18
end
assign w_fifo_full = r_fifo_full;
end else begin
//
// Strict ordering, but can only read every fourth addresses
//
assign w_fifo_full = 1'b0;
always @(posedge i_clk)
o_wb_data <= i_axi_rdata;
o_wb_data <= i_axi_rdata[31:0];
always @(posedge i_clk)
o_wb_ack <= ((i_axi_rvalid)&&(o_axi_rready))
||((i_axi_bvalid)&&(o_axi_bready));
o_wb_ack <= (i_wb_cyc)&&(
((i_axi_rvalid)&&(o_axi_rready))
||((i_axi_bvalid)&&(o_axi_bready)));
always @(posedge i_clk)
o_wb_err <= (!i_wb_cyc)&&((o_wb_err)
o_wb_err <= (i_wb_cyc)&&((o_wb_err)
||((i_axi_rvalid)&&(i_axi_rresp[1]))
||((i_axi_bvalid)&&(i_axi_bresp[1])));
end endgenerate
/trunk/rtl/migsdram.v
0,0 → 1,305
////////////////////////////////////////////////////////////////////////////////
//
// Filename: migsdram.v
//
// Project: Pipelined Wishbone to AXI converter
//
// Purpose: This file isn't really a part of the synthesis implementation
// of the wb2axip project itself, but rather it is an example
// of how the wb2axip project can be used to connect a MIG generated
// IP component.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module migsdram(i_clk, i_clk_200mhz, o_sys_clk, i_rst, o_sys_reset,
// Wishbone components
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel,
o_wb_ack, o_wb_stall, o_wb_data, o_wb_err,
// SDRAM connections
o_ddr_ck_p, o_ddr_ck_n,
o_ddr_reset_n, o_ddr_cke,
o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
o_ddr_ba, o_ddr_addr,
o_ddr_odt, o_ddr_dm,
io_ddr_dqs_p, io_ddr_dqs_n,
io_ddr_data
);
parameter DDRWIDTH = 16, WBDATAWIDTH=32;
parameter AXIDWIDTH = 6;
// The SDRAM address bits (RAMABITS) are a touch more difficult to work
// out. Here we leave them as a fixed parameter, but there are
// consequences to this. Specifically, the wishbone data width, the
// wishbone address width, and this number have interactions not
// well captured here.
parameter RAMABITS = 28;
// All DDR3 memories have 8 timeslots. This, if the DDR3 memory
// has 16 bits to it (as above), the entire transaction must take
// AXIWIDTH bits ...
localparam AXIWIDTH= DDRWIDTH *8;
localparam DW=WBDATAWIDTH;
localparam AW=(WBDATAWIDTH==32)? RAMABITS-2
:((WBDATAWIDTH==64) ? RAMABITS-3
:((WBDATAWIDTH==128) ? RAMABITS-4
: RAMABITS-5)); // (WBDATAWIDTH==256)
localparam SELW= (WBDATAWIDTH/8);
//
input i_clk, i_clk_200mhz, i_rst;
output o_sys_clk;
output reg o_sys_reset;
//
input i_wb_cyc, i_wb_stb, i_wb_we;
input [(AW-1):0] i_wb_addr;
input [(DW-1):0] i_wb_data;
input [(SELW-1):0] i_wb_sel;
output wire o_wb_ack, o_wb_stall;
output wire [(DW-1):0] o_wb_data;
output wire o_wb_err;
//
output wire [0:0] o_ddr_ck_p, o_ddr_ck_n;
output wire [0:0] o_ddr_cke;
output wire o_ddr_reset_n,
o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n;
output wire [0:0] o_ddr_cs_n;
output wire [2:0] o_ddr_ba;
output wire [13:0] o_ddr_addr;
output wire [0:0] o_ddr_odt;
output wire [(DDRWIDTH/8-1):0] o_ddr_dm;
inout wire [1:0] io_ddr_dqs_p, io_ddr_dqs_n;
inout wire [(DDRWIDTH-1):0] io_ddr_data;
 
 
`define SDRAM_ACCESS
`ifdef SDRAM_ACCESS
 
wire aresetn;
assign aresetn = 1'b1; // Never reset
 
// Write address channel
wire [(AXIDWIDTH-1):0] s_axi_awid;
wire [(RAMABITS-1):0] s_axi_awaddr;
wire [7:0] s_axi_awlen;
wire [2:0] s_axi_awsize;
wire [1:0] s_axi_awburst;
wire [0:0] s_axi_awlock;
wire [3:0] s_axi_awcache;
wire [2:0] s_axi_awprot;
wire [3:0] s_axi_awqos;
wire s_axi_awvalid;
wire s_axi_awready;
// Writei data channel
wire [(AXIWIDTH-1):0] s_axi_wdata;
wire [(AXIWIDTH/8-1):0] s_axi_wstrb;
wire s_axi_wlast, s_axi_wvalid, s_axi_wready;
// Write response channel
wire s_axi_bready;
wire [(AXIDWIDTH-1):0] s_axi_bid;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
 
// Read address channel
wire [(AXIDWIDTH-1):0] s_axi_arid;
wire [(RAMABITS-1):0] s_axi_araddr;
wire [7:0] s_axi_arlen;
wire [2:0] s_axi_arsize;
wire [1:0] s_axi_arburst;
wire [0:0] s_axi_arlock;
wire [3:0] s_axi_arcache;
wire [2:0] s_axi_arprot;
wire [3:0] s_axi_arqos;
wire s_axi_arvalid;
// Read response/data channel
wire [(AXIDWIDTH-1):0] s_axi_rid;
wire [(AXIWIDTH-1):0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rlast;
wire s_axi_rvalid;
 
// Other wires ...
wire init_calib_complete, mmcm_locked;
wire app_sr_active, app_ref_ack, app_zq_ack;
wire app_sr_req, app_ref_req, app_zq_req;
wire w_sys_reset;
wire [11:0] w_device_temp;
 
 
mig_axis mig_sdram(
.ddr3_ck_p(o_ddr_ck_p), .ddr3_ck_n(o_ddr_ck_n),
.ddr3_reset_n(o_ddr_reset_n), .ddr3_cke(o_ddr_cke),
.ddr3_cs_n(o_ddr_cs_n), .ddr3_ras_n(o_ddr_ras_n),
.ddr3_we_n(o_ddr_we_n), .ddr3_cas_n(o_ddr_cas_n),
.ddr3_ba(o_ddr_ba), .ddr3_addr(o_ddr_addr),
.ddr3_odt(o_ddr_odt),
.ddr3_dqs_p(io_ddr_dqs_p), .ddr3_dqs_n(io_ddr_dqs_n),
.ddr3_dq(io_ddr_data), .ddr3_dm(o_ddr_dm),
//
.sys_clk_i(i_clk),
.clk_ref_i(i_clk_200mhz),
.ui_clk(o_sys_clk),
.ui_clk_sync_rst(w_sys_reset),
.mmcm_locked(mmcm_locked),
.aresetn(aresetn),
.app_sr_req(1'b0),
.app_ref_req(1'b0),
.app_zq_req(1'b0),
.app_sr_active(app_sr_active),
.app_ref_ack(app_ref_ack),
.app_zq_ack(app_zq_ack),
//
.s_axi_awid(s_axi_awid), .s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen), .s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst), .s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache), .s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos), .s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
//
.s_axi_wready( s_axi_wready),
.s_axi_wdata( s_axi_wdata),
.s_axi_wstrb( s_axi_wstrb),
.s_axi_wlast( s_axi_wlast),
.s_axi_wvalid( s_axi_wvalid),
//
.s_axi_bready(s_axi_bready), .s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp), .s_axi_bvalid(s_axi_bvalid),
//
.s_axi_arid(s_axi_arid), .s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen), .s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst), .s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache), .s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos), .s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
//
.s_axi_rready(s_axi_rready), .s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata), .s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast), .s_axi_rvalid(s_axi_rvalid),
.init_calib_complete(init_calib_complete),
.sys_rst(i_rst),
.device_temp(w_device_temp)
);
 
wbm2axisp #(
.C_AXI_ID_WIDTH(AXIDWIDTH),
.C_AXI_DATA_WIDTH(AXIWIDTH),
.C_AXI_ADDR_WIDTH(RAMABITS),
.AW(AW), .DW(DW)
)
bus_translator(
.i_clk(o_sys_clk),
// .i_reset(i_rst), // internally unused
// Write address channel signals
.o_axi_awid( s_axi_awid),
.o_axi_awaddr( s_axi_awaddr),
.o_axi_awlen( s_axi_awlen),
.o_axi_awsize( s_axi_awsize),
.o_axi_awburst( s_axi_awburst),
.o_axi_awlock( s_axi_awlock),
.o_axi_awcache( s_axi_awcache),
.o_axi_awprot( s_axi_awprot), // s_axi_awqos
.o_axi_awqos( s_axi_awqos), // s_axi_awqos
.o_axi_awvalid( s_axi_awvalid),
.i_axi_awready( s_axi_awready),
//
.i_axi_wready( s_axi_wready),
.o_axi_wdata( s_axi_wdata),
.o_axi_wstrb( s_axi_wstrb),
.o_axi_wlast( s_axi_wlast),
.o_axi_wvalid( s_axi_wvalid),
//
.o_axi_bready( s_axi_bready),
.i_axi_bid( s_axi_bid),
.i_axi_bresp( s_axi_bresp),
.i_axi_bvalid( s_axi_bvalid),
//
.i_axi_arready( s_axi_arready),
.o_axi_arid( s_axi_arid),
.o_axi_araddr( s_axi_araddr),
.o_axi_arlen( s_axi_arlen),
.o_axi_arsize( s_axi_arsize),
.o_axi_arburst( s_axi_arburst),
.o_axi_arlock( s_axi_arlock),
.o_axi_arcache( s_axi_arcache),
.o_axi_arprot( s_axi_arprot),
.o_axi_arqos( s_axi_arqos),
.o_axi_arvalid( s_axi_arvalid),
//
.o_axi_rready( s_axi_rready),
.i_axi_rid( s_axi_rid),
.i_axi_rdata( s_axi_rdata),
.i_axi_rresp( s_axi_rresp),
.i_axi_rlast( s_axi_rlast),
.i_axi_rvalid( s_axi_rvalid),
//
.i_wb_cyc( i_wb_cyc),
.i_wb_stb( i_wb_stb),
.i_wb_we( i_wb_we),
.i_wb_addr( i_wb_addr),
.i_wb_data( i_wb_data),
.i_wb_sel( i_wb_sel),
//
.o_wb_ack( o_wb_ack),
.o_wb_stall( o_wb_stall),
.o_wb_data( o_wb_data),
.o_wb_err( o_wb_err)
);
 
// Convert from active low to active high, *and* hold the system in
// reset until the memory comes up.
initial o_sys_reset = 1'b1;
always @(posedge o_sys_clk)
o_sys_reset <= (!w_sys_reset)
||(!init_calib_complete)
||(!mmcm_locked);
`else
BUFG sysclk(i_clk, o_sys_clk);
initial o_sys_reset <= 1'b1;
always @(posedge i_clk)
o_sys_reset <= 1'b1;
 
OBUFDS ckobuf(.I(i_clk), .O(o_ddr_ck_p), .OB(o_ddr_ck_n));
 
assign o_ddr_reset_n = 1'b0;
assign o_ddr_cke[0] = 1'b0;
assign o_ddr_cs_n[0] = 1'b1;
assign o_ddr_cas_n = 1'b1;
assign o_ddr_ras_n = 1'b1;
assign o_ddr_we_n = 1'b1;
assign o_ddr_ba = 3'h0;
assign o_ddr_addr = 14'h00;
assign o_ddr_dm = 2'b00;
assign io_ddr_data = 16'h0;
 
OBUFDS dqsbufa(.I(i_clk), .O(io_ddr_dqs_p[1]), .OB(io_ddr_dqs_n[1]));
OBUFDS dqsbufb(.I(i_clk), .O(io_ddr_dqs_p[0]), .OB(io_ddr_dqs_n[0]));
 
`endif
 
endmodule
 
 

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