URL
https://opencores.org/ocsvn/wb4pb/wb4pb/trunk
Subversion Repositories wb4pb
Compare Revisions
- This comparison shows the changes necessary to convert path
/wb4pb
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/trunk/sim/hdl/picoblaze_wb_uart_tb.vhd
71,6 → 71,7
|
begin |
|
-- system signal generation |
rst_n <= '1' after PERIOD*2; |
clk <= not clk after PERIOD/2; |
|
77,6 → 78,7
-- simple serial loopback |
uart_rx_si <= uart_tx_so; |
|
-- design under test instance |
dut : picoblaze_wb_uart |
port map |
( |
/trunk/sim/hdl/picoblaze_wb_gpio_tb.vhd
54,7 → 54,7
component picoblaze_wb_gpio is |
port |
( |
p_rst_i : in std_logic; |
p_rst_n_i : in std_logic; |
p_clk_i : in std_logic; |
|
p_gpio_io : inout std_logic_vector(7 downto 0) |
61,7 → 61,7
); |
end component; |
|
signal rst : std_logic := '1'; |
signal rst_n : std_logic := '0'; |
signal clk : std_logic := '1'; |
|
signal gpio : std_logic_vector(7 downto 0) := (others => 'Z'); |
72,20 → 72,20
|
begin |
|
rst <= '0' after PERIOD*2; |
-- system signal generation |
rst_n <= '1' after PERIOD*2; |
clk <= not clk after PERIOD/2; |
|
process |
begin |
wait for 2500 ns; |
test_data_in <= std_logic_vector(unsigned(test_data_in) + 1); |
end process; |
-- 4 bit counting data, changing after some micro seconds |
test_data_in <= std_logic_vector(unsigned(test_data_in) + 1) after 3000 ns; |
-- stimulus at upper gpio nibble |
gpio(7 downto 4) <= test_data_in; |
|
-- design under test instance |
dut : picoblaze_wb_gpio |
port map |
( |
p_rst_i => rst, |
p_rst_n_i => rst_n, |
p_clk_i => clk, |
|
p_gpio_io => gpio |
/trunk/sim/hdl/picoblaze_wb_uart_tb.v
55,6 → 55,7
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parameter PERIOD = 20; |
|
// system signal generation |
initial begin |
clk = 1'b1; |
rst_n = 1'b0; |
65,6 → 66,7
// simple serial loopback |
assign uart_rx_si = uart_tx_so; |
|
// design under test instance |
picoblaze_wb_uart dut ( |
.p_rst_n_i(rst_n), |
.p_clk_i(clk), |
/trunk/sim/hdl/picoblaze_wb_gpio_tb.v
47,7 → 47,7
|
module picoblaze_wb_gpio_tb; |
|
reg rst; |
reg rst_n; |
reg clk; |
|
wire[7:0] gpio; |
56,19 → 56,23
|
reg[7:4] test_data_in; |
|
// system signal generation |
initial begin |
test_data_in = 4'h0; |
clk = 1'b1; |
rst = 1'b1; |
#(PERIOD*2) rst = 1'b0; |
rst_n = 1'b0; |
#(PERIOD*2) rst_n = 1'b1; |
end |
always #(PERIOD/2) clk = ! clk; |
|
always #2500 test_data_in = test_data_in + 1; |
// 4 bit counting data, changing after some micro seconds |
always #3000 test_data_in = test_data_in + 1; |
// stimulus at upper gpio nibble |
assign gpio[7:4] = test_data_in; |
|
// design under test instance |
picoblaze_wb_gpio dut ( |
.p_rst_i(rst), |
.p_rst_n_i(rst_n), |
.p_clk_i(clk), |
|
.p_gpio_io(gpio) |