OpenCores
URL https://opencores.org/ocsvn/wb_to_amba/wb_to_amba/trunk

Subversion Repositories wb_to_amba

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Rev 1 → Rev 2

/src/wb_arm_phase_fsm.v
0,0 → 1,71
//
//
//
 
`timescale 1ns / 100ps
 
 
 
module wb_arm_phase_fsm(
input ahb_hclk,
input ahb_hreset,
input ahb_hsel,
input ahb_hready_in,
input ahb_hready_out,
output ahb_data_phase,
output fsm_error
);
 
 
// -----------------------------
// state machine binary definitions
parameter IDLE_STATE = 3'b001;
parameter DATA_STATE = 3'b010;
parameter ERROR_STATE = 3'b100;
 
// -----------------------------
// state machine flop
reg [2:0] state;
reg [2:0] next_state;
 
always @(posedge ahb_hclk)
if(~ahb_hreset)
state <= IDLE_STATE;
else
state <= next_state;
 
 
// -----------------------------
// state machine
always @(*)
case(state)
IDLE_STATE: if( ahb_hsel & ahb_hready_in )
next_state <= DATA_STATE;
else
next_state <= IDLE_STATE;
 
DATA_STATE: if( ahb_hready_out )
next_state <= IDLE_STATE;
else
next_state <= DATA_STATE;
 
ERROR_STATE: next_state <= IDLE_STATE;
 
default: next_state <= ERROR_STATE;
 
endcase
 
 
// -----------------------------
// outputs
assign ahb_data_phase = (state == DATA_STATE);
assign fsm_error = (state == ERROR_STATE);
 
endmodule
 
 
 
 
 
 
/src/wb_arm_slave_top.v
0,0 → 1,153
//
//
//
 
`timescale 1ns / 100ps
 
module
wb_arm_slave_top
#(
parameter AWIDTH = 8,
parameter DWIDTH = 32
)
(
// -----------------------------
// AHB interface
input ahb_hclk,
input ahb_hreset,
output [DWIDTH-1:0] ahb_hrdata,
output [1:0] ahb_hresp,
output ahb_hready_out,
output [15:0] ahb_hsplit,
input [DWIDTH-1:0] ahb_hwdata,
input [AWIDTH-1:0] ahb_haddr,
input [2:0] ahb_hsize,
input ahb_hwrite,
input [2:0] ahb_hburst,
input [1:0] ahb_htrans,
input [3:0] ahb_hprot,
input ahb_hsel,
input ahb_hready_in,
// -----------------------------
// Data WISHBONE interface
input wb_ack_i, // normal termination
input wb_err_i, // termination w/ error
input wb_rty_i, // termination w/ retry
input [DWIDTH-1:0] wb_dat_i, // input data bus
output wb_cyc_o, // cycle valid output
output [AWIDTH-1:0] wb_adr_o, // address bus outputs
output wb_stb_o, // strobe output
output wb_we_o, // indicates write transfer
output [3:0] wb_sel_o, // byte select outputs
output [DWIDTH-1:0] wb_dat_o, // output data bus
output wb_clk_o, // clock input
output wb_rst_o // reset input
);
// -----------------------------
// ahb_haddr & control flops
wire flop_en = ahb_hready_in & ahb_hsel;
reg [AWIDTH-1:0] ahb_haddr_r;
always @ (posedge ahb_hclk)
if ( flop_en )
ahb_haddr_r <= ahb_haddr;
reg [1:0] ahb_htrans_r;
always @ (posedge ahb_hclk)
if ( flop_en )
ahb_htrans_r <= ahb_htrans;
reg ahb_hwrite_r;
always @ (posedge ahb_hclk)
if ( flop_en )
ahb_hwrite_r <= ahb_hwrite;
reg [2:0] ahb_hsize_r;
always @ (posedge ahb_hclk)
if ( flop_en )
ahb_hsize_r <= ahb_hsize;
reg [2:0] ahb_hburst_r;
always @ (posedge ahb_hclk)
if ( flop_en )
ahb_hburst_r <= ahb_hburst;
// -----------------------------
// wb_arm_phase_fsm
wire ahb_data_phase;
wire fsm_error;
wb_arm_phase_fsm i_wb_arm_phase_fsm(
.ahb_hclk (ahb_hclk),
.ahb_hreset (ahb_hreset),
.ahb_hsel (ahb_hsel),
.ahb_hready_in (ahb_hready_in),
.ahb_hready_out (ahb_hready_out),
.ahb_data_phase (ahb_data_phase),
.fsm_error (fsm_error)
);
// -----------------------------
// hresp encoder
reg [1:0] enc_hresp;
always @(*)
casez( { ahb_htrans_r, fsm_error } )
{ 2'b??, 1'b1 }: enc_hresp = 2'b01;
{ 2'b11, 1'b? }: enc_hresp = 2'b01; // burst not supported yet
default: enc_hresp = 2'b00;
endcase
// -----------------------------
// wb_sel encoder
reg [3:0] enc_wb_sel;
always @(*)
casez( { ahb_hsize_r, ahb_haddr_r[1:0] } )
{ 3'b010, 2'b?? }: enc_wb_sel = 4'b1111;
{ 3'b001, 2'b0? }: enc_wb_sel = 4'b0011;
{ 3'b001, 2'b1? }: enc_wb_sel = 4'b1100;
{ 3'b000, 2'b00 }: enc_wb_sel = 4'b0001;
{ 3'b000, 2'b01 }: enc_wb_sel = 4'b0010;
{ 3'b000, 2'b10 }: enc_wb_sel = 4'b0100;
{ 3'b000, 2'b11 }: enc_wb_sel = 4'b1000;
default: enc_wb_sel = 4'b0000;
endcase
// -----------------------------
// outputs
 
assign ahb_hresp = enc_hresp;
assign ahb_hready_out = wb_ack_i;
assign ahb_hsplit = 0;
assign wb_sel_o = enc_wb_sel;
assign wb_adr_o = ahb_haddr_r;
assign ahb_hrdata = wb_dat_i;
assign wb_we_o = ahb_hwrite_r & ( (ahb_htrans_r != 2'b00) | (ahb_htrans_r != 2'b01) );
assign wb_cyc_o = ahb_data_phase;
assign wb_stb_o = ahb_data_phase;
assign wb_dat_o = ahb_hwdata;
assign wb_clk_o = ahb_hclk;
assign wb_rst_o = ~ahb_hreset;
endmodule
 
 
 
 
 
/sim/tests/debug/debug.cr.mti
0,0 → 1,47
C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/wb_slave_model.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/wb_slave_model.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_slave_model
 
Top level modules:
wb_slave_model
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_dut.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_dut
 
Top level modules:
tb_dut
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/bfm_ahb.v {2 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/bfm_ahb.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module bfm_ahb
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/bfm_ahb.v(324): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/bfm_ahb.v(325): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/bfm_ahb.v(326): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/bfm_ahb.v(327): [RDGN] - Redundant digits in numeric literal.
 
Top level modules:
bfm_ahb
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_to_amba/src/wb_arm_slave_top.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/wb_to_amba/src/wb_arm_slave_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_arm_slave_top
 
Top level modules:
wb_arm_slave_top
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v {2 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_top
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v(54): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v(57): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v(60): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v(65): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v(68): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v(71): [RDGN] - Redundant digits in numeric literal.
** Warning: C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v(74): [RDGN] - Redundant digits in numeric literal.
 
Top level modules:
tb_top
 
} {} {}}
/sim/tests/debug/wb_slave_32_bit.txt
0,0 → 1,64
00
00
00
00
11
11
11
11
22
22
22
22
33
33
33
33
44
44
44
44
55
55
55
55
66
66
66
66
77
77
77
77
88
88
88
88
99
99
99
99
aa
aa
aa
aa
bb
bb
bb
bb
cc
cc
cc
cc
dd
dd
dd
dd
ee
ee
ee
ee
ff
ff
ff
ff
/sim/tests/debug/tb_dut.v
0,0 → 1,126
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
 
 
// -----------------------------
// bfm_ahb
wire hclk;
wire hresetn;
wire [31:0] haddr;
wire [1:0] htrans;
wire hwrite;
wire [2:0] hsize;
wire [2:0] hburst;
wire [3:0] hprot;
wire [31:0] hwdata;
wire hsel;
 
wire [31:0] hrdata;
wire hready_in;
wire hready_out;
wire [1:0] hresp;
bfm_ahb
i_bfm_ahb(
.hclk(hclk),
.hresetn(hresetn),
.haddr(haddr),
.htrans(htrans),
.hwrite(hwrite),
.hsize(hsize),
.hburst(hburst),
.hprot(hprot),
.hwdata(hwdata),
.hsel(hsel),
.hrdata(hrdata),
.hready_in(hready_in),
.hready_out(hready_out),
.hresp(hresp),
.bfm_clk(tb_clk),
.bfm_reset(tb_rst)
);
 
// --------------------------------------------------------------------
// wb_slave_model
wire wb_clk_o;
wire wb_rst_o;
wire [31:0] wb_data_i;
wire [31:0] wb_data_o;
wire [31:0] wb_addr_o;
wire [3:0] wb_sel_o;
wire wb_we_o;
wire wb_cyc_o;
wire wb_stb_o;
wire wb_ack_i;
wire wb_err_i;
wire wb_rty_i;
wb_arm_slave_top
i_wb_arm_slave_top(
.ahb_hclk(hclk),
.ahb_hreset(hresetn),
.ahb_hrdata(hrdata),
.ahb_hresp(hresp),
.ahb_hready_out(hready_out),
.ahb_hsplit(),
.ahb_hwdata(hwdata),
.ahb_haddr(haddr[7:0]),
.ahb_hsize(hsize),
.ahb_hwrite(hwrite),
.ahb_hburst(hburst),
.ahb_htrans(htrans),
.ahb_hprot(),
.ahb_hsel(hsel),
.ahb_hready_in(hready_in),
.wb_clk_o(wb_clk_o),
.wb_rst_o(wb_rst_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_rty_i(wb_rty_i),
.wb_dat_i(wb_data_i),
.wb_cyc_o(wb_cyc_o),
.wb_adr_o(wb_addr_o[7:0]),
.wb_stb_o(wb_stb_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_dat_o(wb_data_o)
);
// --------------------------------------------------------------------
// wb_slave_model
wb_slave_model #(.DWIDTH(32), .AWIDTH(8), .ACK_DELAY(0), .SLAVE_RAM_INIT("wb_slave_32_bit.txt") )
i_wb_slave_model(
.clk_i(wb_clk_o),
.rst_i(wb_rst_o),
.dat_o(wb_data_i),
.dat_i(wb_data_o),
.adr_i( wb_addr_o[7:0] ),
.cyc_i(wb_cyc_o),
.stb_i(wb_stb_o),
.we_i(wb_we_o),
.sel_i(wb_sel_o),
.ack_o(wb_ack_i),
.err_o(wb_err_i),
.rty_o(wb_rty_i)
);
// --------------------------------------------------------------------
//
endmodule
 
 
/sim/tests/debug/debug.mpf
0,0 → 1,458
; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
 
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
max = $MODEL_TECH/../altera/vhdl/max
maxii = $MODEL_TECH/../altera/vhdl/maxii
stratix = $MODEL_TECH/../altera/vhdl/stratix
stratixii = $MODEL_TECH/../altera/vhdl/stratixii
stratixiigx = $MODEL_TECH/../altera/vhdl/stratixiigx
hardcopyii = $MODEL_TECH/../altera/vhdl/hardcopyii
hardcopyiii = $MODEL_TECH/../altera/vhdl/hardcopyiii
hardcopyiv = $MODEL_TECH/../altera/vhdl/hardcopyiv
cyclone = $MODEL_TECH/../altera/vhdl/cyclone
cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
cycloneiii = $MODEL_TECH/../altera/vhdl/cycloneiii
cycloneiiils = $MODEL_TECH/../altera/vhdl/cycloneiiils
sgate = $MODEL_TECH/../altera/vhdl/sgate
stratixgx = $MODEL_TECH/../altera/vhdl/stratixgx
altgxb = $MODEL_TECH/../altera/vhdl/altgxb
stratixgx_gxb = $MODEL_TECH/../altera/vhdl/stratixgx_gxb
stratixiigx_hssi = $MODEL_TECH/../altera/vhdl/stratixiigx_hssi
arriagx_hssi = $MODEL_TECH/../altera/vhdl/arriagx_hssi
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriagx = $MODEL_TECH/../altera/vhdl/arriagx
altgxb_lib = $MODEL_TECH/../altera/vhdl/altgxb
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
hardcopyiv_hssi = $MODEL_TECH/../altera/vhdl/hardcopyiv_hssi
hardcopyiv_pcie_hip = $MODEL_TECH/../altera/vhdl/hardcopyiv_pcie_hip
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
max_ver = $MODEL_TECH/../altera/verilog/max
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
stratix_ver = $MODEL_TECH/../altera/verilog/stratix
stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
stratixiigx_ver = $MODEL_TECH/../altera/verilog/stratixiigx
arriagx_ver = $MODEL_TECH/../altera/verilog/arriagx
hardcopyii_ver = $MODEL_TECH/../altera/verilog/hardcopyii
hardcopyiii_ver = $MODEL_TECH/../altera/verilog/hardcopyiii
hardcopyiv_ver = $MODEL_TECH/../altera/verilog/hardcopyiv
cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
cycloneiii_ver = $MODEL_TECH/../altera/verilog/cycloneiii
cycloneiiils_ver = $MODEL_TECH/../altera/verilog/cycloneiiils
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
stratixgx_ver = $MODEL_TECH/../altera/verilog/stratixgx
altgxb_ver = $MODEL_TECH/../altera/verilog/altgxb
stratixgx_gxb_ver = $MODEL_TECH/../altera/verilog/stratixgx_gxb
stratixiigx_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiigx_hssi
arriagx_hssi_ver = $MODEL_TECH/../altera/verilog/arriagx_hssi
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi
hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
[vlog]
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 100 ps
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
 
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
 
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
 
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
 
[lmc]
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 6
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/bfm_ahb.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1265069728 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/wb_to_amba/sim/models/wb_slave_model.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1255568776 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_dut.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1265052852 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/wb_to_amba/src/wb_arm_slave_top.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1265062742 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/wb_to_amba/src/wb_arm_phase_fsm.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1265060796 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/wb_to_amba/sim/tests/debug/tb_top.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1265069546 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
Project_Major_Version = 6
Project_Minor_Version = 5
/sim/tests/debug/tb_top.v
0,0 → 1,93
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module tb_top();
 
parameter CLK_PERIOD = 10;
 
reg tb_clk, tb_rst;
 
initial
begin
tb_clk <= 1'b1;
tb_rst <= 1'b1;
#(CLK_PERIOD); #(CLK_PERIOD/3);
tb_rst = 1'b0;
end
 
always
#(CLK_PERIOD/2) tb_clk = ~tb_clk;
// --------------------------------------------------------------------
// tb_dut
tb_dut dut( tb_clk, tb_rst );
 
// --------------------------------------------------------------------
// insert test below
 
initial
begin
wait( ~tb_rst );
repeat(2) @(posedge tb_clk);
//
$display("\n^^^- \n");
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000000, 1'b1, 32'h00000000 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000004, 1'b1, 32'h11111111 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000008, 1'b1, 32'h22222222 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h0000000c, 1'b1, 32'h33333333 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000010, 1'b1, 32'h44444444 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000014, 1'b1, 32'h55555555 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000018, 1'b1, 32'h66666666 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h0000001c, 1'b1, 32'h77777777 );
dut.i_bfm_ahb.bfm_ahb_write32( 32'h000000000, 32'habbabeef );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000000, 1'b1, 32'habbabeef );
dut.i_bfm_ahb.bfm_ahb_write16( 32'h000000004, 16'habcd );
dut.i_bfm_ahb.bfm_ahb_read16( 32'h00000004, 1'b1, 16'habcd );
dut.i_bfm_ahb.bfm_ahb_write16( 32'h000000006, 16'h1234 );
dut.i_bfm_ahb.bfm_ahb_read16( 32'h00000006, 1'b1, 16'h1234 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000004, 1'b1, 32'h1234abcd );
dut.i_bfm_ahb.bfm_ahb_write8( 32'h000000008, 8'ha1 );
dut.i_bfm_ahb.bfm_ahb_read8( 32'h00000008, 1'b1, 8'ha1 );
dut.i_bfm_ahb.bfm_ahb_write8( 32'h000000009, 8'hb2 );
dut.i_bfm_ahb.bfm_ahb_read8( 32'h00000009, 1'b1, 8'hb2 );
dut.i_bfm_ahb.bfm_ahb_write8( 32'h00000000a, 8'hc3 );
dut.i_bfm_ahb.bfm_ahb_read8( 32'h0000000a, 1'b1, 8'hc3 );
dut.i_bfm_ahb.bfm_ahb_write8( 32'h00000000b, 8'hd4 );
dut.i_bfm_ahb.bfm_ahb_read8( 32'h0000000b, 1'b1, 8'hd4 );
dut.i_bfm_ahb.bfm_ahb_read32( 32'h00000008, 1'b1, 32'hd4c3b2a1 );
repeat(2) @(posedge tb_clk);
if( dut.i_bfm_ahb.read_error )
$display("-!- Read mismatch. Testbench Failed. %t.\n", $time);
$display("\n^^^---------------------------------\n");
$display("^^^- Testbench done. %t.\n", $time);
$stop();
end
endmodule
 
/sim/models/bfm_ahb.v
0,0 → 1,426
//
//
//
 
`timescale 1ns / 100ps
 
 
 
module bfm_ahb(
output hclk,
output hresetn,
output [31:0] haddr,
output [1:0] htrans,
output hwrite,
output [2:0] hsize,
output [2:0] hburst,
output [3:0] hprot,
output [31:0] hwdata,
output hsel,
input [31:0] hrdata,
output hready_in,
input hready_out,
input [1:0] hresp,
input bfm_clk,
input bfm_reset
);
parameter LOG_LEVEL = 3;
 
// -----------------------------
//
reg read_error;
reg hready_out_wait_r;
reg [31:0] haddr_r;
reg [1:0] htrans_r;
reg hwrite_r;
reg [2:0] hsize_r;
reg [2:0] hburst_r;
reg [3:0] hprot_r;
reg [31:0] hwdata_r;
reg hsel_r;
reg hready_in_r;
assign haddr = haddr_r;
assign htrans = htrans_r;
assign hwrite = hwrite_r;
assign hsize = hsize_r;
assign hburst = hburst_r;
assign hprot = hprot_r;
assign hwdata = hwdata_r;
assign hsel = hsel_r;
assign hready_in = hready_in_r;
// -----------------------------
// initialize the bus
initial
begin
read_error <= 0;
bfm_ahb_default;
end
// -----------------------------
// addr_control_default
task addr_control_default;
begin
haddr_r <= 32'hxxxxxxxx;
htrans_r <= 2'bxx;
hwrite_r <= 1'bx;
hsize_r <= 3'bxxx;
hburst_r <= 3'bxxx;
hprot_r <= 4'bxxxx;
end
endtask
 
// -----------------------------
// bfm_ahb_default
task bfm_ahb_default;
begin
hready_out_wait_r <= 1'b0;
addr_control_default();
hwdata_r <= 32'hxxxxxxxx;
hsel_r <= 1'b0;
hready_in_r <= 1'b0;
end
endtask
// -----------------------------
// bfm_ahb_write32
task bfm_ahb_write32;
input [31:0] target_addr;
input [31:0] target_data;
begin
 
if(LOG_LEVEL >= 3)
$display( "-+- bfm_ahb_write32: write 0x%x to 0x%x.", target_data, target_addr);
@(posedge hclk);
#1;
haddr_r <= target_addr;
hwdata_r <= target_data;
htrans_r <= 2'b10;
hwrite_r <= 1'b1;
hsize_r <= 3'b010;
hburst_r <= 3'b000;
hprot_r <= 4'b0000;
hsel_r <= 1'b1;
hready_in_r <= 1'b1;
@(negedge hclk);
@(negedge hclk);
 
hready_in_r = 1'b0;
hsel_r <= 1'b0;
addr_control_default();
 
hready_out_wait_r <= 1'b1;
wait(hready_out);
hready_out_wait_r <= 1'b0;
@(posedge hclk);
bfm_ahb_default;
end
endtask
// -----------------------------
// bfm_ahb_read32
task bfm_ahb_read32;
input [31:0] target_addr;
input check_data;
input [31:0] data_compare;
reg [31:0] read_data_r;
begin
 
@(posedge hclk);
#1;
haddr_r <= target_addr;
htrans_r <= 2'b10;
hwrite_r <= 1'b0;
hsize_r <= 3'b010;
hburst_r <= 3'b000;
hprot_r <= 4'b0000;
hsel_r <= 1'b1;
hready_in_r <= 1'b1;
@(negedge hclk);
@(negedge hclk);
hready_in_r = 1'b0;
hsel_r <= 1'b0;
addr_control_default();
 
hready_out_wait_r <= 1'b1;
wait(hready_out);
hready_out_wait_r <= 1'b0;
 
@(posedge hclk);
read_data_r <= hrdata;
@(posedge hclk);
bfm_ahb_default;
if(LOG_LEVEL >= 3)
$display( "-+- bfm_ahb_read32: read 0x%x from 0x%x.", read_data_r, target_addr);
if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )
begin
read_error = 1'b1;
$display( "-!- bfm_ahb_read32: Data mismatch. Should be 0x%x.", data_compare);
end
end
endtask
// -----------------------------
// bfm_ahb_write16
task bfm_ahb_write16;
input [31:0] target_addr;
input [15:0] target_data;
reg [15:0] target_data_lo;
reg [15:0] target_data_hi;
begin
 
if(LOG_LEVEL >= 3)
$display( "-+- bfm_ahb_write16: write 0x%x to 0x%x.", target_data, target_addr);
@(posedge hclk);
#1;
haddr_r <= target_addr;
target_data_lo = target_addr[1] ? 16'hxxxx : target_data;
target_data_hi = target_addr[1] ? target_data : 16'hxxxx;
hwdata_r <= { target_data_hi, target_data_lo };
htrans_r <= 2'b10;
hwrite_r <= 1'b1;
hsize_r <= 3'b001;
hburst_r <= 3'b000;
hprot_r <= 4'b0000;
hsel_r <= 1'b1;
hready_in_r <= 1'b1;
@(negedge hclk);
@(negedge hclk);
hready_in_r = 1'b0;
hsel_r <= 1'b0;
addr_control_default();
 
hready_out_wait_r <= 1'b1;
wait(hready_out);
hready_out_wait_r <= 1'b0;
@(posedge hclk);
bfm_ahb_default;
end
endtask
// -----------------------------
// bfm_ahb_read16
task bfm_ahb_read16;
input [31:0] target_addr;
input check_data;
input [15:0] data_compare;
reg [15:0] read_data_r;
begin
 
@(posedge hclk);
#1;
haddr_r <= target_addr;
htrans_r <= 2'b10;
hwrite_r <= 1'b0;
hsize_r <= 3'b001;
hburst_r <= 3'b000;
hprot_r <= 4'b0000;
hsel_r <= 1'b1;
hready_in_r <= 1'b1;
@(negedge hclk);
@(negedge hclk);
hready_in_r = 1'b0;
hsel_r <= 1'b0;
addr_control_default();
 
hready_out_wait_r <= 1'b1;
wait(hready_out);
hready_out_wait_r <= 1'b0;
@(posedge hclk);
read_data_r <= target_addr[1] ? hrdata[31:16] : hrdata[15:0];
@(posedge hclk);
bfm_ahb_default;
if(LOG_LEVEL >= 3)
$display( "-+- bfm_ahb_read16: read 0x%x from 0x%x.", read_data_r, target_addr);
if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )
begin
read_error = 1'b1;
$display( "-!- bfm_ahb_read32: Data mismatch. Should be 0x%x.", data_compare);
end
end
endtask
// -----------------------------
// bfm_ahb_write8
task bfm_ahb_write8;
input [31:0] target_addr;
input [7:0] target_data;
reg [7:0] target_data_0;
reg [7:0] target_data_1;
reg [7:0] target_data_2;
reg [7:0] target_data_3;
begin
 
if(LOG_LEVEL >= 3)
$display( "-+- bfm_ahb_write8: write 0x%x to 0x%x.", target_data, target_addr);
@(posedge hclk);
#1;
haddr_r <= target_addr;
target_data_0 = (target_addr[1:0] == 2'b00) ? target_data : 8'hxxxx;
target_data_1 = (target_addr[1:0] == 2'b01) ? target_data : 8'hxxxx;
target_data_2 = (target_addr[1:0] == 2'b10) ? target_data : 8'hxxxx;
target_data_3 = (target_addr[1:0] == 2'b11) ? target_data : 8'hxxxx;
hwdata_r <= { target_data_3, target_data_2, target_data_1, target_data_0 };
htrans_r <= 2'b10;
hwrite_r <= 1'b1;
hsize_r <= 3'b000;
hburst_r <= 3'b000;
hprot_r <= 4'b0000;
hsel_r <= 1'b1;
hready_in_r <= 1'b1;
@(negedge hclk);
@(negedge hclk);
hready_in_r = 1'b0;
hsel_r <= 1'b0;
addr_control_default();
 
hready_out_wait_r <= 1'b1;
wait(hready_out);
hready_out_wait_r <= 1'b0;
@(posedge hclk);
bfm_ahb_default;
end
endtask
// -----------------------------
// bfm_ahb_read8
task bfm_ahb_read8;
input [31:0] target_addr;
input check_data;
input [7:0] data_compare;
reg [7:0] read_data_r;
begin
 
@(posedge hclk);
#1;
haddr_r <= target_addr;
htrans_r <= 2'b10;
hwrite_r <= 1'b0;
hsize_r <= 3'b000;
hburst_r <= 3'b000;
hprot_r <= 4'b0000;
hsel_r <= 1'b1;
hready_in_r <= 1'b1;
@(negedge hclk);
@(negedge hclk);
hready_in_r = 1'b0;
hsel_r <= 1'b0;
addr_control_default();
 
hready_out_wait_r <= 1'b1;
wait(hready_out);
hready_out_wait_r <= 1'b0;
@(posedge hclk);
case( target_addr[1:0] )
2'b00: read_data_r = hrdata[7:0];
2'b01: read_data_r = hrdata[15:8];
2'b10: read_data_r = hrdata[23:16];
2'b11: read_data_r = hrdata[31:24];
endcase
@(posedge hclk);
bfm_ahb_default;
if(LOG_LEVEL >= 3)
$display( "-+- bfm_ahb_read8: read 0x%x from 0x%x.", read_data_r, target_addr);
if( LOG_LEVEL >= 1 & check_data & (data_compare !== read_data_r) )
begin
read_error = 1'b1;
$display( "-!- bfm_ahb_read8: Data mismatch. Should be 0x%x.", data_compare);
end
end
endtask
// -----------------------------
// outputs
assign hclk = bfm_clk;
assign hresetn = ~bfm_reset;
endmodule
 
 
/sim/models/wb_slave_model.v
0,0 → 1,138
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
`timescale 1ns/10ps
 
 
module wb_slave_model( clk_i, rst_i, dat_o, dat_i, adr_i,
cyc_i, stb_i, we_i, sel_i,
ack_o, err_o, rty_o );
 
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter ACK_DELAY = 2;
parameter SLAVE_RAM_INIT = "wb_slave_model.txt";
input clk_i;
input rst_i;
output [DWIDTH-1:0] dat_o;
input [DWIDTH-1:0] dat_i;
input [AWIDTH-1:0] adr_i;
input cyc_i;
input stb_i;
input we_i;
input [( (DWIDTH/8) - 1 ):0] sel_i;
output ack_o;
output err_o;
output rty_o;
// --------------------------------------------------------------------
// slave ram
reg [7:0] ram[2**AWIDTH-1:0];
initial
$readmemh( SLAVE_RAM_INIT, ram );
 
// --------------------------------------------------------------------
//
generate
case( DWIDTH )
8: begin
initial
$display( "###- wb_slave_model(): WISHBONE 8 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[adr_i] <= dat_i[7:0];
assign dat_o = ram[adr_i];
end
16: begin
initial
$display( "###- wb_slave_model(): WISHBONE 16 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[{adr_i[AWIDTH-1:1], 1'b0}] <= dat_i[7:0];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[1])
ram[{adr_i[AWIDTH-1:1], 1'b1}] <= dat_i[15:8];
assign dat_o = { ram[{adr_i[AWIDTH-1:1], 1'b1}], ram[{adr_i[AWIDTH-1:1], 1'b0}] };
end
32: begin
initial
$display( "###- wb_slave_model(): WISHBONE 32 BIT SLAVE MODEL INSTANTIATED " );
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[0])
ram[{adr_i[AWIDTH-1:2], 2'b00}] <= dat_i[7:0];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[1])
ram[{adr_i[AWIDTH-1:2], 2'b01}] <= dat_i[15:8];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[2])
ram[{adr_i[AWIDTH-1:2], 2'b10}] <= dat_i[23:16];
always @ (posedge clk_i)
if (we_i & cyc_i & stb_i & sel_i[3])
ram[{adr_i[AWIDTH-1:2], 2'b11}] <= dat_i[31:24];
assign dat_o = { ram[{adr_i[AWIDTH-1:2], 2'b11}], ram[{adr_i[AWIDTH-1:2], 2'b10}], ram[{adr_i[AWIDTH-1:2], 2'b01}], ram[{adr_i[AWIDTH-1:2], 2'b00}] };
end
default: begin
localparam SLAVE_SIZE = -1;
initial
begin
$display( "!!!- wb_slave_model(): invalad DWIDTH parameter" );
$stop();
end
end
endcase
endgenerate
 
// --------------------------------------------------------------------
// ack delay
reg ack_delayed;
initial
ack_delayed = 1'b0;
always @(posedge clk_i or cyc_i or stb_i)
begin
if(cyc_i & stb_i)
begin
ack_delayed = 1'b0;
repeat(ACK_DELAY) @(posedge clk_i);
if(cyc_i & stb_i)
ack_delayed = 1'b1;
else
ack_delayed = 1'b0;
end
else
ack_delayed = 1'b0;
end
// --------------------------------------------------------------------
// assign outputs
assign ack_o = ack_delayed;
assign err_o = 1'b0;
assign rty_o = 1'b0;
 
endmodule

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