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URL https://opencores.org/ocsvn/wbscope/wbscope/trunk

Subversion Repositories wbscope

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  • This comparison shows the changes necessary to convert path 
    /wbscope/trunk/bench/rtl
    from Rev 12 to Rev 13
    ↔ Reverse comparison
  •

Rev 12 → Rev 13

/Makefile
1,15 → 1,14
################################################################################
#
# Filename: Makefile
#
# Project: WBScope, a wishbone hosted scope
#
# Purpose: This makefile builds a verilator simulation of the rtl
# testbenches necessary to test certain components of the
# wishbone scope using Verilator. It does not make the system within
## Icarus, Vivado or Quartus.
##
## Filename: Makefile
##
## Project: WBScope, a wishbone hosted scope
##
## Purpose: This makefile builds a verilator simulation of the rtl
## testbenches necessary to test certain components of both the
## wishbone scope and its RLE compressed brother using Verilator.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
40,13 → 39,18
##
##
.PHONY: all
all: wbscope_tb
all: wbscope_tb wbscopc_tb
 
RTLD := ../../rtl
VOBJ := obj_dir
 
#
#
# Building the wbscope test bench
#
#
$(VOBJ)/Vwbscope_tb.cpp: $(RTLD)/wbscope.v wbscope_tb.v
verilator -trace -cc -y $(RTLD) wbscope_tb.v
verilator -Wall -O3 -trace -cc -y $(RTLD) wbscope_tb.v
$(VOBJ)/Vwbscope_tb.h: $(VOBJ)/Vwbscope_tb.cpp
 
$(VOBJ)/Vwbscope_tb__ALL.a: $(VOBJ)/Vwbscope_tb.cpp $(VOBJ)/Vwbscope_tb.h
55,6 → 59,21
.PHONY: wbscope_tb
wbscope_tb: $(VOBJ)/Vwbscope_tb__ALL.a
 
#
#
# Building the wbscopc test bench, for the compressed wbscope
#
#
$(VOBJ)/Vwbscopc_tb.cpp: $(RTLD)/wbscopc.v wbscopc_tb.v
verilator -Wall -O3 -trace -cc -y $(RTLD) wbscopc_tb.v
$(VOBJ)/Vwbscopc_tb.h: $(VOBJ)/Vwbscopc_tb.cpp
 
$(VOBJ)/Vwbscopc_tb__ALL.a: $(VOBJ)/Vwbscopc_tb.cpp $(VOBJ)/Vwbscopc_tb.h
make --no-print-directory --directory=$(VOBJ) -f Vwbscopc_tb.mk
 
.PHONY: wbscopc_tb
wbscopc_tb: $(VOBJ)/Vwbscopc_tb__ALL.a
 
# $(VOBJ)/Vaxiscope_tb.cpp: $(RTLD)/axiscope.v axiscope.v
# verilator -trace -cc -y $(RTLD) wbscope_tb.v
# $(VOBJ)/Vaxiscope_tb.h: $(VOBJ)/Vwbscope_tb.cpp
/wbscopc_tb.v
0,0 → 1,92
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbscopc_tb.v
//
// Project: WBScope, a wishbone hosted scope
//
// Purpose: This file is a test bench wrapper around the compressed
// wishbone scope, designed to create a "signal" which can then
// be scoped and proven. Unlike the case of the normal wishbone scope,
// this scope needs a test signal that has lots of idle time surrounded
// my sudden changes. We'll handle our sudden changes via a counter.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbscope_tb(i_clk,
// i_rst is required by our test infrastructure, yet unused here
i_rst,
// The test data. o_data is internally generated here from
// o_counter, i_trigger is given externally
i_trigger, o_data, o_counter,
// Wishbone bus interaction
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
// wishbone bus outputs
o_wb_ack, o_wb_stall, o_wb_data,
// And our output interrupt
o_interrupt);
input i_clk, i_rst, i_trigger;
output wire [30:0] o_data;
output wire [29:0] o_counter;
//
input i_wb_cyc, i_wb_stb, i_wb_we;
input i_wb_addr;
input [31:0] i_wb_data;
//
output wire o_wb_ack;
output wire [31:0] o_wb_data;
output wire o_wb_stall;
//
output o_interrupt;
 
reg [29:0] counter;
initial counter = 0;
always @(posedge i_clk)
counter <= counter + 1'b1;
always @(posedge i_clk)
if (counter[11:8] == 4'h0)
o_data <= { i_trigger, counter };
else if ((counter[10])&&(counter[1]))
o_data <= { i_trigger, counter };
else
o_data <= { i_trigger, counter[29:12], 12'h0 };
 
wire wb_stall_ignored;
 
wbscopc #(.LGMEM(5'd14), .BUSW(32), .SYNCHRONOUS(1), .MAX_STEP(768),
.DEFAULT_HOLDOFF(36))
scope(i_clk, 1'b1, i_trigger, o_data,
i_clk, i_wb_cyc, i_wb_stb, i_wb_we,
i_wb_addr, i_wb_data,
o_wb_ack, wb_stall_ignored, o_wb_data,
o_interrupt);
 
assign o_wb_stall = 1'b0;
 
endmodule
/wbscope_tb.v
4,7 → 4,12
//
// Project: WBScope, a wishbone hosted scope
//
// Purpose:
// Purpose: This file is a test bench wrapper around the wishbone scope,
// designed to create a "signal" which can then be scoped and
// proven. In our case here, the "signal" is a counter. When we test
// the scope within our bench/cpp Verilator testbench, we'll know if our
// test was "correct" if the counter 1) only ever counts by 1, and 2) if
// the trigger lands on thte right data sample.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
35,9 → 40,18
////////////////////////////////////////////////////////////////////////////////
//
//
module wbscope_tb(i_clk, i_rst, i_trigger, o_data,
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_data, o_interrupt);
module wbscope_tb(i_clk,
// i_rst is required by our test infrastructure, yet unused here
i_rst,
// The test data. o_data is internally generated here from a
// counter, i_trigger is given externally
i_trigger, o_data,
// Wishbone bus interaction
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
// wishbone bus outputs
o_wb_ack, o_wb_stall, o_wb_data,
// And our output interrupt
o_interrupt);
input i_clk, i_rst, i_trigger;
output wire [31:0] o_data;
//
46,6 → 60,7
input [31:0] i_wb_data;
//
output wire o_wb_ack;
output wire o_wb_stall;
output wire [31:0] o_wb_data;
//
output o_interrupt;
59,7 → 74,8
 
wire wb_stall_ignored;
 
wbscope #(5'd6, 32, 1)
wbscope #(.LGMEM(5'd6), .BUSW(32), .SYNCHRONOUS(1),
.DEFAULT_HOLDOFF(1))
scope(i_clk, 1'b1, i_trigger, o_data,
i_clk, i_wb_cyc, i_wb_stb, i_wb_we,
i_wb_addr, i_wb_data,
66,4 → 82,10
o_wb_ack, wb_stall_ignored, o_wb_data,
o_interrupt);
 
assign o_wb_stall = 1'b0;
 
// verilator lint_off UNUSED
wire [1:0] unused;
assign unused = { i_rst, wb_stall_ignored };
// verilator lint_on UNUSED
endmodule

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