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URL https://opencores.org/ocsvn/wbscope/wbscope/trunk

Subversion Repositories wbscope

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  • This comparison shows the changes necessary to convert path 
    /wbscope/trunk/rtl
    from Rev 12 to Rev 13
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  •

Rev 12 → Rev 13

/Makefile
0,0 → 1,69
################################################################################
##
## Filename: rtl/Makefile
##
## Project: WBScope, a wishbone hosted scope
##
## Purpose: To direct the Verilator build of the SoC sources. The result
## is C++ code (built by Verilator), that is then built (herein)
## into a library.
##
## Targets: The default target, all, builds the target test, which includes
## the libraries necessary for Verilator testing.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015-2017, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory. Run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
################################################################################
##
##
all: test axi
FBDIR := .
VDIRFB:= $(FBDIR)/obj_dir
 
.PHONY: test
test: $(VDIRFB)/Vwbscope__ALL.a
test: $(VDIRFB)/Vwbscopc__ALL.a
.PHONY: axi
axi: $(VDIRFB)/Vaxi4lscope__ALL.a
 
$(VDIRFB)/Vwbscope__ALL.a: $(VDIRFB)/Vwbscope.h $(VDIRFB)/Vwbscope.cpp
$(VDIRFB)/Vwbscope__ALL.a: $(VDIRFB)/Vwbscope.mk
$(VDIRFB)/Vwbscope.h $(VDIRFB)/Vwbscope.cpp $(VDIRFB)/Vwbscope.mk: wbscope.v
 
$(VDIRFB)/Vwbscopc__ALL.a: $(VDIRFB)/Vwbscopc.h $(VDIRFB)/Vwbscopc.cpp
$(VDIRFB)/Vwbscopc__ALL.a: $(VDIRFB)/Vwbscopc.mk
$(VDIRFB)/Vwbscopc.h $(VDIRFB)/Vwbscopc.cpp $(VDIRFB)/Vwbscopc.mk: wbscopc.v
 
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator -Wall -cc $*.v
 
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
cd $(VDIRFB); make -f V$*.mk
 
.PHONY: clean
clean:
rm -rf $(VDIRFB)/
 
/axi4lscope.v
3,7 → 3,7
//
// Filename: axi4lscope.v
//
// Project: FPGA Library of Routines
// Project: WBScope, a wishbone hosted scope
//
// Purpose: This is a generic/library routine for providing a bus accessed
// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer.
12,7 → 12,7
// reset, the scope records a copy of the input data every time the clock
// ticks with the circuit enabled. That is, it records these values up
// until the trigger. Once the trigger goes high, the scope will record
// for bw_holdoff more counts before stopping. Values may then be read
// for br_holdoff more counts before stopping. Values may then be read
// from the buffer, oldest to most recent. After reading, the scope may
// then be reset for another run.
//
28,7 → 28,7
// 5. The scope recording is then paused until the next reset.
// 6. While stopped, the CPU can read the data from the scope
// 7. -- oldest to most recent
// 8. -- one value per i_rd&i_clk
// 8. -- one value per i_rd&i_data_clk
// 9. Writes to the data register reset the address to the
// beginning of the buffer
//
68,7 → 68,7
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
81,7 → 81,7
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
92,13 → 92,17
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module axi4lscope
#(
// Users to add parameters here
parameter LGMEM = 5'd10,
parameter [4:0] LGMEM = 5'd10,
parameter BUSW = 32,
parameter SYNCHRONOUS=1,
parameter DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4),
parameter HOLDOFFBITS = 20,
parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF
= ((1<<(LGMEM-1))-4),
// User parameters ends
// DO NOT EDIT BELOW THIS LINE ---------------------
// Do not modify the parameters beyond this line
109,7 → 113,7
)
(
// Users to add ports here
input wire i_clk, // The data clock, can be set to ACLK
input wire i_data_clk, // The data clock, can be set to ACLK
input wire i_ce, // = '1' when recordable data is present
input wire i_trigger,// = '1' when interesting event hapns
input wire [31:0] i_data,
188,11 → 192,12
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
// reg [1 : 0] axi_rresp;
reg axi_rvalid;
 
 
wire write_stb;
 
///////////////////////////////////////////////////
//
// Decode and handle the AXI/Bus signaling
234,8 → 239,6
axi_wready <= 1'b0;
assign S_AXI_WREADY = axi_wready;
 
wire write_stb;
 
always @(posedge S_AXI_ACLK)
if (i_reset)
begin
303,6 → 306,9
// From here on down, Gisselquist Technology, LLC,
// claims a copyright on the code.
//
wire bus_clock;
assign bus_clock = S_AXI_ACLK;
 
wire read_from_data;
assign read_from_data = (S_AXI_ARVALID)&&(S_AXI_ARREADY)
&&(axi_araddr[0]);
312,6 → 318,9
wire write_to_control;
assign write_to_control = (write_stb)&&(!axi_awaddr[0]);
 
reg read_address;
always @(posedge bus_clock)
read_address <= axi_araddr[0];
 
wire [31:0] i_wb_data;
assign i_wb_data = S_AXI_WDATA;
338,22 → 347,22
// Our status/config register
wire bw_reset_request, bw_manual_trigger,
bw_disable_trigger, bw_reset_complete;
reg [22:0] br_config;
wire [19:0] bw_holdoff;
initial br_config = DEFAULT_HOLDOFF;
always @(posedge S_AXI_ACLK)
reg [2:0] br_config;
reg [(HOLDOFFBITS-1):0] br_holdoff;
initial br_config = 3'b0;
initial br_holdoff = DEFAULT_HOLDOFF;
always @(posedge bus_clock)
if (write_to_control)
begin
br_config <= { i_wb_data[31],
(i_wb_data[27]),
i_wb_data[26],
i_wb_data[19:0] };
i_wb_data[27],
i_wb_data[26] };
br_holdoff <= i_wb_data[(HOLDOFFBITS-1):0];
end else if (bw_reset_complete)
br_config[22] <= 1'b1;
assign bw_reset_request = (~br_config[22]);
assign bw_manual_trigger = (br_config[21]);
assign bw_disable_trigger = (br_config[20]);
assign bw_holdoff = br_config[19:0];
br_config[2] <= 1'b1;
assign bw_reset_request = (!br_config[2]);
assign bw_manual_trigger = (br_config[1]);
assign bw_disable_trigger = (br_config[0]);
 
wire dw_reset, dw_manual_trigger, dw_disable_trigger;
generate
372,7 → 381,7
// so do a clock transfer here
initial q_iflags = 3'b000;
initial r_reset_complete = 1'b0;
always @(posedge i_clk)
always @(posedge i_data_clk)
begin
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
r_iflags <= q_iflags;
389,7 → 398,7
// clock that the reset has been accomplished
initial q_reset_complete = 1'b0;
initial qq_reset_complete = 1'b0;
always @(posedge S_AXI_ACLK)
always @(posedge bus_clock)
begin
q_reset_complete <= r_reset_complete;
qq_reset_complete <= q_reset_complete;
403,15 → 412,14
//
//
// Write with the i-clk, or input clock. All outputs read with the
// WISHBONE-clk, or S_AXI_ACLK clock.
// bus clock, or bus_clock as we've called it here.
reg dr_triggered, dr_primed;
wire dw_trigger;
assign dw_trigger = (dr_primed)&&(
((i_trigger)&&(~dw_disable_trigger))
||(dr_triggered)
((i_trigger)&&(!dw_disable_trigger))
||(dw_manual_trigger));
initial dr_triggered = 1'b0;
always @(posedge i_clk)
always @(posedge i_data_clk)
if (dw_reset)
dr_triggered <= 1'b0;
else if ((i_ce)&&(dw_trigger))
421,24 → 429,26
// Determine when memory is full and capture is complete
//
// Writes take place on the data clock
// The counter is unsigned
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] counter;
 
reg dr_stopped;
reg [19:0] counter; // This is unsigned
initial dr_stopped = 1'b0;
initial counter = 20'h0000;
always @(posedge i_clk)
initial counter = 0;
always @(posedge i_data_clk)
if (dw_reset)
counter <= 0;
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
begin
counter <= 0;
counter <= counter + 1'b1;
end
always @(posedge i_data_clk)
if ((!dr_triggered)||(dw_reset))
dr_stopped <= 1'b0;
end else if ((i_ce)&&(dr_triggered))
begin // MUST BE a < and not <=, so that we can keep this w/in
// 20 bits. Else we'd need to add a bit to comparison
// here.
if (counter < bw_holdoff)
counter <= counter + 20'h01;
else
dr_stopped <= 1'b1;
end
else if (HOLDOFFBITS > 1) // if (i_ce)
dr_stopped <= (counter >= br_holdoff);
else if (HOLDOFFBITS <= 1)
dr_stopped <= ((i_ce)&&(dw_trigger));
 
//
// Actually do our writes to memory. Record, via 'primed' when
453,21 → 463,58
reg [(LGMEM-1):0] waddr;
initial waddr = {(LGMEM){1'b0}};
initial dr_primed = 1'b0;
always @(posedge i_clk)
always @(posedge i_data_clk)
if (dw_reset) // For simulation purposes, supply a valid value
begin
waddr <= 0; // upon reset.
dr_primed <= 1'b0;
end else if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
end else if ((i_ce)&&(!dr_stopped))
begin
// mem[waddr] <= i_data;
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
dr_primed <= (dr_primed)||(&waddr);
if (!dr_primed)
begin
//if (br_holdoff[(HOLDOFFBITS-1):LGMEM]==0)
// dr_primed <= (waddr >= br_holdoff[(LGMEM-1):0]);
// else
dr_primed <= (&waddr);
end
end
always @(posedge i_clk)
if ((i_ce)&&((~dr_triggered)||(counter < bw_holdoff)))
mem[waddr] <= i_data;
 
// Delay the incoming data so that we can get our trigger
// logic to line up with the data. The goal is to have a
// hold off of zero place the trigger in the last memory
// address.
localparam STOPDELAY = 1;
wire [(BUSW-1):0] wr_piped_data;
generate
if (STOPDELAY == 0)
// No delay ... just assign the wires to our input lines
assign wr_piped_data = i_data;
else if (STOPDELAY == 1)
begin
//
// Delay by one means just register this once
reg [(BUSW-1):0] data_pipe;
always @(posedge i_data_clk)
if (i_ce)
data_pipe <= i_data;
assign wr_piped_data = data_pipe;
end else begin
// Arbitrary delay ... use a longer pipe
reg [(STOPDELAY*BUSW-1):0] data_pipe;
 
always @(posedge i_data_clk)
if (i_ce)
data_pipe <= { data_pipe[((STOPDELAY-1)*BUSW-1):0], i_data };
assign wr_piped_data = { data_pipe[(STOPDELAY*BUSW-1):((STOPDELAY-1)*BUSW)] };
end endgenerate
 
always @(posedge i_data_clk)
if ((i_ce)&&(!dr_stopped))
mem[waddr] <= wr_piped_data;
 
//
// Clock transfer of the status signals
//
488,7 → 535,7
reg [2:0] r_oflags;
initial q_oflags = 3'h0;
initial r_oflags = 3'h0;
always @(posedge S_AXI_ACLK)
always @(posedge bus_clock)
if (bw_reset_request)
begin
q_oflags <= 3'h0;
504,34 → 551,37
end endgenerate
 
// Reads use the bus clock
reg br_wb_ack;
initial br_wb_ack = 1'b0;
always @(posedge S_AXI_ACLK)
always @(posedge bus_clock)
begin
if ((bw_reset_request)||((write_stb)&&(axi_awaddr[0])))
if ((bw_reset_request)||(write_to_control))
raddr <= 0;
else if ((read_from_data)&&(bw_stopped))
// Data read ... only takes place when stopped
raddr <= raddr + {{(LGMEM-1){1'b0}},1'b1};
raddr <= raddr + 1'b1; // Data read, when stopped
end
 
reg [(LGMEM-1):0] this_addr;
always @(posedge bus_clock)
if (read_from_data)
this_addr <= raddr + waddr + 1'b1;
else
this_addr <= raddr + waddr;
 
reg [31:0] nxt_mem;
always @(posedge S_AXI_ACLK)
nxt_mem <= mem[raddr+waddr+ ((read_from_data) ?
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
always @(posedge bus_clock)
nxt_mem <= mem[this_addr];
 
wire [19:0] full_holdoff;
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
generate if (HOLDOFFBITS < 20)
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
endgenerate
 
 
 
 
 
 
reg [31:0] o_bus_data;
wire [4:0] bw_lgmem;
assign bw_lgmem = LGMEM;
always @(posedge S_AXI_ACLK)
if (~axi_araddr[0]) // Control register read
axi_rdata <= { bw_reset_request,
always @(posedge bus_clock)
if (!read_address) // Control register read
o_bus_data <= { bw_reset_request,
bw_stopped,
bw_triggered,
bw_primed,
539,24 → 589,29
bw_disable_trigger,
(raddr == {(LGMEM){1'b0}}),
bw_lgmem,
bw_holdoff };
else if (~bw_stopped) // read, prior to stopping
axi_rdata <= i_data;
full_holdoff };
else if (!bw_stopped) // read, prior to stopping
o_bus_data <= i_data;
else // if (i_wb_addr) // Read from FIFO memory
axi_rdata <= nxt_mem; // mem[raddr+waddr];
assign S_AXI_RDATA = axi_rdata;
o_bus_data <= nxt_mem; // mem[raddr+waddr];
 
assign S_AXI_RDATA = o_bus_data;
 
reg br_level_interrupt;
initial br_level_interrupt = 1'b0;
assign o_interrupt = (bw_stopped)&&(~bw_disable_trigger)
&&(~br_level_interrupt);
always @(posedge S_AXI_ACLK)
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
&&(!br_level_interrupt);
always @(posedge bus_clock)
if ((bw_reset_complete)||(bw_reset_request))
br_level_interrupt<= 1'b0;
else
br_level_interrupt<= (bw_stopped)&&(~bw_disable_trigger);
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
 
// verilator lint_off UNUSED
// Make verilator happy
wire [44:0] unused;
assign unused = { S_AXI_WSTRB, S_AXI_ARPROT, S_AXI_AWPROT,
axi_awaddr[3:1], axi_araddr[3:1],
i_wb_data[30:28], i_wb_data[25:0] };
// verilator lint_on UNUSED
endmodule
 
 
/wbscopc.v
5,12 → 5,10
// Project: WBScope, a wishbone hosted scope
//
// Purpose: This scope is identical in function to the wishbone scope
// found in wbscope, save that the output is compressed and that (as a
// result) it can only handle recording 31 bits at a time. This allows
// the top bit to indicate an 'address difference'. Okay, there's
// another difference as well: this version only works in a synchronous
// fashion with the clock from the WB bus. You cannot have a separate
// bus and data clock.
// found in wbscope, save that the output is compressed via a run-length
// encoding scheme and that (as a result) it can only handle recording
// 31 bits at a time. This allows the top bit to indicate the presence
// of an 'address difference' rather than actual incoming recorded data.
//
// Reading/decompressing the output of this scope works in this fashion:
// Once the scope has stopped, read from the port. Any time the high
18,46 → 16,28
// the last value. If the high order bit is not set, then the value
// is a new data value.
//
// I've provided this version of a compressed scope to OpenCores for
// discussion purposes. While wbscope.v works and works well by itself,
// this compressed scope has a couple of fundamental flaw that I have
// yet to fix. One of them is that it is impossible to know when the
// trigger took place. The second problem is that it may be impossible
// to know the state of the scope at the beginning of the buffer--should
// the buffer begin with an address difference value instead of a data
// value.
// Previous versions of the compressed scope have had some fundamental
// flaws: 1) it was impossible to know when the trigger took place, and
// 2) if things never changed, the scope would never fill or complete
// its capture. These two flaws have been fixed with this release.
//
// Ideally, the first item read out of the scope should be a data value,
// even if the scope was skipping values to a new address at the time.
// If it was in the middle of a skip, the next item out of the scope
// should be the skip length. This, though, violates the rule that there
// are (1<<LGMEMLEN) items in the memory, and that the trigger took place
// on the last item of memory ... so that portion of this compressed
// scope is still to be defined.
// When dealing with a slow interface such as the PS/2 interface, or even
// the 16x2 LCD interface, it is often true that things can change _very_
// slowly. They could change so slowly that the standard wishbone scope
// doesn't work. This scope then gives you a working scope, by sampling
// at diverse intervals, and only capturing anything that changes within
// those intervals.
//
// Like I said, this version is placed here for discussion purposes,
// not because it runs well nor because I have recognized that it has any
// particular value (yet).
// Indeed, I'm finding this compressed scope very valuable for evaluating
// the timing associated with a GPS PPS and associated NMEA stream. I
// need to collect over a seconds worth of data, and I don't have enough
// memory to handle one memory value per clock, yet I still want to know
// exactly when the GPS PPS goes high, when it goes low, when I'm
// adjusting my clock, and when the clock's PPS output goes high. Did I
// synchronize them well? Oh, and when does the NMEA time string show up
// when compared with the PPS? All of those are valuable, but could never
// be done if the scope wasn't compressed.
//
// Well, I take that back. When dealing with an interface such as the
// PS/2 interface, or even the 16x2 LCD interface, it is often true
// that things change _very_ slowly. They could change so slowly that
// the other approach to the scope doesn't work. This then gives you
// a working scope, by only capturing the changes. You'll still need
// to figure out (after the fact) when the trigge took place. Perhaps
// you'll wish to add the trigger as another data line, so you can find
// when it took place in your own data?
//
// Okay, I take that back twice: I'm finding this compressed scope very
// valuable for evaluating the timing associated with a GPS PPS and
// associated NMEA stream. I need to collect over a seconds worth of
// data, and I don't have enough memory to handle one memory value per
// clock, yet I still want to know exactly when the GPS PPS goes high,
// when it goes low, when I'm adjusting my clock, and when the clock's
// PPS output goes high. Did I synchronize them well? Oh, and when does
// the NMEA time string show up when compared with the PPS? All of those
// are valuable, but could never be done if the scope wasn't compressed.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
87,20 → 67,28
////////////////////////////////////////////////////////////////////////////////
//
//
module wbscopc(i_clk, i_ce, i_trigger, i_data,
`default_nettype none
//
module wbscopc(i_data_clk, i_ce, i_trigger, i_data,
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_interrupt);
parameter LGMEM = 5'd10, NELM=31, BUSW = 32, SYNCHRONOUS=1;
parameter [4:0] LGMEM = 5'd10;
parameter BUSW = 32, NELM=(BUSW-1);
parameter [0:0] SYNCHRONOUS=1;
parameter HOLDOFFBITS=20;
parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
parameter STEP_BITS=BUSW-1;
parameter [(STEP_BITS-1):0] MAX_STEP= {(STEP_BITS){1'b1}};
// The input signals that we wish to record
input i_clk, i_ce, i_trigger;
input [(NELM-1):0] i_data;
input wire i_data_clk, i_ce, i_trigger;
input wire [(NELM-1):0] i_data;
// The WISHBONE bus for reading and configuring this scope
input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
input i_wb_addr; // One address line only
input [(BUSW-1):0] i_wb_data;
input wire i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
input wire i_wb_addr; // One address line only
input wire [(BUSW-1):0] i_wb_data;
output wire o_wb_ack, o_wb_stall;
output wire [(BUSW-1):0] o_wb_data;
output reg [(BUSW-1):0] o_wb_data;
// And, finally, for a final flair --- offer to interrupt the CPU after
// our trigger has gone off. This line is equivalent to the scope
// being stopped. It is not maskable here.
107,47 → 95,216
output wire o_interrupt;
 
 
// Let's first see how far we can get by cheating. We'll use the
// wbscope program, and suffer a lack of several features
 
// When is the full scope reset? Capture that reset bit from any
// write.
wire lcl_reset;
assign lcl_reset = (i_wb_stb)&&(~i_wb_addr)&&(i_wb_we)
&&(~i_wb_data[31]);
reg [(LGMEM-1):0] raddr;
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
 
// A big part of this scope is the 'address' of any particular
// data value. As of this current version, the 'address' changed
// in definition from an absolute time (which had all kinds of
// problems) to a difference in time. Hence, when the address line
// is high on decompression, the 'address' field will record an
// Our status/config register
wire bw_reset_request, bw_manual_trigger,
bw_disable_trigger, bw_reset_complete;
reg [2:0] br_config;
reg [(HOLDOFFBITS-1):0] br_holdoff;
initial br_config = 3'b0;
initial br_holdoff = DEFAULT_HOLDOFF;
always @(posedge i_wb_clk)
if ((i_wb_stb)&&(!i_wb_addr))
begin
if (i_wb_we)
begin
br_config <= { i_wb_data[31],
i_wb_data[27],
i_wb_data[26] };
br_holdoff <= i_wb_data[(HOLDOFFBITS-1):0];
end
end else if (bw_reset_complete)
br_config[2] <= 1'b1;
assign bw_reset_request = (!br_config[2]);
assign bw_manual_trigger = (br_config[1]);
assign bw_disable_trigger = (br_config[0]);
 
 
wire dw_reset, dw_manual_trigger, dw_disable_trigger;
generate
if (SYNCHRONOUS > 0)
begin
assign dw_reset = bw_reset_request;
assign dw_manual_trigger = bw_manual_trigger;
assign dw_disable_trigger = bw_disable_trigger;
assign bw_reset_complete = bw_reset_request;
end else begin
reg r_reset_complete;
(* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags;
reg [2:0] r_iflags;
 
// Resets are synchronous to the bus clock, not the data clock
// so do a clock transfer here
initial q_iflags = 3'b000;
initial r_reset_complete = 1'b0;
always @(posedge i_data_clk)
begin
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
r_iflags <= q_iflags;
r_reset_complete <= (dw_reset);
end
 
assign dw_reset = r_iflags[2];
assign dw_manual_trigger = r_iflags[1];
assign dw_disable_trigger = r_iflags[0];
 
(* ASYNC_REG = "TRUE" *) reg q_reset_complete;
reg qq_reset_complete;
// Pass an acknowledgement back from the data clock to the bus
// clock that the reset has been accomplished
initial q_reset_complete = 1'b0;
initial qq_reset_complete = 1'b0;
always @(posedge i_wb_clk)
begin
q_reset_complete <= r_reset_complete;
qq_reset_complete <= q_reset_complete;
end
 
assign bw_reset_complete = qq_reset_complete;
end endgenerate
 
//
// Set up the trigger
//
//
// Write with the i-clk, or input clock. All outputs read with the
// WISHBONE-clk, or i_wb_clk clock.
reg dr_triggered, dr_primed;
wire dw_trigger;
assign dw_trigger = (dr_primed)&&(
((i_trigger)&&(!dw_disable_trigger))
||(dw_manual_trigger));
initial dr_triggered = 1'b0;
always @(posedge i_data_clk)
if (dw_reset)
dr_triggered <= 1'b0;
else if ((i_ce)&&(dw_trigger))
dr_triggered <= 1'b1;
 
//
// Determine when memory is full and capture is complete
//
// Writes take place on the data clock
// The counter is unsigned
(* ASYNC_REG="TRUE" *) reg [(HOLDOFFBITS-1):0] holdoff_counter;
 
reg dr_stopped;
initial dr_stopped = 1'b0;
initial holdoff_counter = 0;
always @(posedge i_data_clk)
if (dw_reset)
holdoff_counter <= 0;
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
begin
holdoff_counter <= holdoff_counter + 1'b1;
end
 
always @(posedge i_data_clk)
if ((!dr_triggered)||(dw_reset))
dr_stopped <= 1'b0;
else if ((i_ce)&&(!dr_stopped))
begin
if (HOLDOFFBITS > 1) // if (i_ce)
dr_stopped <= (holdoff_counter >= br_holdoff);
else if (HOLDOFFBITS <= 1)
dr_stopped <= ((i_ce)&&(dw_trigger));
end
 
localparam DLYSTOP=5;
reg [(DLYSTOP-1):0] dr_stop_pipe;
always @(posedge i_data_clk)
if (dw_reset)
dr_stop_pipe <= 0;
else if (i_ce)
dr_stop_pipe <= { dr_stop_pipe[(DLYSTOP-2):0], dr_stopped };
 
wire dw_final_stop;
assign dw_final_stop = dr_stop_pipe[(DLYSTOP-1)];
 
// A big part of this scope is the run length of any particular
// data value. Hence, when the address line (i.e. data[31])
// is high on decompression, the run length field will record an
// address difference.
//
// To implement this, we set our 'address' to zero any time the
// To implement this, we set our run length to zero any time the
// data changes, but increment it on all other clocks. Should the
// address difference get to our maximum value, we let it saturate
// rather than overflow.
reg [(BUSW-2):0] ck_addr;
reg [(NELM-1):0] lst_dat;
reg [(STEP_BITS-1):0] ck_addr;
reg [(NELM-1):0] qd_data;
reg dr_force_write, dr_run_timeout,
new_data;
 
//
// The "dr_force_write" logic here is designed to make sure we write
// at least every MAX_STEP samples, and that we stop as soon as
// we are able. Hence, if an interface is slow
// and idle, we'll at least prime the scope, and even if the interface
// doesn't have enough transitions to fill our buffer, we'll at least
// fill the buffer with repeats.
//
reg dr_force_inhibit;
initial ck_addr = 0;
always @(posedge i_clk)
if ((lcl_reset)||((i_ce)&&(i_data != lst_dat)))
initial dr_force_write = 1'b0;
always @(posedge i_data_clk)
if (dw_reset)
begin
dr_force_write <= 1'b1;
dr_force_inhibit <= 1'b0;
end else if (i_ce)
begin
dr_force_inhibit <= (dr_force_write);
if ((dr_run_timeout)&&(!dr_force_write)&&(!dr_force_inhibit))
dr_force_write <= 1'b1;
else if (((dw_trigger)&&(!dr_triggered))||(!dr_primed))
dr_force_write <= 1'b1;
else
dr_force_write <= 1'b0;
end
 
//
// Keep track of how long it has been since the last write
//
always @(posedge i_data_clk)
if (dw_reset)
ck_addr <= 0;
else if (&ck_addr)
; // Saturated (non-overflowing) address diff
else
ck_addr <= ck_addr + 1;
else if (i_ce)
begin
if ((dr_force_write)||(new_data)||(dr_stopped))
ck_addr <= 0;
else
ck_addr <= ck_addr + 1'b1;
end
 
always @(posedge i_data_clk)
if (dw_reset)
dr_run_timeout <= 1'b1;
else if (i_ce)
dr_run_timeout <= (ck_addr >= MAX_STEP-1'b1);
 
always @(posedge i_data_clk)
if (dw_reset)
new_data <= 1'b1;
else if (i_ce)
new_data <= (i_data != qd_data);
 
always @(posedge i_data_clk)
if (i_ce)
qd_data <= i_data;
 
wire [(BUSW-2):0] w_data;
generate
if (NELM == BUSW-1)
assign w_data = i_data;
assign w_data = qd_data;
else
assign w_data = { {(BUSW-NELM-1){1'b0}}, i_data };
assign w_data = { {(BUSW-NELM-1){1'b0}}, qd_data };
endgenerate
 
//
// To do our compression, we keep track of two registers: the most
// To do our RLE compression, we keep track of two registers: the most
// recent data to the device (imm_ prefix) and the data from one
// clock ago. This allows us to suppress writes to the scope which
// would otherwise be two address writes in a row.
154,29 → 311,29
reg imm_adr, lst_adr; // Is this an address (1'b1) or data value?
reg [(BUSW-2):0] lst_val, // Data for the scope, delayed by one
imm_val; // Data to write to the scope
initial lst_dat = 0;
initial lst_adr = 1'b1;
initial imm_adr = 1'b1;
always @(posedge i_clk)
if (lcl_reset)
always @(posedge i_data_clk)
if (dw_reset)
begin
imm_val <= 31'h0;
imm_adr <= 1'b1;
lst_val <= 31'h0;
lst_adr <= 1'b1;
lst_dat <= 0;
end else if ((i_ce)&&(i_data != lst_dat))
end else if (i_ce)
begin
imm_val <= w_data;
imm_adr <= 1'b0;
lst_val <= imm_val;
lst_adr <= imm_adr;
lst_dat <= i_data;
end else begin
imm_val <= ck_addr; // Minimum value here is '1'
imm_adr <= 1'b1;
lst_val <= imm_val;
lst_adr <= imm_adr;
if ((new_data)||(dr_force_write)||(dr_stopped))
begin
imm_val <= w_data;
imm_adr <= 1'b0; // Last thing we wrote was data
lst_val <= imm_val;
lst_adr <= imm_adr;
end else begin
imm_val <= ck_addr; // Minimum value here is '1'
imm_adr <= 1'b1; // This (imm) is an address
lst_val <= imm_val;
lst_adr <= imm_adr;
end
end
 
//
183,38 → 340,163
// Here's where we suppress writing pairs of address words to the
// scope at once.
//
reg r_ce;
reg record_ce;
reg [(BUSW-1):0] r_data;
initial r_ce = 1'b0;
always @(posedge i_clk)
r_ce <= (~lst_adr)||(~imm_adr);
always @(posedge i_clk)
r_data <= ((~lst_adr)||(~imm_adr))
initial record_ce = 1'b0;
always @(posedge i_data_clk)
record_ce <= (i_ce)&&((!lst_adr)||(!imm_adr))&&(!dr_stop_pipe[2]);
always @(posedge i_data_clk)
r_data <= ((!lst_adr)||(!imm_adr))
? { lst_adr, lst_val }
: { {(32 - NELM){1'b0}}, i_data };
: { {(32 - NELM){1'b0}}, qd_data };
 
//
// Actually do our writes to memory. Record, via 'primed' when
// the memory is full.
//
// The 'waddr' address that we are using really crosses two clock
// domains. While writing and changing, it's in the data clock
// domain. Once stopped, it becomes part of the bus clock domain.
// The clock transfer on the stopped line handles the clock
// transfer for these signals.
//
reg [(LGMEM-1):0] waddr;
initial waddr = {(LGMEM){1'b0}};
initial dr_primed = 1'b0;
always @(posedge i_data_clk)
if (dw_reset) // For simulation purposes, supply a valid value
begin
waddr <= 0; // upon reset.
dr_primed <= 1'b0;
end else if (record_ce)
begin
// mem[waddr] <= i_data;
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
dr_primed <= (dr_primed)||(&waddr);
end
always @(posedge i_data_clk)
if (record_ce)
mem[waddr] <= r_data;
 
 
//
// The trigger needs some extra attention, in order to keep triggers
// that happen between events from being ignored.
//
wire w_trigger;
assign w_trigger = (r_trigger)||(i_trigger);
//
// Bus response
//
//
 
reg r_trigger;
initial r_trigger = 1'b0;
always @(posedge i_clk)
if (lcl_reset)
r_trigger <= 1'b0;
else
r_trigger <= w_trigger;
//
// Clock transfer of the status signals
//
wire bw_stopped, bw_triggered, bw_primed;
generate
if (SYNCHRONOUS > 0)
begin
assign bw_stopped = dw_final_stop;
assign bw_triggered = dr_triggered;
assign bw_primed = dr_primed;
end else begin
// These aren't a problem, since none of these are strobe
// signals. They goes from low to high, and then stays high
// for many clocks. Swapping is thus easy--two flip flops to
// protect against meta-stability and we're done.
//
(* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags;
reg [2:0] r_oflags;
initial q_oflags = 3'h0;
initial r_oflags = 3'h0;
always @(posedge i_wb_clk)
if (bw_reset_request)
begin
q_oflags <= 3'h0;
r_oflags <= 3'h0;
end else begin
q_oflags <= { dw_final_stop, dr_triggered, dr_primed };
r_oflags <= q_oflags;
end
 
assign bw_stopped = r_oflags[2];
assign bw_triggered = r_oflags[1];
assign bw_primed = r_oflags[0];
end endgenerate
 
 
//
// Call the regular wishbone scope to do all of our real work, now
// that we've compressed the input.
// Reads use the bus clock
//
wbscope #(.SYNCHRONOUS(1), .LGMEM(LGMEM),
.BUSW(BUSW)) cheatersscope(i_clk, r_ce, w_trigger, r_data,
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data, o_interrupt);
reg br_wb_ack, br_pre_wb_ack;
initial br_wb_ack = 1'b0;
wire bw_cyc_stb;
assign bw_cyc_stb = (i_wb_stb);
initial br_pre_wb_ack = 1'b0;
initial br_wb_ack = 1'b0;
always @(posedge i_wb_clk)
begin
if ((bw_reset_request)
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
raddr <= 0;
else if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)&&(bw_stopped))
raddr <= raddr + 1'b1; // Data read, when stopped
 
br_pre_wb_ack <= bw_cyc_stb;
br_wb_ack <= (br_pre_wb_ack)&&(i_wb_cyc);
end
 
 
 
reg [(LGMEM-1):0] this_addr;
always @(posedge i_wb_clk)
if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we))
this_addr <= raddr + waddr + 1'b1;
else
this_addr <= raddr + waddr;
 
reg [31:0] nxt_mem;
always @(posedge i_wb_clk)
nxt_mem <= mem[this_addr];
 
wire [19:0] full_holdoff;
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
generate if (HOLDOFFBITS < 20)
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
endgenerate
 
wire [4:0] bw_lgmem;
assign bw_lgmem = LGMEM;
always @(posedge i_wb_clk)
if (!i_wb_addr) // Control register read
o_wb_data <= { bw_reset_request,
bw_stopped,
bw_triggered,
bw_primed,
bw_manual_trigger,
bw_disable_trigger,
(raddr == {(LGMEM){1'b0}}),
bw_lgmem,
full_holdoff };
else if (!bw_stopped) // read, prior to stopping
o_wb_data <= {1'b0, w_data };// Violates clk tfr rules
else // if (i_wb_addr) // Read from FIFO memory
o_wb_data <= nxt_mem; // mem[raddr+waddr];
 
assign o_wb_stall = 1'b0;
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
 
reg br_level_interrupt;
initial br_level_interrupt = 1'b0;
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
&&(!br_level_interrupt);
always @(posedge i_wb_clk)
if ((bw_reset_complete)||(bw_reset_request))
br_level_interrupt<= 1'b0;
else
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
 
// Make Verilator happy
// verilator lint_off UNUSED
wire [3+5+(20-HOLDOFFBITS)-1:0] unused;
assign unused = { i_wb_data[30:28], i_wb_data[25:HOLDOFFBITS] };
// verilator lint_on UNUSED
 
endmodule
/wbscope.v
27,7 → 27,7
// 5. The scope recording is then paused until the next reset.
// 6. While stopped, the CPU can read the data from the scope
// 7. -- oldest to most recent
// 8. -- one value per i_rd&i_clk
// 8. -- one value per i_rd&i_data_clk
// 9. Writes to the data register reset the address to the
// beginning of the buffer
//
83,7 → 83,9
////////////////////////////////////////////////////////////////////////////////
//
//
module wbscope(i_clk, i_ce, i_trigger, i_data,
`default_nettype none
//
module wbscope(i_data_clk, i_ce, i_trigger, i_data,
i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
o_wb_ack, o_wb_stall, o_wb_data,
o_interrupt);
93,19 → 95,45
parameter HOLDOFFBITS = 20;
parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4);
// The input signals that we wish to record
input i_clk, i_ce, i_trigger;
input [(BUSW-1):0] i_data;
input wire i_data_clk, i_ce, i_trigger;
input wire [(BUSW-1):0] i_data;
// The WISHBONE bus for reading and configuring this scope
input i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
input i_wb_addr; // One address line only
input [(BUSW-1):0] i_wb_data;
input wire i_wb_clk, i_wb_cyc, i_wb_stb, i_wb_we;
input wire i_wb_addr; // One address line only
input wire [(BUSW-1):0] i_wb_data;
output wire o_wb_ack, o_wb_stall;
output reg [(BUSW-1):0] o_wb_data;
output wire [(BUSW-1):0] o_wb_data;
// And, finally, for a final flair --- offer to interrupt the CPU after
// our trigger has gone off. This line is equivalent to the scope
// being stopped. It is not maskable here.
output wire o_interrupt;
 
wire bus_clock;
assign bus_clock = i_wb_clk;
 
///////////////////////////////////////////////////
//
// Decode and handle the WB bus signaling in a
// (somewhat) portable manner
//
///////////////////////////////////////////////////
//
//
assign o_wb_stall = 1'b0;
 
wire read_from_data;
assign read_from_data = (i_wb_stb)&&(!i_wb_we)&&(i_wb_addr);
 
wire write_stb;
assign write_stb = (i_wb_stb)&&(i_wb_we);
 
wire write_to_control;
assign write_to_control = (write_stb)&&(!i_wb_addr);
 
reg read_address;
always @(posedge bus_clock)
read_address <= i_wb_addr;
 
reg [(LGMEM-1):0] raddr;
reg [(BUSW-1):0] mem[0:((1<<LGMEM)-1)];
 
116,16 → 144,13
reg [(HOLDOFFBITS-1):0] br_holdoff;
initial br_config = 3'b0;
initial br_holdoff = DEFAULT_HOLDOFF;
always @(posedge i_wb_clk)
if ((i_wb_stb)&&(!i_wb_addr))
always @(posedge bus_clock)
if (write_to_control)
begin
if (i_wb_we)
begin
br_config <= { i_wb_data[31],
i_wb_data[27],
i_wb_data[26] };
br_holdoff = i_wb_data[(HOLDOFFBITS-1):0];
end
br_config <= { i_wb_data[31],
i_wb_data[27],
i_wb_data[26] };
br_holdoff <= i_wb_data[(HOLDOFFBITS-1):0];
end else if (bw_reset_complete)
br_config[2] <= 1'b1;
assign bw_reset_request = (!br_config[2]);
149,7 → 174,7
// so do a clock transfer here
initial q_iflags = 3'b000;
initial r_reset_complete = 1'b0;
always @(posedge i_clk)
always @(posedge i_data_clk)
begin
q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger };
r_iflags <= q_iflags;
166,7 → 191,7
// clock that the reset has been accomplished
initial q_reset_complete = 1'b0;
initial qq_reset_complete = 1'b0;
always @(posedge i_wb_clk)
always @(posedge bus_clock)
begin
q_reset_complete <= r_reset_complete;
qq_reset_complete <= q_reset_complete;
180,7 → 205,7
//
//
// Write with the i-clk, or input clock. All outputs read with the
// WISHBONE-clk, or i_wb_clk clock.
// bus clock, or bus_clock as we've called it here.
reg dr_triggered, dr_primed;
wire dw_trigger;
assign dw_trigger = (dr_primed)&&(
187,7 → 212,7
((i_trigger)&&(!dw_disable_trigger))
||(dw_manual_trigger));
initial dr_triggered = 1'b0;
always @(posedge i_clk)
always @(posedge i_data_clk)
if (dw_reset)
dr_triggered <= 1'b0;
else if ((i_ce)&&(dw_trigger))
203,20 → 228,20
reg dr_stopped;
initial dr_stopped = 1'b0;
initial counter = 0;
always @(posedge i_clk)
always @(posedge i_data_clk)
if (dw_reset)
counter <= 0;
else if ((i_ce)&&(dr_triggered)&&(!dr_stopped))
begin // MUST BE a < and not <=, so that we can keep this w/in
// 20 bits. Else we'd need to add a bit to comparison
// here.
begin
counter <= counter + 1'b1;
end
always @(posedge i_clk)
always @(posedge i_data_clk)
if ((!dr_triggered)||(dw_reset))
dr_stopped <= 1'b0;
else
else if (HOLDOFFBITS > 1) // if (i_ce)
dr_stopped <= (counter >= br_holdoff);
else if (HOLDOFFBITS <= 1)
dr_stopped <= ((i_ce)&&(dw_trigger));
 
//
// Actually do our writes to memory. Record, via 'primed' when
231,7 → 256,7
reg [(LGMEM-1):0] waddr;
initial waddr = {(LGMEM){1'b0}};
initial dr_primed = 1'b0;
always @(posedge i_clk)
always @(posedge i_data_clk)
if (dw_reset) // For simulation purposes, supply a valid value
begin
waddr <= 0; // upon reset.
240,11 → 265,48
begin
// mem[waddr] <= i_data;
waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1};
dr_primed <= (dr_primed)||(&waddr);
if (!dr_primed)
begin
//if (br_holdoff[(HOLDOFFBITS-1):LGMEM]==0)
// dr_primed <= (waddr >= br_holdoff[(LGMEM-1):0]);
// else
dr_primed <= (&waddr);
end
end
always @(posedge i_clk)
 
// Delay the incoming data so that we can get our trigger
// logic to line up with the data. The goal is to have a
// hold off of zero place the trigger in the last memory
// address.
localparam STOPDELAY = 1;
wire [(BUSW-1):0] wr_piped_data;
generate
if (STOPDELAY == 0)
// No delay ... just assign the wires to our input lines
assign wr_piped_data = i_data;
else if (STOPDELAY == 1)
begin
//
// Delay by one means just register this once
reg [(BUSW-1):0] data_pipe;
always @(posedge i_data_clk)
if (i_ce)
data_pipe <= i_data;
assign wr_piped_data = data_pipe;
end else begin
// Arbitrary delay ... use a longer pipe
reg [(STOPDELAY*BUSW-1):0] data_pipe;
 
always @(posedge i_data_clk)
if (i_ce)
data_pipe <= { data_pipe[((STOPDELAY-1)*BUSW-1):0], i_data };
assign wr_piped_data = { data_pipe[(STOPDELAY*BUSW-1):((STOPDELAY-1)*BUSW)] };
end endgenerate
 
always @(posedge i_data_clk)
if ((i_ce)&&(!dr_stopped))
mem[waddr] <= i_data;
mem[waddr] <= wr_piped_data;
 
//
// Clock transfer of the status signals
266,7 → 328,7
reg [2:0] r_oflags;
initial q_oflags = 3'h0;
initial r_oflags = 3'h0;
always @(posedge i_wb_clk)
always @(posedge bus_clock)
if (bw_reset_request)
begin
q_oflags <= 3'h0;
282,33 → 344,34
end endgenerate
 
// Reads use the bus clock
reg br_wb_ack;
reg br_wb_ack, br_pre_wb_ack;
initial br_wb_ack = 1'b0;
wire bw_cyc_stb;
assign bw_cyc_stb = (i_wb_stb);
always @(posedge i_wb_clk)
initial br_pre_wb_ack = 1'b0;
initial br_wb_ack = 1'b0;
always @(posedge bus_clock)
begin
if ((bw_reset_request)
||((bw_cyc_stb)&&(i_wb_addr)&&(i_wb_we)))
if ((bw_reset_request)||(write_to_control))
raddr <= 0;
else if ((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)&&(bw_stopped))
else if ((read_from_data)&&(bw_stopped))
raddr <= raddr + 1'b1; // Data read, when stopped
 
if ((bw_cyc_stb)&&(!i_wb_we))
begin // Read from the bus
br_wb_ack <= 1'b1;
end else if ((bw_cyc_stb)&&(i_wb_we))
// We did this write above
br_wb_ack <= 1'b1;
else // Do nothing if either i_wb_cyc or i_wb_stb are low
br_wb_ack <= 1'b0;
br_pre_wb_ack <= bw_cyc_stb;
br_wb_ack <= (br_pre_wb_ack)&&(i_wb_cyc);
end
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
 
reg [(LGMEM-1):0] this_addr;
always @(posedge bus_clock)
if (read_from_data)
this_addr <= raddr + waddr + 1'b1;
else
this_addr <= raddr + waddr;
 
reg [31:0] nxt_mem;
always @(posedge i_wb_clk)
nxt_mem <= mem[raddr+waddr+
(((bw_cyc_stb)&&(i_wb_addr)&&(!i_wb_we)) ?
{{(LGMEM-1){1'b0}},1'b1} : { (LGMEM){1'b0}} )];
always @(posedge bus_clock)
nxt_mem <= mem[this_addr];
 
wire [19:0] full_holdoff;
assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff;
316,11 → 379,12
assign full_holdoff[19:(HOLDOFFBITS)] = 0;
endgenerate
 
reg [31:0] o_bus_data;
wire [4:0] bw_lgmem;
assign bw_lgmem = LGMEM;
always @(posedge i_wb_clk)
if (!i_wb_addr) // Control register read
o_wb_data <= { bw_reset_request,
always @(posedge bus_clock)
if (!read_address) // Control register read
o_bus_data <= { bw_reset_request,
bw_stopped,
bw_triggered,
bw_primed,
330,21 → 394,25
bw_lgmem,
full_holdoff };
else if (!bw_stopped) // read, prior to stopping
o_wb_data <= i_data;
o_bus_data <= i_data;
else // if (i_wb_addr) // Read from FIFO memory
o_wb_data <= nxt_mem; // mem[raddr+waddr];
o_bus_data <= nxt_mem; // mem[raddr+waddr];
 
assign o_wb_stall = 1'b0;
assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack);
assign o_wb_data = o_bus_data;
 
reg br_level_interrupt;
initial br_level_interrupt = 1'b0;
assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger)
&&(!br_level_interrupt);
always @(posedge i_wb_clk)
always @(posedge bus_clock)
if ((bw_reset_complete)||(bw_reset_request))
br_level_interrupt<= 1'b0;
else
br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger);
 
// verilator lint_off UNUSED
// Make verilator happy
wire [28:0] unused;
assign unused = { i_wb_data[30:28], i_wb_data[25:0] };
// verilator lint_on UNUSED
endmodule

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