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/trunk/bench/testcase_1.v
0,0 → 1,77
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "wiegand_defines.v"
`include "testbench_top.v"
 
module testcase_1;
testbench_top testbench();
initial
begin
testbench.wb_rst;
//#40 testbench.wb_write_async(32'h0);
//#40 testbench.wb_write_sync(32'h0);
//#40 testbench.wb_read_async;
//#40 testbench.wb_read_sync;
#40 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesize_async(32'h86);
#40 testbench.wb_writesend_async(32'hFF);
$stop;
end
endmodule
/trunk/bench/testbench_top.v.bak
0,0 → 1,254
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "wiegand_defines.v"
 
module testbench_top;
reg [5:0] wb_addr_i;
reg [31:0] wb_dat_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
reg wb_rst_i;
reg wb_clk_i;
//DUTs
//wiegand_tx_top wiegand_tx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,
// wb_ack_o,wb_err_o,wb_rty_o);
//wiegand_rx_top wiegand_rx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,
// wb_ack_o,wb_err_o,wb_rty_o);
//tasks for simulation
initial begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
wb_rst_i = 1'b0;
wb_clk_i = 1'b0;
end
always
#5 wb_clk_i = !wb_clk_i;
task wb_rst;
begin
wb_rst_i = 1'b1;
#20 wb_rst_i = 1'b0;
end
endtask
task wb_write_async;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WIEGAND_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_write_sync;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WIEGAND_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = `WIEGAND_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writep2p_async;
input [31:0] p2p;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_P2P;
wb_dat_i = p2p;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writepw_async;
input [31:0] pw;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_PW;
wb_dat_i = pw;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writesize_async;
input [31:0] size;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_MSGSIZE;
wb_dat_i = (size & 32'h7F);
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writesend_async;
input [31:0] size;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_MSGSIZE;
wb_dat_i = (size | 32'h80);
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_read_async;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
task wb_read_sync;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
endmodule
/trunk/bench/fifoTestBench.v.bak
0,0 → 1,91
//////////////////////////////////////////////////////////////////////
//// ////
//// fifoTestBench.v ////
//// ////
//// ////
//// This file is part of the ONFI controller ////
//// http://opencores.org/project,onfi ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Author(s) ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History at EOF
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
 
module fifoTestBench();
reg clk_rd,clk_wr,rst,wr_en,rd_en;
reg[7:0] d_i;
wire[7:0] d_o;
wire full, empty;
fifo fifo(clk_rd,clk_wr,d_i[7:0],d_o[7:0],rst,wr_en,rd_en,full,empty);
initial begin
clk_rd = 0;
clk_wr = 0;
rst = 1;
d_i = 8'h1;
wr_en = 0;
rd_en = 0;
end
always
#5 clk_wr = !clk_wr;
always
#15 clk_rd = !clk_rd;
initial begin
#20 rst = 0;
#10 wr_en = 1;
#150 wr_en = 0;
#10 rd_en = 1;
end
endmodule
 
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: $
//
/trunk/bench/wb_bus_fn_mdl.v --- trunk/bench/tasks.v.bak (nonexistent) +++ trunk/bench/tasks.v.bak (revision 2) @@ -0,0 +1,59 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// weigand_tx_top.v //// +//// //// +//// //// +//// This file is part of the Time Triggered Protocol Controller //// +//// http://www.opencores.org/projects/weigand/ //// +//// //// +//// //// +//// Author(s): //// +//// Jeff Anderson //// +//// jeaander@opencores.org //// +//// //// +//// //// +//// All additional information is available in the README.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2013 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +//// The Weigand protocol is maintained by //// +//// This product has been tested to interoperate with certified //// +//// devices, but has not been certified itself. This product //// +//// should be certified through prior to claiming strict //// +//// adherence to the standard. //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Revisions at end of file +// + +`include "timescale.v" + +module testcase_1; + testbench_top testbench(); + +endmodule \ No newline at end of file
/trunk/bench/testbench_top.v
0,0 → 1,254
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "wiegand_defines.v"
 
module testbench_top;
reg [5:0] wb_addr_i;
reg [31:0] wb_dat_i;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
reg wb_rst_i;
reg wb_clk_i;
//DUTs
wiegand_tx_top wiegand_tx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,
wb_ack_o,wb_err_o,wb_rty_o);
//wiegand_rx_top wiegand_rx_top(one_o,zero_o,wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_we_i,wb_adr_i,
// wb_ack_o,wb_err_o,wb_rty_o);
//tasks for simulation
initial begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
wb_rst_i = 1'b0;
wb_clk_i = 1'b0;
end
always
#5 wb_clk_i = !wb_clk_i;
task wb_rst;
begin
wb_rst_i = 1'b1;
#20 wb_rst_i = 1'b0;
end
endtask
task wb_write_async;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WIEGAND_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_write_sync;
input [31:0] wb_data;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WIEGAND_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = `WIEGAND_ADDR;
wb_dat_i = wb_data;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writep2p_async;
input [31:0] p2p;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_P2P;
wb_dat_i = p2p;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writepw_async;
input [31:0] pw;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_PW;
wb_dat_i = pw;
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writesize_async;
input [31:0] size;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_MSGSIZE;
wb_dat_i = (size & 32'h7F);
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_writesend_async;
input [31:0] size;
begin
@ (posedge wb_clk_i) begin
wb_addr_i = `WB_CNFG_MSGSIZE;
wb_dat_i = (size | 32'h80);
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_addr_i = 6'h0;
wb_dat_i = 32'h0;
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
wb_we_i = 1'b0;
end
end
endtask
task wb_read_async;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
task wb_read_sync;
begin
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
wb_we_i = 1'b0;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b1;
wb_cyc_i = 1'b1;
end
@ (posedge wb_clk_i) begin
wb_stb_i = 1'b0;
wb_cyc_i = 1'b0;
end
end
endtask
endmodule
/trunk/bench/timescale.v.bak
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/12/27 00:12:48 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
`timescale 1ns/10ps
/trunk/bench/fifoTestBench.v
0,0 → 1,90
//////////////////////////////////////////////////////////////////////
//// ////
//// fifoTestBench.v ////
//// ////
//// ////
//// This file is part of the ONFI controller ////
//// http://opencores.org/project,onfi ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Author(s) ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History at EOF
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
 
module fifoTestBench();
reg clk_rd,clk_wr,rst,wr_en,rd_en;
reg[7:0] d_i;
wire[7:0] d_o;
wire full, empty;
fifo fifo(clk_rd,clk_wr,d_i[7:0],d_o[7:0],rst,wr_en,rd_en,full,empty);
initial begin
clk_rd = 0;
clk_wr = 0;
rst = 1;
d_i = 8'h1;
wr_en = 0;
rd_en = 0;
end
always
#5 clk_wr = !clk_wr;
always
#15 clk_rd = !clk_rd;
initial begin
#20 rst = 0;
#10 wr_en = 1;
#150 wr_en = 0;
#10 rd_en = 1;
end
endmodule
 
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: $
//
/trunk/bench/tasks.v
0,0 → 1,60
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
 
module testcase_1;
testbench_top testbench();
endmodule
/trunk/bench/timescale.v
0,0 → 1,63
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// igorm@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/12/27 00:12:48 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
`timescale 1ns/1ps
/trunk/bench/testcase_1.v.bak
0,0 → 1,77
//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
 
`include "timescale.v"
`include "wiegand_defines.v"
`include "testbench_top.v"
 
module testcase_1;
testbench_top testbench();
initial
begin
testbench.wb_rst;
//#40 testbench.wb_write_async(32'h0);
//#40 testbench.wb_write_sync(32'h0);
//#40 testbench.wb_read_async;
//#40 testbench.wb_read_sync;
#40 testbench.wb_write_async(32'hA5A5A50F);
#40 testbench.wb_writep2p_async(32'h7);
#40 testbench.wb_writepw_async(32'h3);
#40 testbench.wb_writesize_async(32'hFF);
#40 testbench.wb_writesend_async(32'hFF);
$stop;
end
endmodule

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