OpenCores
URL https://opencores.org/ocsvn/xenie/xenie/trunk

Subversion Repositories xenie

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    /xenie
    from Rev 5 to Rev 6
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Rev 5 → Rev 6

/trunk/examples/Eth_example/doc/Xenie_ethernet_example.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/examples/Eth_example/src/tcl/build_all_xc7k160t.bat
0,0 → 1,6
 
 
REM Recreate Vivado project for example design
vivado -mode batch -source build_all_xc7k160t.tcl
 
 
/trunk/examples/Eth_example/src/tcl/build_all_xc7k160t.tcl
0,0 → 1,28
 
#
# This script run all necessary scripts to get final MCSs to be loaded to
# Xenie 1.0.
#
#
 
# Recreate Vivado project for example design
source recreate_project_xc7k160t.tcl
 
# Run synthesis, implementation, generate bitstream and HW description for SDK
source build_project.tcl
 
# Recreate SDK workspace, create HW platform project, rebuild SW
exec xsdk -batch -source xsdk_prepare_workspace.tcl
 
# Create MCS with Marvell FW
source ../../outputs/create_mcs_marvell_only.tcl
 
# Gather all generated files needed to create MCS with Microblaze
source ../../outputs/update_src_data.tcl
 
# Create MCS with Microblaze with test application loaded to BRAM
source ../../outputs/create_mcs_microblaze.tcl
 
#
# All needed to program flash is available. When ready run program_xenie.bat
#
/trunk/examples/Eth_example/src/tcl/program_xenie.tcl
28,7 → 28,7
open_hw_target
 
 
current_hw_device [lindex [get_hw_devices xc7k70t_0] 0]
current_hw_device [lindex [get_hw_devices -regexp xc7k.*] 0]
refresh_hw_device -update_hw_probes false [current_hw_device]
 
 
/trunk/examples/Eth_example/src/tcl/recreate_bd_xc7k160t.tcl
0,0 → 1,814
 
################################################################
# This is a generated script based on design: main_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################
 
namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]
 
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2016.4
set current_vivado_version [version -short]
 
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
 
return 1
}
 
################################################################
# START
################################################################
 
# To test this script, run the following commands from Vivado Tcl console:
# source main_bd_script.tcl
 
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.
 
set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7k160tffg676-1
}
 
 
# CHANGE DESIGN NAME HERE
set design_name main_bd
 
# This script was generated for a remote BD. To create a non-remote design,
# change the variable <run_remote_bd_flow> to <0>.
 
set run_remote_bd_flow 1
if { $run_remote_bd_flow == 1 } {
# Set the reference directory for source file relative paths (by default
# the value is script directory path)
set origin_dir ./bd
 
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
 
set str_bd_folder [file normalize ${origin_dir}]
set str_bd_filepath ${str_bd_folder}/${design_name}/${design_name}.bd
 
# Check if remote design exists on disk
if { [file exists $str_bd_filepath ] == 1 } {
catch {common::send_msg_id "BD_TCL-110" "ERROR" "The remote BD file path <$str_bd_filepath> already exists!"}
common::send_msg_id "BD_TCL-008" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0>."
common::send_msg_id "BD_TCL-009" "INFO" "Also make sure there is no design <$design_name> existing in your current project."
 
return 1
}
 
# Check if design exists in memory
set list_existing_designs [get_bd_designs -quiet $design_name]
if { $list_existing_designs ne "" } {
catch {common::send_msg_id "BD_TCL-111" "ERROR" "The design <$design_name> already exists in this project! Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
 
common::send_msg_id "BD_TCL-010" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
 
return 1
}
 
# Check if design exists on disk within project
set list_existing_designs [get_files */${design_name}.bd]
if { $list_existing_designs ne "" } {
catch {common::send_msg_id "BD_TCL-112" "ERROR" "The design <$design_name> already exists in this project at location:
$list_existing_designs"}
catch {common::send_msg_id "BD_TCL-113" "ERROR" "Will not create the remote BD <$design_name> at the folder <$str_bd_folder>."}
 
common::send_msg_id "BD_TCL-011" "INFO" "To create a non-remote BD, change the variable <run_remote_bd_flow> to <0> or please set a different value to variable <design_name>."
 
return 1
}
 
# Now can create the remote BD
# NOTE - usage of <-dir> will create <$str_bd_folder/$design_name/$design_name.bd>
create_bd_design -dir $str_bd_folder $design_name
} else {
 
# Create regular design
if { [catch {create_bd_design $design_name} errmsg] } {
common::send_msg_id "BD_TCL-012" "INFO" "Please set a different value to variable <design_name>."
 
return 1
}
}
 
current_bd_design $design_name
 
 
##################################################################
# MIG PRJ FILE TCL PROCs
##################################################################
 
proc write_mig_file_main_bd_mig_7series_0_0 { str_mig_prj_filepath } {
 
set mig_prj_file [open $str_mig_prj_filepath w+]
 
puts $mig_prj_file {<?xml version='1.0' encoding='UTF-8'?>}
puts $mig_prj_file {<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->}
puts $mig_prj_file {<Project NoOfControllers="1" >}
puts $mig_prj_file { <ModuleName>main_bd_mig_7series_0_0</ModuleName>}
puts $mig_prj_file { <dci_inouts_inputs>1</dci_inouts_inputs>}
puts $mig_prj_file { <dci_inputs>1</dci_inputs>}
puts $mig_prj_file { <Debug_En>OFF</Debug_En>}
puts $mig_prj_file { <DataDepth_En>1024</DataDepth_En>}
puts $mig_prj_file { <LowPower_En>ON</LowPower_En>}
puts $mig_prj_file { <XADC_En>Enabled</XADC_En>}
puts $mig_prj_file { <TargetFPGA>xc7k160t-ffg676/-1</TargetFPGA>}
puts $mig_prj_file { <Version>4.0</Version>}
puts $mig_prj_file { <SystemClock>No Buffer</SystemClock>}
puts $mig_prj_file { <ReferenceClock>Use System Clock</ReferenceClock>}
puts $mig_prj_file { <SysResetPolarity>ACTIVE LOW</SysResetPolarity>}
puts $mig_prj_file { <BankSelectionFlag>FALSE</BankSelectionFlag>}
puts $mig_prj_file { <InternalVref>0</InternalVref>}
puts $mig_prj_file { <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>}
puts $mig_prj_file { <dci_cascade>0</dci_cascade>}
puts $mig_prj_file { <Controller number="0" >}
puts $mig_prj_file { <MemoryDevice>DDR3_SDRAM/Components/MT41K256M16XX-125</MemoryDevice>}
puts $mig_prj_file { <TimePeriod>3077</TimePeriod>}
puts $mig_prj_file { <VccAuxIO>1.8V</VccAuxIO>}
puts $mig_prj_file { <PHYRatio>4:1</PHYRatio>}
puts $mig_prj_file { <InputClkFreq>199.995</InputClkFreq>}
puts $mig_prj_file { <UIExtraClocks>1</UIExtraClocks>}
puts $mig_prj_file { <MMCM_VCO>649</MMCM_VCO>}
puts $mig_prj_file { <MMCMClkOut0> 1.000</MMCMClkOut0>}
puts $mig_prj_file { <MMCMClkOut1>1</MMCMClkOut1>}
puts $mig_prj_file { <MMCMClkOut2>1</MMCMClkOut2>}
puts $mig_prj_file { <MMCMClkOut3>1</MMCMClkOut3>}
puts $mig_prj_file { <MMCMClkOut4>1</MMCMClkOut4>}
puts $mig_prj_file { <DataWidth>32</DataWidth>}
puts $mig_prj_file { <DeepMemory>1</DeepMemory>}
puts $mig_prj_file { <DataMask>1</DataMask>}
puts $mig_prj_file { <ECC>Disabled</ECC>}
puts $mig_prj_file { <Ordering>Normal</Ordering>}
puts $mig_prj_file { <BankMachineCnt>4</BankMachineCnt>}
puts $mig_prj_file { <CustomPart>FALSE</CustomPart>}
puts $mig_prj_file { <NewPartName></NewPartName>}
puts $mig_prj_file { <RowAddress>15</RowAddress>}
puts $mig_prj_file { <ColAddress>10</ColAddress>}
puts $mig_prj_file { <BankAddress>3</BankAddress>}
puts $mig_prj_file { <MemoryVoltage>1.35V</MemoryVoltage>}
puts $mig_prj_file { <C0_MEM_SIZE>1073741824</C0_MEM_SIZE>}
puts $mig_prj_file { <UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>}
puts $mig_prj_file { <PinSelection>}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF10" SLEW="" name="ddr3_addr[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD13" SLEW="" name="ddr3_addr[11]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE11" SLEW="" name="ddr3_addr[12]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF13" SLEW="" name="ddr3_addr[13]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC12" SLEW="" name="ddr3_addr[14]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA9" SLEW="" name="ddr3_addr[1]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE12" SLEW="" name="ddr3_addr[4]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF12" SLEW="" name="ddr3_addr[6]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE13" SLEW="" name="ddr3_addr[7]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC13" SLEW="" name="ddr3_addr[8]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AB9" SLEW="" name="ddr3_ba[1]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD10" SLEW="" name="ddr3_ba[2]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD8" SLEW="" name="ddr3_cas_n" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135" PADName="AF7" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135" PADName="AE7" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AB7" SLEW="" name="ddr3_cke[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD9" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AD5" SLEW="" name="ddr3_dm[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="V3" SLEW="" name="ddr3_dm[2]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="Y2" SLEW="" name="ddr3_dm[3]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AB4" SLEW="" name="ddr3_dq[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[10]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AD1" SLEW="" name="ddr3_dq[11]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[12]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AD4" SLEW="" name="ddr3_dq[13]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[14]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[15]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U1" SLEW="" name="ddr3_dq[16]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V4" SLEW="" name="ddr3_dq[17]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U7" SLEW="" name="ddr3_dq[18]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="W3" SLEW="" name="ddr3_dq[19]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[1]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U5" SLEW="" name="ddr3_dq[20]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V6" SLEW="" name="ddr3_dq[21]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U2" SLEW="" name="ddr3_dq[22]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="U6" SLEW="" name="ddr3_dq[23]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AA3" SLEW="" name="ddr3_dq[24]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y1" SLEW="" name="ddr3_dq[25]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y3" SLEW="" name="ddr3_dq[26]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V2" SLEW="" name="ddr3_dq[27]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AB2" SLEW="" name="ddr3_dq[28]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="V1" SLEW="" name="ddr3_dq[29]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y5" SLEW="" name="ddr3_dq[2]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[30]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="W1" SLEW="" name="ddr3_dq[31]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AA4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="Y6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AC3" SLEW="" name="ddr3_dq[7]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AF3" SLEW="" name="ddr3_dq[8]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135_T_DCI" PADName="AE2" SLEW="" name="ddr3_dq[9]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AB5" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AF4" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="W5" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AC1" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AA5" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AF5" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="W6" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="DIFF_SSTL135_T_DCI" PADName="AB1" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AE8" SLEW="" name="ddr3_odt[0]" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AC7" SLEW="" name="ddr3_ras_n" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AA2" SLEW="" name="ddr3_reset_n" IN_TERM="" />}
puts $mig_prj_file { <Pin VCCAUX_IO="NORMAL" IOSTANDARD="SSTL135" PADName="AF8" SLEW="" name="ddr3_we_n" IN_TERM="" />}
puts $mig_prj_file { </PinSelection>}
puts $mig_prj_file { <System_Control>}
puts $mig_prj_file { <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />}
puts $mig_prj_file { <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />}
puts $mig_prj_file { <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />}
puts $mig_prj_file { </System_Control>}
puts $mig_prj_file { <TimingParameters>}
puts $mig_prj_file { <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="260" trp="13.75" tras="35" trcd="13.75" />}
puts $mig_prj_file { </TimingParameters>}
puts $mig_prj_file { <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>}
puts $mig_prj_file { <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>}
puts $mig_prj_file { <mrCasLatency name="CAS Latency" >5</mrCasLatency>}
puts $mig_prj_file { <mrMode name="Mode" >Normal</mrMode>}
puts $mig_prj_file { <mrDllReset name="DLL Reset" >No</mrDllReset>}
puts $mig_prj_file { <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>}
puts $mig_prj_file { <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>}
puts $mig_prj_file { <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>}
puts $mig_prj_file { <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>}
puts $mig_prj_file { <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>}
puts $mig_prj_file { <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>}
puts $mig_prj_file { <emrPosted name="Additive Latency (AL)" >0</emrPosted>}
puts $mig_prj_file { <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>}
puts $mig_prj_file { <emrDQS name="TDQS enable" >Enabled</emrDQS>}
puts $mig_prj_file { <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>}
puts $mig_prj_file { <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>}
puts $mig_prj_file { <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>}
puts $mig_prj_file { <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>}
puts $mig_prj_file { <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>}
puts $mig_prj_file { <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>}
puts $mig_prj_file { <PortInterface>AXI</PortInterface>}
puts $mig_prj_file { <AXIParameters>}
puts $mig_prj_file { <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>}
puts $mig_prj_file { <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>}
puts $mig_prj_file { <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>}
puts $mig_prj_file { <C0_S_AXI_ID_WIDTH>2</C0_S_AXI_ID_WIDTH>}
puts $mig_prj_file { <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>}
puts $mig_prj_file { </AXIParameters>}
puts $mig_prj_file { </Controller>}
puts $mig_prj_file {</Project>}
 
close $mig_prj_file
}
# End of write_mig_file_main_bd_mig_7series_0_0()
 
 
 
##################################################################
# DESIGN PROCs
##################################################################
 
 
# Hierarchical cell: microblaze_0_local_memory
proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {
 
variable script_folder
 
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_msg_id "BD_TCL-102" "ERROR" create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"}
return
}
 
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
 
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
 
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
 
# Set parent object as current
current_bd_instance $parentObj
 
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
 
# Create interface pins
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB
create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:lmb_rtl:1.0 SLMB1
 
# Create pins
create_bd_pin -dir I -type clk LMB_Clk
create_bd_pin -dir I -type rst SYS_Rst
 
# Create instance: dlmb_bram_if_cntlr, and set properties
set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ]
set_property -dict [ list \
CONFIG.C_ECC {0} \
CONFIG.C_NUM_LMB {2} \
] $dlmb_bram_if_cntlr
 
# Create instance: dlmb_v10, and set properties
set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ]
set_property -dict [ list \
CONFIG.C_LMB_NUM_SLAVES {1} \
] $dlmb_v10
 
# Create instance: ilmb_bram_if_cntlr, and set properties
set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ]
set_property -dict [ list \
CONFIG.C_ECC {0} \
] $ilmb_bram_if_cntlr
 
# Create instance: ilmb_v10, and set properties
set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ]
 
# Create instance: lmb_bram, and set properties
set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.3 lmb_bram ]
set_property -dict [ list \
CONFIG.Memory_Type {True_Dual_Port_RAM} \
CONFIG.use_bram_block {BRAM_Controller} \
] $lmb_bram
 
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins SLMB1] [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB1]
connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M]
connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0]
connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA]
connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M]
connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0]
connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB]
 
# Create port connections
connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk]
connect_bd_net -net microblaze_0_LMB_Rst [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst]
 
# Restore current instance
current_bd_instance $oldCurInst
}
 
 
# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {
 
variable script_folder
 
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
 
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
 
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
 
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
 
# Set parent object as current
current_bd_instance $parentObj
 
 
# Create interface ports
set DDR3 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3 ]
set IIC_RTL [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_RTL ]
set MB_MDIO [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_rtl:1.0 MB_MDIO ]
set MB_UART [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 MB_UART ]
set SPI_RTL [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 SPI_RTL ]
 
# Create ports
set AXI_CLK [ create_bd_port -dir O -type clk AXI_CLK ]
set GPIO2_IO_I [ create_bd_port -dir I -from 31 -to 0 GPIO2_IO_I ]
set GPIO2_IO_O [ create_bd_port -dir O -from 31 -to 0 GPIO2_IO_O ]
set GPIO2_IO_T [ create_bd_port -dir O -from 31 -to 0 GPIO2_IO_T ]
set GPIO_IO_I [ create_bd_port -dir I -from 31 -to 0 GPIO_IO_I ]
set GPIO_IO_O [ create_bd_port -dir O -from 31 -to 0 GPIO_IO_O ]
set GPIO_IO_T [ create_bd_port -dir O -from 31 -to 0 GPIO_IO_T ]
set HOST_IP [ create_bd_port -dir O -from 31 -to 0 HOST_IP ]
set HOST_IP_NETMASK [ create_bd_port -dir O -from 31 -to 0 HOST_IP_NETMASK ]
set HOST_MAC0 [ create_bd_port -dir O -from 31 -to 0 HOST_MAC0 ]
set HOST_MAC1 [ create_bd_port -dir O -from 31 -to 0 HOST_MAC1 ]
set SYS_CLK_I [ create_bd_port -dir I -type clk SYS_CLK_I ]
set_property -dict [ list \
CONFIG.CLK_DOMAIN {main_bd_util_ds_buf_0_0_IBUF_OUT} \
CONFIG.FREQ_HZ {200000000} \
] $SYS_CLK_I
set VERSION_GPIO [ create_bd_port -dir I -from 63 -to 0 VERSION_GPIO ]
 
# Create instance: Const_no_ext_rst, and set properties
set Const_no_ext_rst [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 Const_no_ext_rst ]
 
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
set_property -dict [ list \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_0
 
# Create instance: axi_gpio_1_version, and set properties
set axi_gpio_1_version [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1_version ]
set_property -dict [ list \
CONFIG.C_ALL_INPUTS {1} \
CONFIG.C_ALL_INPUTS_2 {1} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_1_version
 
# Create instance: axi_gpio_2_netInfo, and set properties
set axi_gpio_2_netInfo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_2_netInfo ]
set_property -dict [ list \
CONFIG.C_ALL_INPUTS {0} \
CONFIG.C_ALL_INPUTS_2 {0} \
CONFIG.C_ALL_OUTPUTS {0} \
CONFIG.C_ALL_OUTPUTS_2 {0} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_2_netInfo
 
# Create instance: axi_iic_0, and set properties
set axi_iic_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_0 ]
set_property -dict [ list \
CONFIG.C_SCL_INERTIAL_DELAY {5} \
CONFIG.C_SDA_INERTIAL_DELAY {5} \
] $axi_iic_0
 
# Create instance: axi_interconnect_0_ddr, and set properties
set axi_interconnect_0_ddr [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0_ddr ]
set_property -dict [ list \
CONFIG.NUM_MI {1} \
CONFIG.NUM_SI {3} \
] $axi_interconnect_0_ddr
 
# Create instance: axi_quad_spi_0, and set properties
set axi_quad_spi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0 ]
set_property -dict [ list \
CONFIG.C_FIFO_DEPTH {16} \
CONFIG.C_SCK_RATIO {2} \
CONFIG.C_SHARED_STARTUP {0} \
CONFIG.C_SPI_MEMORY {3} \
CONFIG.C_SPI_MODE {2} \
CONFIG.C_USE_STARTUP {1} \
CONFIG.C_USE_STARTUP_INT {1} \
] $axi_quad_spi_0
 
# Create instance: axi_timer_0, and set properties
set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
 
# Create instance: axi_uartlite_0, and set properties
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
set_property -dict [ list \
CONFIG.C_BAUDRATE {115200} \
] $axi_uartlite_0
 
# Create instance: clk_wiz_0, and set properties
set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.3 clk_wiz_0 ]
set_property -dict [ list \
CONFIG.CLKIN1_JITTER_PS {50.0} \
CONFIG.CLKOUT1_JITTER {112.316} \
CONFIG.CLKOUT1_PHASE_ERROR {89.971} \
CONFIG.MMCM_CLKFBOUT_MULT_F {5.000} \
CONFIG.MMCM_CLKIN1_PERIOD {5.0} \
CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \
CONFIG.MMCM_COMPENSATION {ZHOLD} \
CONFIG.PRIM_SOURCE {No_buffer} \
CONFIG.USE_RESET {false} \
] $clk_wiz_0
 
# Need to retain value_src of defaults
set_property -dict [ list \
CONFIG.CLKIN1_JITTER_PS.VALUE_SRC {DEFAULT} \
CONFIG.CLKOUT1_JITTER.VALUE_SRC {DEFAULT} \
CONFIG.CLKOUT1_PHASE_ERROR.VALUE_SRC {DEFAULT} \
CONFIG.MMCM_CLKFBOUT_MULT_F.VALUE_SRC {DEFAULT} \
CONFIG.MMCM_CLKIN1_PERIOD.VALUE_SRC {DEFAULT} \
CONFIG.MMCM_CLKIN2_PERIOD.VALUE_SRC {DEFAULT} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F.VALUE_SRC {DEFAULT} \
CONFIG.MMCM_COMPENSATION.VALUE_SRC {DEFAULT} \
] $clk_wiz_0
 
# Create instance: mdio_master_top_0, and set properties
set mdio_master_top_0 [ create_bd_cell -type ip -vlnv dfcdesign.cz:dfc:mdio_master_top:1.1 mdio_master_top_0 ]
 
# Create instance: mdm_1, and set properties
set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]
set_property -dict [ list \
CONFIG.C_DBG_MEM_ACCESS {1} \
CONFIG.C_USE_UART {1} \
] $mdm_1
 
# Create instance: microblaze_0, and set properties
set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ]
set_property -dict [ list \
CONFIG.C_DCACHE_LINE_LEN {8} \
CONFIG.C_DEBUG_ENABLED {1} \
CONFIG.C_D_AXI {1} \
CONFIG.C_D_LMB {1} \
CONFIG.C_ICACHE_LINE_LEN {8} \
CONFIG.C_I_LMB {1} \
CONFIG.C_USE_DCACHE {1} \
CONFIG.C_USE_ICACHE {1} \
] $microblaze_0
 
# Create instance: microblaze_0_axi_intc, and set properties
set microblaze_0_axi_intc [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 microblaze_0_axi_intc ]
set_property -dict [ list \
CONFIG.C_HAS_FAST {0} \
] $microblaze_0_axi_intc
 
# Create instance: microblaze_0_axi_periph, and set properties
set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
set_property -dict [ list \
CONFIG.NUM_MI {10} \
CONFIG.NUM_SI {1} \
] $microblaze_0_axi_periph
 
# Create instance: microblaze_0_int_concat, and set properties
set microblaze_0_int_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 microblaze_0_int_concat ]
set_property -dict [ list \
CONFIG.NUM_PORTS {5} \
] $microblaze_0_int_concat
 
# Create instance: microblaze_0_local_memory
create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory
 
# Create instance: mig_7series_0, and set properties
set mig_7series_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:4.0 mig_7series_0 ]
 
# Generate the PRJ File for MIG
set str_mig_folder [get_property IP_DIR [ get_ips [ get_property CONFIG.Component_Name $mig_7series_0 ] ] ]
set str_mig_file_name mig_b.prj
set str_mig_file_path ${str_mig_folder}/${str_mig_file_name}
 
write_mig_file_main_bd_mig_7series_0_0 $str_mig_file_path
 
set_property -dict [ list \
CONFIG.BOARD_MIG_PARAM {Custom} \
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.XML_INPUT_FILE {mig_b.prj} \
] $mig_7series_0
 
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
 
# Create instance: rst_mig_7series_0_100M, and set properties
set rst_mig_7series_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_mig_7series_0_100M ]
 
# Create instance: version_slice_0, and set properties
set version_slice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 version_slice_0 ]
set_property -dict [ list \
CONFIG.DIN_FROM {31} \
CONFIG.DIN_TO {0} \
CONFIG.DIN_WIDTH {64} \
CONFIG.DOUT_WIDTH {32} \
] $version_slice_0
 
# Create instance: version_slice_1, and set properties
set version_slice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 version_slice_1 ]
set_property -dict [ list \
CONFIG.DIN_FROM {63} \
CONFIG.DIN_TO {32} \
CONFIG.DIN_WIDTH {64} \
CONFIG.DOUT_WIDTH {32} \
] $version_slice_1
 
# Create interface connections
connect_bd_intf_net -intf_net axi_iic_0_IIC [get_bd_intf_ports IIC_RTL] [get_bd_intf_pins axi_iic_0/IIC]
connect_bd_intf_net -intf_net axi_interconnect_0_ddr_M00_AXI [get_bd_intf_pins axi_interconnect_0_ddr/M00_AXI] [get_bd_intf_pins mig_7series_0/S_AXI]
connect_bd_intf_net -intf_net axi_quad_spi_0_SPI_0 [get_bd_intf_ports SPI_RTL] [get_bd_intf_pins axi_quad_spi_0/SPI_0]
connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports MB_UART] [get_bd_intf_pins axi_uartlite_0/UART]
connect_bd_intf_net -intf_net mdio_master_top_0_mdio [get_bd_intf_ports MB_MDIO] [get_bd_intf_pins mdio_master_top_0/mdio]
connect_bd_intf_net -intf_net mdm_1_LMB_0 [get_bd_intf_pins mdm_1/LMB_0] [get_bd_intf_pins microblaze_0_local_memory/SLMB1]
connect_bd_intf_net -intf_net mdm_1_M_AXI [get_bd_intf_pins axi_interconnect_0_ddr/S02_AXI] [get_bd_intf_pins mdm_1/M_AXI]
connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_interconnect_0_ddr/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC]
connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_interconnect_0_ddr/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC]
connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins mdio_master_top_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins mdm_1/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_quad_spi_0/AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M06_AXI [get_bd_intf_pins axi_gpio_1_version/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M06_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M07_AXI [get_bd_intf_pins axi_iic_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M07_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M08_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M08_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M09_AXI [get_bd_intf_pins axi_gpio_2_netInfo/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M09_AXI]
connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]
connect_bd_intf_net -intf_net microblaze_0_intc_axi [get_bd_intf_pins microblaze_0_axi_intc/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net microblaze_0_interrupt [get_bd_intf_pins microblaze_0/INTERRUPT] [get_bd_intf_pins microblaze_0_axi_intc/interrupt]
connect_bd_intf_net -intf_net mig_7series_0_DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins mig_7series_0/DDR3]
 
# Create port connections
connect_bd_net -net Const_no_ext_rst_dout [get_bd_pins Const_no_ext_rst/dout] [get_bd_pins mig_7series_0/sys_rst] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins rst_mig_7series_0_100M/aux_reset_in]
connect_bd_net -net M00_ARESETN_1 [get_bd_pins axi_interconnect_0_ddr/M00_ARESETN] [get_bd_pins mig_7series_0/aresetn] [get_bd_pins rst_mig_7series_0_100M/peripheral_aresetn]
connect_bd_net -net VERSION_GPIO_1 [get_bd_ports VERSION_GPIO] [get_bd_pins version_slice_0/Din] [get_bd_pins version_slice_1/Din]
connect_bd_net -net axi_gpio_0_gpio2_io_o [get_bd_ports GPIO2_IO_O] [get_bd_pins axi_gpio_0/gpio2_io_o]
connect_bd_net -net axi_gpio_0_gpio2_io_t [get_bd_ports GPIO2_IO_T] [get_bd_pins axi_gpio_0/gpio2_io_t]
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_ports GPIO_IO_O] [get_bd_pins axi_gpio_0/gpio_io_o]
connect_bd_net -net axi_gpio_0_gpio_io_t [get_bd_ports GPIO_IO_T] [get_bd_pins axi_gpio_0/gpio_io_t]
connect_bd_net -net axi_gpio_2_netInfo_gpio2_io_o [get_bd_ports HOST_IP] [get_bd_pins axi_gpio_2_netInfo/gpio2_io_o]
connect_bd_net -net axi_gpio_2_netInfo_gpio2_io_t [get_bd_ports HOST_IP_NETMASK] [get_bd_pins axi_gpio_2_netInfo/gpio2_io_t]
connect_bd_net -net axi_gpio_2_netInfo_gpio_io_o [get_bd_ports HOST_MAC0] [get_bd_pins axi_gpio_2_netInfo/gpio_io_o]
connect_bd_net -net axi_gpio_2_netInfo_gpio_io_t [get_bd_ports HOST_MAC1] [get_bd_pins axi_gpio_2_netInfo/gpio_io_t]
connect_bd_net -net axi_iic_0_iic2intc_irpt [get_bd_pins axi_iic_0/iic2intc_irpt] [get_bd_pins microblaze_0_int_concat/In3]
connect_bd_net -net axi_quad_spi_0_ip2intc_irpt [get_bd_pins axi_quad_spi_0/ip2intc_irpt] [get_bd_pins microblaze_0_int_concat/In1]
connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins microblaze_0_int_concat/In4]
connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins microblaze_0_int_concat/In2]
connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins proc_sys_reset_0/dcm_locked]
connect_bd_net -net gpio2_io_i_1 [get_bd_ports GPIO2_IO_I] [get_bd_pins axi_gpio_0/gpio2_io_i]
connect_bd_net -net gpio_io_i_1 [get_bd_ports GPIO_IO_I] [get_bd_pins axi_gpio_0/gpio_io_i]
connect_bd_net -net mdm_1_Debug_SYS_Rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins proc_sys_reset_0/mb_debug_sys_rst]
connect_bd_net -net mdm_1_Interrupt [get_bd_pins mdm_1/Interrupt] [get_bd_pins microblaze_0_int_concat/In0]
connect_bd_net -net microblaze_0_intr [get_bd_pins microblaze_0_axi_intc/intr] [get_bd_pins microblaze_0_int_concat/dout]
connect_bd_net -net mig_7series_0_mmcm_locked [get_bd_pins mig_7series_0/mmcm_locked] [get_bd_pins rst_mig_7series_0_100M/dcm_locked]
connect_bd_net -net mig_7series_0_ui_clk [get_bd_ports AXI_CLK] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1_version/s_axi_aclk] [get_bd_pins axi_gpio_2_netInfo/s_axi_aclk] [get_bd_pins axi_iic_0/s_axi_aclk] [get_bd_pins axi_interconnect_0_ddr/ACLK] [get_bd_pins axi_interconnect_0_ddr/S00_ACLK] [get_bd_pins axi_interconnect_0_ddr/S01_ACLK] [get_bd_pins axi_interconnect_0_ddr/S02_ACLK] [get_bd_pins axi_quad_spi_0/ext_spi_clk] [get_bd_pins axi_quad_spi_0/s_axi_aclk] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins mdio_master_top_0/S_AXI_ACLK] [get_bd_pins mdm_1/M_AXI_ACLK] [get_bd_pins mdm_1/S_AXI_ACLK] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_intc/s_axi_aclk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/M06_ACLK] [get_bd_pins microblaze_0_axi_periph/M07_ACLK] [get_bd_pins microblaze_0_axi_periph/M08_ACLK] [get_bd_pins microblaze_0_axi_periph/M09_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk]
connect_bd_net -net mig_7series_0_ui_clk1 [get_bd_pins axi_interconnect_0_ddr/M00_ACLK] [get_bd_pins mig_7series_0/ui_clk] [get_bd_pins rst_mig_7series_0_100M/slowest_sync_clk]
connect_bd_net -net mig_7series_0_ui_clk_sync_rst [get_bd_pins mig_7series_0/ui_clk_sync_rst] [get_bd_pins rst_mig_7series_0_100M/ext_reset_in]
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0_ddr/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn]
connect_bd_net -net rst_mig_7series_0_100M_interconnect_aresetn [get_bd_pins proc_sys_reset_0/aux_reset_in] [get_bd_pins rst_mig_7series_0_100M/interconnect_aresetn]
connect_bd_net -net rst_mig_7series_0_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins proc_sys_reset_0/mb_reset]
connect_bd_net -net rst_mig_7series_0_100M_peripheral_aresetn [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1_version/s_axi_aresetn] [get_bd_pins axi_gpio_2_netInfo/s_axi_aresetn] [get_bd_pins axi_iic_0/s_axi_aresetn] [get_bd_pins axi_interconnect_0_ddr/S00_ARESETN] [get_bd_pins axi_interconnect_0_ddr/S01_ARESETN] [get_bd_pins axi_interconnect_0_ddr/S02_ARESETN] [get_bd_pins axi_quad_spi_0/s_axi_aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins mdio_master_top_0/S_AXI_ARESETN] [get_bd_pins mdm_1/M_AXI_ARESETN] [get_bd_pins mdm_1/S_AXI_ARESETN] [get_bd_pins microblaze_0_axi_intc/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/M06_ARESETN] [get_bd_pins microblaze_0_axi_periph/M07_ARESETN] [get_bd_pins microblaze_0_axi_periph/M08_ARESETN] [get_bd_pins microblaze_0_axi_periph/M09_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
connect_bd_net -net sys_clk_i_1 [get_bd_ports SYS_CLK_I] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins mig_7series_0/sys_clk_i]
connect_bd_net -net xlslice_0_Dout [get_bd_pins axi_gpio_1_version/gpio_io_i] [get_bd_pins version_slice_0/Dout]
connect_bd_net -net xlslice_1_Dout [get_bd_pins axi_gpio_1_version/gpio2_io_i] [get_bd_pins version_slice_1/Dout]
 
# Create address segments
create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB1/Mem] SEG_dlmb_bram_if_cntlr_Mem
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces mdm_1/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_1_version/S_AXI/Reg] SEG_axi_gpio_1_version_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_2_netInfo/S_AXI/Reg] SEG_axi_gpio_2_netInfo_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x40800000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_iic_0/S_AXI/Reg] SEG_axi_iic_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_quad_spi_0/AXI_LITE/Reg] SEG_axi_quad_spi_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem
create_bd_addr_seg -range 0x00020000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem
create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mdio_master_top_0/S_AXI/reg0] SEG_mdio_master_top_0_reg0
create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mdm_1/S_AXI/Reg] SEG_mdm_1_Reg
create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_axi_intc/S_AXI/Reg] SEG_microblaze_0_axi_intc_Reg
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs mig_7series_0/memmap/memaddr] SEG_mig_7series_0_memaddr
 
# Perform GUI Layout
regenerate_bd_layout -layout_string {
guistr: "# # String gsaved with Nlview 6.6.5b 2016-09-06 bk=1.3687 VDI=39 GEI=35 GUI=JA:1.6
# -string -flagsOSRD
preplace port SYS_CLK_I -pg 1 -y -1190 -defaultsOSRD
preplace port IIC_RTL -pg 1 -y 670 -defaultsOSRD
preplace port SPI_RTL -pg 1 -y 810 -defaultsOSRD
preplace port MB_MDIO -pg 1 -y 1550 -defaultsOSRD
preplace port DDR3 -pg 1 -y -1200 -defaultsOSRD
preplace port AXI_CLK -pg 1 -y 530 -defaultsOSRD
preplace port MB_UART -pg 1 -y 1310 -defaultsOSRD
preplace portBus GPIO2_IO_O -pg 1 -y 1090 -defaultsOSRD
preplace portBus GPIO_IO_T -pg 1 -y 1030 -defaultsOSRD
preplace portBus HOST_MAC0 -pg 1 -y 2320 -defaultsOSRD
preplace portBus GPIO_IO_I -pg 1 -y 590 -defaultsOSRD
preplace portBus HOST_MAC1 -pg 1 -y 2340 -defaultsOSRD
preplace portBus HOST_IP -pg 1 -y 2380 -defaultsOSRD
preplace portBus GPIO2_IO_T -pg 1 -y 1110 -defaultsOSRD
preplace portBus VERSION_GPIO -pg 1 -y 310 -defaultsOSRD
preplace portBus GPIO2_IO_I -pg 1 -y 610 -defaultsOSRD
preplace portBus GPIO_IO_O -pg 1 -y 1010 -defaultsOSRD
preplace portBus HOST_IP_NETMASK -pg 1 -y 2400 -defaultsOSRD
preplace inst rst_mig_7series_0_100M -pg 1 -lvl 4 -y -1370 -defaultsOSRD
preplace inst axi_iic_0 -pg 1 -lvl 4 -y 690 -defaultsOSRD
preplace inst mig_7series_0 -pg 1 -lvl 4 -y -1160 -defaultsOSRD
preplace inst version_slice_0 -pg 1 -lvl 3 -y 310 -defaultsOSRD
preplace inst microblaze_0_axi_periph -pg 1 -lvl 4 -y -370 -defaultsOSRD
preplace inst version_slice_1 -pg 1 -lvl 3 -y 390 -defaultsOSRD
preplace inst proc_sys_reset_0 -pg 1 -lvl 4 -y -1580 -defaultsOSRD
preplace inst microblaze_0_int_concat -pg 1 -lvl 4 -y 300 -defaultsOSRD
preplace inst axi_timer_0 -pg 1 -lvl 4 -y -930 -defaultsOSRD
preplace inst axi_gpio_0 -pg 1 -lvl 4 -y 1040 -defaultsOSRD
preplace inst microblaze_0_axi_intc -pg 1 -lvl 5 -y -140 -defaultsOSRD
preplace inst mdm_1 -pg 1 -lvl 2 -y -330 -defaultsOSRD
preplace inst mdio_master_top_0 -pg 1 -lvl 4 -y 1550 -defaultsOSRD
preplace inst axi_gpio_1_version -pg 1 -lvl 4 -y 510 -defaultsOSRD
preplace inst Const_no_ext_rst -pg 1 -lvl 3 -y -1370 -defaultsOSRD
preplace inst microblaze_0 -pg 1 -lvl 3 -y -330 -defaultsOSRD
preplace inst axi_uartlite_0 -pg 1 -lvl 4 -y 1320 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 1 -y -1060 -defaultsOSRD
preplace inst microblaze_0_local_memory -pg 1 -lvl 4 -y 140 -defaultsOSRD
preplace inst axi_quad_spi_0 -pg 1 -lvl 4 -y 830 -defaultsOSRD
preplace inst axi_interconnect_0_ddr -pg 1 -lvl 3 -y -980 -defaultsOSRD
preplace inst axi_gpio_2_netInfo -pg 1 -lvl 4 -y 2350 -defaultsOSRD
preplace netloc axi_quad_spi_0_SPI_0 1 4 2 NJ 810 NJ
preplace netloc axi_interconnect_0_ddr_M00_AXI 1 3 1 1250J
preplace netloc mig_7series_0_mmcm_locked 1 3 2 1400 -1250 2020
preplace netloc microblaze_0_axi_periph_M08_AXI 1 3 2 1400 -1030 2050
preplace netloc microblaze_0_axi_periph_M04_AXI 1 3 2 1380 20 2070
preplace netloc xlslice_1_Dout 1 3 2 NJ 390 2050
preplace netloc sys_clk_i_1 1 0 4 -130J -1190 NJ -1190 NJ -1190 1240J
preplace netloc gpio2_io_i_1 1 0 5 NJ 610 NJ 610 NJ 610 NJ 610 2020
preplace netloc clk_wiz_0_locked 1 1 3 180 -1540 NJ -1540 NJ
preplace netloc axi_gpio_2_netInfo_gpio2_io_o 1 4 2 NJ 2380 NJ
preplace netloc Const_no_ext_rst_dout 1 3 1 1310J
preplace netloc mig_7series_0_DDR3 1 4 2 NJ -1200 NJ
preplace netloc microblaze_0_intr 1 4 1 2140J
preplace netloc axi_uartlite_0_interrupt 1 3 2 1410 420 2070
preplace netloc axi_iic_0_iic2intc_irpt 1 3 2 1430 410 2040
preplace netloc axi_gpio_0_gpio2_io_t 1 4 2 NJ 1110 NJ
preplace netloc microblaze_0_interrupt 1 2 4 590J -70 NJ -70 2120J -220 2420
preplace netloc microblaze_0_intc_axi 1 4 1 2130J
preplace netloc microblaze_0_axi_periph_M06_AXI 1 3 2 1360 -10 2020
preplace netloc microblaze_0_axi_periph_M03_AXI 1 3 2 1370 10 2080
preplace netloc gpio_io_i_1 1 0 5 NJ 590 NJ 590 NJ 590 NJ 590 2030
preplace netloc microblaze_0_ilmb_1 1 3 1 1260J
preplace netloc microblaze_0_M_AXI_DC 1 2 2 560 -760 1240
preplace netloc mdm_1_M_AXI 1 2 1 510J
preplace netloc mdm_1_LMB_0 1 2 2 530J 140 NJ
preplace netloc mdm_1_Interrupt 1 2 2 510J 260 NJ
preplace netloc axi_gpio_2_netInfo_gpio_io_o 1 4 2 NJ 2320 NJ
preplace netloc microblaze_0_axi_periph_M05_AXI 1 3 2 1330 -20 2030
preplace netloc microblaze_0_axi_dp 1 3 1 1300J
preplace netloc proc_sys_reset_0_interconnect_aresetn 1 2 3 590J -790 1310J -790 2070
preplace netloc mig_7series_0_ui_clk1 1 2 3 580J -1270 1240J -1270 2030
preplace netloc mig_7series_0_ui_clk 1 1 5 160 -750 550J -750 1290J -750 2140 -750 2430
preplace netloc axi_gpio_2_netInfo_gpio2_io_t 1 4 2 NJ 2400 NJ
preplace netloc mdio_master_top_0_mdio 1 4 2 NJ 1550 NJ
preplace netloc rst_mig_7series_0_100M_peripheral_aresetn 1 1 4 170J -780 530J -780 1320J -780 2110J
preplace netloc rst_mig_7series_0_100M_interconnect_aresetn 1 3 2 1400 -1670 2060
preplace netloc axi_gpio_0_gpio_io_o 1 4 2 NJ 1010 NJ
preplace netloc microblaze_0_axi_periph_M01_AXI 1 3 2 1340 0 2090
preplace netloc microblaze_0_M_AXI_IC 1 2 2 570 -770 1250
preplace netloc VERSION_GPIO_1 1 0 3 NJ 310 NJ 310 550J
preplace netloc axi_uartlite_0_UART 1 4 2 NJ 1310 NJ
preplace netloc axi_iic_0_IIC 1 4 2 NJ 670 NJ
preplace netloc rst_mig_7series_0_100M_mb_reset 1 2 3 600J -40 1280J -40 2100
preplace netloc mig_7series_0_ui_clk_sync_rst 1 3 2 1390 -1280 2050
preplace netloc mdm_1_Debug_SYS_Rst 1 2 2 520J -1560 NJ
preplace netloc microblaze_0_dlmb_1 1 3 1 1270J
preplace netloc microblaze_0_axi_periph_M07_AXI 1 3 2 1400 30 2060
preplace netloc microblaze_0_axi_periph_M02_AXI 1 1 4 180J -60 NJ -60 NJ -60 2040
preplace netloc axi_gpio_2_netInfo_gpio_io_t 1 4 2 NJ 2340 NJ
preplace netloc axi_gpio_0_gpio2_io_o 1 4 2 NJ 1090 NJ
preplace netloc M00_ARESETN_1 1 2 3 600J -800 1310J -800 2060
preplace netloc microblaze_0_debug 1 2 1 540J
preplace netloc axi_quad_spi_0_ip2intc_irpt 1 3 2 1420 400 2060
preplace netloc microblaze_0_axi_periph_M09_AXI 1 3 2 1350 40 2050
preplace netloc xlslice_0_Dout 1 3 2 1250J 430 2020
preplace netloc axi_timer_0_interrupt 1 3 2 1390 -1050 2020
preplace netloc axi_gpio_0_gpio_io_t 1 4 2 NJ 1030 NJ
levelinfo -pg 1 -150 80 380 1020 1860 2310 2490 -top -1690 -bot 2650
",
}
 
# Restore current instance
current_bd_instance $oldCurInst
 
save_bd_design
}
# End of create_root_design()
 
 
##################################################################
# MAIN FLOW
##################################################################
 
create_root_design ""
 
 
/trunk/examples/Eth_example/src/tcl/recreate_project_xc7k160t.tcl
0,0 → 1,496
#
# Vivado (TM) v2016.4 (64-bit)
#
# recreate_project_xc7k160t.tcl: Tcl script for re-creating project 'eth_example'
#
# Generated by Vivado on Thu May 03 14:34:55 +0200 2018
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (recreate_project_xc7k160t.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "C:/projects/dfc/xenie/Eth_example/trunk/src/bd/main_bd/main_bd.bd"
# "C:/projects/dfc/xenie/Eth_example/trunk/src/hdl/udp_ip_10g_test_app.vhd"
# "C:/projects/dfc/xenie/Eth_example/trunk/src/ip/rxaui_0/rxaui_0.xci"
# "C:/projects/dfc/xenie/Eth_example/trunk/src/hdl/xenie_eth_example.vhd"
# "C:/projects/dfc/xenie/Eth_example/trunk/src/bd/main_bd/ip/main_bd_mig_7series_0_0/mig_a.prj"
# "C:/projects/dfc/xenie/Eth_example/trunk/src/ip/udp_ip_10g_0/udp_ip_10g_0.xci"
# "C:/projects/dfc/xenie/Eth_example/trunk/src/constr/xenie_1_0.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
# <none>
#
#*****************************************************************************************
 
# Set the reference directory to where the script is
set origin_dir [file normalize [file dirname [info script]]]
 
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
 
variable script_file
set script_file "recreate_project_xc7k160t.tcl"
 
# Help information for this script
proc help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
 
if { $::argc > 0 } {
for {set i 0} {$i < [llength $::argc]} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
 
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/../../vivado"]"
 
# Create project
create_project eth_example $orig_proj_dir
 
 
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
 
# Reconstruct message rules
# None
 
# Set project properties
set obj [get_projects eth_example]
set_property "board_part" "" $obj
set_property "compxlib.activehdl_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/activehdl" $obj
set_property "compxlib.funcsim" "1" $obj
set_property "compxlib.ies_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/ies" $obj
set_property "compxlib.modelsim_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/modelsim" $obj
set_property "compxlib.overwrite_libs" "0" $obj
set_property "compxlib.questa_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/questa" $obj
set_property "compxlib.riviera_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/riviera" $obj
set_property "compxlib.timesim" "1" $obj
set_property "compxlib.vcs_compiled_library_dir" "$proj_dir/eth_example.cache/compile_simlib/vcs" $obj
set_property "compxlib.xsim_compiled_library_dir" "" $obj
set_property "corecontainer.enable" "0" $obj
set_property "default_lib" "xil_defaultlib" $obj
set_property "dsa.num_compute_units" "16" $obj
set_property "enable_optional_runs_sta" "0" $obj
set_property "generate_ip_upgrade_log" "1" $obj
set_property "ip_cache_permissions" "read write" $obj
set_property "ip_output_repo" "$proj_dir/eth_example.cache/ip" $obj
set_property "managed_ip" "0" $obj
set_property "part" "xc7k160tffg676-1" $obj
set_property "pr_flow" "0" $obj
set_property "sim.ip.auto_export_scripts" "1" $obj
set_property "sim.use_ip_compiled_libs" "1" $obj
set_property "simulator_language" "Mixed" $obj
set_property "source_mgmt_mode" "All" $obj
set_property "target_language" "VHDL" $obj
set_property "target_simulator" "XSim" $obj
set_property "xpm_libraries" "XPM_CDC XPM_FIFO XPM_MEMORY" $obj
set_property "xsim.array_display_limit" "64" $obj
set_property "xsim.radix" "hex" $obj
set_property "xsim.time_unit" "ns" $obj
set_property "xsim.trace_limit" "65536" $obj
 
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
 
# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../ip_repo"]" $obj
 
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
 
 
# Create Block Design
set old_path [pwd]
cd $origin_dir/../
proc wrap_recreate_bd {run_dir} {
source $run_dir/recreate_bd_xc7k160t.tcl
# Generate the wrapper (unused)
#set design_name [get_bd_designs]
#make_wrapper -files [get_files $design_name.bd] -top -import
}
wrap_recreate_bd $origin_dir
 
cd $old_path
 
 
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
"[file normalize "$origin_dir/../bd/main_bd/main_bd.bd"]"\
"[file normalize "$origin_dir/../hdl/udp_ip_10g_test_app.vhd"]"\
"[file normalize "$origin_dir/../ip/rxaui_0/rxaui_0.xci"]"\
"[file normalize "$origin_dir/../hdl/xenie_eth_example.vhd"]"\
"[file normalize "$origin_dir/../bd/main_bd/ip/main_bd_mig_7series_0_0/mig_b.prj"]"\
]
add_files -norecurse -fileset $obj $files
 
# Set 'sources_1' fileset file properties for remote files
# None
 
# Set 'sources_1' fileset file properties for local files
set file "main_bd/main_bd.bd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "exclude_debug_logic" "0" $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property "generate_synth_checkpoint" "1" $file_obj
}
set_property "is_enabled" "1" $file_obj
set_property "is_global_include" "0" $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property "is_locked" "0" $file_obj
}
set_property "library" "xil_defaultlib" $file_obj
set_property "path_mode" "RelativeFirst" $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property "synth_checkpoint_mode" "Hierarchical" $file_obj
}
set_property "used_in" "synthesis implementation simulation" $file_obj
set_property "used_in_implementation" "1" $file_obj
set_property "used_in_simulation" "1" $file_obj
set_property "used_in_synthesis" "1" $file_obj
 
set file "hdl/udp_ip_10g_test_app.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj
set_property "is_enabled" "1" $file_obj
set_property "is_global_include" "0" $file_obj
set_property "library" "xil_defaultlib" $file_obj
set_property "path_mode" "RelativeFirst" $file_obj
set_property "used_in" "synthesis simulation" $file_obj
set_property "used_in_simulation" "1" $file_obj
set_property "used_in_synthesis" "1" $file_obj
 
set file "rxaui_0/rxaui_0.xci"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "is_enabled" "1" $file_obj
set_property "is_global_include" "0" $file_obj
set_property "library" "xil_defaultlib" $file_obj
set_property "path_mode" "RelativeFirst" $file_obj
set_property "used_in" "synthesis implementation simulation" $file_obj
set_property "used_in_implementation" "1" $file_obj
set_property "used_in_simulation" "1" $file_obj
set_property "used_in_synthesis" "1" $file_obj
 
set file "hdl/xenie_eth_example.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj
set_property "is_enabled" "1" $file_obj
set_property "is_global_include" "0" $file_obj
set_property "library" "xil_defaultlib" $file_obj
set_property "path_mode" "RelativeFirst" $file_obj
set_property "used_in" "synthesis simulation" $file_obj
set_property "used_in_simulation" "1" $file_obj
set_property "used_in_synthesis" "1" $file_obj
 
set file "main_bd_mig_7series_0_0/mig_b.prj"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "is_enabled" "1" $file_obj
set_property "is_global_include" "0" $file_obj
set_property "library" "xil_defaultlib" $file_obj
set_property "path_mode" "RelativeFirst" $file_obj
set_property "scoped_to_cells" "" $file_obj
set_property "scoped_to_ref" "" $file_obj
set_property "used_in" "synthesis" $file_obj
set_property "used_in_synthesis" "1" $file_obj
 
 
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property "design_mode" "RTL" $obj
set_property "edif_extra_search_paths" "" $obj
set_property "elab_link_dcps" "1" $obj
set_property "elab_load_timing_constraints" "1" $obj
set_property "generic" "" $obj
set_property "include_dirs" "" $obj
set_property "lib_map_file" "" $obj
set_property "loop_count" "1000" $obj
set_property "name" "sources_1" $obj
set_property "top" "xenie_eth_example" $obj
set_property "verilog_define" "" $obj
set_property "verilog_uppercase" "0" $obj
 
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
"[file normalize "$origin_dir/../ip/udp_ip_10g_0/udp_ip_10g_0.xci"]"\
]
add_files -norecurse -fileset $obj $files
 
# Set 'sources_1' fileset file properties for remote files
# None
 
# Set 'sources_1' fileset file properties for local files
set file "udp_ip_10g_0/udp_ip_10g_0.xci"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
if { ![get_property "is_locked" $file_obj] } {
set_property "generate_synth_checkpoint" "1" $file_obj
}
set_property "is_enabled" "1" $file_obj
set_property "is_global_include" "0" $file_obj
set_property "library" "xil_defaultlib" $file_obj
set_property "path_mode" "RelativeFirst" $file_obj
set_property "used_in" "synthesis implementation simulation" $file_obj
set_property "used_in_implementation" "1" $file_obj
set_property "used_in_simulation" "1" $file_obj
set_property "used_in_synthesis" "1" $file_obj
 
 
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1
}
 
# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]
 
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/../constr/xenie_1_0.xdc"]"
set file_added [add_files -norecurse -fileset $obj $file]
set file "constr/xenie_1_0.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property "file_type" "XDC" $file_obj
set_property "is_enabled" "1" $file_obj
set_property "is_global_include" "0" $file_obj
set_property "library" "xil_defaultlib" $file_obj
set_property "path_mode" "RelativeFirst" $file_obj
set_property "processing_order" "NORMAL" $file_obj
set_property "scoped_to_cells" "" $file_obj
set_property "scoped_to_ref" "" $file_obj
set_property "used_in" "synthesis implementation" $file_obj
set_property "used_in_implementation" "1" $file_obj
set_property "used_in_synthesis" "1" $file_obj
 
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property "name" "constrs_1" $obj
set_property "target_constrs_file" "[file normalize "$origin_dir/../constr/xenie_1_0.xdc"]" $obj
 
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
create_fileset -simset sim_1
}
 
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)
 
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property "generic" "" $obj
set_property "include_dirs" "" $obj
set_property "name" "sim_1" $obj
set_property "nl.cell" "" $obj
set_property "nl.incl_unisim_models" "0" $obj
set_property "nl.process_corner" "slow" $obj
set_property "nl.rename_top" "" $obj
set_property "nl.sdf_anno" "1" $obj
set_property "nl.write_all_overrides" "0" $obj
set_property "runtime" "1000ns" $obj
set_property "source_set" "sources_1" $obj
set_property "top" "xenie_eth_example" $obj
set_property "transport_int_delay" "0" $obj
set_property "transport_path_delay" "0" $obj
set_property "unit_under_test" "" $obj
set_property "verilog_define" "" $obj
set_property "verilog_uppercase" "0" $obj
set_property "xelab.debug_level" "typical" $obj
set_property "xelab.dll" "0" $obj
set_property "xelab.load_glbl" "1" $obj
set_property "xelab.more_options" "" $obj
set_property "xelab.mt_level" "auto" $obj
set_property "xelab.nosort" "1" $obj
set_property "xelab.rangecheck" "0" $obj
set_property "xelab.relax" "1" $obj
set_property "xelab.sdf_delay" "sdfmax" $obj
set_property "xelab.snapshot" "" $obj
set_property "xelab.unifast" "" $obj
set_property "xsim.compile.incremental" "0" $obj
set_property "xsim.compile.xvhdl.more_options" "" $obj
set_property "xsim.compile.xvhdl.nosort" "1" $obj
set_property "xsim.compile.xvhdl.relax" "1" $obj
set_property "xsim.compile.xvlog.more_options" "" $obj
set_property "xsim.compile.xvlog.nosort" "1" $obj
set_property "xsim.compile.xvlog.relax" "1" $obj
set_property "xsim.elaborate.debug_level" "typical" $obj
set_property "xsim.elaborate.load_glbl" "1" $obj
set_property "xsim.elaborate.mt_level" "auto" $obj
set_property "xsim.elaborate.rangecheck" "0" $obj
set_property "xsim.elaborate.relax" "1" $obj
set_property "xsim.elaborate.sdf_delay" "sdfmax" $obj
set_property "xsim.elaborate.snapshot" "" $obj
set_property "xsim.elaborate.xelab.more_options" "" $obj
set_property "xsim.more_options" "" $obj
set_property "xsim.saif" "" $obj
set_property "xsim.simulate.log_all_signals" "0" $obj
set_property "xsim.simulate.runtime" "1000ns" $obj
set_property "xsim.simulate.saif" "" $obj
set_property "xsim.simulate.saif_all_signals" "0" $obj
set_property "xsim.simulate.saif_scope" "" $obj
set_property "xsim.simulate.wdb" "" $obj
set_property "xsim.simulate.xsim.more_options" "" $obj
set_property "xsim.tclbatch" "" $obj
set_property "xsim.view" "" $obj
set_property "xsim.wdb" "" $obj
 
# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7k160tffg676-1 -flow {Vivado Synthesis 2016} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2016" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property "constrset" "constrs_1" $obj
set_property "description" "Vivado Synthesis Defaults" $obj
set_property "flow" "Vivado Synthesis 2016" $obj
set_property "name" "synth_1" $obj
set_property "needs_refresh" "0" $obj
set_property "part" "xc7k160tffg676-1" $obj
set_property "srcset" "sources_1" $obj
set_property "strategy" "Vivado Synthesis Defaults" $obj
set_property "incremental_checkpoint" "" $obj
set_property "include_in_archive" "1" $obj
set_property "steps.synth_design.tcl.pre" "[file normalize "$origin_dir/setCompileTime.tcl"]" $obj
set_property "steps.synth_design.tcl.post" "" $obj
set_property "steps.synth_design.args.flatten_hierarchy" "none" $obj
set_property "steps.synth_design.args.gated_clock_conversion" "off" $obj
set_property "steps.synth_design.args.bufg" "12" $obj
set_property "steps.synth_design.args.fanout_limit" "10000" $obj
set_property "steps.synth_design.args.directive" "Default" $obj
set_property "steps.synth_design.args.retiming" "0" $obj
set_property "steps.synth_design.args.fsm_extraction" "auto" $obj
set_property "steps.synth_design.args.keep_equivalent_registers" "0" $obj
set_property "steps.synth_design.args.resource_sharing" "auto" $obj
set_property "steps.synth_design.args.control_set_opt_threshold" "auto" $obj
set_property "steps.synth_design.args.no_lc" "0" $obj
set_property "steps.synth_design.args.no_srlextract" "0" $obj
set_property "steps.synth_design.args.shreg_min_size" "3" $obj
set_property "steps.synth_design.args.max_bram" "-1" $obj
set_property "steps.synth_design.args.max_uram" "-1" $obj
set_property "steps.synth_design.args.max_dsp" "-1" $obj
set_property "steps.synth_design.args.max_bram_cascade_height" "-1" $obj
set_property "steps.synth_design.args.max_uram_cascade_height" "-1" $obj
set_property "steps.synth_design.args.cascade_dsp" "auto" $obj
set_property "steps.synth_design.args.assert" "0" $obj
set_property -name {steps.synth_design.args.more options} -value {-generic g_compilation_date=$compileTime} -objects $obj
 
# set the current synth run
current_run -synthesis [get_runs synth_1]
 
# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7k160tffg676-1 -flow {Vivado Implementation 2016} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2016" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property "constrset" "constrs_1" $obj
set_property "description" "Default settings for Implementation." $obj
set_property "flow" "Vivado Implementation 2016" $obj
set_property "name" "impl_1" $obj
set_property "needs_refresh" "0" $obj
set_property "part" "xc7k160tffg676-1" $obj
set_property "pr_configuration" "" $obj
set_property "srcset" "sources_1" $obj
set_property "strategy" "Vivado Implementation Defaults" $obj
set_property "incremental_checkpoint" "" $obj
set_property "include_in_archive" "1" $obj
set_property "steps.opt_design.is_enabled" "1" $obj
set_property "steps.opt_design.tcl.pre" "" $obj
set_property "steps.opt_design.tcl.post" "" $obj
set_property "steps.opt_design.args.verbose" "0" $obj
set_property "steps.opt_design.args.directive" "Default" $obj
set_property -name {steps.opt_design.args.more options} -value {} -objects $obj
set_property "steps.power_opt_design.is_enabled" "0" $obj
set_property "steps.power_opt_design.tcl.pre" "" $obj
set_property "steps.power_opt_design.tcl.post" "" $obj
set_property -name {steps.power_opt_design.args.more options} -value {} -objects $obj
set_property "steps.place_design.tcl.pre" "" $obj
set_property "steps.place_design.tcl.post" "" $obj
set_property "steps.place_design.args.directive" "Default" $obj
set_property -name {steps.place_design.args.more options} -value {} -objects $obj
set_property "steps.post_place_power_opt_design.is_enabled" "0" $obj
set_property "steps.post_place_power_opt_design.tcl.pre" "" $obj
set_property "steps.post_place_power_opt_design.tcl.post" "" $obj
set_property -name {steps.post_place_power_opt_design.args.more options} -value {} -objects $obj
set_property "steps.phys_opt_design.is_enabled" "0" $obj
set_property "steps.phys_opt_design.tcl.pre" "" $obj
set_property "steps.phys_opt_design.tcl.post" "" $obj
set_property "steps.phys_opt_design.args.directive" "Default" $obj
set_property -name {steps.phys_opt_design.args.more options} -value {} -objects $obj
set_property "steps.route_design.tcl.pre" "" $obj
set_property "steps.route_design.tcl.post" "" $obj
set_property "steps.route_design.args.directive" "Default" $obj
set_property -name {steps.route_design.args.more options} -value {} -objects $obj
set_property "steps.post_route_phys_opt_design.is_enabled" "0" $obj
set_property "steps.post_route_phys_opt_design.tcl.pre" "" $obj
set_property "steps.post_route_phys_opt_design.tcl.post" "" $obj
set_property "steps.post_route_phys_opt_design.args.directive" "Default" $obj
set_property -name {steps.post_route_phys_opt_design.args.more options} -value {} -objects $obj
set_property "steps.write_bitstream.tcl.pre" "" $obj
set_property "steps.write_bitstream.tcl.post" "" $obj
set_property "steps.write_bitstream.args.raw_bitfile" "0" $obj
set_property "steps.write_bitstream.args.mask_file" "0" $obj
set_property "steps.write_bitstream.args.no_binary_bitfile" "0" $obj
set_property "steps.write_bitstream.args.bin_file" "0" $obj
set_property "steps.write_bitstream.args.readback_file" "0" $obj
set_property "steps.write_bitstream.args.logic_location_file" "0" $obj
set_property "steps.write_bitstream.args.verbose" "0" $obj
set_property -name {steps.write_bitstream.args.more options} -value {} -objects $obj
 
# set the current impl run
current_run -implementation [get_runs impl_1]
 
puts "INFO: Project created:eth_example"

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