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Rev 7 → Rev 8

/trunk/SinglePathFPAdder/special_cases.v
0,0 → 1,57
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:56:11 10/07/2013
// Design Name:
// Module Name: special_cases_mul_acc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module special_cases #( parameter size_exception_field = 2'd2,
parameter [size_exception_field - 1 : 0] zero = 0, //00
parameter [size_exception_field - 1 : 0] normal_number= 1, //01
parameter [size_exception_field - 1 : 0] infinity = 2, //10
parameter [size_exception_field - 1 : 0] NaN = 3) //11
( input [size_exception_field - 1 : 0] sp_case_a_number,
input [size_exception_field - 1 : 0] sp_case_b_number,
output reg [size_exception_field - 1 : 0] sp_case_result_o);
always
@(*)
begin
case ({sp_case_a_number, sp_case_b_number})
{zero, zero}: sp_case_result_o = zero;
{zero, normal_number}: sp_case_result_o = normal_number;
{zero, infinity}: sp_case_result_o = infinity;
{zero, NaN}: sp_case_result_o = NaN;
{normal_number,zero}: sp_case_result_o = normal_number;
{normal_number,normal_number}: sp_case_result_o = normal_number;
{normal_number,infinity}: sp_case_result_o = infinity;
{normal_number,NaN}: sp_case_result_o = NaN;
{infinity, zero}: sp_case_result_o = infinity;
{infinity, normal_number}: sp_case_result_o = infinity;
{infinity, infinity}: sp_case_result_o = infinity;
{infinity, NaN}: sp_case_result_o = NaN;
{NaN, zero}: sp_case_result_o = NaN;
{NaN, normal_number}: sp_case_result_o = NaN;
{NaN, infinity}: sp_case_result_o = NaN;
{NaN, NaN}: sp_case_result_o = NaN;
default: sp_case_result_o = zero;
endcase
end
endmodule
/trunk/SinglePathFPAdder/effective_op.v
0,0 → 1,40
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:41:11 11/04/2013
// Design Name:
// Module Name: effective_op
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module effective_op( input a_sign,
input b_sign,
input sub,
output reg eff_op);
always
@(*)
begin
case ({sub,a_sign, b_sign})
3'b000: eff_op = 0;
3'b001: eff_op = 1;
3'b010: eff_op = 1;
3'b011: eff_op = 0;
3'b100: eff_op = 1;
3'b101: eff_op = 0;
3'b110: eff_op = 0;
3'b111: eff_op = 1;
endcase
end
endmodule
/trunk/SinglePathFPAdder/d_ff.v
0,0 → 1,37
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:39:58 02/04/2013
// Design Name:
// Module Name: d_ff
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 / File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module d_ff (clk, rst, d, q);
parameter SIZE = 24;
input clk;
input rst;
input [SIZE-1 : 0] d;
output reg [SIZE-1 : 0] q;
always
@(posedge clk, posedge rst)
begin
if (rst)
q <= {SIZE{1'b0}};
else
q <= d;
end
endmodule
/trunk/SinglePathFPAdder/shifter.v
0,0 → 1,112
 
 
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:00:33 10/15/2013
// Design Name:
// Module Name: shifter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shifter #( parameter INPUT_SIZE = 13,
parameter SHIFT_SIZE = 4,
parameter OUTPUT_SIZE = 24, //>INPUT_SIZE
parameter DIRECTION = 1,
parameter PIPELINE = 1,
parameter [7:0] POSITION = 8'b00000000)
(a, arith, shft, shifted_a);
input [INPUT_SIZE-1:0] a;
input arith;
input [SHIFT_SIZE-1:0] shft;
output [OUTPUT_SIZE-1:0] shifted_a;
wire [OUTPUT_SIZE-1:0] a_temp_d[SHIFT_SIZE:0];
wire [OUTPUT_SIZE-1:0] a_temp_q[SHIFT_SIZE:0];
assign a_temp_q[0][OUTPUT_SIZE-1 : OUTPUT_SIZE-INPUT_SIZE] = a;
assign a_temp_q[0][OUTPUT_SIZE-1-INPUT_SIZE : 0] = arith;
generate
begin : GENERATING
genvar i;
for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
begin : BARREL_SHIFTER_GENERATION
if (DIRECTION == 1)
begin : LEFT
//begin : 1st_check
genvar j;
for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
begin : MUX_GEN_L
if (j < 2 ** i)
begin : ZERO_INS_L
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
end
if (j >= 2 ** i)
begin : BIT_INS_L
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
end
end
//end
end
if (DIRECTION == 0)
begin : RIGHT
//begin : 2nd_check
genvar j;
for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
begin : MUX_GEN_R
if (OUTPUT_SIZE - 1 < 2 ** i + j)
begin : ZERO_INS_R
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
end
if (OUTPUT_SIZE - 1 >= 2 ** i + j)
begin : BIT_INS_R
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
end
end
//end
end
if (PIPELINE != 0)
begin : PIPELINE_INSERTION
if (POSITION[i] == 1'b1)
begin : LATCH
d_ff #(OUTPUT_SIZE) D_INS(.clk(clk), .rst(rst), .d(a_temp_d[i]), .q(a_temp_q[i + 1]));
end
if (POSITION[i] == 1'b0)
begin : NO_LATCH
assign a_temp_q[i + 1] = a_temp_d[i];
end
end
if (PIPELINE == 0)
begin : NO_PIPELINE
assign a_temp_q[i + 1] = a_temp_d[i];
end
end
end
endgenerate
assign shifted_a = a_temp_q[SHIFT_SIZE];
endmodule
 
/trunk/SinglePathFPAdder/SinglePathFPAdder.v
0,0 → 1,157
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:09:49 11/04/2013
// Design Name:
// Module Name: SinglePathFPAdder
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SinglePathFPAdder #( parameter size_mantissa = 24, //1.M
parameter size_exponent = 8,
parameter size_exception_field = 2,
parameter size_counter = 5, //log2(size_mantissa) + 1 = 5)
parameter [size_exception_field - 1 : 0] zero = 0, //00
parameter [size_exception_field - 1 : 0] normal_number= 1, //01
parameter [size_exception_field - 1 : 0] infinity = 2, //10
parameter [size_exception_field - 1 : 0] NaN = 3, //11
parameter pipeline = 0,
parameter pipeline_pos = 0, // 8 bits
parameter double_size_mantissa = size_mantissa + size_mantissa,
parameter double_size_counter = size_counter + 1,
parameter size = size_mantissa + size_exponent + size_exception_field)
(sub, a_number_i, b_number_i, resulted_number_o);
 
input sub;
input [size - 1 : 0] a_number_i;
input [size - 1 : 0] b_number_i;
output[size - 1 : 0] resulted_number_o;
wire [size_mantissa - 1 : 0] m_a_number, m_b_number;
wire [size_exponent - 1 : 0] e_a_number, e_b_number;
wire s_a_number, s_b_number;
wire [size_exception_field - 1 : 0] sp_case_a_number, sp_case_b_number;
wire [size_exponent - 1 : 0] exp_difference;
wire [size_exponent - 1 : 0] modify_exp_a, modify_exp_b;
wire [double_size_mantissa - 1 : 0] shifted_m_a, shifted_m_b;
wire eff_op;
wire [double_size_mantissa : 0] unnormalized_mantissa;
wire [double_size_counter-1: 0] lzs;
wire [size_mantissa-1: 0] unrounded_mantissa;
wire [size_mantissa-1: 0] resulted_mantissa;
wire [size_exponent-1: 0] resulted_exponent;
wire resulted_sign;
wire [size_exception_field - 1 : 0] resulted_exception_field;
wire [size_mantissa + 1 : 0] dummy_bits;
assign m_a_number = {1'b1, a_number_i[size_mantissa - 2 :0]};
assign m_b_number = {1'b1, b_number_i[size_mantissa - 2 :0]};
assign e_a_number = a_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
assign e_b_number = b_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
assign s_a_number = a_number_i[size - size_exception_field - 1];
assign s_b_number = b_number_i[size - size_exception_field - 1];
assign sp_case_a_number = a_number_i[size - 1 : size - size_exception_field];
assign sp_case_b_number = b_number_i[size - 1 : size - size_exception_field];
 
//find the difference between exponents
assign exp_difference = (e_a_number > e_b_number)? (e_a_number - e_b_number) : (e_b_number - e_a_number);
 
assign {modify_exp_a, modify_exp_b} = (e_a_number > e_b_number)? {8'd0, exp_difference} : {exp_difference, 8'd0};
//shift the right mantissa
shifter #( .INPUT_SIZE(size_mantissa),
.SHIFT_SIZE(size_exponent),
.OUTPUT_SIZE(double_size_mantissa),
.DIRECTION(1'b0), //0=right, 1=left
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
m_a_shifter_instance( .a(m_a_number),//mantissa
.arith(1'b0),//logical shift
.shft(modify_exp_a),
.shifted_a(shifted_m_a));
shifter #( .INPUT_SIZE(size_mantissa),
.SHIFT_SIZE(size_exponent),
.OUTPUT_SIZE(double_size_mantissa),
.DIRECTION(1'b0), //0=right, 1=left
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
m_b_shifter_instance( .a(m_b_number),//mantissa
.arith(1'b0),//logical shift
.shft(modify_exp_b),
.shifted_a(shifted_m_b));
//istantiate effective_operation_component
effective_op effective_op_instance( .a_sign(s_a_number), .b_sign(s_b_number), .sub(sub), .eff_op(eff_op));
//compute unnormalized_mantissa
assign unnormalized_mantissa = (eff_op)? ((shifted_m_a > shifted_m_b)? (shifted_m_a - shifted_m_b) : (shifted_m_b - shifted_m_a)) :
shifted_m_a + shifted_m_b;
//compute leading_zeros over unnormalized mantissa
leading_zeros #( .SIZE_INT(double_size_mantissa + 1'b1), .SIZE_COUNTER(double_size_counter), .PIPELINE(pipeline))
leading_zeros_instance (.a(unnormalized_mantissa),
.ovf(1'b0),
.lz(lzs));
//compute shifting over unnormalized_mantissa
shifter #( .INPUT_SIZE(double_size_mantissa + 1'b1),
.SHIFT_SIZE(double_size_counter),
.OUTPUT_SIZE(double_size_mantissa + 2'd2),
.DIRECTION(1'b1), //0=right, 1=left
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
shifter_instance( .a(unnormalized_mantissa),//mantissa
.arith(1'b0),//logical shift
.shft(lzs),
.shifted_a({unrounded_mantissa, dummy_bits}));
//
//assign g = dummy_bits[size_mantissa + 1];
//assign sticky = |(dummy_bits[size_mantissa : 0]);
//assign round_dec = g & (unrounded_mantissa[0] | sticky);
//instantiate rounding_component
rounding #( .SIZE_MOST_S_MANTISSA(size_mantissa),
.SIZE_LEAST_S_MANTISSA(size_mantissa + 2'd2))
rounding_instance( .unrounded_mantissa(unrounded_mantissa),
.dummy_bits(dummy_bits),
.rounded_mantissa(resulted_mantissa));
//compute resulted_exponent
assign resulted_exponent = (e_a_number >= e_b_number)? (e_a_number - lzs + 1'b1) : (e_b_number - lzs + 1'b1);
//compute resulted_sign
assign resulted_sign = (eff_op)? ((shifted_m_a > shifted_m_b)? s_a_number : ~s_a_number) : s_a_number;
//compute exception_field
special_cases #( .size_exception_field(size_exception_field),
.zero(zero),
.normal_number(normal_number),
.infinity(infinity),
.NaN(NaN))
special_cases_instance( .sp_case_a_number(sp_case_a_number),
.sp_case_b_number(sp_case_b_number),
.sp_case_result_o(resulted_exception_field));
//generate final result
assign resulted_number_o = {resulted_exception_field, resulted_sign, resulted_exponent, resulted_mantissa[size_mantissa-2 : 0]};
endmodule
/trunk/SinglePathFPAdder/rounding.v
0,0 → 1,35
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:09:49 11/04/2013
// Design Name:
// Module Name: rounding
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module rounding #( parameter SIZE_MOST_S_MANTISSA = 24,
parameter SIZE_LEAST_S_MANTISSA= 25)
( input [SIZE_MOST_S_MANTISSA - 1 : 0] unrounded_mantissa,
input [SIZE_LEAST_S_MANTISSA- 1 : 0] dummy_bits,
output[SIZE_MOST_S_MANTISSA - 1 : 0] rounded_mantissa);
wire g, sticky, round_dec;
assign g = dummy_bits[SIZE_LEAST_S_MANTISSA - 1];
assign sticky = |(dummy_bits[SIZE_LEAST_S_MANTISSA - 2 : 0]);
assign round_dec = g & (unrounded_mantissa[0] | sticky);
assign rounded_mantissa = unrounded_mantissa + round_dec;
endmodule
/trunk/SinglePathFPAdder/leading_zeros.v
0,0 → 1,139
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:50:09 10/17/2013
// Design Name:
// Module Name: leading_zeros
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module leading_zeros #( parameter SIZE_INT = 24, //mantissa bits
parameter SIZE_COUNTER = 5, //log2(size_mantissa) + 1 = 5)
parameter PIPELINE = 2)
(a, ovf, lz);
input [SIZE_INT-1:0] a;
input ovf;
output [SIZE_COUNTER-1:0] lz;
parameter nr_levels = SIZE_COUNTER - 1;
parameter max_pow_2 = 2 ** SIZE_COUNTER;
parameter size_lz = SIZE_COUNTER;
wire [max_pow_2-1:0] a_complete;
wire [max_pow_2-1:0] v_d[nr_levels-1:0];
wire [max_pow_2-1:0] v_q[nr_levels-1:0];
wire [max_pow_2-1:0] p_d[nr_levels-1:0];
wire [max_pow_2-1:0] p_q[nr_levels-1:0];
wire [size_lz-1:0] lzc;
assign a_complete[max_pow_2 - 1 : max_pow_2 - 1 - SIZE_INT + 1] = a;
generate
if (max_pow_2 != SIZE_INT)
begin : gen_if
assign a_complete[max_pow_2 - 1 - SIZE_INT : 0] = 0;
end
endgenerate
generate
begin : level_0
genvar i;
for (i = max_pow_2/4 - 1; i >= 0; i = i - 1)
begin : level_0
assign v_d[0][i] = (a_complete[4 * i + 3 : 4 * i] == 4'b0000) ? 1'b0 : 1'b1;
assign p_d[0][2*i+1:2*i] = (a_complete[4 * i + 3] == 1'b1) ? 2'b00 :
(a_complete[4 * i + 2] == 1'b1) ? 2'b01 :
(a_complete[4 * i + 1] == 1'b1) ? 2'b10 : 2'b11;
end
end
endgenerate
generate
begin : level_generation_begin
genvar i;
for (i = 1; i <= nr_levels - 1; i = i + 1)
begin : level_generation
//begin : v_levels_begin
genvar j;
for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
begin : v_levels
assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
end
//end
//begin : p_levels_begin
// genvar j;
for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
begin : p_levels
assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
end
//end
end
end
endgenerate
generate
if (PIPELINE != 0)
begin : pipeline_stages
//begin : INSERTION_begin
genvar i;
for (i = 0; i <= nr_levels - 2; i = i + 1)
begin : INSERTION
if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
begin : INS
d_ff #(max_pow_2) P_Di(.clk(clk), .rst(rst), .d(p_d[i]), .q(p_q[i]));
d_ff #(max_pow_2) V_Di(.clk(clk), .rst(rst), .d(v_d[i]), .q(v_q[i]));
end
if ((i + 1) % nr_levels/(PIPELINE + 1) != 0)
begin : NO_INS
assign p_q[i] = p_d[i];
assign v_q[i] = v_d[i];
end
end
//end
assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
end
endgenerate
generate
if (PIPELINE == 0)
begin : no_pipeline
//begin : xhdl4
genvar i;
for (i = 0; i <= nr_levels - 1; i = i + 1)
begin : NO_INSERTION
assign p_q[i] = p_d[i];
assign v_q[i] = v_d[i];
end
//end
end
endgenerate
assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
generate
begin : lz_ovf_begin
genvar i;
for (i = 0; i <= size_lz - 1; i = i + 1)
begin : lz_ovf
assign lz[i] = lzc[i] & ((~ovf));
end
end
endgenerate
endmodule
/trunk/DualPathFPAdder/special_cases.v
0,0 → 1,57
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:56:11 10/07/2013
// Design Name:
// Module Name: special_cases_mul_acc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module special_cases #( parameter size_exception_field = 2'd2,
parameter [size_exception_field - 1 : 0] zero = 0, //00
parameter [size_exception_field - 1 : 0] normal_number= 1, //01
parameter [size_exception_field - 1 : 0] infinity = 2, //10
parameter [size_exception_field - 1 : 0] NaN = 3) //11
( input [size_exception_field - 1 : 0] sp_case_a_number,
input [size_exception_field - 1 : 0] sp_case_b_number,
output reg [size_exception_field - 1 : 0] sp_case_result_o);
always
@(*)
begin
case ({sp_case_a_number, sp_case_b_number})
{zero, zero}: sp_case_result_o = zero;
{zero, normal_number}: sp_case_result_o = normal_number;
{zero, infinity}: sp_case_result_o = infinity;
{zero, NaN}: sp_case_result_o = NaN;
{normal_number,zero}: sp_case_result_o = normal_number;
{normal_number,normal_number}: sp_case_result_o = normal_number;
{normal_number,infinity}: sp_case_result_o = infinity;
{normal_number,NaN}: sp_case_result_o = NaN;
{infinity, zero}: sp_case_result_o = infinity;
{infinity, normal_number}: sp_case_result_o = infinity;
{infinity, infinity}: sp_case_result_o = infinity;
{infinity, NaN}: sp_case_result_o = NaN;
{NaN, zero}: sp_case_result_o = NaN;
{NaN, normal_number}: sp_case_result_o = NaN;
{NaN, infinity}: sp_case_result_o = NaN;
{NaN, NaN}: sp_case_result_o = NaN;
default: sp_case_result_o = zero;
endcase
end
endmodule
/trunk/DualPathFPAdder/effective_op.v
0,0 → 1,40
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:41:11 11/04/2013
// Design Name:
// Module Name: effective_op
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module effective_op( input a_sign,
input b_sign,
input sub,
output reg eff_op);
always
@(*)
begin
case ({sub,a_sign, b_sign})
3'b000: eff_op = 0;
3'b001: eff_op = 1;
3'b010: eff_op = 1;
3'b011: eff_op = 0;
3'b100: eff_op = 1;
3'b101: eff_op = 0;
3'b110: eff_op = 0;
3'b111: eff_op = 1;
endcase
end
endmodule
/trunk/DualPathFPAdder/d_ff.v
0,0 → 1,37
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:39:58 02/04/2013
// Design Name:
// Module Name: d_ff
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 / File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module d_ff (clk, rst, d, q);
parameter SIZE = 24;
input clk;
input rst;
input [SIZE-1 : 0] d;
output reg [SIZE-1 : 0] q;
always
@(posedge clk, posedge rst)
begin
if (rst)
q <= {SIZE{1'b0}};
else
q <= d;
end
endmodule
/trunk/DualPathFPAdder/ClosePath.v
0,0 → 1,66
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:32:10 11/19/2013
// Design Name:
// Module Name: ClosePath
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ClosePath #( parameter size_in_mantissa = 48, //1.M
parameter size_out_mantissa = 24,
parameter size_exponent = 8,
parameter pipeline = 0,
parameter pipeline_pos = 0, // 8 bits
parameter size_counter = 5, //log2(size_mantissa) + 1 = 5)
parameter double_size_counter = size_counter + 1,
parameter double_size_mantissa = size_in_mantissa + size_in_mantissa)
( input eff_op,
input [size_in_mantissa-1 :0] m_a_number,
input [size_in_mantissa-1 :0] m_b_number,
input [size_exponent - 1 : 0] e_a_number,
input [size_exponent - 1 : 0] e_b_number,
output[size_out_mantissa-1:0] resulted_m_o,
output[size_exponent - 1 : 0] resulted_e_o);
 
wire [size_in_mantissa:0] unnormalized_mantissa;
wire [double_size_counter-1: 0] lzs;
wire [size_out_mantissa + 1 : 0] dummy_bits;
//compute unnormalized_mantissa
assign unnormalized_mantissa = (eff_op)? ((m_a_number > m_b_number)? (m_a_number - m_b_number) : (m_b_number - m_a_number)) :
m_a_number + m_b_number;
//compute leading_zeros over unnormalized mantissa
leading_zeros #( .SIZE_INT(double_size_mantissa + 1'b1), .SIZE_COUNTER(double_size_counter), .PIPELINE(pipeline))
leading_zeros_instance (.a(unnormalized_mantissa),
.ovf(1'b0),
.lz(lzs));
//compute shifting over unnormalized_mantissa
shifter #( .INPUT_SIZE(size_in_mantissa + 1'b1),
.SHIFT_SIZE(double_size_counter),
.OUTPUT_SIZE(size_in_mantissa + 2'd2),
.DIRECTION(1'b1), //0=right, 1=left
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
shifter_instance( .a(unnormalized_mantissa),//mantissa
.arith(1'b0),//logical shift
.shft(lzs),
.shifted_a({resulted_m_o, dummy_bits}));
assign resulted_e_o = (e_a_number > e_b_number)? (e_a_number - lzs + 1) : (e_b_number - lzs + 1);
endmodule
/trunk/DualPathFPAdder/shifter.v
0,0 → 1,112
 
 
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:00:33 10/15/2013
// Design Name:
// Module Name: shifter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shifter #( parameter INPUT_SIZE = 13,
parameter SHIFT_SIZE = 4,
parameter OUTPUT_SIZE = 24, //>INPUT_SIZE
parameter DIRECTION = 1,
parameter PIPELINE = 1,
parameter [7:0] POSITION = 8'b00000000)
(a, arith, shft, shifted_a);
input [INPUT_SIZE-1:0] a;
input arith;
input [SHIFT_SIZE-1:0] shft;
output [OUTPUT_SIZE-1:0] shifted_a;
wire [OUTPUT_SIZE-1:0] a_temp_d[SHIFT_SIZE:0];
wire [OUTPUT_SIZE-1:0] a_temp_q[SHIFT_SIZE:0];
assign a_temp_q[0][OUTPUT_SIZE-1 : OUTPUT_SIZE-INPUT_SIZE] = a;
assign a_temp_q[0][OUTPUT_SIZE-1-INPUT_SIZE : 0] = arith;
generate
begin : GENERATING
genvar i;
for (i = 0; i <= SHIFT_SIZE - 1; i = i + 1)
begin : BARREL_SHIFTER_GENERATION
if (DIRECTION == 1)
begin : LEFT
//begin : 1st_check
genvar j;
for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
begin : MUX_GEN_L
if (j < 2 ** i)
begin : ZERO_INS_L
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
end
if (j >= 2 ** i)
begin : BIT_INS_L
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j-2**i];
end
end
//end
end
if (DIRECTION == 0)
begin : RIGHT
//begin : 2nd_check
genvar j;
for (j = 0; j <= OUTPUT_SIZE - 1; j = j + 1)
begin : MUX_GEN_R
if (OUTPUT_SIZE - 1 < 2 ** i + j)
begin : ZERO_INS_R
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : arith;
end
if (OUTPUT_SIZE - 1 >= 2 ** i + j)
begin : BIT_INS_R
assign a_temp_d[i][j] = (shft[i] == 1'b0) ? a_temp_q[i][j] : a_temp_q[i][j+2**i];
end
end
//end
end
if (PIPELINE != 0)
begin : PIPELINE_INSERTION
if (POSITION[i] == 1'b1)
begin : LATCH
d_ff #(OUTPUT_SIZE) D_INS(.clk(clk), .rst(rst), .d(a_temp_d[i]), .q(a_temp_q[i + 1]));
end
if (POSITION[i] == 1'b0)
begin : NO_LATCH
assign a_temp_q[i + 1] = a_temp_d[i];
end
end
if (PIPELINE == 0)
begin : NO_PIPELINE
assign a_temp_q[i + 1] = a_temp_d[i];
end
end
end
endgenerate
assign shifted_a = a_temp_q[SHIFT_SIZE];
endmodule
 
/trunk/DualPathFPAdder/rounding.v
0,0 → 1,35
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:09:49 11/04/2013
// Design Name:
// Module Name: rounding
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
 
module rounding #( parameter SIZE_MOST_S_MANTISSA = 24,
parameter SIZE_LEAST_S_MANTISSA= 25)
( input [SIZE_MOST_S_MANTISSA - 1 : 0] unrounded_mantissa,
input [SIZE_LEAST_S_MANTISSA- 1 : 0] dummy_bits,
output[SIZE_MOST_S_MANTISSA - 1 : 0] rounded_mantissa);
wire g, sticky, round_dec;
assign g = dummy_bits[SIZE_LEAST_S_MANTISSA - 1];
assign sticky = |(dummy_bits[SIZE_LEAST_S_MANTISSA - 2 : 0]);
assign round_dec = g & (unrounded_mantissa[0] | sticky);
assign rounded_mantissa = unrounded_mantissa + round_dec;
endmodule
/trunk/DualPathFPAdder/leading_zeros.v
0,0 → 1,139
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:50:09 10/17/2013
// Design Name:
// Module Name: leading_zeros
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module leading_zeros #( parameter SIZE_INT = 24, //mantissa bits
parameter SIZE_COUNTER = 5, //log2(size_mantissa) + 1 = 5)
parameter PIPELINE = 2)
(a, ovf, lz);
input [SIZE_INT-1:0] a;
input ovf;
output [SIZE_COUNTER-1:0] lz;
parameter nr_levels = SIZE_COUNTER - 1;
parameter max_pow_2 = 2 ** SIZE_COUNTER;
parameter size_lz = SIZE_COUNTER;
wire [max_pow_2-1:0] a_complete;
wire [max_pow_2-1:0] v_d[nr_levels-1:0];
wire [max_pow_2-1:0] v_q[nr_levels-1:0];
wire [max_pow_2-1:0] p_d[nr_levels-1:0];
wire [max_pow_2-1:0] p_q[nr_levels-1:0];
wire [size_lz-1:0] lzc;
assign a_complete[max_pow_2 - 1 : max_pow_2 - 1 - SIZE_INT + 1] = a;
generate
if (max_pow_2 != SIZE_INT)
begin : gen_if
assign a_complete[max_pow_2 - 1 - SIZE_INT : 0] = 0;
end
endgenerate
generate
begin : level_0
genvar i;
for (i = max_pow_2/4 - 1; i >= 0; i = i - 1)
begin : level_0
assign v_d[0][i] = (a_complete[4 * i + 3 : 4 * i] == 4'b0000) ? 1'b0 : 1'b1;
assign p_d[0][2*i+1:2*i] = (a_complete[4 * i + 3] == 1'b1) ? 2'b00 :
(a_complete[4 * i + 2] == 1'b1) ? 2'b01 :
(a_complete[4 * i + 1] == 1'b1) ? 2'b10 : 2'b11;
end
end
endgenerate
generate
begin : level_generation_begin
genvar i;
for (i = 1; i <= nr_levels - 1; i = i + 1)
begin : level_generation
//begin : v_levels_begin
genvar j;
for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
begin : v_levels
assign v_d[i][j] = v_q[i - 1][2*j+1] | v_q[i - 1][2*j];
end
//end
//begin : p_levels_begin
// genvar j;
for (j = 0; j <= max_pow_2/(2 ** (i + 2)) - 1; j = j + 1)
begin : p_levels
assign p_d[i][(i+2)*j+i+1] = (~(v_q[i - 1][2*j+1]));
assign p_d[i][(i+2)*j+i : (i+2)*j] = (v_q[i - 1][2*j+1] == 1'b1) ? p_q[i - 1][j*(2*i+2)+2*i+1 : j*(2*i+2) + i + 1] : p_q[i - 1][j*(2*i+2)+i : j*(2*i+2)];
end
//end
end
end
endgenerate
generate
if (PIPELINE != 0)
begin : pipeline_stages
//begin : INSERTION_begin
genvar i;
for (i = 0; i <= nr_levels - 2; i = i + 1)
begin : INSERTION
if ((i + 1) % nr_levels/(PIPELINE + 1) == 0)
begin : INS
d_ff #(max_pow_2) P_Di(.clk(clk), .rst(rst), .d(p_d[i]), .q(p_q[i]));
d_ff #(max_pow_2) V_Di(.clk(clk), .rst(rst), .d(v_d[i]), .q(v_q[i]));
end
if ((i + 1) % nr_levels/(PIPELINE + 1) != 0)
begin : NO_INS
assign p_q[i] = p_d[i];
assign v_q[i] = v_d[i];
end
end
//end
assign p_q[nr_levels - 1] = p_d[nr_levels - 1];
assign v_q[nr_levels - 1] = v_d[nr_levels - 1];
end
endgenerate
generate
if (PIPELINE == 0)
begin : no_pipeline
//begin : xhdl4
genvar i;
for (i = 0; i <= nr_levels - 1; i = i + 1)
begin : NO_INSERTION
assign p_q[i] = p_d[i];
assign v_q[i] = v_d[i];
end
//end
end
endgenerate
assign lzc[size_lz - 1:0] = p_q[nr_levels - 1][size_lz - 1:0];
generate
begin : lz_ovf_begin
genvar i;
for (i = 0; i <= size_lz - 1; i = i + 1)
begin : lz_ovf
assign lz[i] = lzc[i] & ((~ovf));
end
end
endgenerate
endmodule
/trunk/DualPathFPAdder/FarPath.v
0,0 → 1,72
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:31:57 11/19/2013
// Design Name:
// Module Name: FarPath
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FarPath #( parameter size_in_mantissa = 24, //1.M
parameter size_out_mantissa = 24,
parameter size_exponent = 8,
parameter pipeline = 0,
parameter pipeline_pos = 0, // 8 bits
parameter size_counter = 5, //log2(size_mantissa) + 1 = 5)
parameter double_size_counter = size_counter + 1,
parameter double_size_mantissa = size_in_mantissa + size_in_mantissa)
( input eff_op,
input [size_in_mantissa-1 :0] m_a_number,
input [size_in_mantissa-1 :0] m_b_number,
input [size_exponent - 1 : 0] e_a_number,
input [size_exponent - 1 : 0] e_b_number,
output[size_out_mantissa-1:0] resulted_m_o,
output[size_exponent - 1 : 0] resulted_e_o);
 
wire [double_size_mantissa:0] unnormalized_mantissa;
wire [7:0] adjust_mantissa;
wire [double_size_mantissa:0] normalized_mantissa;
wire dummy_bit;
//compute unnormalized_mantissa
assign unnormalized_mantissa = (eff_op)? ((m_a_number > m_b_number)? (m_a_number - m_b_number) : (m_b_number - m_a_number)) :
m_a_number + m_b_number;
assign adjust_mantissa = unnormalized_mantissa[double_size_mantissa]? 8'd0 :
unnormalized_mantissa[double_size_mantissa-1]? 2'd1 : 8'd2;
//compute shifting over unnormalized_mantissa
shifter #( .INPUT_SIZE(double_size_mantissa+1),
.SHIFT_SIZE(size_exponent),
.OUTPUT_SIZE(double_size_mantissa+2),
.DIRECTION(1'b1),
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
unnormalized_no_shifter_instance(.a(unnormalized_mantissa),
.arith(1'b0),
.shft(adjust_mantissa),
.shifted_a({normalized_mantissa, dummy_bit}));
//instantiate rounding_component
rounding #( .SIZE_MOST_S_MANTISSA(size_out_mantissa),
.SIZE_LEAST_S_MANTISSA(size_out_mantissa + 2'd1))
rounding_instance( .unrounded_mantissa(normalized_mantissa[double_size_mantissa : double_size_mantissa - size_out_mantissa + 1]),
.dummy_bits(normalized_mantissa[double_size_mantissa - size_out_mantissa: 0]),
.rounded_mantissa(resulted_m_o));
assign resulted_e_o = (e_a_number > e_b_number)? (e_a_number + 1 - adjust_mantissa):(e_b_number + 1 - adjust_mantissa);
endmodule
/trunk/DualPathFPAdder/DualPathFPAdder.v
0,0 → 1,146
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:31:28 11/19/2013
// Design Name:
// Module Name: DualPathFPAdder
// Project Name:
// Target Devices:
// Tool versions:
 
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DualPathFPAdder #( parameter size_mantissa = 24, //1.M
parameter size_exponent = 8,
parameter size_exception_field = 2,
parameter size_counter = 5, //log2(size_mantissa) + 1 = 5)
parameter [size_exception_field - 1 : 0] zero = 0, //00
parameter [size_exception_field - 1 : 0] normal_number= 1, //01
parameter [size_exception_field - 1 : 0] infinity = 2, //10
parameter [size_exception_field - 1 : 0] NaN = 3, //11
parameter pipeline = 0,
parameter pipeline_pos = 0, // 8 bits
parameter double_size_mantissa = size_mantissa + size_mantissa,
parameter double_size_counter = size_counter + 1,
parameter size = size_mantissa + size_exponent + size_exception_field)
(sub, a_number_i, b_number_i, resulted_number_o);
input sub;
input [size - 1 : 0] a_number_i;
input [size - 1 : 0] b_number_i;
output[size - 1 : 0] resulted_number_o;
 
wire [size_mantissa - 1 : 0] m_a_number, m_b_number;
wire [size_exponent - 1 : 0] e_a_number, e_b_number;
wire s_a_number, s_b_number;
wire [size_exception_field - 1 : 0] sp_case_a_number, sp_case_b_number;
 
wire [size_exponent - 1 : 0] exp_difference;
wire [size_exponent - 1 : 0] modify_exp_a, modify_exp_b;
wire [double_size_mantissa - 1 : 0] shifted_m_a, shifted_m_b;
wire [size_mantissa-1 : 0] fp_resulted_m_o, cp_resulted_m_o;
wire [size_exponent-1 : 0] fp_resulted_e_o, cp_resulted_e_o;
wire resulted_sign;
wire [size_exception_field - 1 : 0] resulted_exception_field;
 
assign m_a_number = {1'b1, a_number_i[size_mantissa - 2 :0]};
assign m_b_number = {1'b1, b_number_i[size_mantissa - 2 :0]};
assign e_a_number = a_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
assign e_b_number = b_number_i[size_mantissa + size_exponent - 1 : size_mantissa - 1];
assign s_a_number = a_number_i[size - size_exception_field - 1];
assign s_b_number = b_number_i[size - size_exception_field - 1];
assign sp_case_a_number = a_number_i[size - 1 : size - size_exception_field];
assign sp_case_b_number = b_number_i[size - 1 : size - size_exception_field];
 
//find the difference between exponents
assign exp_difference = (e_a_number > e_b_number)? (e_a_number - e_b_number) : (e_b_number - e_a_number);
assign {modify_exp_a, modify_exp_b} = (e_a_number > e_b_number)? {8'd0, exp_difference} : {exp_difference, 8'd0};
//shift the right mantissa
shifter #( .INPUT_SIZE(size_mantissa),
.SHIFT_SIZE(size_exponent),
.OUTPUT_SIZE(double_size_mantissa),
.DIRECTION(1'b0),
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
m_a_shifter_instance( .a(m_a_number),
.arith(1'b0),
.shft(modify_exp_a),
.shifted_a(shifted_m_a));
shifter #( .INPUT_SIZE(size_mantissa),
.SHIFT_SIZE(size_exponent),
.OUTPUT_SIZE(double_size_mantissa),
.DIRECTION(1'b0),
.PIPELINE(pipeline),
.POSITION(pipeline_pos))
m_b_shifter_instance( .a(m_b_number),
.arith(1'b0),
.shft(modify_exp_b),
.shifted_a(shifted_m_b));
//istantiate effective_operation_component
effective_op effective_op_instance( .a_sign(s_a_number), .b_sign(s_b_number), .sub(sub), .eff_op(eff_op));
 
 
//instantiate special_cases component
special_cases #( .size_exception_field(size_exception_field),
.zero(zero),
.normal_number(normal_number),
.infinity(infinity),
.NaN(NaN))
special_cases_instance ( .sp_case_a_number(sp_case_a_number),
.sp_case_b_number(sp_case_b_number),
.sp_case_result_o(resulted_exception_field));
//instantiate FarPath component
FarPath #( .size_in_mantissa(double_size_mantissa),
.size_out_mantissa(size_mantissa),
.size_exponent(size_exponent),
.pipeline(pipeline),
.pipeline_pos(pipeline_pos),
.size_counter(size_counter),
.double_size_counter(double_size_counter),
.double_size_mantissa(double_size_mantissa))
FarPath_instance ( .eff_op(eff_op),
.m_a_number(shifted_m_a),
.m_b_number(shifted_m_b),
.e_a_number(e_a_number),
.e_b_number(e_b_number),
.resulted_m_o(fp_resulted_m_o),
.resulted_e_o(fp_resulted_e_o));
 
//instantiate ClosePath component
ClosePath #(.size_in_mantissa(double_size_mantissa),
.size_out_mantissa(size_mantissa),
.size_exponent(size_exponent),
.pipeline(pipeline),
.pipeline_pos(pipeline_pos),
.size_counter(size_counter),
.double_size_counter(double_size_counter),
.double_size_mantissa(double_size_mantissa))
ClosePath_instance( .eff_op(eff_op),
.m_a_number(shifted_m_a),
.m_b_number(shifted_m_b),
.e_a_number(e_a_number),
.e_b_number(e_b_number),
.resulted_m_o(cp_resulted_m_o),
.resulted_e_o(cp_resulted_e_o));
assign resulted_sign = (eff_op)? ((shifted_m_a > shifted_m_b)? s_a_number : ~s_a_number) : s_a_number;
assign resulted_number_o = (exp_difference > 1)? {resulted_exception_field, resulted_sign, fp_resulted_e_o, fp_resulted_m_o[size_mantissa-2 : 0]}:
{resulted_exception_field, resulted_sign, cp_resulted_e_o, cp_resulted_m_o[size_mantissa-2 : 0]};
endmodule

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