URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
Subversion Repositories xucpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/xucpu
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/trunk/src/components/BRAM/ram_parts.vhdl
56,6 → 56,23
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END COMPONENT RAM32K; |
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COMPONENT generic_memory_block IS |
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GENERIC ( |
init_data : cstr_array_type; |
w_data : NATURAL RANGE 1 TO 32 := 16; |
w_addr : NATURAL RANGE 8 TO 14 := 10); |
PORT ( |
clk : IN STD_LOGIC; |
we : IN STD_LOGIC; |
a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address |
a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address |
d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input |
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output |
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output |
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END COMPONENT generic_memory_block; |
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END PACKAGE ram_parts; |
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LIBRARY ieee; |
127,6 → 144,7
USE ieee.numeric_std.ALL; |
USE work.mux_parts.ALL; |
USE work.hexio.ALL; |
USE work.ram_parts.all; |
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ENTITY RAM32K IS |
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150,23 → 168,6
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ARCHITECTURE Structural OF RAM32K IS |
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COMPONENT generic_memory_block IS |
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GENERIC ( |
init_data : cstr_array_type; |
w_data : NATURAL RANGE 1 TO 32 := 16; |
w_addr : NATURAL RANGE 8 TO 14 := 10); |
PORT ( |
clk : IN STD_LOGIC; |
we : IN STD_LOGIC; |
a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address |
a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address |
d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input |
q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output |
q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output |
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END COMPONENT generic_memory_block; |
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SIGNAL memory_array : B32K_array_type; |
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SIGNAL data_address : STD_LOGIC_VECTOR(12 DOWNTO 0); |
/trunk/src/components/BRAM/Makefile
1,6 → 1,14
GHDL:=/opt/ghdl/ghdl_mcode/translate/ghdldrv/ghdl_mcode |
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SOURCE:= ../../util/file/hexio.vhdl \ |
../../components/multiplexer/MUX.vhdl \ |
generic_memory_block.vhdl \ |
ram_parts.vhdl \ |
RAM.vhdl \ |
tb_generic_ram.vhdl |
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tb_generic: |
ghdl -a ../../util/file/hexio.vhdl ../../components/multiplexer/MUX.vhdl ram_parts.vhdl tb_generic_ram.vhdl |
ghdl -e tb_generic_ram |
$(GHDL) -a $(SOURCE) |
$(GHDL) -e tb_generic_ram |
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# vim: set tw=0: |
# vim: set tw=0: |