OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

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Rev 28 → Rev 29

/trunk/src/system/system_8k.vhdl
0,0 → 1,351
 
--
-- This file is part of the Experimental Unstable CPU System.
--
-- The Experimental Unstable CPU System Is free software: you can redistribute
-- it and/or modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- The Experimental Unstable CPU System is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
-- General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.components.ALL;
USE work.RAM.ALL;
USE work.mux_parts.ALL;
USE work.controllers.ALL;
 
-- LIBRARY unisim;
-- USE unisim.vcomponents.ALL;
 
ENTITY system IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
led_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
switch_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pushb_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
END system;
 
ARCHITECTURE Structural OF system IS
 
CONSTANT w_data : POSITIVE := 16;
CONSTANT w_addr : POSITIVE := 13;
 
SIGNAL CLK : STD_LOGIC; -- System clock
SIGNAL CLK_VAL : STD_LOGIC; -- System clock valid
SIGNAL RST : STD_LOGIC; -- System synchronous reset
 
-- All signals for the instruction and data processing
-- Ordered in proper bundles per pipeline stage
 
-- FiRST stage in the instruction pipeline is the program counter circuitry
SIGNAL PC_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL LD_PC : STD_LOGIC := '0';
SIGNAL PC_INC : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_NEXT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
 
-- The second stage in the instruction pipeline is the memory, followed by
-- the instruction queue.
SIGNAL LD_IR : STD_LOGIC := '0';
SIGNAL LD_DP : STD_LOGIC := '0';
SIGNAL LD_REG : STD_LOGIC := '0';
 
SIGNAL RFA_A : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL RFA_B : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL ALU_OP : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
 
SIGNAL REG_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
SIGNAL DATABUS_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL DATABUS_READ : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL REG_WR : STD_LOGIC := '1';
SIGNAL REG_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL A_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL B_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL LD_MAR : STD_LOGIC;
SIGNAL LD_MDR : STD_LOGIC;
 
SIGNAL QA : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL QB : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DATA_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL DATABUS_WRITE : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DOSEL : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL EOUT1 : STD_LOGIC;
SIGNAL EIN1 : STD_LOGIC;
SIGNAL EIN2 : STD_LOGIC;
 
SIGNAL MEM_WR : STD_LOGIC := '1';
SIGNAL PC_OUT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_TO_REG : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DO1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO2 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO3 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL MEMO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL IMMED : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL I_ZERO : STD_LOGIC;
SIGNAL ZERO : STD_LOGIC;
SIGNAL INT : STD_LOGIC;
 
BEGIN
 
 
-- Clock generator with selectable speed and reset
--CLOCK1 : clock_gen
-- PORT MAP (
-- CLK_IN => CLOCK,
-- RESET => RESET,
-- CLK_VALID => CLK_VAL,
-- CLK_OUT => CLK);
 
-- Synchronous reset
--RST1 : sync_reset
-- PORT MAP (
-- ASYNC_RST => RESET,
-- CLK => CLK,
-- CLK_VALID => CLK_VAL,
-- RST => RST);
 
CLK <= CLOCK;
RST <= RESET;
 
PC_TO_REG <= '0' & PC_OUT;
 
-- Input multiplexer to register file
REG_MUX : mux8to1
PORT MAP (
SEL => REG_SRC,
S0 => ALU_OUT, -- "000"
S1 => DATABUS_READ, -- "001"
S2 => IMMED, -- "010"
S3 => PC_TO_REG, -- "011"
S4 => A_OUT, -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
Y => REG_BUS);
 
-- True if A output of register file is zero
Z1 : zerof
PORT MAP (
A => A_OUT,
zero => I_ZERO);
 
PROCESS(CLK)
BEGIN
IF rising_edge(CLK) THEN
ZERO <= I_ZERO;
END IF;
END PROCESS;
 
-- 16-register register file
RF1 : regf
PORT MAP (
CLK => CLK,
we => REG_WR,
a1 => RFA_A,
a2 => RFA_B,
d => REG_BUS,
q1 => A_OUT,
q2 => B_OUT);
 
-- Memory address register from B output
MAR : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MAR,
D => B_OUT(14 DOWNTO 0),
Q => DATA_ADDRESS);
 
-- Memory data register from A output
MDR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MDR,
D => A_OUT,
Q => DATABUS_WRITE);
 
-- 16 function A output
ALU1 : alu
PORT MAP (
clk => CLK,
op => ALU_OP,
A => A_OUT,
B => B_OUT,
Y => ALU_OUT);
 
-- Multiplexer for program counter input
PC_MUX : mux8to1
GENERIC MAP (
w_data => 15)
PORT MAP (
SEL => PC_SRC,
S0 => A_OUT(14 DOWNTO 0), -- "000"
S1 => PC_INC, -- "001"
S2 => IMMED(14 DOWNTO 0), -- "010"
S3 => PC_OUT, -- "011"
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#7FF0#, 15)), -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "101"
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "110"
S7 => INSO4(14 DOWNTO 0), -- "111"
Y => PC_NEXT);
 
-- Program counter
PC : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_PC,
D => PC_NEXT,
Q => PC_OUT);
 
-- Incrementer for program counter
PC_INC1 : incr
GENERIC MAP (
w_data => 15)
PORT MAP (
A => PC_OUT,
Y => PC_INC);
 
CTRL1 : uctrl
PORT MAP (
CLK => CLK,
RST => RST,
PC_SRC => PC_SRC,
LD_PC => LD_PC,
LD_IR => LD_IR,
LD_DP => LD_DP,
REG_SRC => REG_SRC,
RFA_A => RFA_A,
RFA_B => RFA_B,
REG_WR => REG_WR,
LD_MAR => LD_MAR,
LD_MDR => LD_MDR,
MEM_WR => MEM_WR,
ALU_OP => ALU_OP,
INT => INT,
ZERO => ZERO,
IR_IN => INSTR);
 
-- Decoder for IO
IO_DEC : decoder
PORT MAP (
clk => CLK,
ena => LD_MAR,
a1 => B_OUT(14 DOWNTO 0),
gpio_1 => EOUT1,
gpio_2 => EIN1,
gpio_3 => EIN2,
bus_sel => DOSEL);
 
-- Simple output register for LED output port
OUT1 : gpio_out
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EOUT1,
we => MEM_WR,
D => DATABUS_WRITE,
Q => DO1,
port_out => led_out);
 
-- Simple input register for switches
IN1 : gpio_in
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN1,
Q => DO2,
port_in => switch_in);
 
-- Simple input register for push buttons
IN2 : gpio_in
GENERIC MAP (
w_port => 5)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN2,
Q => DO3,
port_in => pushb_in);
 
-- 32kx16 two port RAM
MEM1 : memory
GENERIC MAP (
w_data => w_data,
w_addr => w_addr,
filename => "")
PORT MAP (
CLK => CLK,
we => MEM_WR,
a1 => B_OUT(w_addr - 1 DOWNTO 0),
a2 => PC_NEXT(w_addr - 1 DOWNTO 0),
d1 => A_OUT,
q1 => MEMO4, -- Data memory output
q2 => INSO4); -- Instruction memory output
 
IR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_IR,
D => INSO4,
Q => INSTR);
 
DR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_DP,
D => INSO4,
Q => IMMED);
 
-- RAM/input device READ multiplexer
BUS_MUX : mux8to1
PORT MAP (
SEL => DOSEL,
S0 => DO1,
S1 => DO2,
S2 => DO3,
S3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => MEMO4,
Y => DATABUS_OUT);
 
BUSR : data_reg_2 PORT MAP (
CLK => CLK,
D => DATABUS_OUT,
Q => DATABUS_READ);
 
END Structural;
/trunk/src/system/system_16k.vhdl
0,0 → 1,351
 
--
-- This file is part of the Experimental Unstable CPU System.
--
-- The Experimental Unstable CPU System Is free software: you can redistribute
-- it and/or modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- The Experimental Unstable CPU System is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
-- General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.components.ALL;
USE work.RAM.ALL;
USE work.mux_parts.ALL;
USE work.controllers.ALL;
 
-- LIBRARY unisim;
-- USE unisim.vcomponents.ALL;
 
ENTITY system IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
led_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
switch_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pushb_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
END system;
 
ARCHITECTURE Structural OF system IS
 
CONSTANT w_data : POSITIVE := 16;
CONSTANT w_addr : POSITIVE := 14;
 
SIGNAL CLK : STD_LOGIC; -- System clock
SIGNAL CLK_VAL : STD_LOGIC; -- System clock valid
SIGNAL RST : STD_LOGIC; -- System synchronous reset
 
-- All signals for the instruction and data processing
-- Ordered in proper bundles per pipeline stage
 
-- FiRST stage in the instruction pipeline is the program counter circuitry
SIGNAL PC_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL LD_PC : STD_LOGIC := '0';
SIGNAL PC_INC : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_NEXT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
 
-- The second stage in the instruction pipeline is the memory, followed by
-- the instruction queue.
SIGNAL LD_IR : STD_LOGIC := '0';
SIGNAL LD_DP : STD_LOGIC := '0';
SIGNAL LD_REG : STD_LOGIC := '0';
 
SIGNAL RFA_A : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL RFA_B : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL ALU_OP : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
 
SIGNAL REG_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
SIGNAL DATABUS_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL DATABUS_READ : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL REG_WR : STD_LOGIC := '1';
SIGNAL REG_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL A_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL B_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL LD_MAR : STD_LOGIC;
SIGNAL LD_MDR : STD_LOGIC;
 
SIGNAL QA : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL QB : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DATA_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL DATABUS_WRITE : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DOSEL : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL EOUT1 : STD_LOGIC;
SIGNAL EIN1 : STD_LOGIC;
SIGNAL EIN2 : STD_LOGIC;
 
SIGNAL MEM_WR : STD_LOGIC := '1';
SIGNAL PC_OUT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_TO_REG : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DO1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO2 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO3 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL MEMO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL IMMED : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL I_ZERO : STD_LOGIC;
SIGNAL ZERO : STD_LOGIC;
SIGNAL INT : STD_LOGIC;
 
BEGIN
 
 
-- Clock generator with selectable speed and reset
--CLOCK1 : clock_gen
-- PORT MAP (
-- CLK_IN => CLOCK,
-- RESET => RESET,
-- CLK_VALID => CLK_VAL,
-- CLK_OUT => CLK);
 
-- Synchronous reset
--RST1 : sync_reset
-- PORT MAP (
-- ASYNC_RST => RESET,
-- CLK => CLK,
-- CLK_VALID => CLK_VAL,
-- RST => RST);
 
CLK <= CLOCK;
RST <= RESET;
 
PC_TO_REG <= '0' & PC_OUT;
 
-- Input multiplexer to register file
REG_MUX : mux8to1
PORT MAP (
SEL => REG_SRC,
S0 => ALU_OUT, -- "000"
S1 => DATABUS_READ, -- "001"
S2 => IMMED, -- "010"
S3 => PC_TO_REG, -- "011"
S4 => A_OUT, -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
Y => REG_BUS);
 
-- True if A output of register file is zero
Z1 : zerof
PORT MAP (
A => A_OUT,
zero => I_ZERO);
 
PROCESS(CLK)
BEGIN
IF rising_edge(CLK) THEN
ZERO <= I_ZERO;
END IF;
END PROCESS;
 
-- 16-register register file
RF1 : regf
PORT MAP (
CLK => CLK,
we => REG_WR,
a1 => RFA_A,
a2 => RFA_B,
d => REG_BUS,
q1 => A_OUT,
q2 => B_OUT);
 
-- Memory address register from B output
MAR : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MAR,
D => B_OUT(14 DOWNTO 0),
Q => DATA_ADDRESS);
 
-- Memory data register from A output
MDR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MDR,
D => A_OUT,
Q => DATABUS_WRITE);
 
-- 16 function A output
ALU1 : alu
PORT MAP (
clk => CLK,
op => ALU_OP,
A => A_OUT,
B => B_OUT,
Y => ALU_OUT);
 
-- Multiplexer for program counter input
PC_MUX : mux8to1
GENERIC MAP (
w_data => 15)
PORT MAP (
SEL => PC_SRC,
S0 => A_OUT(14 DOWNTO 0), -- "000"
S1 => PC_INC, -- "001"
S2 => IMMED(14 DOWNTO 0), -- "010"
S3 => PC_OUT, -- "011"
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#7FF0#, 15)), -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "101"
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "110"
S7 => INSO4(14 DOWNTO 0), -- "111"
Y => PC_NEXT);
 
-- Program counter
PC : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_PC,
D => PC_NEXT,
Q => PC_OUT);
 
-- Incrementer for program counter
PC_INC1 : incr
GENERIC MAP (
w_data => 15)
PORT MAP (
A => PC_OUT,
Y => PC_INC);
 
CTRL1 : uctrl
PORT MAP (
CLK => CLK,
RST => RST,
PC_SRC => PC_SRC,
LD_PC => LD_PC,
LD_IR => LD_IR,
LD_DP => LD_DP,
REG_SRC => REG_SRC,
RFA_A => RFA_A,
RFA_B => RFA_B,
REG_WR => REG_WR,
LD_MAR => LD_MAR,
LD_MDR => LD_MDR,
MEM_WR => MEM_WR,
ALU_OP => ALU_OP,
INT => INT,
ZERO => ZERO,
IR_IN => INSTR);
 
-- Decoder for IO
IO_DEC : decoder
PORT MAP (
clk => CLK,
ena => LD_MAR,
a1 => B_OUT(14 DOWNTO 0),
gpio_1 => EOUT1,
gpio_2 => EIN1,
gpio_3 => EIN2,
bus_sel => DOSEL);
 
-- Simple output register for LED output port
OUT1 : gpio_out
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EOUT1,
we => MEM_WR,
D => DATABUS_WRITE,
Q => DO1,
port_out => led_out);
 
-- Simple input register for switches
IN1 : gpio_in
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN1,
Q => DO2,
port_in => switch_in);
 
-- Simple input register for push buttons
IN2 : gpio_in
GENERIC MAP (
w_port => 5)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN2,
Q => DO3,
port_in => pushb_in);
 
-- 32kx16 two port RAM
MEM1 : memory
GENERIC MAP (
w_data => w_data,
w_addr => w_addr,
filename => "")
PORT MAP (
CLK => CLK,
we => MEM_WR,
a1 => B_OUT(w_addr - 1 DOWNTO 0),
a2 => PC_NEXT(w_addr - 1 DOWNTO 0),
d1 => A_OUT,
q1 => MEMO4, -- Data memory output
q2 => INSO4); -- Instruction memory output
 
IR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_IR,
D => INSO4,
Q => INSTR);
 
DR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_DP,
D => INSO4,
Q => IMMED);
 
-- RAM/input device READ multiplexer
BUS_MUX : mux8to1
PORT MAP (
SEL => DOSEL,
S0 => DO1,
S1 => DO2,
S2 => DO3,
S3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => MEMO4,
Y => DATABUS_OUT);
 
BUSR : data_reg_2 PORT MAP (
CLK => CLK,
D => DATABUS_OUT,
Q => DATABUS_READ);
 
END Structural;
/trunk/src/system/system_1k.vhdl
0,0 → 1,351
 
--
-- This file is part of the Experimental Unstable CPU System.
--
-- The Experimental Unstable CPU System Is free software: you can redistribute
-- it and/or modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- The Experimental Unstable CPU System is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
-- General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.components.ALL;
USE work.RAM.ALL;
USE work.mux_parts.ALL;
USE work.controllers.ALL;
 
-- LIBRARY unisim;
-- USE unisim.vcomponents.ALL;
 
ENTITY system IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
led_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
switch_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pushb_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
END system;
 
ARCHITECTURE Structural OF system IS
 
CONSTANT w_data : POSITIVE := 16;
CONSTANT w_addr : POSITIVE := 15;
 
SIGNAL CLK : STD_LOGIC; -- System clock
SIGNAL CLK_VAL : STD_LOGIC; -- System clock valid
SIGNAL RST : STD_LOGIC; -- System synchronous reset
 
-- All signals for the instruction and data processing
-- Ordered in proper bundles per pipeline stage
 
-- FiRST stage in the instruction pipeline is the program counter circuitry
SIGNAL PC_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL LD_PC : STD_LOGIC := '0';
SIGNAL PC_INC : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_NEXT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
 
-- The second stage in the instruction pipeline is the memory, followed by
-- the instruction queue.
SIGNAL LD_IR : STD_LOGIC := '0';
SIGNAL LD_DP : STD_LOGIC := '0';
SIGNAL LD_REG : STD_LOGIC := '0';
 
SIGNAL RFA_A : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL RFA_B : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL ALU_OP : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
 
SIGNAL REG_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
SIGNAL DATABUS_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL DATABUS_READ : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL REG_WR : STD_LOGIC := '1';
SIGNAL REG_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL A_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL B_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL LD_MAR : STD_LOGIC;
SIGNAL LD_MDR : STD_LOGIC;
 
SIGNAL QA : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL QB : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DATA_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL DATABUS_WRITE : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DOSEL : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL EOUT1 : STD_LOGIC;
SIGNAL EIN1 : STD_LOGIC;
SIGNAL EIN2 : STD_LOGIC;
 
SIGNAL MEM_WR : STD_LOGIC := '1';
SIGNAL PC_OUT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_TO_REG : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DO1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO2 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO3 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL MEMO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL IMMED : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL I_ZERO : STD_LOGIC;
SIGNAL ZERO : STD_LOGIC;
SIGNAL INT : STD_LOGIC;
 
BEGIN
 
 
-- Clock generator with selectable speed and reset
--CLOCK1 : clock_gen
-- PORT MAP (
-- CLK_IN => CLOCK,
-- RESET => RESET,
-- CLK_VALID => CLK_VAL,
-- CLK_OUT => CLK);
 
-- Synchronous reset
--RST1 : sync_reset
-- PORT MAP (
-- ASYNC_RST => RESET,
-- CLK => CLK,
-- CLK_VALID => CLK_VAL,
-- RST => RST);
 
CLK <= CLOCK;
RST <= RESET;
 
PC_TO_REG <= '0' & PC_OUT;
 
-- Input multiplexer to register file
REG_MUX : mux8to1
PORT MAP (
SEL => REG_SRC,
S0 => ALU_OUT, -- "000"
S1 => DATABUS_READ, -- "001"
S2 => IMMED, -- "010"
S3 => PC_TO_REG, -- "011"
S4 => A_OUT, -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
Y => REG_BUS);
 
-- True if A output of register file is zero
Z1 : zerof
PORT MAP (
A => A_OUT,
zero => I_ZERO);
 
PROCESS(CLK)
BEGIN
IF rising_edge(CLK) THEN
ZERO <= I_ZERO;
END IF;
END PROCESS;
 
-- 16-register register file
RF1 : regf
PORT MAP (
CLK => CLK,
we => REG_WR,
a1 => RFA_A,
a2 => RFA_B,
d => REG_BUS,
q1 => A_OUT,
q2 => B_OUT);
 
-- Memory address register from B output
MAR : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MAR,
D => B_OUT(14 DOWNTO 0),
Q => DATA_ADDRESS);
 
-- Memory data register from A output
MDR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MDR,
D => A_OUT,
Q => DATABUS_WRITE);
 
-- 16 function A output
ALU1 : alu
PORT MAP (
clk => CLK,
op => ALU_OP,
A => A_OUT,
B => B_OUT,
Y => ALU_OUT);
 
-- Multiplexer for program counter input
PC_MUX : mux8to1
GENERIC MAP (
w_data => 15)
PORT MAP (
SEL => PC_SRC,
S0 => A_OUT(14 DOWNTO 0), -- "000"
S1 => PC_INC, -- "001"
S2 => IMMED(14 DOWNTO 0), -- "010"
S3 => PC_OUT, -- "011"
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#7FF0#, 15)), -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "101"
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "110"
S7 => INSO4(14 DOWNTO 0), -- "111"
Y => PC_NEXT);
 
-- Program counter
PC : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_PC,
D => PC_NEXT,
Q => PC_OUT);
 
-- Incrementer for program counter
PC_INC1 : incr
GENERIC MAP (
w_data => 15)
PORT MAP (
A => PC_OUT,
Y => PC_INC);
 
CTRL1 : uctrl
PORT MAP (
CLK => CLK,
RST => RST,
PC_SRC => PC_SRC,
LD_PC => LD_PC,
LD_IR => LD_IR,
LD_DP => LD_DP,
REG_SRC => REG_SRC,
RFA_A => RFA_A,
RFA_B => RFA_B,
REG_WR => REG_WR,
LD_MAR => LD_MAR,
LD_MDR => LD_MDR,
MEM_WR => MEM_WR,
ALU_OP => ALU_OP,
INT => INT,
ZERO => ZERO,
IR_IN => INSTR);
 
-- Decoder for IO
IO_DEC : decoder
PORT MAP (
clk => CLK,
ena => LD_MAR,
a1 => B_OUT(14 DOWNTO 0),
gpio_1 => EOUT1,
gpio_2 => EIN1,
gpio_3 => EIN2,
bus_sel => DOSEL);
 
-- Simple output register for LED output port
OUT1 : gpio_out
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EOUT1,
we => MEM_WR,
D => DATABUS_WRITE,
Q => DO1,
port_out => led_out);
 
-- Simple input register for switches
IN1 : gpio_in
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN1,
Q => DO2,
port_in => switch_in);
 
-- Simple input register for push buttons
IN2 : gpio_in
GENERIC MAP (
w_port => 5)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN2,
Q => DO3,
port_in => pushb_in);
 
-- 32kx16 two port RAM
MEM1 : memory
GENERIC MAP (
w_data => w_data,
w_addr => w_addr,
filename => "")
PORT MAP (
CLK => CLK,
we => MEM_WR,
a1 => B_OUT(w_addr - 1 DOWNTO 0),
a2 => PC_NEXT(w_addr - 1 DOWNTO 0),
d1 => A_OUT,
q1 => MEMO4, -- Data memory output
q2 => INSO4); -- Instruction memory output
 
IR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_IR,
D => INSO4,
Q => INSTR);
 
DR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_DP,
D => INSO4,
Q => IMMED);
 
-- RAM/input device READ multiplexer
BUS_MUX : mux8to1
PORT MAP (
SEL => DOSEL,
S0 => DO1,
S1 => DO2,
S2 => DO3,
S3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => MEMO4,
Y => DATABUS_OUT);
 
BUSR : data_reg_2 PORT MAP (
CLK => CLK,
D => DATABUS_OUT,
Q => DATABUS_READ);
 
END Structural;
/trunk/src/system/system_2k.vhdl
21,7 → 21,7
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.components.ALL;
USE work.ram_parts.ALL;
USE work.RAM.ALL;
USE work.mux_parts.ALL;
USE work.controllers.ALL;
 
40,6 → 40,7
ARCHITECTURE Structural OF system IS
 
CONSTANT w_data : POSITIVE := 16;
CONSTANT w_addr : POSITIVE := 11;
 
SIGNAL CLK : STD_LOGIC; -- System clock
SIGNAL CLK_VAL : STD_LOGIC; -- System clock valid
65,7 → 66,7
SIGNAL ALU_OP : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
 
SIGNAL REG_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
SIGNAL DATABUS_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL DATABUS_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL DATABUS_READ : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
74,8 → 75,8
SIGNAL A_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL B_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL LD_MAR : STD_LOGIC;
SIGNAL LD_MDR : STD_LOGIC;
SIGNAL LD_MAR : STD_LOGIC;
SIGNAL LD_MDR : STD_LOGIC;
 
SIGNAL QA : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL QB : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
107,7 → 108,7
 
BEGIN
 
 
-- Clock generator with selectable speed and reset
--CLOCK1 : clock_gen
-- PORT MAP (
215,7 → 216,7
-- Program counter
PC : data_reg
GENERIC MAP (
w_data => 15)
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
233,23 → 234,23
 
CTRL1 : uctrl
PORT MAP (
CLK => CLK,
RST => RST,
PC_SRC => PC_SRC,
LD_PC => LD_PC,
LD_IR => LD_IR,
LD_DP => LD_DP,
REG_SRC => REG_SRC,
RFA_A => RFA_A,
RFA_B => RFA_B,
REG_WR => REG_WR,
LD_MAR => LD_MAR,
LD_MDR => LD_MDR,
MEM_WR => MEM_WR,
ALU_OP => ALU_OP,
INT => INT,
ZERO => ZERO,
IR_IN => INSTR);
CLK => CLK,
RST => RST,
PC_SRC => PC_SRC,
LD_PC => LD_PC,
LD_IR => LD_IR,
LD_DP => LD_DP,
REG_SRC => REG_SRC,
RFA_A => RFA_A,
RFA_B => RFA_B,
REG_WR => REG_WR,
LD_MAR => LD_MAR,
LD_MDR => LD_MDR,
MEM_WR => MEM_WR,
ALU_OP => ALU_OP,
INT => INT,
ZERO => ZERO,
IR_IN => INSTR);
 
-- Decoder for IO
IO_DEC : decoder
297,16 → 298,17
Q => DO3,
port_in => pushb_in);
 
-- 1kx16 two port RAM
MEM1 : generic_ram
-- 32kx16 two port RAM
MEM1 : memory
GENERIC MAP (
filename => "input_data.txt",
w_addr => 11)
w_data => w_data,
w_addr => w_addr,
filename => "")
PORT MAP (
CLK => CLK,
we => MEM_WR,
a1 => B_OUT(10 DOWNTO 0),
a2 => PC_NEXT(10 DOWNTO 0),
a1 => B_OUT(w_addr - 1 DOWNTO 0),
a2 => PC_NEXT(w_addr - 1 DOWNTO 0),
d1 => A_OUT,
q1 => MEMO4, -- Data memory output
q2 => INSO4); -- Instruction memory output
/trunk/src/system/system_4k.vhdl
0,0 → 1,351
 
--
-- This file is part of the Experimental Unstable CPU System.
--
-- The Experimental Unstable CPU System Is free software: you can redistribute
-- it and/or modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
--
-- The Experimental Unstable CPU System is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
-- General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.components.ALL;
USE work.RAM.ALL;
USE work.mux_parts.ALL;
USE work.controllers.ALL;
 
-- LIBRARY unisim;
-- USE unisim.vcomponents.ALL;
 
ENTITY system IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
led_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
switch_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
pushb_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
END system;
 
ARCHITECTURE Structural OF system IS
 
CONSTANT w_data : POSITIVE := 16;
CONSTANT w_addr : POSITIVE := 12;
 
SIGNAL CLK : STD_LOGIC; -- System clock
SIGNAL CLK_VAL : STD_LOGIC; -- System clock valid
SIGNAL RST : STD_LOGIC; -- System synchronous reset
 
-- All signals for the instruction and data processing
-- Ordered in proper bundles per pipeline stage
 
-- FiRST stage in the instruction pipeline is the program counter circuitry
SIGNAL PC_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL LD_PC : STD_LOGIC := '0';
SIGNAL PC_INC : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_NEXT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
 
-- The second stage in the instruction pipeline is the memory, followed by
-- the instruction queue.
SIGNAL LD_IR : STD_LOGIC := '0';
SIGNAL LD_DP : STD_LOGIC := '0';
SIGNAL LD_REG : STD_LOGIC := '0';
 
SIGNAL RFA_A : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL RFA_B : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
SIGNAL ALU_OP : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
 
SIGNAL REG_SRC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
SIGNAL DATABUS_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL DATABUS_READ : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL REG_WR : STD_LOGIC := '1';
SIGNAL REG_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL A_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL B_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL LD_MAR : STD_LOGIC;
SIGNAL LD_MDR : STD_LOGIC;
 
SIGNAL QA : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL QB : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL ALU_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DATA_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL DATABUS_WRITE : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DOSEL : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
SIGNAL EOUT1 : STD_LOGIC;
SIGNAL EIN1 : STD_LOGIC;
SIGNAL EIN2 : STD_LOGIC;
 
SIGNAL MEM_WR : STD_LOGIC := '1';
SIGNAL PC_OUT : STD_LOGIC_VECTOR(14 DOWNTO 0) := "000000000000000";
SIGNAL PC_TO_REG : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL DO1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO2 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL DO3 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL MEMO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSO4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL INSTR : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
SIGNAL IMMED : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0000";
 
SIGNAL I_ZERO : STD_LOGIC;
SIGNAL ZERO : STD_LOGIC;
SIGNAL INT : STD_LOGIC;
 
BEGIN
 
 
-- Clock generator with selectable speed and reset
--CLOCK1 : clock_gen
-- PORT MAP (
-- CLK_IN => CLOCK,
-- RESET => RESET,
-- CLK_VALID => CLK_VAL,
-- CLK_OUT => CLK);
 
-- Synchronous reset
--RST1 : sync_reset
-- PORT MAP (
-- ASYNC_RST => RESET,
-- CLK => CLK,
-- CLK_VALID => CLK_VAL,
-- RST => RST);
 
CLK <= CLOCK;
RST <= RESET;
 
PC_TO_REG <= '0' & PC_OUT;
 
-- Input multiplexer to register file
REG_MUX : mux8to1
PORT MAP (
SEL => REG_SRC,
S0 => ALU_OUT, -- "000"
S1 => DATABUS_READ, -- "001"
S2 => IMMED, -- "010"
S3 => PC_TO_REG, -- "011"
S4 => A_OUT, -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
Y => REG_BUS);
 
-- True if A output of register file is zero
Z1 : zerof
PORT MAP (
A => A_OUT,
zero => I_ZERO);
 
PROCESS(CLK)
BEGIN
IF rising_edge(CLK) THEN
ZERO <= I_ZERO;
END IF;
END PROCESS;
 
-- 16-register register file
RF1 : regf
PORT MAP (
CLK => CLK,
we => REG_WR,
a1 => RFA_A,
a2 => RFA_B,
d => REG_BUS,
q1 => A_OUT,
q2 => B_OUT);
 
-- Memory address register from B output
MAR : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MAR,
D => B_OUT(14 DOWNTO 0),
Q => DATA_ADDRESS);
 
-- Memory data register from A output
MDR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_MDR,
D => A_OUT,
Q => DATABUS_WRITE);
 
-- 16 function A output
ALU1 : alu
PORT MAP (
clk => CLK,
op => ALU_OP,
A => A_OUT,
B => B_OUT,
Y => ALU_OUT);
 
-- Multiplexer for program counter input
PC_MUX : mux8to1
GENERIC MAP (
w_data => 15)
PORT MAP (
SEL => PC_SRC,
S0 => A_OUT(14 DOWNTO 0), -- "000"
S1 => PC_INC, -- "001"
S2 => IMMED(14 DOWNTO 0), -- "010"
S3 => PC_OUT, -- "011"
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#7FF0#, 15)), -- "100"
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "101"
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(16#0000#, 15)), -- "110"
S7 => INSO4(14 DOWNTO 0), -- "111"
Y => PC_NEXT);
 
-- Program counter
PC : data_reg
GENERIC MAP (
w_data => 15)
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_PC,
D => PC_NEXT,
Q => PC_OUT);
 
-- Incrementer for program counter
PC_INC1 : incr
GENERIC MAP (
w_data => 15)
PORT MAP (
A => PC_OUT,
Y => PC_INC);
 
CTRL1 : uctrl
PORT MAP (
CLK => CLK,
RST => RST,
PC_SRC => PC_SRC,
LD_PC => LD_PC,
LD_IR => LD_IR,
LD_DP => LD_DP,
REG_SRC => REG_SRC,
RFA_A => RFA_A,
RFA_B => RFA_B,
REG_WR => REG_WR,
LD_MAR => LD_MAR,
LD_MDR => LD_MDR,
MEM_WR => MEM_WR,
ALU_OP => ALU_OP,
INT => INT,
ZERO => ZERO,
IR_IN => INSTR);
 
-- Decoder for IO
IO_DEC : decoder
PORT MAP (
clk => CLK,
ena => LD_MAR,
a1 => B_OUT(14 DOWNTO 0),
gpio_1 => EOUT1,
gpio_2 => EIN1,
gpio_3 => EIN2,
bus_sel => DOSEL);
 
-- Simple output register for LED output port
OUT1 : gpio_out
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EOUT1,
we => MEM_WR,
D => DATABUS_WRITE,
Q => DO1,
port_out => led_out);
 
-- Simple input register for switches
IN1 : gpio_in
GENERIC MAP (
w_port => 8)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN1,
Q => DO2,
port_in => switch_in);
 
-- Simple input register for push buttons
IN2 : gpio_in
GENERIC MAP (
w_port => 5)
PORT MAP (
RST => RST,
CLK => CLK,
ena => EIN2,
Q => DO3,
port_in => pushb_in);
 
-- 32kx16 two port RAM
MEM1 : memory
GENERIC MAP (
w_data => w_data,
w_addr => w_addr,
filename => "")
PORT MAP (
CLK => CLK,
we => MEM_WR,
a1 => B_OUT(w_addr - 1 DOWNTO 0),
a2 => PC_NEXT(w_addr - 1 DOWNTO 0),
d1 => A_OUT,
q1 => MEMO4, -- Data memory output
q2 => INSO4); -- Instruction memory output
 
IR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_IR,
D => INSO4,
Q => INSTR);
 
DR : data_reg
PORT MAP (
RST => RST,
CLK => CLK,
ENA => LD_DP,
D => INSO4,
Q => IMMED);
 
-- RAM/input device READ multiplexer
BUS_MUX : mux8to1
PORT MAP (
SEL => DOSEL,
S0 => DO1,
S1 => DO2,
S2 => DO3,
S3 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S4 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S5 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data)),
S7 => MEMO4,
Y => DATABUS_OUT);
 
BUSR : data_reg_2 PORT MAP (
CLK => CLK,
D => DATABUS_OUT,
Q => DATABUS_READ);
 
END Structural;
/trunk/Xilinx/32k/system.ucf
1,4 → 1,4
 
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/07
NET "clock" TNM_NET = clock;
TIMESPEC TS_clock = PERIOD "clock" 13 ns HIGH 50%;
TIMESPEC TS_clock = PERIOD "clock" 6 ns HIGH 50%;
/trunk/Xilinx/32k/iseconfig/mem_32k_xucpu.projectmgr
1,4 → 1,4
<?xml version="1.0" encoding="utf-8"?>
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
13,14 → 13,15
<ClosedNode>/mux32to1 - Behavioral |home|jurgen|Projects|xucpu|src|components|multiplexer|MUX.vhdl</ClosedNode>
<ClosedNode>/summation - Behavioral |home|jurgen|Projects|xucpu|src|components|ALU|summation.vhdl</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system.vhdl</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system_mem_32k.vhdl</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system_mem_32k.vhdl/MEM1 - RAM32K - Structural</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>system - Structural (/home/jurgen/Projects/xucpu/src/system/system_mem_32k.vhdl)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >6</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000038e000000020000000000000000000000000200000064ffffffff0000008100000003000000020000038e0000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>system - Structural (/home/jurgen/Projects/xucpu/src/system/system_mem_32k.vhdl)</CurrentItem>
</ItemView>
28,13 → 29,16
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="vertical" >12</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000010f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000010f0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
61,7 → 65,7
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000011f000000010001000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000121000000010001000100000000000000000000000064ffffffff000000810000000000000001000001210000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
81,4 → 85,49
</ItemView>
<SourceProcessView>000000ff0000000000000002000000f0000000c801000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/mux32to1 - Behavioral |home|jurgen|Projects|xucpu|src|components|multiplexer|MUX.vhdl</ClosedNode>
<ClosedNode>/startup_sim - behavior |home|jurgen|Projects|xucpu|tb|startup_sim.vhdl</ClosedNode>
<ClosedNode>/summation - Behavioral |home|jurgen|Projects|xucpu|src|components|ALU|summation.vhdl</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>startup_sim - behavior (/home/jurgen/Projects/xucpu/tb/startup_sim.vhdl)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >1</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>startup_sim - behavior (/home/jurgen/Projects/xucpu/tb/startup_sim.vhdl)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>ISim Simulator</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000000000000000000011f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000011f0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<CopyAdditionalFiles/>
</Project>
/trunk/Xilinx/32k/mem_32k_xucpu.gise
101,7 → 101,9
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="system.lso"/>
123,6 → 125,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="system.bld"/>
133,6 → 136,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="system.pcf"/>
<outfile xil_pn:name="system_map.map"/>
146,6 → 150,7
<transform xil_pn:end_ts="1444328004" xil_pn:in_ck="-1623301197055523146" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="4636075835883639084" xil_pn:start_ts="1444327979">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="system.ncd"/>
<outfile xil_pn:name="system.pad"/>
160,10 → 165,12
<transform xil_pn:end_ts="1444329853" xil_pn:in_ck="3350087116985295193" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1444329853">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform>
<transform xil_pn:end_ts="1444328014" xil_pn:in_ck="3350087116985295193" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1444328004">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="system.twr"/>
<outfile xil_pn:name="system.twx"/>
172,6 → 179,7
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>
/trunk/Xilinx/16k/system_16k/system.ucf
0,0 → 1,5
 
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/07
NET "clock" TNM_NET = clock;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/09
TIMESPEC TS_clock = PERIOD "clock" 6.8 ns HIGH 50%;
/trunk/Xilinx/16k/system_16k/iseconfig/system.xreport
0,0 → 1,215
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2015-10-09T22:15:39</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/jurgen/Projects/xucpu/Xilinx/16k/system_16k/iseconfig/system.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/jurgen/Projects/xucpu/Xilinx/16k/system_16k</ImplementationReportsDirectory>
<DateInitialized>2015-10-09T22:15:39</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="system_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="system_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="system_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="system_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="system_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="system.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="system_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="system_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="system.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="system_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="system_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="system.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="system.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="system.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="system.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="system.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="system_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="system.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="system.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="system.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="system.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="system.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="system.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/system_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/system_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="system_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="system_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
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<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/system_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="system_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="system.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="system_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/system_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="system_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
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<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="system.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
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<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="system.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/system_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
/trunk/Xilinx/16k/system_16k/system_16k.gise
0,0 → 1,172
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="system.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="system.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="system.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="system.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="system.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="system.pad"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="system.xst"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="system_pad.csv" xil_pn:subbranch="Par"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="system_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="system_summary.xml"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="system.ncd"/>
<outfile xil_pn:name="system.pad"/>
<outfile xil_pn:name="system.par"/>
<outfile xil_pn:name="system.ptwx"/>
<outfile xil_pn:name="system.unroutes"/>
<outfile xil_pn:name="system.xpi"/>
<outfile xil_pn:name="system_pad.csv"/>
<outfile xil_pn:name="system_pad.txt"/>
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/trunk/Xilinx/16k/system_16k/system_16k.xise
93,10 → 93,6
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../src/system/system_mem_32k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/util/file/hexio.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
109,9 → 105,13
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../32k/system.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="system.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/system/system_16k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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<autoManagedFiles>
241,7 → 241,7
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|system|Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_mem_32k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_16k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/system" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
453,7 → 453,9
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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<bindings>
<binding xil_pn:location="/system" xil_pn:name="system.ucf"/>
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/trunk/Xilinx/8k/system_8k/system.ucf
0,0 → 1,5
 
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/07
NET "clock" TNM_NET = clock;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/09
TIMESPEC TS_clock = PERIOD "clock" 5.8 ns HIGH 50%;
/trunk/Xilinx/8k/system_8k/iseconfig/system_8k.projectmgr
0,0 → 1,86
<?xml version="1.0" encoding="utf-8"?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="system_8k" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/clock_gen - Behavioral |home|jurgen|Projects|xucpu|src|system|clock.vhdl</ClosedNode>
<ClosedNode>/memory - Structural |home|jurgen|Projects|xucpu|src|components|BRAM|RAM.vhdl</ClosedNode>
<ClosedNode>/mux32to1 - Behavioral |home|jurgen|Projects|xucpu|src|components|multiplexer|MUX.vhdl</ClosedNode>
<ClosedNode>/summation - Behavioral |home|jurgen|Projects|xucpu|src|components|ALU|summation.vhdl</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system_8k.vhdl</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system_mem_32k.vhdl</ClosedNode>
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<SelectedItem>system - Structural (/home/jurgen/Projects/xucpu/src/system/system_8k.vhdl)</SelectedItem>
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<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000294000000020000000000000000000000000200000064ffffffff000000810000000300000002000002940000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>system - Structural (/home/jurgen/Projects/xucpu/src/system/system_8k.vhdl)</CurrentItem>
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<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
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<SelectedItem>Analyze Post-Place &amp; Route Static Timing</SelectedItem>
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<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001c8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001c80000000100000000</ViewHeaderState>
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<CurrentItem>/home/jurgen/Projects/xucpu/src/components/ALU/alu2.vhdl</CurrentItem>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="system_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="system_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="system_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="system_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="system_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="system_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="system_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1444420767" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1444420767">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1444420767" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4196876386745094078" xil_pn:start_ts="1444420767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444420767" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1064230273442268978" xil_pn:start_ts="1444420767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444420767" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1444420767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444420767" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7985063770380526916" xil_pn:start_ts="1444420767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444420767" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1444420767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444420767" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-181465252883709124" xil_pn:start_ts="1444420767">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444421125" xil_pn:in_ck="4997410063219343631" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-7603409937253613426" xil_pn:start_ts="1444421107">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="system.lso"/>
<outfile xil_pn:name="system.ngc"/>
<outfile xil_pn:name="system.ngr"/>
<outfile xil_pn:name="system.prj"/>
<outfile xil_pn:name="system.stx"/>
<outfile xil_pn:name="system.syr"/>
<outfile xil_pn:name="system.xst"/>
<outfile xil_pn:name="system_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1444421345" xil_pn:in_ck="5512551163982481" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="8690297421775466745" xil_pn:start_ts="1444421345">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444421355" xil_pn:in_ck="3550723964054938012" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1781924448807838723" xil_pn:start_ts="1444421345">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="system.bld"/>
<outfile xil_pn:name="system.ngd"/>
<outfile xil_pn:name="system_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1444421395" xil_pn:in_ck="3552255543040202461" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="8611893017033431545" xil_pn:start_ts="1444421355">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="system.pcf"/>
<outfile xil_pn:name="system_map.map"/>
<outfile xil_pn:name="system_map.mrp"/>
<outfile xil_pn:name="system_map.ncd"/>
<outfile xil_pn:name="system_map.ngm"/>
<outfile xil_pn:name="system_map.xrpt"/>
<outfile xil_pn:name="system_summary.xml"/>
<outfile xil_pn:name="system_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1444421525" xil_pn:in_ck="-1623301197055523146" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="4636075835883639084" xil_pn:start_ts="1444421395">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="system.ncd"/>
<outfile xil_pn:name="system.pad"/>
<outfile xil_pn:name="system.par"/>
<outfile xil_pn:name="system.ptwx"/>
<outfile xil_pn:name="system.unroutes"/>
<outfile xil_pn:name="system.xpi"/>
<outfile xil_pn:name="system_pad.csv"/>
<outfile xil_pn:name="system_pad.txt"/>
<outfile xil_pn:name="system_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1444421537" xil_pn:in_ck="3350087116985295193" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1444421525">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="system.twr"/>
<outfile xil_pn:name="system.twx"/>
</transform>
<transform xil_pn:end_ts="1444420798" xil_pn:in_ck="3552255543040202461" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1444420798">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
</transforms>
 
</generated_project>
/trunk/Xilinx/8k/system_8k/system_8k.xise
93,10 → 93,6
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../src/system/system_mem_32k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/util/file/hexio.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
109,9 → 105,13
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../32k/system.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="system.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../src/system/system_8k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
</files>
 
<autoManagedFiles>
241,7 → 241,7
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|system|Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_mem_32k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_8k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/system" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
453,7 → 453,9
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
<bindings>
<binding xil_pn:location="/system" xil_pn:name="system.ucf"/>
</bindings>
 
<libraries/>
 
/trunk/Xilinx/2k/system_2k/system.ucf
0,0 → 1,5
 
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/07
NET "clock" TNM_NET = clock;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/09
TIMESPEC TS_clock = PERIOD "clock" 5.5 ns HIGH 50%;
/trunk/Xilinx/2k/system_2k/system_2k.gise
0,0 → 1,177
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
<!-- -->
 
<!-- For tool use only. Do not edit. -->
 
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<!-- ProjectNavigator created generated project file. -->
 
<!-- For use in tracking generated file and other information -->
 
<!-- allowing preservation of process status. -->
 
<!-- -->
 
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
 
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="system_2k.xise"/>
 
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="system.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="system.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="system.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="system.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="system.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="system.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="system.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="system.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="system.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="system.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="system.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="system.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="system.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="system.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="system.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="system.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="system.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="system.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="system.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="system_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="system_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="system_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="system_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="system_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="system_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="system_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="system_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="system_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="system_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="system_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="system_xst.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
 
<transforms xmlns="http://www.xilinx.com/XMLSchema">
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<status xil_pn:value="SuccessfullyRun"/>
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<transform xil_pn:end_ts="1444416619" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4196876386745094078" xil_pn:start_ts="1444416619">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1444416619" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1064230273442268978" xil_pn:start_ts="1444416619">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1444416619" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1444416619">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1444416619" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7985063770380526916" xil_pn:start_ts="1444416619">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1444416619" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="8977612015756273942" xil_pn:start_ts="1444416619">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1444416619" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-181465252883709124" xil_pn:start_ts="1444416619">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1444417413" xil_pn:in_ck="-2881698894554817207" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-7603409937253613426" xil_pn:start_ts="1444417400">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="system.lso"/>
<outfile xil_pn:name="system.ngc"/>
<outfile xil_pn:name="system.ngr"/>
<outfile xil_pn:name="system.prj"/>
<outfile xil_pn:name="system.stx"/>
<outfile xil_pn:name="system.syr"/>
<outfile xil_pn:name="system.xst"/>
<outfile xil_pn:name="system_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1444419986" xil_pn:in_ck="5512551163982481" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="8690297421775466745" xil_pn:start_ts="1444419986">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1444419996" xil_pn:in_ck="3550723964054938012" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1781924448807838723" xil_pn:start_ts="1444419986">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="system.bld"/>
<outfile xil_pn:name="system.ngd"/>
<outfile xil_pn:name="system_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1444420034" xil_pn:in_ck="3552255543040202461" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="8611893017033431545" xil_pn:start_ts="1444419996">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="system.pcf"/>
<outfile xil_pn:name="system_map.map"/>
<outfile xil_pn:name="system_map.mrp"/>
<outfile xil_pn:name="system_map.ncd"/>
<outfile xil_pn:name="system_map.ngm"/>
<outfile xil_pn:name="system_map.xrpt"/>
<outfile xil_pn:name="system_summary.xml"/>
<outfile xil_pn:name="system_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1444420077" xil_pn:in_ck="-1623301197055523146" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="4636075835883639084" xil_pn:start_ts="1444420034">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="system.ncd"/>
<outfile xil_pn:name="system.pad"/>
<outfile xil_pn:name="system.par"/>
<outfile xil_pn:name="system.ptwx"/>
<outfile xil_pn:name="system.unroutes"/>
<outfile xil_pn:name="system.xpi"/>
<outfile xil_pn:name="system_pad.csv"/>
<outfile xil_pn:name="system_pad.txt"/>
<outfile xil_pn:name="system_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1444420163" xil_pn:in_ck="3350087116985295193" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1444420077">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
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/trunk/Xilinx/2k/system_2k/iseconfig/system.xreport
0,0 → 1,215
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2015-10-09T20:50:14</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/jurgen/Projects/xucpu/Xilinx/2k/system_2k/iseconfig/system.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/jurgen/Projects/xucpu/Xilinx/2k/system_2k</ImplementationReportsDirectory>
<DateInitialized>2015-10-09T20:50:14</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
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<body>
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<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
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</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
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<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="system.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
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<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
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<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
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<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
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<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
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<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
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<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
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<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
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<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
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<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="system.rpt" label="CPLD Fitter Report (Text)" >
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<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
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<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
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<toc-item title="Timing Report Description" target="Device,package,speed:" />
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<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
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/trunk/Xilinx/2k/system_2k/iseconfig/system_2k.projectmgr
0,0 → 1,75
<?xml version="1.0" encoding="utf-8"?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="system_2k" >
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<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
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<ClosedNode>/clock_gen - Behavioral |home|jurgen|Projects|xucpu|src|system|clock.vhdl</ClosedNode>
<ClosedNode>/memory - Structural |home|jurgen|Projects|xucpu|src|components|BRAM|RAM.vhdl</ClosedNode>
<ClosedNode>/mux32to1 - Behavioral |home|jurgen|Projects|xucpu|src|components|multiplexer|MUX.vhdl</ClosedNode>
<ClosedNode>/summation - Behavioral |home|jurgen|Projects|xucpu|src|components|ALU|summation.vhdl</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system_2k.vhdl</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system_2k.vhdl/MEM1 - memory - Structural</ClosedNode>
<ClosedNode>/system - Structural |home|jurgen|Projects|xucpu|src|system|system_mem_32k.vhdl</ClosedNode>
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<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Back-annotate Pin Locations</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route/Generate IBIS Model</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
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/trunk/Xilinx/2k/system_2k/system_2k.xise
93,10 → 93,6
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../src/system/system_mem_32k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/util/file/hexio.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
109,7 → 105,11
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../32k/system.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../../src/system/system_2k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="system.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
241,7 → 241,7
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|system|Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_mem_32k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_2k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/system" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
260,6 → 260,7
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance without IOB Packing;/opt/Xilinx/13.4/ISE_DS/ISE/spartan6/data/spartan6_performance_without_iobpacking.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Selected UCF File" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
453,7 → 454,9
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
<bindings>
<binding xil_pn:location="/system" xil_pn:name="system.ucf"/>
</bindings>
 
<libraries/>
 
/trunk/Xilinx/2k/system_2k/system.xdl
0,0 → 1,186
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/trunk/Xilinx/4k/system_4k/system.ucf
0,0 → 1,5
 
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/07
NET "clock" TNM_NET = clock;
#Created by Constraints Editor (xc6slx45-csg324-2) - 2015/10/09
TIMESPEC TS_clock = PERIOD "clock" 5.5 ns HIGH 50%;
/trunk/Xilinx/4k/system_4k/iseconfig/system.xreport
0,0 → 1,215
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2015-10-09T21:54:20</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2015-10-09T21:53:40</SummaryTimeStamp>
<SavedFilePath>/home/jurgen/Projects/xucpu/Xilinx/4k/system_4k/iseconfig/system.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/jurgen/Projects/xucpu/Xilinx/4k/system_4k</ImplementationReportsDirectory>
<DateInitialized>2015-10-09T21:54:20</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="system_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
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<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="system_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="system_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="system.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="system_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="system_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="system.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="system_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="system_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="system.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="system.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="system.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="system.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="system.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="system_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
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/trunk/Xilinx/4k/system_4k/iseconfig/system_4k.projectmgr
0,0 → 1,71
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<outfile xil_pn:name="system_ngdbuild.xrpt"/>
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<transform xil_pn:end_ts="1444420576" xil_pn:in_ck="3552255543040202461" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="8611893017033431545" xil_pn:start_ts="1444420530">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="system.pcf"/>
<outfile xil_pn:name="system_map.map"/>
<outfile xil_pn:name="system_map.mrp"/>
<outfile xil_pn:name="system_map.ncd"/>
<outfile xil_pn:name="system_map.ngm"/>
<outfile xil_pn:name="system_map.xrpt"/>
<outfile xil_pn:name="system_summary.xml"/>
<outfile xil_pn:name="system_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1444420622" xil_pn:in_ck="-1623301197055523146" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="4636075835883639084" xil_pn:start_ts="1444420576">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="system.ncd"/>
<outfile xil_pn:name="system.pad"/>
<outfile xil_pn:name="system.par"/>
<outfile xil_pn:name="system.ptwx"/>
<outfile xil_pn:name="system.unroutes"/>
<outfile xil_pn:name="system.xpi"/>
<outfile xil_pn:name="system_pad.csv"/>
<outfile xil_pn:name="system_pad.txt"/>
<outfile xil_pn:name="system_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1444420634" xil_pn:in_ck="3350087116985295193" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1444420622">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="system.twr"/>
<outfile xil_pn:name="system.twx"/>
</transform>
<transform xil_pn:end_ts="1444420512" xil_pn:in_ck="3552255543040202461" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1444420512">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
 
</generated_project>
/trunk/Xilinx/4k/system_4k/system_4k.xise
93,10 → 93,6
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../src/system/system_mem_32k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../src/util/file/hexio.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
109,7 → 105,11
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../32k/system.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../../src/system/system_4k.vhdl" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="system.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
241,7 → 241,7
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|system|Structural" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_mem_32k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../src/system/system_4k.vhdl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/system" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
453,7 → 453,9
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
 
<bindings/>
<bindings>
<binding xil_pn:location="/system" xil_pn:name="system.ucf"/>
</bindings>
 
<libraries/>
 

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