URL
https://opencores.org/ocsvn/xucpu/xucpu/trunk
Subversion Repositories xucpu
Compare Revisions
- This comparison shows the changes necessary to convert path
/xucpu
- from Rev 30 to Rev 31
- ↔ Reverse comparison
Rev 30 → Rev 31
/trunk/src/system/S2MEM.vhdl
--- trunk/src/system/S2.vhdl (nonexistent)
+++ trunk/src/system/S2.vhdl (revision 31)
@@ -0,0 +1,147 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+USE work.S2LIB.ALL;
+
+ENTITY S2 IS
+
+ PORT (
+ CLOCK : IN STD_LOGIC;
+ RESET : IN STD_LOGIC;
+ LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SWITCH : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ BUTTON : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
+
+END ENTITY S2;
+
+ARCHITECTURE Structural OF S2 IS
+
+ SIGNAL CLK : STD_LOGIC;
+ SIGNAL RST : STD_LOGIC;
+
+ SIGNAL DATA_BUS : STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL ADDRESS_BUS : STD_LOGIC_VECTOR(14 DOWNTO 0);
+ SIGNAL RD : STD_LOGIC;
+ SIGNAL WR : STD_LOGIC;
+
+ SIGNAL BA_ADDR_SEL : STD_LOGIC;
+ SIGNAL BA_ICC_ACK : STD_LOGIC;
+ SIGNAL BA_DCC_ACK : STD_LOGIC;
+
+ SIGNAL ICC_RD : STD_LOGIC;
+ SIGNAL ICC_WR : STD_LOGIC;
+ SIGNAL ICC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
+ SIGNAL ICC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL DCC_RD : STD_LOGIC;
+ SIGNAL DCC_WR : STD_LOGIC;
+ SIGNAL DCC_ADDRESS : STD_LOGIC_VECTOR(14 DOWNTO 0);
+ SIGNAL DCC_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+ SIGNAL CPU_IF : STD_LOGIC;
+ SIGNAL CPU_INSTR_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);
+ SIGNAL CPU_INSTRUCTION : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+ SIGNAL CPU_RD : STD_LOGIC;
+ SIGNAL CPU_WR : STD_LOGIC;
+ SIGNAL CPU_DATA_ADDR : STD_LOGIC_VECTOR(14 DOWNTO 0);
+ SIGNAL CPU_DATA_OUT : STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL CPU_DATA_IN : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+ SIGNAL MEM_DATA : STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+BEGIN -- ARCHITECTURE Structural
+
+ BA1 : S2ARB
+ PORT MAP (
+ -- Main component connections
+ CLK => CLK,
+ RST => RST,
+ -- Bus requests from ICC
+ I_RD_ICC => ICC_RD,
+ I_WR_ICC => ICC_WR,
+ -- Bus requests from DCC
+ I_RD_DCC => DCC_RD,
+ I_WR_DCC => DCC_WR,
+ -- Arbiter control signals
+ O_ADDRESS_MUX_SEL => BA_ADDR_SEL,
+ O_ACK_ICC => BA_ICC_ACK,
+ O_ACK_DCC => BA_DCC_ACK);
+
+
+ ICC1 : S2ICC
+ PORT MAP (
+ -- Main component connections
+ CLK => CLK,
+ RST => RST,
+ -- To main bus
+ O_ADDRESS => ICC_ADDRESS,
+ O_DATA => ICC_DATA,
+ O_RD => ICC_RD,
+ O_WR => ICC_WR,
+ -- From bus arbiter
+ I_ACK => BA_ICC_ACK,
+ -- From main bus
+ I_ADDRESS => ADDRESS_BUS,
+ I_DATA => DATA_BUS,
+ I_RD => RD,
+ I_WR => WR,
+ -- CPU specific connections
+ I_CPU_IF => CPU_IF,
+ I_CPU_INSTR_ADDR => CPU_INSTR_ADDR,
+ I_CPU_INSTRUCTION => CPU_INSTRUCTION);
+
+ DCC1 : S2DCC
+ PORT MAP (
+ -- Main component connections
+ CLK => CLK,
+ RST => RST,
+ -- To main bus
+ O_ADDRESS => DCC_ADDRESS,
+ O_DATA => DCC_DATA,
+ O_RD => DCC_RD,
+ O_WR => DCC_WR,
+ -- From bus arbiter
+ I_ACK => BA_DCC_ACK,
+ -- From main bus
+ I_ADDRESS => ADDRESS_BUS,
+ I_DATA => DATA_BUS,
+ I_RD => RD,
+ I_WR => WR,
+ -- CPU specific connections
+ I_CPU_RD => CPU_RD,
+ I_CPU_WR => CPU_WR,
+ I_CPU_DATA_ADDR => CPU_DATA_ADDRESS,
+ I_CPU_DATA => CPU_DATA_OUT,
+ O_CPU_DATA => CPU_DATA_IN);
+
+ CPU1 : S2CPU
+ PORT MAP (
+ -- Main component connections
+ CLK => CLK,
+ RST => RST,
+ -- Instruction cache connections
+ O_IF => CPU_IF,
+ O_INSTR_ADDR => CPU_INSTR_ADDR,
+ I_INSTRUCTION => CPU_INSTRUCTION,
+ -- Data cache connections
+ O_RD => CPU_RD,
+ O_WR => CPU_WR,
+ O_DATA_ADDR => CPU_DATA_ADDRESS,
+ O_DATA => CPU_DATA_OUT,
+ I_DATA => CPU_DATA_IN);
+
+ MEM1 : S2MEM
+ PORT MAP (
+ CLK => CLK,
+ RST => RST,
+ I_RD => RD,
+ I_WR => WR,
+ I_ADDRESS => ADDRESS_BUS,
+ I_DATA => DATA_BUS,
+ O_DATA => MEM_DATA);
+
+
+
+
+
+END ARCHITECTURE Structural;
/trunk/src/system/S2LIB.vhdl
0,0 → 1,79
PACKAGE S2LIB IS |
|
COMPONENT S2ARB IS |
PORT ( |
I_RD_ICC : IN STD_LOGIC; |
I_WR_ICC : IN STD_LOGIC; |
I_RD_DCC : IN STD_LOGIC; |
I_WR_DCC : IN STD_LOGIC; |
O_ADDRESS_MUX_SEL : OUT STD_LOGIC; |
O_ACK_ICC : OUT STD_LOGIC; |
O_ACK_DCC : OUT STD_LOGIC; |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC); |
END COMPONENT S2ARB; |
|
COMPONENT S2ICC IS |
PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
O_ADDRESS : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_RD : OUT STD_LOGIC; |
O_WR : OUT STD_LOGIC; |
I_ACK : IN STD_LOGIC; |
I_ADDRESS : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
I_RD : IN STD_LOGIC; |
I_WR : IN STD_LOGIC; |
I_CPU_IF : IN STD_LOGIC; |
I_CPU_INSTR_ADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_CPU_INSTRUCTION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); |
END COMPONENT S2ICC; |
|
COMPONENT S2DCC IS |
PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
O_ADDRESS : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_RD : OUT STD_LOGIC; |
O_WR : OUT STD_LOGIC; |
I_ACK : IN STD_LOGIC; |
I_ADDRESS : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
I_RD : IN STD_LOGIC; |
I_WR : IN STD_LOGIC; |
I_CPU_RD : IN STD_LOGIC; |
I_CPU_WR : IN STD_LOGIC; |
I_CPU_DATA_ADDR : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_CPU_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_CPU_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); |
END COMPONENT S2DCC; |
|
COMPONENT S2CPU IS |
PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
O_IF : OUT STD_LOGIC; |
O_INSTR_ADDR : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_INSTRUCTION : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_RD : OUT STD_LOGIC; |
O_WR : OUT STD_LOGIC; |
O_DATA_ADDR : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0)); |
END COMPONENT S2CPU; |
|
COMPONENT S2MEM IS |
PORT ( |
CLK : IN STD_LOGIC; |
RST : IN STD_LOGIC; |
I_RD : IN STD_LOGIC; |
I_WR : IN STD_LOGIC; |
I_ADDRESS : IN STD_LOGIC_VECTOR(14 DOWNTO 0); |
I_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
O_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); |
END COMPONENT S2MEM; |
|
END PACKAGE S2LIB; |