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Rev 39 → Rev 40

/trunk/VHDL/ALU.vhdl
16,98 → 16,118
-- along with Experimental Unstable CPU System. If not, see
-- http://www.gnu.org/licenses/lgpl.txt.
 
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.NUMERIC_STD.ALL;
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alu IS
GENERIC(
w_data : NATURAL RANGE 1 TO 32 := 16);
PORT(
op : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));
 
ENTITY ALU IS
PORT (A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR (5 DOWNTO 0));
END ALU;
FUNCTION alu_add (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR;
 
ARCHITECTURE Behavioral OF ALU IS
FUNCTION alu_add(
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR IS
BEGIN -- alu_add
RETURN STD_LOGIC_VECTOR(UNSIGNED(A) + UNSIGNED(B));
END alu_add;
 
COMPONENT boole IS
GENERIC (
width : NATURAL := 32);
PORT (A : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR (2 DOWNTO 0));
END COMPONENT boole;
FUNCTION alu_sub (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR;
 
COMPONENT shift IS
GENERIC (
width : NATURAL := 16);
PORT (A : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
X : OUT STD_LOGIC_VECTOR (width - 1 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR (2 DOWNTO 0));
END COMPONENT shift;
FUNCTION alu_sub(
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);
SIGNAL B : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR IS
BEGIN -- alu_sub
RETURN STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B));
END alu_sub;
 
COMPONENT addsub IS
PORT (A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
CARRY : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
SEL : IN STD_LOGIC_VECTOR (1 DOWNTO 0));
END COMPONENT addsub;
FUNCTION alu_inc (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR;
 
COMPONENT multiplier IS
PORT (A : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
PRODUCT_HIGH : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
PRODUCT_LOW : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END COMPONENT multiplier;
FUNCTION alu_inc (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(UNSIGNED(A) + 1);
END alu_inc;
 
SIGNAL bool_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL shift_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL add_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL carry_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL prod_low_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL prod_high_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
FUNCTION alu_dec (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR;
 
BOOL1 : boole
GENERIC MAP (
width => 16)
PORT MAP (
A => A,
B => B,
X => bool_out,
SEL => SEL(2 DOWNTO 0));
FUNCTION alu_dec (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(UNSIGNED(A) - 1);
END alu_dec;
 
SHIFT1 : shift PORT MAP (
A => A,
B => B,
X => shift_out,
SEL => SEL(2 DOWNTO 0));
FUNCTION shift_left (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR;
 
ADD1 : addsub PORT MAP (
A => A,
B => B,
SUM => add_out,
CARRY => carry_out,
SEL => SEL(1 DOWNTO 0));
FUNCTION shift_left (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(shift_left(UNSIGNED(A), 1));
END shift_left;
 
MULT1 : multiplier PORT MAP (
A => A,
B => B,
PRODUCT_HIGH => prod_high_out,
PRODUCT_LOW => prod_low_out);
FUNCTION shift_right (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR;
 
WITH SEL(5 DOWNTO 3) SELECT
X <=
bool_out WHEN "000",
shift_out WHEN "001",
add_out WHEN "010",
carry_out WHEN "011",
prod_low_out WHEN "100",
prod_high_out WHEN "101",
X"0000" WHEN OTHERS;
FUNCTION shift_right (
SIGNAL A : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0))
RETURN STD_LOGIC_VECTOR IS
BEGIN
RETURN STD_LOGIC_VECTOR(shift_right(UNSIGNED(A), 1));
END shift_right;
 
END Behavioral;
END ENTITY alu;
 
ARCHITECTURE Behavioral OF alu IS
 
CONSTANT ZERO : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)
:= STD_LOGIC_VECTOR(TO_UNSIGNED(0, w_data));
CONSTANT ONE : STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)
:= STD_LOGIC_VECTOR(TO_UNSIGNED(1, w_data));
 
BEGIN -- ARCHITECTURE Behavioral
 
WITH op SELECT
y <=
alu_inc(A) WHEN "0000",
alu_dec(A) WHEN "0001",
ZERO WHEN "0010", -- Place holder
ONE WHEN "0011", -- Place holder
B WHEN "0100",
A WHEN "0101", -- Place holder
A WHEN "0110", -- Place holder
alu_add(A, B) WHEN "0111",
alu_sub(A, B) WHEN "1000",
A WHEN "1001", -- Place holder
A AND B WHEN "1010",
A OR B WHEN "1011",
A XOR B WHEN "1100",
NOT A WHEN "1101",
shift_left(A) WHEN "1110",
shift_right(A) WHEN "1111",
A WHEN OTHERS;
 
END ARCHITECTURE Behavioral;

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