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  • This comparison shows the changes necessary to convert path 
    /xulalx25soc/trunk/rtl
    from Rev 8 to Rev 9
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Rev 8 → Rev 9

/wbusixchar.v
51,6 → 51,7
output wire o_busy;
input i_busy;
 
initial o_char = 8'h00;
always @(posedge i_clk)
if ((i_stb)&&(~o_busy))
begin
/wbudecompress.v
42,8 → 42,13
output reg o_stb;
output reg [35:0] o_word;
 
 
// Clock zero
// { o_stb, r_stb } = 0
wire cmd_write_not_compressed = (i_word[35:33] == 3'h3);
 
 
// Clock one: { o_stb, r_stb } = 4'h1 when done
reg [7:0] wr_addr;
initial wr_addr = 8'h0;
always @(posedge i_clk)
54,28 → 59,30
always @(posedge i_clk)
compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] };
 
// Clock 0, calculate the table address ... 1 is the smallest address
wire [7:0] cmd_addr;
assign cmd_addr = wr_addr - { i_word[32:31], i_word[29:24] };
reg [35:0] r_word;
always @(posedge i_clk)
r_word <= i_word;
 
// Clock one, read the table value
reg [31:0] cword;
 
// Clock two, calculate the table address ... 1 is the smallest address
// { o_stb, r_stb } = 4'h2 when done
reg [7:0] cmd_addr;
always @(posedge i_clk)
cword <= compression_tbl[cmd_addr];
cmd_addr = wr_addr - { r_word[32:31], r_word[29:24] };
 
// Let's also calculate the address, in case this is a compressed
// address word
reg [24:0] r_addr;
always @(posedge i_clk)
case(i_word[32:30])
3'b000: r_addr <= { 19'h0, i_word[29:24] };
3'b010: r_addr <= { 13'h0, i_word[29:18] };
3'b100: r_addr <= { 7'h0, i_word[29:12] };
3'b110: r_addr <= { 1'h0, i_word[29: 6] };
3'b001: r_addr <= { {(19){ i_word[29]}}, i_word[29:24] };
3'b011: r_addr <= { {(13){ i_word[29]}}, i_word[29:18] };
3'b101: r_addr <= { {( 7){ i_word[29]}}, i_word[29:12] };
3'b111: r_addr <= { {( 1){ i_word[29]}}, i_word[29: 6] };
case(r_word[32:30])
3'b000: r_addr <= { 19'h0, r_word[29:24] };
3'b010: r_addr <= { 13'h0, r_word[29:18] };
3'b100: r_addr <= { 7'h0, r_word[29:12] };
3'b110: r_addr <= { 1'h0, r_word[29: 6] };
3'b001: r_addr <= { {(19){ r_word[29]}}, r_word[29:24] };
3'b011: r_addr <= { {(13){ r_word[29]}}, r_word[29:18] };
3'b101: r_addr <= { {( 7){ r_word[29]}}, r_word[29:12] };
3'b111: r_addr <= { {( 1){ r_word[29]}}, r_word[29: 6] };
endcase
wire [31:0] w_addr;
assign w_addr = { {(7){r_addr[24]}}, r_addr };
82,24 → 89,40
 
reg [9:0] rd_len;
always @(posedge i_clk)
if (~i_word[34])
rd_len <= 10'h01 + { 6'h00, i_word[33:31] };
if (~r_word[34])
rd_len <= 10'h01 + { 6'h00, r_word[33:31] };
else
rd_len <= 10'h08 + { 1'b0, i_word[33:31], i_word[29:24] };
rd_len <= 10'h08 + { 1'b0, r_word[33:31], r_word[29:24] };
// Clock three, read the table value
// { o_stb, r_stb } = 4'h4 when done
// Maintaining ...
// r_word (clock 1)
// r_addr, rd_len (clock 2)
reg [31:0] cword;
always @(posedge i_clk)
cword <= compression_tbl[cmd_addr];
 
// Clock one, copy the input strobe, and input word
reg r_stb;
reg [35:0] r_word;
 
// Pipeline the strobe signal to create an output strobe, 3 clocks later
reg [2:0] r_stb;
initial r_stb = 0;
always @(posedge i_clk)
r_stb <= i_stb;
always @(posedge i_clk)
r_word <= i_word;
r_stb <= { r_stb[1:0], i_stb };
 
// Clock two, now that the table value is valid, let's set our output
// Clock four, now that the table value is valid, let's set our output
// word.
// { o_stb, r_stb } = 4'h8 when done
always @(posedge i_clk)
o_stb <= r_stb;
o_stb <= r_stb[2];
// Maintaining ...
// r_word (clock 1)
// r_addr, rd_len (clock 2)
// cword (clock 3)
// Any/all of these can be pipelined for faster operation
// However, speed is really limited by the speed of the I/O port. At
// it's fastest, it's 1 bit per clock, 48 clocks per codeword therefore,
// thus ... things will hold still for much longer than just 5 clocks.
always @(posedge i_clk)
if (r_word[35:30] == 6'b101110)
o_word <= r_word;
/toplevel.v
82,7 → 82,7
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(3),
.CLKFX_MULTIPLY(20),
.CLKFX_MULTIPLY(19),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(83.333333),
.CLKOUT_PHASE_SHIFT("NONE"),
/wbubus.v
129,7 → 129,7
r_wdt_reset <= 1'b1;
r_wdt_timer <= 0;
end else begin
r_wdt_timer <= r_wdt_timer+1;
r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1};
r_wdt_reset <= 1'b0;
end
 
/uartdev.v
60,24 → 60,26
reg [7:0] r_tx_data;
initial r_setup = DEFAULT_SETUP;
always @(posedge i_clk)
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we))
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(~i_wb_addr[1]))
r_setup <= i_wb_data[29:0];
 
initial r_tx_stb = 1'b0;
always @(posedge i_clk)
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)&&(i_wb_addr == 2'b10))
begin
case(i_wb_addr)
2'b00: r_setup <= i_wb_data[29:0];
2'b10: begin
r_tx_data <= i_wb_data[7:0];
r_tx_stb <= 1'b1;
end
default: begin end
endcase
// Note: there's no check for overflow here.
// You're on your own: verify that the device
// isn't busy first.
r_tx_data <= i_wb_data[7:0];
r_tx_stb <= 1'b1;
end else
r_tx_stb <= 1'b0;
 
wire rx_stb, rx_break, rx_parity_err, rx_frame_err, rx_ignored;
wire rx_stb, rx_break, rx_parity_err, rx_frame_err;
wire [7:0] rx_data;
rxuart rxmod(i_clk, 1'b0, r_setup, i_rx_uart,
rx_stb, rx_data, rx_break,
rx_parity_err, rx_frame_err, rx_ignored);
rx_parity_err, rx_frame_err);
 
wire tx_break, tx_busy;
assign tx_break = 1'b0;
88,6 → 90,8
always @(posedge i_clk)
if (rx_stb)
r_data <= rx_data;
 
initial o_wb_data = 32'h00;
always @(posedge i_clk)
begin
if (rx_stb)
99,11 → 103,11
2'b10: o_wb_data <= { 31'h00,tx_busy };
2'b11: begin
if ((i_wb_cyc)&&(i_wb_stb)&&(~i_wb_we))
rx_rdy <= 1'b0;
rx_rdy <= rx_stb;
o_wb_data <= { 20'h00, rx_break, rx_frame_err, rx_parity_err, ~rx_rdy, r_data };
end
endcase
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb);
o_wb_ack <= (i_wb_cyc)&&(i_wb_stb); // Read or write, we ack
end
 
assign o_wb_stall = 1'b0;
/wbpwmaudio.v
84,7 → 84,7
o_pwm, o_int);
parameter DEFAULT_RELOAD = 32'd1814, // about 44.1 kHz @ 80MHz
//DEFAULT_RELOAD = 32'd2268,//about 44.1 kHz @ 100MHz
VARIABLE_RATE=0;
VARIABLE_RATE=1;
input i_clk;
input i_wb_cyc, i_wb_stb, i_wb_we;
input i_wb_addr;
105,7 → 105,7
reg [31:0] r_reload_value;
initial r_reload_value = DEFAULT_RELOAD;
always @(posedge i_clk) // Data write
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr))
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr)&&(i_wb_we))
reload_value <= i_wb_data;
wire [31:0] w_reload_value;
assign w_reload_value = r_reload_value;
133,7 → 133,8
initial next_valid = 1'b1;
initial next_sample = 16'h8000;
always @(posedge i_clk) // Data write
if ((i_wb_cyc)&&(i_wb_stb)&&((~i_wb_addr)||(VARIABLE_RATE==0)))
if ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)
&&((~i_wb_addr)||(VARIABLE_RATE==0)))
begin
// Write with two's complement data, convert it
// internally to binary offset
154,7 → 155,7
wire [15:0] br_counter;
genvar k;
generate for(k=0; k<16; k=k+1)
begin
begin : bit_reversal_loop
assign br_counter[k] = pwm_counter[15-k];
end endgenerate
 
/rxuart.v
107,7 → 107,7
`define RXU_IDLE 4'hf
 
module rxuart(i_clk, i_reset, i_setup, i_uart, o_wr, o_data, o_break,
o_parity_err, o_frame_err, o_ck_uart);
o_parity_err, o_frame_err);
// parameter // CLOCKS_PER_BAUD = 25'd004340,
// BREAK_CONDITION = CLOCKS_PER_BAUD * 12,
// CLOCKS_PER_HALF_BAUD = CLOCKS_PER_BAUD/2;
119,7 → 119,6
output reg [7:0] o_data;
output reg o_break;
output reg o_parity_err, o_frame_err;
output wire o_ck_uart;
 
 
wire [27:0] clocks_per_baud, break_condition, half_baud;
145,7 → 144,7
qq_uart <= q_uart;
ck_uart <= qq_uart;
end
assign o_ck_uart = ck_uart;
// assign o_ck_uart = ck_uart;
 
reg [27:0] chg_counter;
initial chg_counter = 28'h00;
/txuart.v
148,7 → 148,7
o_busy <= 1'b1;
end else if (baud_counter != 0)
begin // o_busy needs to be set coming into here
baud_counter <= baud_counter - 1;
baud_counter <= baud_counter - 28'h01;
o_busy <= 1'b1;
end else if (state == `TXU_BREAK)
begin
/builddate.v
1,7 → 148,7
link ../20151230-build.v
link ../20160102-build.v
/ioslave.v
159,7 → 159,11
//
wire [31:0] ck_data;
wire ck_ppd;
rtclight #(32'h35afe5)
rtclight
#(32'h388342) // 76 MHz clock (2^48 / 76e6)
// #(32'h35afe5) // 80 MHz clock
// #(32'h2eaf36) // 92 MHz clock
// #(32'h2af31d) // 100 MHz clock
theclock(i_clk, i_wb_cyc, (i_wb_stb)&&(i_wb_addr[4]),
i_wb_we, i_wb_addr[2:0], i_wb_data,
ck_data, ck_int, ck_ppd);
/busmaster.v
45,8 → 45,8
`define FANCY_ICAP_ACCESS
`define FLASH_ACCESS
// `define FLASH_SCOPE
// `define CFG_SCOPE
`define SDRAM_SCOPE
`define CFG_SCOPE
// `define SDRAM_SCOPE
`define ZIP_SCOPE
// `define SDCARD_ACCESS
module busmaster(i_clk, i_rst,
115,7 → 115,7
wire w_interrupt;
// Oh, and the debug control for the ZIP CPU
wire wbu_zip_sel, zip_dbg_ack, zip_dbg_stall;
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]);
assign wbu_zip_sel =((wbu_cyc)&&(wbu_addr[24]));
wire [31:0] zip_dbg_data;
wbubus genbus(i_clk, i_rx_stb, i_rx_data,
wbu_cyc, wbu_stb, wbu_we, wbu_addr, wbu_data,
364,8 → 364,8
//
uartdev serialport(i_clk, i_rx_uart, o_tx_uart,
wb_cyc, (wb_stb)&&(uart_sel), wb_we,
{ ~wb_addr[2], wb_addr[0]},
wb_data, uart_ack, uart_stall, uart_data,
{ ~wb_addr[2], wb_addr[0]}, wb_data,
uart_ack, uart_stall, uart_data,
uart_rx_int, uart_tx_int);
 
//
574,7 → 574,7
r_trigger <= 1'b0;
*/
wbscope #(5'hd) sdramscope(i_clk, 1'b1, sdram_trigger,
wbscope #(5'ha) sdramscope(i_clk, 1'b1, sdram_trigger,
sdram_debug,
// zip_debug,
// Wishbone interface
594,7 → 594,7
`ifdef ZIP_SCOPE
wire zip_trigger;
assign zip_trigger=(wbu_zip_sel)&&(wbu_we)&&(wbu_stb)&&(~wbu_addr[0]);
wbscope #(5'hd) zipscope(i_clk, 1'b1, zip_trigger,
wbscope #(5'ha) zipscope(i_clk, 1'b1, zip_trigger,
zip_debug,
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b11)), wb_we, wb_addr[0],
/wbucompress.v
121,12 → 121,7
reg r_stb;
always @(posedge i_clk)
r_stb <= a_stb;
/*
reg [35:0] r_word;
always @(posedge i_clk)
if (a_stb)
r_word <= a_addrword;
*/
 
wire [35:0] r_word;
assign r_word = a_addrword;
 
237,7 → 232,7
r_compressed <= 1'b0; // to our output
else if (r_compressed)//Already compressed, wait 'til sent
;
else if ((match)&&(matchaddr < 10'd521)&&(r_word == a_addrword))
else if ((match)&&(matchaddr < 10'd521))
begin
if (matchaddr == 10'h1)
r_cword[35:30] <= { 5'h3, r_word[30] };

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