URL
https://opencores.org/ocsvn/z80control/z80control/trunk
Subversion Repositories z80control
Compare Revisions
- This comparison shows the changes necessary to convert path
/z80control
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/DE1/z80soc.qpf
File deleted
/DE1/z80soc.pin
File deleted
/DE1/z80soc.sof
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
DE1/z80soc.sof
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: DE1/ROM/dostools/imac.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: DE1/ROM/dostools/imac.exe
===================================================================
--- DE1/ROM/dostools/imac.exe (revision 8)
+++ DE1/ROM/dostools/imac.exe (nonexistent)
DE1/ROM/dostools/imac.exe
Property changes :
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## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: DE1/ROM/dostools/m.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: DE1/ROM/dostools/m.exe
===================================================================
--- DE1/ROM/dostools/m.exe (revision 8)
+++ DE1/ROM/dostools/m.exe (nonexistent)
DE1/ROM/dostools/m.exe
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: DE1/ROM/dostools/tools.ini
===================================================================
--- DE1/ROM/dostools/tools.ini (revision 8)
+++ DE1/ROM/dostools/tools.ini (nonexistent)
@@ -1,156 +0,0 @@
-; TOOLS.INI file for QUICK configuration
-
-[M]
-Arg:Alt+A
-Assign:Alt+=
-Backtab:Shift+Tab
-Begline:Home
-Cancel:Esc
-Cdelete:Ctrl+G
-Compile:Shift+F3
-Copy:Ctrl+Ins
-Down:Down
-Down:Ctrl+X
-Emacscdel:Bksp
-Emacsnewl:Enter
-Endline:End
-Execute:f10
-Exit:Alt+X
-exit:f10
-Help:F1
-Home:Ctrl+Home
-Information:Shift+F1
-Initialize:Alt+F10
-Insertmode:Ins
-Insertmode:Ctrl+V
-Lasttext:Alt+L
-Ldelete:Ctrl+Y
-Left:Left
-Linsert:Ctrl+N
-Mark:Alt+M
-Meta:F9
-Mlines:Ctrl+W
-Mpage:Pgup
-Mpage:Ctrl+R
-Mpara:Ctrl+Pgup
-Msearch:F4
-Mword:Ctrl+Left
-Paste:Shift+Ins
-Pbal:Ctrl+[
-Plines:Ctrl+Z
-Ppage:Pgdn
-Ppage:Ctrl+C
-Ppara:Ctrl+Pgdn
-Psearch:F3
-Pword:Ctrl+Right
-Pword:Ctrl+F
-Qreplace:Alt+F3
-Quote:Alt+Q
-Refresh:Alt+R
-Replace:Ctrl+L
-Right:Right
-Right:Ctrl+D
-Sdelete:Del
-Setfile:F2
-Setwindow:Ctrl+]
-Shell:Shift+F9
-Sinsert:Alt+Ins
-Tab:Tab
-Undo:Alt+Bksp
-Up:Up
-Up:Ctrl+E
-Window:F6
-;
-; to load the wordstar extension to enable ctrl+QS and ctrl+QD
-; remove the semicolon from the following line and fill in the correct
-; path
-; load:ws.zxt
-Tabstops:10
-Fgcolor:17
-Rmargin:80
-Vscroll:1
-Hscroll:1
-Hike:1
-Backup:bak
-
-donot:=META CURDAY " " CURDATE " " CURTIME
-donot:f5
-
-Curtime:Alt+T
-
-DTATE:=META CURDAY " " CURDATE " " CURTIME
-DTATE:ALT+D
-
-
-ONEDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
-ONEDEL:CTRL+O
-
-BACKDEL:=META CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE
-BACKDEL:CTRL+B
-
-COP2LIN:= DOWN Ldelete Ldelete Ldelete Ldelete
-COP2LIN:ALT+Y
-
-COPYADR:=ARG RIGHT RIGHT RIGHT RIGHT RIGHT SDELETE
-COPYADR:ALT+C
-
-MOVADR:=COPYADR RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT DOWN LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT
-MOVADR:ALT+V
-
-SSWLB2:=DOWN LEFT LEFT LEFT LEFT " "
-SSWLB2:ALT+S
-
-SSWDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
-SSWDEL:ALT+W
-
-ISWDEL:=DOWN META BEGLINE ";"
-ISWDEL:ALT+N
-
-SLDD:=DOWN BEGLINE " "
-SLDD:ALT+U
-
-
-PLACE00:=META "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT
-PLACE00:ALT+`
-
-PLACE1:=META "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT
-PLACE1:ALT+1
-
-PLACE2:=META "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT
-PLACE2:ALT+2
-
-PLACE3:=META "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT
-PLACE3:ALT+3
-
-PLACE4:=META "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT
-PLACE4:ALT+4
-
-PLACE5:=META "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT
-PLACE5:ALT+5
-
-PLACE6:=META "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT
-PLACE6:ALT+6
-
-PLACE7:=META "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT
-PLACE7:ALT+7
-
-PLACE8:=META "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT
-PLACE8:ALT+8
-
-PLACE9:=META "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT
-PLACE9:ALT+9
-
-PLACE0:=META "0" DOWN LEFT "1" DOWN LEFT "2" DOWN LEFT "3" DOWN LEFT "4" DOWN LEFT "5" DOWN LEFT "6" DOWN LEFT "7" DOWN LEFT "8" DOWN LEFT "9" DOWN LEFT
-PLACE0:ALT+0
-;
-PCHEK:=META PPAGE SETFILE PPAGE
-PCHEK:ALT+G
-;
-CHWIN:=META SETFILE
-CHWIN:ALT+F
-;
-MOVAD:=BEGLINE ARG TAB SDELETE DOWN TAB "EQU " PASTE DOWN
-MOVAD:ALT+J
-;
-DOIT:=ARG TAB TAB TAB RIGHT RIGHT SDELETE BEGLINE DOWN DOWN
-DOIT:CTRL+P
Index: DE1/ROM/z80test.bat
===================================================================
--- DE1/ROM/z80test.bat (revision 8)
+++ DE1/ROM/z80test.bat (nonexistent)
@@ -1,4 +0,0 @@
-m z80test.asm
-imac z80test
-copy z80test.hex HexFiles\z80test.hex
-pause
\ No newline at end of file
Index: DE1/ROM/z80.lib
===================================================================
--- DE1/ROM/z80.lib (revision 8)
+++ DE1/ROM/z80.lib (nonexistent)
@@ -1,475 +0,0 @@
-; @CHK MACRO USED FOR CHECKING 8 BIT DISPLACMENTS
-;
-@CHK MACRO ?DD ; USED FOR CHECKING RANGE OF 8-BIT DISP.S
- IF (?DD GT 7FH) AND (?DD LT 0FF80H)
- 'DISPLACEMENT RANGE ERROR - Z80 LIB'
- ENDIF
- ENDM
-LDX MACRO ?R,?D
- @CHK ?D
- DB 0DDH,?R*8+46H,?D ;LDX
- ENDM
-LDY MACRO ?R,?D
- @CHK ?D
- DB 0FDH,?R*8+46H,?D ;LDY
- ENDM
-STX MACRO ?R,?D
- @CHK ?D
- DB 0DDH,70H+?R,?D ;STX
- ENDM
-STY MACRO ?R,?D
- @CHK ?D
- DB 0FDH,70H+?R,?D ;STY
- ENDM
-;
-;MVIX MACRO ?N,?D
-; @CHK ?D
-; DB 0DDH,36H,?D,?N ;MVIX
-; ENDM
-;MVIY MACRO ?N,?D
-; @CHK ?D
-; DB 0FDH,36H,?D,?N ;MVIY
-; ENDM
-
-LDAI MACRO
- DB 0EDH,57H ;LDAI
- ENDM
-LDAR MACRO
- DB 0EDH,5FH ;LDAR
- ENDM
-STAI MACRO
- DB 0EDH,47H ;STAI
- ENDM
-STAR MACRO
- DB 0EDH,4FH ;STAR
- ENDM
-
-LXIX MACRO ?NNNN
- DB 0DDH,21H ;LXIX
- DW ?NNNN
- ENDM
-LXIY MACRO ?NNNN
- DB 0FDH,21H ;LXIY
- DW ?NNNN
- ENDM
-LDED MACRO ?NNNN
- DB 0EDH,5BH ;LDED
- DW ?NNNN
- ENDM
-LBCD MACRO ?NNNN
- DB 0EDH,4BH ;LBCD
- DW ?NNNN
- ENDM
-;
-;LSPD MACRO ?NNNN
-; DB 0EDH,07BH ;LSPD
-; DW ?NNNN
-; ENDM
-;LIXD MACRO ?NNNN
-; DB 0DDH,2AH ;LIXD
-; DW ?NNNN
-; ENDM
-;
-;LIYD MACRO ?NNNN
-; DB 0FDH,2AH ;LIYD
-; DW ?NNNN
-; ENDM
-;
-SBCD MACRO ?NNNN
- DB 0EDH,43H ;SBCD
- DW ?NNNN
- ENDM
-SDED MACRO ?NNNN
- DB 0EDH,53H ;SDED
- DW ?NNNN
- ENDM
-;
-;SSPD MACRO ?NNNN
-; DB 0EDH,73H ;SSPD
-; DW ?NNNN
-; ENDM
-;SIXD MACRO ?NNNN
-; DB 0DDH,22H ;SIXD
-; DW ?NNNN
-; ENDM
-;SIYD MACRO ?NNNN
-; DB 0FDH,22H ;SIYD
-; DW ?NNNN
-; ENDM
-;SPIX MACRO
-; DB 0DDH,0F9H ;SPIX
-; ENDM
-;SPIY MACRO
-; DB 0FDH,0F9H ;SPIY
-; ENDM
-;
-PUSHIX MACRO
- DB 0DDH,0E5H ;PUSHIX
- ENDM
-PUSHIY MACRO
- DB 0FDH,0E5H ;PUSHIY
- ENDM
-POPIX MACRO
- DB 0DDH,0E1H ;POPIX
- ENDM
-POPIY MACRO
- DB 0FDH,0E1H ;POPIY
- ENDM
-EXAF MACRO
- DB 08H ;EXAF
- ENDM
-EXX MACRO
- DB 0D9H ;EXX
- ENDM
-;
-;XTIX MACRO
-; DB 0DDH,0E3H ;XTIX
-; ENDM
-;XTIY MACRO
-; DB 0FDH,0E3H ;XTIY
-; ENDM
-;
-LDI MACRO
- DB 0EDH,0A0H ;LDI
- ENDM
-LDIR MACRO
- DB 0EDH,0B0H ;LDIR
- ENDM
-LDD MACRO
- DB 0EDH,0A8H ;LDD
- ENDM
-LDDR MACRO
- DB 0EDH,0B8H ;LDDR
- ENDM
-CCI MACRO
- DB 0EDH,0A1H ;CCI
- ENDM
-CCIR MACRO
- DB 0EDH,0B1H ;CCIR
- ENDM
-CCD MACRO
- DB 0EDH,0A9H ;CCD
- ENDM
-CCDR MACRO
- DB 0EDH,0B9H ;CCDR
- ENDM
-;
-;ADDX MACRO ?D
-; @CHK ?D
-; DB 0DDH,86H,?D ;ADDX
-; ENDM
-;ADDY MACRO ?D
-; @CHK ?D
-; DB 0FDH,86H,?D ;ADDY
-; ENDM
-;ADCX MACRO ?D
-; @CHK ?D
-; DB 0DDH,8EH,?D ;ADCX
-; ENDM
-;ADCY MACRO ?D
-; @CHK ?D
-; DB 0FDH,8EH,?D ;ADCY
-; ENDM
-;SUBX MACRO ?D
-; @CHK ?D
-; DB 0DDH,96H,?D ;SUBX
-; ENDM
-;SUBY MACRO ?D
-; @CHK ?D
-; DB 0FDH,96H,?D ;SUBY
-; ENDM
-;SBCX MACRO ?D
-; @CHK ?D
-; DB 0DDH,9EH,?D ;SBCX
-; ENDM
-;SBCY MACRO ?D
-; @CHK ?D
-; DB 0FDH,9EH,?D ;SBCY
-; ENDM
-;ANDX MACRO ?D
-; @CHK ?D
-; DB 0DDH,0A6H,?D ;ANDX
-; ENDM
-;ANDY MACRO ?D
-; @CHK ?D
-; DB 0FDH,0A6H,?D ;ANDY
-; ENDM
-;XORX MACRO ?D
-; @CHK ?D
-; DB 0DDH,0AEH,?D ;XORX
-; ENDM
-;XORY MACRO ?D
-; @CHK ?D
-; DB 0FDH,0AEH,?D ;XORY
-; ENDM
-;ORX MACRO ?D
-; @CHK ?D
-; DB 0DDH,0B6H,?D ;ORX
-; ENDM
-;ORY MACRO ?D
-; @CHK ?D
-; DB 0FDH,0B6H,?D ;ORY
-; ENDM
-;CMPX MACRO ?D
-; @CHK ?D
-; DB 0DDH,0BEH,?D ;CMPX
-; ENDM
-;CMPY MACRO ?D
-; @CHK ?D
-; DB 0FDH,0BEH,?D CMPY
-; ENDM
-;INRX MACRO ?D
-; @CHK ?D
-; DB 0DDH,34H,?D ;INRX
-; ENDM
-;INRY MACRO ?D
-; @CHK ?D
-; DB 0FDH,34H,?D ;INRY
-; ENDM
-;DCRX MACRO ?D
-; @CHK ?D
-; DB 0DDH,035H,?D ;DCRX
-; ENDM
-;DCRY MACRO ?D
-; @CHK ?D
-; DB 0FDH,35H,?D ;DCRY
-; ENDM
-;
-NEG MACRO
- DB 0EDH,44H ;NEG
- ENDM
-IM0 MACRO
- DB 0EDH,46H ;IM0
- ENDM
-IM1 MACRO
- DB 0EDH,56H ;IM1
- ENDM
-IM2 MACRO
- DB 0EDH,5EH ;
- ENDM
-;
-BC EQU 0
-DE EQU 2
-HL EQU 4
-IX EQU 4
-IY EQU 4
-;
-DADC MACRO ?R
- DB 0EDH,?R*8+4AH ;DADC
- ENDM
-DSBC MACRO ?R
- DB 0EDH,?R*8+42H ;DSBC
- ENDM
-;
-;DADX MACRO ?R
-; DB 0DDH,?R*8+09H ;DADX
-; ENDM
-;DADY MACRO ?R
-; DB 0FDH,?R*8+09H ;DADY
-; ENDM
-;
-INXIX MACRO
- DB 0DDH,23H ;INXIX
- ENDM
-INXIY MACRO
- DB 0FDH,23H ;INXIY
- ENDM
-DCXIX MACRO
- DB 0DDH,2BH ;DCXIX
- ENDM
-DCXIY MACRO
- DB 0FDH,2BH ;DCXIY
- ENDM
-
-BIT MACRO ?N,?R
- DB 0CBH,?N*8+?R+40H ;BIT
- ENDM
-SETB MACRO ?N,?R
- DB 0CBH,?N*8+?R+0C0H ;SETB
- ENDM
-RESB MACRO ?N,?R
- DB 0CBH,?N*8+?R+80H ;RESB
- ENDM
-
-BITH MACRO ?N
- DB 0CBH,?N*8+46H ;BITH
- ENDM
-BITX MACRO ?N,?D
- @CHK ?D
- DB 0DDH,0CBH,?D,?N*8+46H ;BITX
- ENDM
-BITY MACRO ?N,?D
- @CHK ?D
- DB 0FDH,0CBH,?D,?N*8+46H ;BITY
- ENDM
-SETH MACRO ?N
- DB 0CBH,?N*8+0C6H ;SETH
- ENDM
-SETX MACRO ?N,?D
- @CHK ?D
- DB 0DDH,0CBH,?D,?N*8+0C6H ;SETX
- ENDM
-SETY MACRO ?N,?D
- @CHK ?D
- DB 0FDH,0CBH,?D,?N*8+0C6H ;SETY
- ENDM
-RESH MACRO ?N
- DB 0CBH,?N*8+86H ;RESH
- ENDM
-RESX MACRO ?N,?D
- @CHK ?D
- DB 0DDH,0CBH,?D,?N*8+86H ;RESX
- ENDM
-RESY MACRO ?N,?D
- @CHK ?D
- DB 0FDH,0CBH,?D,?N*8+86H ;RESY
- ENDM
-
-JR MACRO ?N
- DB 18H,?N-$-1 ;JR
- ENDM
-JRC MACRO ?N
- DB 38H,?N-$-1 ;JRC
- ENDM
-JRNC MACRO ?N
- DB 30H,?N-$-1 ;JRNC
- ENDM
-JRZ MACRO ?N
- DB 28H,?N-$-1 ;JRZ
- ENDM
-JRNZ MACRO ?N
- DB 20H,?N-$-1 ;JRNZ
- ENDM
-DJNZ MACRO ?N
- DB 10H,?N-$-1 ;DJNZ
- ENDM
-;
-;PCIX MACRO
-; DB 0DDH,0E9H ;PCIX
-; ENDM
-;PCIY MACRO
-; DB 0FDH,0E9H ;PCIY
-; ENDM
-;
-RETI MACRO
- DB 0EDH,4DH ;RETI
- ENDM
-RETN MACRO
- DB 0EDH,45H ;RETN
- ENDM
-
-INP MACRO ?R
- DB 0EDH,?R*8+40H ;INP
- ENDM
-OUTP MACRO ?R
- DB 0EDH,?R*8+41H ;OUTP
- ENDM
-INI MACRO
- DB 0EDH,0A2H ;INI
- ENDM
-INIR MACRO
- DB 0EDH,0B2H ;INIR
- ENDM
-IND MACRO
- DB 0EDH,0AAH ;IND
- ENDM
-INDR MACRO
- DB 0EDH,0BAH ;INDR
- ENDM
-OUTI MACRO
- DB 0EDH,0A3H ;OUTI
- ENDM
-OUTIR MACRO
- DB 0EDH,0B3H ;OUTIR
- ENDM
-OUTD MACRO
- DB 0EDH,0ABH ;OUTD
- ENDM
-OUTDR MACRO
- DB 0EDH,0BBH ;OUTDR
- ENDM
-;
-;RLCR MACRO ?R
-; DB 0CBH, 00H + ?R ;RLCR
-; ENDM
-;RLCX MACRO ?D
-; @CHK ?D
-; DB 0DDH, 0CBH, ?D, 06H ;RLCX
-; ENDM
-;RLCY MACRO ?D
-; @CHK ?D
-; DB 0FDH, 0CBH, ?D, 06H ;RLCY
-; ENDM
-;RALR MACRO ?R
-; DB 0CBH, 10H+?R ;RALR
-; ENDM
-;RALX MACRO ?D
-; @CHK ?D
-; DB 0DDH, 0CBH, ?D, 16H ;RALX
-; ENDM
-;RALY MACRO ?D
-; @CHK ?D
-; DB 0FDH, 0CBH, ?D, 16H ;RALY
-; ENDM
-;RRCR MACRO ?R
-; DB 0CBH, 08H + ?R ;RRCR
-; ENDM
-;RRCX MACRO ?D
-; @CHK ?D
-; DB 0DDH, 0CBH, ?D, 0EH ;RRCX
-; ENDM
-;RRCY MACRO ?D
-; @CHK ?D
-; DB 0FDH, 0CBH, ?D, 0EH ;RRCY
-; ENDM
-;RARR MACRO ?R
-; DB 0CBH, 18H + ?R ;RARR
-; ENDM
-;RARX MACRO ?D
-; @CHK ?D
-; DB 0DDH, 0CBH, ?D, 1EH ;RARX
-; ENDM
-;RARY MACRO ?D
-; @CHK ?D
-; DB 0FDH, 0CBH, ?D, 1EH ;RARY
-; ENDM
-;SLAR MACRO ?R
-; DB 0CBH, 20H + ?R ;SLAR
-; ENDM
-;SLAX MACRO ?D
-; @CHK ?D
-; DB 0DDH, 0CBH, ?D, 26H ;SLAX
-; ENDM
-;SLAY MACRO ?D
-; @CHK ?D
-; DB 0FDH, 0CBH, ?D, 26H ;SLAY
-; ENDM
-;SRAR MACRO ?R
-; DB 0CBH, 28H+?R ;SRAR
-; ENDM
-;SRAX MACRO ?D
-; @CHK ?D
-; DB 0DDH, 0CBH, ?D, 2EH ;SRAX
-; ENDM
-;SRAY MACRO ?D
-; @CHK ?D
-; DB 0FDH, 0CBH, ?D, 2EH ;SRAY
-; ENDM
-;SRLR MACRO ?R
-; DB 0CBH, 38H + ?R ;SRLR
-; ENDM
-;SRLX MACRO ?D
-; @CHK ?D
-; DB 0DDH, 0CBH, ?D, 3EH ;SRLX
-; ENDM
-;SRLY MACRO ?D
-; @CHK ?D
-; DB 0FDH, 0CBH, ?D, 3EH ;SRLY
-; ENDM
-;RLD MACRO
-; DB 0EDH, 6FH ;RLD
-; ENDM
-RRD MACRO
- DB 0EDH, 67H ;RRD
- ENDM
-
Index: DE1/ROM/HexFiles/rom.vhd
===================================================================
--- DE1/ROM/HexFiles/rom.vhd (revision 8)
+++ DE1/ROM/HexFiles/rom.vhd (nonexistent)
@@ -1,52 +0,0 @@
-library IEEE;
-use IEEE.std_logic_1164.all;
-use ieee.numeric_std.all;
-entity rom is
- port(
- Clk : in std_logic;
- A : in std_logic_vector(13 downto 0);
- D : out std_logic_vector(7 downto 0)
- );
-end rom;
-architecture rtl of rom is
-begin
-process (Clk)
-begin
- if Clk'event and Clk = '1' then
- case A is
- when "00000000000000" => D <= x"C3";
- when "00000000000001" => D <= x"72";
- when "00000000000010" => D <= x"00";
- when "00000000000011" => D <= x"FF";
- when "00000000000100" => D <= x"AA";
- when "00000000000101" => D <= x"00";
- when "00000000000110" => D <= x"8C";
- when "00000000000111" => D <= x"0C";
- when "00000000001000" => D <= x"01";
- when "00000000001001" => D <= x"00";
- when "00000000001010" => D <= x"00";
- when "00000000001011" => D <= x"00";
- when "00000000001100" => D <= x"00";
- when "00000000001101" => D <= x"00";
- when "00000000001110" => D <= x"00";
- when "00000000001111" => D <= x"00";
- when "00000000010000" => D <= x"00";
- when "00000000010001" => D <= x"00";
- when "00000000010010" => D <= x"00";
- when "00000000010011" => D <= x"00";
- when "00000000010100" => D <= x"00";
- when "00000000010101" => D <= x"00";
- when "00000000010110" => D <= x"00";
- when "00000000010111" => D <= x"00";
- when "00000000011000" => D <= x"00";
- when "00000000011001" => D <= x"00";
- when "00000000011010" => D <= x"00";
- when "00000000011011" => D <= x"00";
- when "00000000011100" => D <= x"00";
- when "00000000011101" => D <= x"00";
- when "00000000011110" => D <= x"00";
- when others => D <= "ZZZZZZZZ";
- end case;
- end if;
-end process;
-end;
Index: DE1/ROM/HexFiles/rom.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: DE1/ROM/HexFiles/rom.bin
===================================================================
--- DE1/ROM/HexFiles/rom.bin (revision 8)
+++ DE1/ROM/HexFiles/rom.bin (nonexistent)
DE1/ROM/HexFiles/rom.bin
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: DE1/ROM/HexFiles/z80test.hex
===================================================================
--- DE1/ROM/HexFiles/z80test.hex (revision 8)
+++ DE1/ROM/HexFiles/z80test.hex (nonexistent)
@@ -1,12 +0,0 @@
-:10000000C37200FFAA008C0C010000000000000079
-:1000100000000000000000000000000000000000E0
-:100020000000000000C3720000000000000000009B
-:1000300000000000000000000000000000C372008B
-:0E0040000000000000000000000000009A0018
-:03006600C3900044
-:10007200F331EADFED5E010000FBCDA000CDA00070
-:10008200CDA000790CD310D324D302C37B00F5C5D5
-:10009200D5E5E1D1C1F1ED45DB24D311FBC9C501A1
-:0E00A20000400DC2A40005C2A400C1C9FFFFAA
-:0000000000
-
\ No newline at end of file
Index: DE1/ROM/Z80TEST.SYM
===================================================================
--- DE1/ROM/Z80TEST.SYM (revision 8)
+++ DE1/ROM/Z80TEST.SYM (nonexistent)
@@ -1,5 +0,0 @@
-0000 BC 0008 CHIP1ID 00AE CHPEND 009A COMMAIN 0002 DE
-00A0 DELAY 00A4 DELLOP 0004 HL 004C IBMVECT 0004 IX
-0004 IY 007B MAINLOOP 0090 POWERF 0072 SFTSTART0 0072 SFTSTART2
-0000 START 0072 STARTU
-
\ No newline at end of file
Index: DE1/ROM/M.TMP
===================================================================
--- DE1/ROM/M.TMP (revision 8)
+++ DE1/ROM/M.TMP (nonexistent)
@@ -1,11 +0,0 @@
-Version 1.00 - 29-Jan-1987
-80 23
-SRCH:COMMAIN
-SRC:
-DST:
-> 0 0 80 23
- c:\altera\cores\vhdl\z80con~1\z80con~1\trunk\de1\rom\z80test.asm 0 0 0 0
- c:\altera\cores\vhdl\z80con~1\de1\rom\z80test.prn 0 147 16 150
- c:\altera\cores\vhdl\z80con~1\de1\rom\z80test.asm 0 78 46 99
- c:\altera\cores\vhdl\z80con~1\de1\rom\z80.lib 0 460 0 460
-
Index: DE1/ROM/HexToBinary.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: DE1/ROM/HexToBinary.exe
===================================================================
--- DE1/ROM/HexToBinary.exe (revision 8)
+++ DE1/ROM/HexToBinary.exe (nonexistent)
DE1/ROM/HexToBinary.exe
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: DE1/ROM/Z80TEST.BAK
===================================================================
--- DE1/ROM/Z80TEST.BAK (revision 8)
+++ DE1/ROM/Z80TEST.BAK (nonexistent)
@@ -1,167 +0,0 @@
-;
-MACLIB Z80
-;
- ORG 0
-;
-START JMP STARTU
- ;
- DB 0FFH
- DW (CHPEND-4)
- DW 3212
-;
-CHIP1ID DB 1 ;CHIP I.D. NUMBER
-;
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- JMP SFTSTART0
-;
-;
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- JMP SFTSTART2
-;
-;
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
-IBMVECT
- DW COMMAIN ;WAS CRTINP ;ARECEIVE
-;
-;@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-;
-; NON MASKABLE INT.
-;
- ORG 66H ;TRAP
-;
- JMP POWERF
-;
-;******************************
-;
- ORG 72H
-;
-
-SFTSTART0
-SFTSTART2
-;
-; POWER UP START UP
-;
-; @ @ @ USED TO TEST COMM @ @ @
-;
-STARTU
- DI
-
- LXI SP,0DFEAH
-
- IM2 ; SET Z80 INT MODE
-
- LXI B,0
-MAINLOOP
- EI
-
- CALL DELAY
- CALL DELAY
- CALL DELAY
-
-
- MOV A,C
- INR C
-
- OUT 10H ; HEX DISPLAY 0,1
-
- OUT 024H ; COMPORT
-
- OUT 002H ; LEDG
-
- JMP MAINLOOP
-
-;
-;
-POWERF PUSH PSW ;+1 NMSK INT 60 TIMES A SEC
- PUSH B ;+2
- PUSH D ;+3
- PUSH H ;+4
-;
- POP H
- POP D
- POP B
- POP PSW
- RETN
-;
-
-
-;4CH
-COMMAIN
- IN 24H ; COMMPORT
- OUT 11H ; HEX DISPLAY
- EI
- RET
-
-
-
-DELAY PUSH B
- LXI B,4000H
-DELLOP
- DCR C
- JNZ DELLOP
- DCR B
- JNZ DELLOP
- POP B
- RET
-
-CHPEND DW 0FFFFH
-;
- END START
Index: DE1/ROM/tools.ini
===================================================================
--- DE1/ROM/tools.ini (revision 8)
+++ DE1/ROM/tools.ini (nonexistent)
@@ -1,156 +0,0 @@
-; TOOLS.INI file for QUICK configuration
-
-[M]
-Arg:Alt+A
-Assign:Alt+=
-Backtab:Shift+Tab
-Begline:Home
-Cancel:Esc
-Cdelete:Ctrl+G
-Compile:Shift+F3
-Copy:Ctrl+Ins
-Down:Down
-Down:Ctrl+X
-Emacscdel:Bksp
-Emacsnewl:Enter
-Endline:End
-Execute:f10
-Exit:Alt+X
-exit:f10
-Help:F1
-Home:Ctrl+Home
-Information:Shift+F1
-Initialize:Alt+F10
-Insertmode:Ins
-Insertmode:Ctrl+V
-Lasttext:Alt+L
-Ldelete:Ctrl+Y
-Left:Left
-Linsert:Ctrl+N
-Mark:Alt+M
-Meta:F9
-Mlines:Ctrl+W
-Mpage:Pgup
-Mpage:Ctrl+R
-Mpara:Ctrl+Pgup
-Msearch:F4
-Mword:Ctrl+Left
-Paste:Shift+Ins
-Pbal:Ctrl+[
-Plines:Ctrl+Z
-Ppage:Pgdn
-Ppage:Ctrl+C
-Ppara:Ctrl+Pgdn
-Psearch:F3
-Pword:Ctrl+Right
-Pword:Ctrl+F
-Qreplace:Alt+F3
-Quote:Alt+Q
-Refresh:Alt+R
-Replace:Ctrl+L
-Right:Right
-Right:Ctrl+D
-Sdelete:Del
-Setfile:F2
-Setwindow:Ctrl+]
-Shell:Shift+F9
-Sinsert:Alt+Ins
-Tab:Tab
-Undo:Alt+Bksp
-Up:Up
-Up:Ctrl+E
-Window:F6
-;
-; to load the wordstar extension to enable ctrl+QS and ctrl+QD
-; remove the semicolon from the following line and fill in the correct
-; path
-; load:ws.zxt
-Tabstops:10
-Fgcolor:17
-Rmargin:80
-Vscroll:1
-Hscroll:1
-Hike:1
-Backup:bak
-
-donot:=META CURDAY " " CURDATE " " CURTIME
-donot:f5
-
-Curtime:Alt+T
-
-DTATE:=META CURDAY " " CURDATE " " CURTIME
-DTATE:ALT+D
-
-
-ONEDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
-ONEDEL:CTRL+O
-
-BACKDEL:=META CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE CDELETE
-BACKDEL:CTRL+B
-
-COP2LIN:= DOWN Ldelete Ldelete Ldelete Ldelete
-COP2LIN:ALT+Y
-
-COPYADR:=ARG RIGHT RIGHT RIGHT RIGHT RIGHT SDELETE
-COPYADR:ALT+C
-
-MOVADR:=COPYADR RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT DOWN LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT LEFT
-MOVADR:ALT+V
-
-SSWLB2:=DOWN LEFT LEFT LEFT LEFT " "
-SSWLB2:ALT+S
-
-SSWDEL:=META SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE SDELETE DOWN
-SSWDEL:ALT+W
-
-ISWDEL:=DOWN META BEGLINE ";"
-ISWDEL:ALT+N
-
-SLDD:=DOWN BEGLINE " "
-SLDD:ALT+U
-
-
-PLACE00:=META "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT "0" DOWN LEFT
-PLACE00:ALT+`
-
-PLACE1:=META "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT "1" DOWN LEFT
-PLACE1:ALT+1
-
-PLACE2:=META "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT "2" DOWN LEFT
-PLACE2:ALT+2
-
-PLACE3:=META "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT "3" DOWN LEFT
-PLACE3:ALT+3
-
-PLACE4:=META "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT "4" DOWN LEFT
-PLACE4:ALT+4
-
-PLACE5:=META "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT "5" DOWN LEFT
-PLACE5:ALT+5
-
-PLACE6:=META "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT "6" DOWN LEFT
-PLACE6:ALT+6
-
-PLACE7:=META "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT "7" DOWN LEFT
-PLACE7:ALT+7
-
-PLACE8:=META "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT "8" DOWN LEFT
-PLACE8:ALT+8
-
-PLACE9:=META "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT "9" DOWN LEFT
-PLACE9:ALT+9
-
-PLACE0:=META "0" DOWN LEFT "1" DOWN LEFT "2" DOWN LEFT "3" DOWN LEFT "4" DOWN LEFT "5" DOWN LEFT "6" DOWN LEFT "7" DOWN LEFT "8" DOWN LEFT "9" DOWN LEFT
-PLACE0:ALT+0
-;
-PCHEK:=META PPAGE SETFILE PPAGE
-PCHEK:ALT+G
-;
-CHWIN:=META SETFILE
-CHWIN:ALT+F
-;
-MOVAD:=BEGLINE ARG TAB SDELETE DOWN TAB "EQU " PASTE DOWN
-MOVAD:ALT+J
-;
-DOIT:=ARG TAB TAB TAB RIGHT RIGHT SDELETE BEGLINE DOWN DOWN
-DOIT:CTRL+P
Index: DE1/ROM/Z80TEST.PRN
===================================================================
--- DE1/ROM/Z80TEST.PRN (revision 8)
+++ DE1/ROM/Z80TEST.PRN (nonexistent)
@@ -1,170 +0,0 @@
- ;
- MACLIB Z80
- ;
- 0000 ORG 0
- ;
- 0000 C37200 START JMP STARTU
- ;
- 0003 FF DB 0FFH
- 0004 AA00 DW (CHPEND-4)
- 0006 8C0C DW 3212
- ;
- 0008 01 CHIP1ID DB 1 ;CHIP I.D. NUMBER
- ;
- 0009 00 NOP
- 000A 00 NOP
- 000B 00 NOP
- 000C 00 NOP
- 000D 00 NOP
- 000E 00 NOP
- 000F 00 NOP
- 0010 00 NOP
- 0011 00 NOP
- 0012 00 NOP
- 0013 00 NOP
- 0014 00 NOP
- 0015 00 NOP
- 0016 00 NOP
- 0017 00 NOP
- 0018 00 NOP
- 0019 00 NOP
- 001A 00 NOP
- 001B 00 NOP
- 001C 00 NOP
- 001D 00 NOP
- 001E 00 NOP
- 001F 00 NOP
- 0020 00 NOP
- 0021 00 NOP
- 0022 00 NOP
- 0023 00 NOP
- 0024 00 NOP
- 0025 C37200 JMP SFTSTART0
- ;
- ;
- 0028 00 NOP
- 0029 00 NOP
- 002A 00 NOP
- 002B 00 NOP
- 002C 00 NOP
- 002D 00 NOP
- 002E 00 NOP
- 002F 00 NOP
- 0030 00 NOP
- 0031 00 NOP
- 0032 00 NOP
- 0033 00 NOP
- 0034 00 NOP
- 0035 00 NOP
- 0036 00 NOP
- 0037 00 NOP
- 0038 00 NOP
- 0039 00 NOP
- 003A 00 NOP
- 003B 00 NOP
- 003C 00 NOP
- 003D C37200 JMP SFTSTART2
- ;
- ;
- 0040 00 NOP
- 0041 00 NOP
- 0042 00 NOP
- 0043 00 NOP
- 0044 00 NOP
- 0045 00 NOP
- 0046 00 NOP
- 0047 00 NOP
- 0048 00 NOP
- 0049 00 NOP
- 004A 00 NOP
- 004B 00 NOP
- IBMVECT
- 004C 9A00 DW COMMAIN ;WAS CRTINP ;ARECEIVE
- ;
- ;@@@@@@@@@@@@@@@@@@@@@@@@@@@@
- ;
- ; NON MASKABLE INT.
- ;
- 0066 ORG 66H ;TRAP
- ;
- 0066 C39000 JMP POWERF
- ;
- ;******************************
- ;
- 0072 ORG 72H
- ;
-
- SFTSTART0
- SFTSTART2
- ;
- ; POWER UP START UP
- ;
- ; @ @ @ USED TO TEST COMM @ @ @
- ;
- STARTU
- 0072 F3 DI
-
- 0073 31EADF LXI SP,0DFEAH
-
- IM2 ; SET Z80 INT MODE
- 0076+ED5E DB 0EDH,5EH ;
-
- 0078 010000 LXI B,0
- MAINLOOP
- 007B FB EI
-
- 007C CDA000 CALL DELAY
- 007F CDA000 CALL DELAY
- 0082 CDA000 CALL DELAY
-
-
- 0085 79 MOV A,C
- 0086 0C INR C
-
- 0087 D310 OUT 10H ; HEX DISPLAY 0,1
-
- 0089 D324 OUT 024H ; COMPORT
-
- 008B D302 OUT 002H ; LEDR
-
- 008D C37B00 JMP MAINLOOP
-
- ;
- ;
- 0090 F5 POWERF PUSH PSW ;+1 NMSK INT 60 TIMES A SEC
- 0091 C5 PUSH B ;+2
- 0092 D5 PUSH D ;+3
- 0093 E5 PUSH H ;+4
- ;
- 0094 E1 POP H
- 0095 D1 POP D
- 0096 C1 POP B
- 0097 F1 POP PSW
- RETN
- 0098+ED45 DB 0EDH,45H ;RETN
- ;
-
-
- ;4CH
- COMMAIN
- 009A DB24 IN 24H ; COMMPORT
- 009C D311 OUT 11H ; HEX DISPLAY
- 009E FB EI
- 009F C9 RET
-
-
-
- 00A0 C5 DELAY PUSH B
- 00A1 010040 LXI B,4000H
- DELLOP
- 00A4 0D DCR C
- 00A5 C2A400 JNZ DELLOP
- 00A8 05 DCR B
- 00A9 C2A400 JNZ DELLOP
- 00AC C1 POP B
- 00AD C9 RET
-
- 00AE FFFF CHPEND DW 0FFFFH
- ;
- 00B0 END START
-
\ No newline at end of file
Index: DE1/ROM/Z80TEST.ASM
===================================================================
--- DE1/ROM/Z80TEST.ASM (revision 8)
+++ DE1/ROM/Z80TEST.ASM (nonexistent)
@@ -1,167 +0,0 @@
-;
-MACLIB Z80
-;
- ORG 0
-;
-START JMP STARTU
- ;
- DB 0FFH
- DW (CHPEND-4)
- DW 3212
-;
-CHIP1ID DB 1 ;CHIP I.D. NUMBER
-;
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- JMP SFTSTART0
-;
-;
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- JMP SFTSTART2
-;
-;
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
- NOP
-IBMVECT
- DW COMMAIN ;WAS CRTINP ;ARECEIVE
-;
-;@@@@@@@@@@@@@@@@@@@@@@@@@@@@
-;
-; NON MASKABLE INT.
-;
- ORG 66H ;TRAP
-;
- JMP POWERF
-;
-;******************************
-;
- ORG 72H
-;
-
-SFTSTART0
-SFTSTART2
-;
-; POWER UP START UP
-;
-; @ @ @ USED TO TEST COMM @ @ @
-;
-STARTU
- DI
-
- LXI SP,0DFEAH
-
- IM2 ; SET Z80 INT MODE
-
- LXI B,0
-MAINLOOP
- EI
-
- CALL DELAY
- CALL DELAY
- CALL DELAY
-
-
- MOV A,C
- INR C
-
- OUT 10H ; HEX DISPLAY 0,1
-
- OUT 024H ; COMPORT
-
- OUT 002H ; LEDR
-
- JMP MAINLOOP
-
-;
-;
-POWERF PUSH PSW ;+1 NMSK INT 60 TIMES A SEC
- PUSH B ;+2
- PUSH D ;+3
- PUSH H ;+4
-;
- POP H
- POP D
- POP B
- POP PSW
- RETN
-;
-
-
-;4CH
-COMMAIN
- IN 24H ; COMMPORT
- OUT 11H ; HEX DISPLAY
- EI
- RET
-
-
-
-DELAY PUSH B
- LXI B,4000H
-DELLOP
- DCR C
- JNZ DELLOP
- DCR B
- JNZ DELLOP
- POP B
- RET
-
-CHPEND DW 0FFFFH
-;
- END START
Index: DE1/ROM/Z80TEST.HEX
===================================================================
--- DE1/ROM/Z80TEST.HEX (revision 8)
+++ DE1/ROM/Z80TEST.HEX (nonexistent)
@@ -1,12 +0,0 @@
-:10000000C37200FFAA008C0C010000000000000079
-:1000100000000000000000000000000000000000E0
-:100020000000000000C3720000000000000000009B
-:1000300000000000000000000000000000C372008B
-:0E0040000000000000000000000000009A0018
-:03006600C3900044
-:10007200F331EADFED5E010000FBCDA000CDA00070
-:10008200CDA000790CD310D324D302C37B00F5C5D5
-:10009200D5E5E1D1C1F1ED45DB24D311FBC9C501A1
-:0E00A20000400DC2A40005C2A400C1C9FFFFAA
-:0000000000
-
\ No newline at end of file
Index: DE1/z80soc.qsf
===================================================================
--- DE1/z80soc.qsf (revision 8)
+++ DE1/z80soc.qsf (nonexistent)
@@ -1,515 +0,0 @@
-# Copyright (C) 1991-2007 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Altera Program License
-# Subscription Agreement, Altera MegaCore Function License
-# Agreement, or other applicable license agreement, including,
-# without limitation, that your use is for the sole purpose of
-# programming logic devices manufactured by Altera and sold by
-# Altera or its authorized distributors. Please refer to the
-# applicable agreement for further details.
-
-
-# The default values for assignments are stored in the file
-# z80soc_caps_assignment_defaults.qdf
-# If this file doesn't exist, and for assignments not listed, see file
-# assignment_defaults.qdf
-
-# Altera recommends that you do not modify this file. This
-# file is updated automatically by the Quartus II software
-# and any changes you make may be lost or overwritten.
-
-
-set_global_assignment -name FAMILY "Cyclone II"
-set_global_assignment -name DEVICE EP2C20F484C7
-set_global_assignment -name TOP_LEVEL_ENTITY top_de1
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:43:12 MAY 01, 2008"
-set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
-set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
-set_global_assignment -name ENABLE_DA_RULE "C101, C102, C103, C104, C105, C106, R101, R102, R103, R104, R105, T101, T102, A101, A102, A103, A104, A105, A106, A107, A108, A109, A110, S101, S102, S103, S104, D101, D102, D103, H101, H102, M101, M102, M103, M104, M105"
-set_location_assignment PIN_A13 -to GPIO_0[0]
-set_location_assignment PIN_B13 -to GPIO_0[1]
-set_location_assignment PIN_A14 -to GPIO_0[2]
-set_location_assignment PIN_B14 -to GPIO_0[3]
-set_location_assignment PIN_A15 -to GPIO_0[4]
-set_location_assignment PIN_B15 -to GPIO_0[5]
-set_location_assignment PIN_A16 -to GPIO_0[6]
-set_location_assignment PIN_B16 -to GPIO_0[7]
-set_location_assignment PIN_A17 -to GPIO_0[8]
-set_location_assignment PIN_B17 -to GPIO_0[9]
-set_location_assignment PIN_A18 -to GPIO_0[10]
-set_location_assignment PIN_B18 -to GPIO_0[11]
-set_location_assignment PIN_A19 -to GPIO_0[12]
-set_location_assignment PIN_B19 -to GPIO_0[13]
-set_location_assignment PIN_A20 -to GPIO_0[14]
-set_location_assignment PIN_B20 -to GPIO_0[15]
-set_location_assignment PIN_C21 -to GPIO_0[16]
-set_location_assignment PIN_C22 -to GPIO_0[17]
-set_location_assignment PIN_D21 -to GPIO_0[18]
-set_location_assignment PIN_D22 -to GPIO_0[19]
-set_location_assignment PIN_E21 -to GPIO_0[20]
-set_location_assignment PIN_E22 -to GPIO_0[21]
-set_location_assignment PIN_F21 -to GPIO_0[22]
-set_location_assignment PIN_F22 -to GPIO_0[23]
-set_location_assignment PIN_G21 -to GPIO_0[24]
-set_location_assignment PIN_G22 -to GPIO_0[25]
-set_location_assignment PIN_J21 -to GPIO_0[26]
-set_location_assignment PIN_J22 -to GPIO_0[27]
-set_location_assignment PIN_K21 -to GPIO_0[28]
-set_location_assignment PIN_K22 -to GPIO_0[29]
-set_location_assignment PIN_J19 -to GPIO_0[30]
-set_location_assignment PIN_J20 -to GPIO_0[31]
-set_location_assignment PIN_J18 -to GPIO_0[32]
-set_location_assignment PIN_K20 -to GPIO_0[33]
-set_location_assignment PIN_L19 -to GPIO_0[34]
-set_location_assignment PIN_L18 -to GPIO_0[35]
-set_location_assignment PIN_H12 -to GPIO_1[0]
-set_location_assignment PIN_H13 -to GPIO_1[1]
-set_location_assignment PIN_H14 -to GPIO_1[2]
-set_location_assignment PIN_G15 -to GPIO_1[3]
-set_location_assignment PIN_E14 -to GPIO_1[4]
-set_location_assignment PIN_E15 -to GPIO_1[5]
-set_location_assignment PIN_F15 -to GPIO_1[6]
-set_location_assignment PIN_G16 -to GPIO_1[7]
-set_location_assignment PIN_F12 -to GPIO_1[8]
-set_location_assignment PIN_F13 -to GPIO_1[9]
-set_location_assignment PIN_C14 -to GPIO_1[10]
-set_location_assignment PIN_D14 -to GPIO_1[11]
-set_location_assignment PIN_D15 -to GPIO_1[12]
-set_location_assignment PIN_D16 -to GPIO_1[13]
-set_location_assignment PIN_C17 -to GPIO_1[14]
-set_location_assignment PIN_C18 -to GPIO_1[15]
-set_location_assignment PIN_C19 -to GPIO_1[16]
-set_location_assignment PIN_C20 -to GPIO_1[17]
-set_location_assignment PIN_D19 -to GPIO_1[18]
-set_location_assignment PIN_D20 -to GPIO_1[19]
-set_location_assignment PIN_E20 -to GPIO_1[20]
-set_location_assignment PIN_F20 -to GPIO_1[21]
-set_location_assignment PIN_E19 -to GPIO_1[22]
-set_location_assignment PIN_E18 -to GPIO_1[23]
-set_location_assignment PIN_G20 -to GPIO_1[24]
-set_location_assignment PIN_G18 -to GPIO_1[25]
-set_location_assignment PIN_G17 -to GPIO_1[26]
-set_location_assignment PIN_H17 -to GPIO_1[27]
-set_location_assignment PIN_J15 -to GPIO_1[28]
-set_location_assignment PIN_H18 -to GPIO_1[29]
-set_location_assignment PIN_N22 -to GPIO_1[30]
-set_location_assignment PIN_N21 -to GPIO_1[31]
-set_location_assignment PIN_P15 -to GPIO_1[32]
-set_location_assignment PIN_N15 -to GPIO_1[33]
-set_location_assignment PIN_P17 -to GPIO_1[34]
-set_location_assignment PIN_P18 -to GPIO_1[35]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[26]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[29]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
-set_location_assignment PIN_L22 -to SW[0]
-set_location_assignment PIN_L21 -to SW[1]
-set_location_assignment PIN_M22 -to SW[2]
-set_location_assignment PIN_V12 -to SW[3]
-set_location_assignment PIN_W12 -to SW[4]
-set_location_assignment PIN_U12 -to SW[5]
-set_location_assignment PIN_U11 -to SW[6]
-set_location_assignment PIN_M2 -to SW[7]
-set_location_assignment PIN_M1 -to SW[8]
-set_location_assignment PIN_L2 -to SW[9]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
-set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
-set_location_assignment PIN_J2 -to HEX0[0]
-set_location_assignment PIN_J1 -to HEX0[1]
-set_location_assignment PIN_H2 -to HEX0[2]
-set_location_assignment PIN_H1 -to HEX0[3]
-set_location_assignment PIN_F2 -to HEX0[4]
-set_location_assignment PIN_F1 -to HEX0[5]
-set_location_assignment PIN_E2 -to HEX0[6]
-set_location_assignment PIN_E1 -to HEX1[0]
-set_location_assignment PIN_H6 -to HEX1[1]
-set_location_assignment PIN_H5 -to HEX1[2]
-set_location_assignment PIN_H4 -to HEX1[3]
-set_location_assignment PIN_G3 -to HEX1[4]
-set_location_assignment PIN_D2 -to HEX1[5]
-set_location_assignment PIN_D1 -to HEX1[6]
-set_location_assignment PIN_G5 -to HEX2[0]
-set_location_assignment PIN_G6 -to HEX2[1]
-set_location_assignment PIN_C2 -to HEX2[2]
-set_location_assignment PIN_C1 -to HEX2[3]
-set_location_assignment PIN_E3 -to HEX2[4]
-set_location_assignment PIN_E4 -to HEX2[5]
-set_location_assignment PIN_D3 -to HEX2[6]
-set_location_assignment PIN_F4 -to HEX3[0]
-set_location_assignment PIN_D5 -to HEX3[1]
-set_location_assignment PIN_D6 -to HEX3[2]
-set_location_assignment PIN_J4 -to HEX3[3]
-set_location_assignment PIN_L8 -to HEX3[4]
-set_location_assignment PIN_F3 -to HEX3[5]
-set_location_assignment PIN_D4 -to HEX3[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
-set_location_assignment PIN_R22 -to KEY[0]
-set_location_assignment PIN_R21 -to KEY[1]
-set_location_assignment PIN_T22 -to KEY[2]
-set_location_assignment PIN_T21 -to KEY[3]
-set_location_assignment PIN_R20 -to LEDR[0]
-set_location_assignment PIN_R19 -to LEDR[1]
-set_location_assignment PIN_U19 -to LEDR[2]
-set_location_assignment PIN_Y19 -to LEDR[3]
-set_location_assignment PIN_T18 -to LEDR[4]
-set_location_assignment PIN_V19 -to LEDR[5]
-set_location_assignment PIN_Y18 -to LEDR[6]
-set_location_assignment PIN_U18 -to LEDR[7]
-set_location_assignment PIN_R18 -to LEDR[8]
-set_location_assignment PIN_R17 -to LEDR[9]
-set_location_assignment PIN_U22 -to LEDG[0]
-set_location_assignment PIN_U21 -to LEDG[1]
-set_location_assignment PIN_V22 -to LEDG[2]
-set_location_assignment PIN_V21 -to LEDG[3]
-set_location_assignment PIN_W22 -to LEDG[4]
-set_location_assignment PIN_W21 -to LEDG[5]
-set_location_assignment PIN_Y22 -to LEDG[6]
-set_location_assignment PIN_Y21 -to LEDG[7]
-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
-set_location_assignment PIN_D12 -to CLOCK_27[0]
-set_location_assignment PIN_E12 -to CLOCK_27[1]
-set_location_assignment PIN_B12 -to CLOCK_24[0]
-set_location_assignment PIN_A12 -to CLOCK_24[1]
-set_location_assignment PIN_L1 -to CLOCK_50
-set_location_assignment PIN_M21 -to EXT_CLOCK
-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
-set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
-set_location_assignment PIN_H15 -to PS2_CLK
-set_location_assignment PIN_J14 -to PS2_DAT
-set_location_assignment PIN_F14 -to UART_RXD
-set_location_assignment PIN_G12 -to UART_TXD
-set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
-set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
-set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
-set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
-set_location_assignment PIN_E8 -to TDI
-set_location_assignment PIN_D8 -to TCS
-set_location_assignment PIN_C7 -to TCK
-set_location_assignment PIN_D7 -to TDO
-set_instance_assignment -name IO_STANDARD LVTTL -to TDI
-set_instance_assignment -name IO_STANDARD LVTTL -to TCS
-set_instance_assignment -name IO_STANDARD LVTTL -to TCK
-set_instance_assignment -name IO_STANDARD LVTTL -to TDO
-set_location_assignment PIN_D9 -to VGA_R[0]
-set_location_assignment PIN_C9 -to VGA_R[1]
-set_location_assignment PIN_A7 -to VGA_R[2]
-set_location_assignment PIN_B7 -to VGA_R[3]
-set_location_assignment PIN_B8 -to VGA_G[0]
-set_location_assignment PIN_C10 -to VGA_G[1]
-set_location_assignment PIN_B9 -to VGA_G[2]
-set_location_assignment PIN_A8 -to VGA_G[3]
-set_location_assignment PIN_A9 -to VGA_B[0]
-set_location_assignment PIN_D11 -to VGA_B[1]
-set_location_assignment PIN_A10 -to VGA_B[2]
-set_location_assignment PIN_B10 -to VGA_B[3]
-set_location_assignment PIN_A11 -to VGA_HS
-set_location_assignment PIN_B11 -to VGA_VS
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
-set_location_assignment PIN_A3 -to I2C_SCLK
-set_location_assignment PIN_B3 -to I2C_SDAT
-set_location_assignment PIN_A6 -to AUD_ADCLRCK
-set_location_assignment PIN_B6 -to AUD_ADCDAT
-set_location_assignment PIN_A5 -to AUD_DACLRCK
-set_location_assignment PIN_B5 -to AUD_DACDAT
-set_location_assignment PIN_B4 -to AUD_XCK
-set_location_assignment PIN_A4 -to AUD_BCLK
-set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
-set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
-set_location_assignment PIN_W4 -to DRAM_ADDR[0]
-set_location_assignment PIN_W5 -to DRAM_ADDR[1]
-set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
-set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
-set_location_assignment PIN_R6 -to DRAM_ADDR[4]
-set_location_assignment PIN_R5 -to DRAM_ADDR[5]
-set_location_assignment PIN_P6 -to DRAM_ADDR[6]
-set_location_assignment PIN_P5 -to DRAM_ADDR[7]
-set_location_assignment PIN_P3 -to DRAM_ADDR[8]
-set_location_assignment PIN_N4 -to DRAM_ADDR[9]
-set_location_assignment PIN_W3 -to DRAM_ADDR[10]
-set_location_assignment PIN_N6 -to DRAM_ADDR[11]
-set_location_assignment PIN_U3 -to DRAM_BA_0
-set_location_assignment PIN_V4 -to DRAM_BA_1
-set_location_assignment PIN_T3 -to DRAM_CAS_N
-set_location_assignment PIN_N3 -to DRAM_CKE
-set_location_assignment PIN_U4 -to DRAM_CLK
-set_location_assignment PIN_T6 -to DRAM_CS_N
-set_location_assignment PIN_U1 -to DRAM_DQ[0]
-set_location_assignment PIN_U2 -to DRAM_DQ[1]
-set_location_assignment PIN_V1 -to DRAM_DQ[2]
-set_location_assignment PIN_V2 -to DRAM_DQ[3]
-set_location_assignment PIN_W1 -to DRAM_DQ[4]
-set_location_assignment PIN_W2 -to DRAM_DQ[5]
-set_location_assignment PIN_Y1 -to DRAM_DQ[6]
-set_location_assignment PIN_Y2 -to DRAM_DQ[7]
-set_location_assignment PIN_N1 -to DRAM_DQ[8]
-set_location_assignment PIN_N2 -to DRAM_DQ[9]
-set_location_assignment PIN_P1 -to DRAM_DQ[10]
-set_location_assignment PIN_P2 -to DRAM_DQ[11]
-set_location_assignment PIN_R1 -to DRAM_DQ[12]
-set_location_assignment PIN_R2 -to DRAM_DQ[13]
-set_location_assignment PIN_T1 -to DRAM_DQ[14]
-set_location_assignment PIN_T2 -to DRAM_DQ[15]
-set_location_assignment PIN_R7 -to DRAM_LDQM
-set_location_assignment PIN_T5 -to DRAM_RAS_N
-set_location_assignment PIN_M5 -to DRAM_UDQM
-set_location_assignment PIN_R8 -to DRAM_WE_N
-set_location_assignment PIN_AB20 -to FL_ADDR[0]
-set_location_assignment PIN_AA14 -to FL_ADDR[1]
-set_location_assignment PIN_Y16 -to FL_ADDR[2]
-set_location_assignment PIN_R15 -to FL_ADDR[3]
-set_location_assignment PIN_T15 -to FL_ADDR[4]
-set_location_assignment PIN_U15 -to FL_ADDR[5]
-set_location_assignment PIN_V15 -to FL_ADDR[6]
-set_location_assignment PIN_W15 -to FL_ADDR[7]
-set_location_assignment PIN_R14 -to FL_ADDR[8]
-set_location_assignment PIN_Y13 -to FL_ADDR[9]
-set_location_assignment PIN_R12 -to FL_ADDR[10]
-set_location_assignment PIN_T12 -to FL_ADDR[11]
-set_location_assignment PIN_AB14 -to FL_ADDR[12]
-set_location_assignment PIN_AA13 -to FL_ADDR[13]
-set_location_assignment PIN_AB13 -to FL_ADDR[14]
-set_location_assignment PIN_AA12 -to FL_ADDR[15]
-set_location_assignment PIN_AB12 -to FL_ADDR[16]
-set_location_assignment PIN_AA20 -to FL_ADDR[17]
-set_location_assignment PIN_U14 -to FL_ADDR[18]
-set_location_assignment PIN_V14 -to FL_ADDR[19]
-set_location_assignment PIN_U13 -to FL_ADDR[20]
-set_location_assignment PIN_R13 -to FL_ADDR[21]
-set_location_assignment PIN_AB16 -to FL_DQ[0]
-set_location_assignment PIN_AA16 -to FL_DQ[1]
-set_location_assignment PIN_AB17 -to FL_DQ[2]
-set_location_assignment PIN_AA17 -to FL_DQ[3]
-set_location_assignment PIN_AB18 -to FL_DQ[4]
-set_location_assignment PIN_AA18 -to FL_DQ[5]
-set_location_assignment PIN_AB19 -to FL_DQ[6]
-set_location_assignment PIN_AA19 -to FL_DQ[7]
-set_location_assignment PIN_AA15 -to FL_OE_N
-set_location_assignment PIN_W14 -to FL_RST_N
-set_location_assignment PIN_Y14 -to FL_WE_N
-set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
-set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
-set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
-set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
-set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
-set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
-set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
-set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
-set_location_assignment PIN_V11 -to SRAM_ADDR[8]
-set_location_assignment PIN_W11 -to SRAM_ADDR[9]
-set_location_assignment PIN_R11 -to SRAM_ADDR[10]
-set_location_assignment PIN_T11 -to SRAM_ADDR[11]
-set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
-set_location_assignment PIN_U10 -to SRAM_ADDR[13]
-set_location_assignment PIN_R10 -to SRAM_ADDR[14]
-set_location_assignment PIN_T7 -to SRAM_ADDR[15]
-set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
-set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
-set_location_assignment PIN_AB5 -to SRAM_CE_N
-set_location_assignment PIN_AA6 -to SRAM_DQ[0]
-set_location_assignment PIN_AB6 -to SRAM_DQ[1]
-set_location_assignment PIN_AA7 -to SRAM_DQ[2]
-set_location_assignment PIN_AB7 -to SRAM_DQ[3]
-set_location_assignment PIN_AA8 -to SRAM_DQ[4]
-set_location_assignment PIN_AB8 -to SRAM_DQ[5]
-set_location_assignment PIN_AA9 -to SRAM_DQ[6]
-set_location_assignment PIN_AB9 -to SRAM_DQ[7]
-set_location_assignment PIN_Y9 -to SRAM_DQ[8]
-set_location_assignment PIN_W9 -to SRAM_DQ[9]
-set_location_assignment PIN_V9 -to SRAM_DQ[10]
-set_location_assignment PIN_U9 -to SRAM_DQ[11]
-set_location_assignment PIN_R9 -to SRAM_DQ[12]
-set_location_assignment PIN_W8 -to SRAM_DQ[13]
-set_location_assignment PIN_V8 -to SRAM_DQ[14]
-set_location_assignment PIN_U8 -to SRAM_DQ[15]
-set_location_assignment PIN_Y7 -to SRAM_LB_N
-set_location_assignment PIN_T8 -to SRAM_OE_N
-set_location_assignment PIN_W7 -to SRAM_UB_N
-set_location_assignment PIN_AA10 -to SRAM_WE_N
-set_global_assignment -name END_TIME "10000 us"
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
-set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name MISC_FILE "C:/altera/Kits/CycloneII_Starter_Kit-v1.0.0/Labs/z80soc/DE1/z80soc.dpf"
-set_global_assignment -name MISC_FILE "C:/altera/cores/z80soc/DE1/z80soc.dpf"
-set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "BSDL (Boundary Scan)"
-set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "C:/altera/cores/vhdl/z80soc/DE1" -section_id eda_board_design_boundary_scan
-set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION POST_CONFIG -section_id eda_board_design_boundary_scan
-set_global_assignment -name LL_ROOT_REGION ON -entity TOP_DE1 -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -entity TOP_DE1 -section_id "Root Region"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity TOP_DE1 -section_id Top
-set_global_assignment -name PARTITION_COLOR 2147039 -entity TOP_DE1 -section_id Top
-set_global_assignment -name MISC_FILE "C:/altera/cores/vhdl/z80soc/DE1/z80soc.dpf"
-set_global_assignment -name VHDL_FILE rtl/VHDL/uart/clkUnit.vhd
-set_global_assignment -name VHDL_FILE rtl/VHDL/uart/clk_div.vhd
-set_global_assignment -name VHDL_FILE rtl/VHDL/uart/uart_lib.vhd
-set_global_assignment -name VHDL_FILE rtl/VHDL/uart/miniUART.vhd
-set_global_assignment -name VHDL_FILE rtl/VHDL/uart/RxUnit.vhd
-set_global_assignment -name VHDL_FILE rtl/VHDL/uart/TxUnit.vhd
-set_global_assignment -name VHDL_FILE rtl/VHDL/t80/T80se.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/CHAR_ROM.VHD
-set_global_assignment -name VHDL_FILE rtl/vhdl/clock_357mhz.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/top_de1.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/decoder_7seg.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_ALU.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_MCode.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_Pack.vhd
-set_global_assignment -name VHDL_FILE rtl/vhdl/t80/T80_Reg.vhd
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: DE1/z80soc.qws
===================================================================
--- DE1/z80soc.qws (revision 8)
+++ DE1/z80soc.qws (nonexistent)
@@ -1,19 +0,0 @@
-[ProjectWorkspace]
-ptn_Child1=Frames
-[ProjectWorkspace.Frames]
-ptn_Child1=ChildFrames
-[ProjectWorkspace.Frames.ChildFrames]
-ptn_Child1=Document-0
-ptn_Child2=Document-1
-ptn_Child3=Document-2
-ptn_Child4=Document-3
-[ProjectWorkspace.Frames.ChildFrames.Document-1]
-ptn_Child1=ViewFrame-0
-[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
-DocPathName=rtl/vhdl/top_de1.vhd
-DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
-IsChildFrameDetached=False
-IsActiveChildFrame=False
-ptn_Child1=StateMap
-[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
-AFC_IN_REPORT=False
Index: DE1/CII_Starter_USB_API.sof
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: DE1/CII_Starter_USB_API.sof
===================================================================
--- DE1/CII_Starter_USB_API.sof (revision 8)
+++ DE1/CII_Starter_USB_API.sof (nonexistent)
DE1/CII_Starter_USB_API.sof
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: DE1/rtl/VHDL/led_driver.vhd
===================================================================
--- DE1/rtl/VHDL/led_driver.vhd (revision 8)
+++ DE1/rtl/VHDL/led_driver.vhd (nonexistent)
@@ -1,23 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.all;
-USE IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity led_driver is
- port
- (
- ENABLE : in std_logic;
- BYTE : in std_logic_vector(7 downto 0);
- LEDBYTE : out std_logic_vector(7 downto 0)
- );
-end led_driver;
-
-architecture rtl of led_driver is
-begin
-process(ENABLE, BYTE)
-begin
- if (ENABLE = '1')then
- LEDBYTE <= BYTE;
- end if;
-end process;
-end rtl;
-
Index: DE1/rtl/VHDL/uart_lib.vhd
===================================================================
--- DE1/rtl/VHDL/uart_lib.vhd (revision 8)
+++ DE1/rtl/VHDL/uart_lib.vhd (nonexistent)
@@ -1,62 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
---
--- Design units : UART_Def
---
--- File name : uart_lib.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 0.1 Ovidiu Lupas 15 January 2000 New model
--- olupas@opencores.org
--------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- package UART_Def
---------------------------------------------------------------------------------
-library IEEE,STD;
-use IEEE.Std_Logic_1164.all;
-use IEEE.Numeric_Std.all;
---**--
-package UART_Def is
- -----------------------------------------------------------------------------
- -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB
- -- Error message for unknowns (U, X, W, Z, -), converted to 0
- -- Verifies whether vector is too long (> 16 bits)
- -----------------------------------------------------------------------------
- function ToInteger (
- Invector : in Unsigned(3 downto 0))
- return Integer;
-end UART_Def; --==================== End of package header ======================--
-package body UART_Def is
- function ToInteger (
- InVector : in Unsigned(3 downto 0))
- return Integer is
- constant HeaderMsg : String := "To_Integer:";
- constant MsgSeverity : Severity_Level := Warning;
- variable Value : Integer := 0;
- begin
- for i in 0 to 3 loop
- if (InVector(i) = '1') then
- Value := Value + (2**I);
- end if;
- end loop;
- return Value;
- end ToInteger;
-end UART_Def; --================ End of package body ================--
-
-
Index: DE1/rtl/VHDL/top_de1.vhd.bak
===================================================================
--- DE1/rtl/VHDL/top_de1.vhd.bak (revision 8)
+++ DE1/rtl/VHDL/top_de1.vhd.bak (nonexistent)
@@ -1,650 +0,0 @@
--------------------------------------------------------------------------------------------------
--- Z80 Control Microprocessor
---
--- Version history:
--------------------
--- Version 0.2 Alpha for for Altera DE1
--- Developer: Tyler Pohl
--- Release Date: 2010 / 10 / 01
---
--- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
--- This version developed and tested on: Altera DE1 Development Board
---
--- Peripherals configured (Using Ports):
---
--- 40 KB Internal ROM Read (0x0000h - 0x9FFFh) -- Location 1FFFH will be used to unlock locked RAM in future
---
--- 08 KB Shared Memory Read/Write (0xA000h - 0xBFFFh)
---
--- Locked Supr1 (0xC000h - 0xC7FFh)
--- Supr2 (0xC800h - 0xCFFFh)
--- Supr3 (0xD000h - 0xD7FFh)
--- Supr4 (0xD800h - 0xDFFFh) -- Stack starts at DFEA and goes down initialize this in z80 code
--- Supr5 (0xE000h - 0xE7FFh)
--- Supr6 (0xE800h - 0xEFFFh)
--- Lacoked Pram (0xF000h - 0xF7FFh) -- Switched between 5 banks
--- Sram (0xF800h - 0xF8FFh) -- Switched between 5 banks
--- Ram (0xF900h - 0xFFFFh) -- Switched between 5 banks
-
--- 08 Green Leds Out (Port 0x01h)
--- 08 Red Leds Out (Port 0x02h)
--- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)
-
--- 01 Uart0 In/Out (Port 0x24h)
-
--- 01 Rom Switching Out (Port 0xDDh)
--- 02 Rom Switching Out (Port 0xDDh)
--- 03 Rom Switching Out (Port 0xDDh)
-
--- 00 to 04 Ram Bank Switching Out (Port 0xDCh)
-
--- Future Ports (Registers)
---PRF F0h
---STATS,RTCIN F0h --Brown Out and Pwr Fail Stat 60Hz
---PFKILL F1h
---RTCRST F2h
---SFTPRT F3h
---MEXPON F4h
---MEXPOFF F5h
---IOXPON F6h
---IOXPOFF F7h
---EPPAGE1 FCh
---EPPAGE2 FDh
---
--- Revision history:
---
--- 2010/10/01 - Modified RAM layout to support new and future improvements
--- - Changed ROM to support 16 bit addresses
--- - Serial port Recived works under Interrupt -- Load z80test and data ends up on hex display
---
---
--- Getting Started
- -- Use CII_Starter_USB_API_v1 project to load flash chip - don't forget to erase chip first
- -- Load rom.bin to flash chip starting at address 0
- -- Connect the serial port up to hyperterminal or minicom
- -- Sends data out and displays on hex display
- -- Type chars to send from PC serial port - z80 recieves and displays on hex display under interrupt
---
---
--- TO-DO:
--- - MOST IMPORTANT
--- - Search for this ????? and figure out why it stops the CPU from running
--- -
--- - Serial communication, to download assembly code from PC
--- - SD/MMC card interface to read/store data and programs
--- - Get Flash Write to Work -- Why does the CPU not run when connecting DO_CPU to the FL_DQ pins ?
--- - Figure out why cpu does not run when having LED, and uart enabled in the Port output section
--- - Get all the memory above.
--- - Get the serial Tx Interrupt to work.
--- - Add registers to uart so baudrate, parity, interrupts can be modified.
--- - Document this project in the form of Microprocessor Datasheets.
--------------------------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_arith.all;
-use IEEE.std_logic_unsigned.all;
-
-entity TOP_DE1 is
- port(
-
- -- Clocks
- CLOCK_27, -- 27 MHz
- CLOCK_50, -- 50 MHz
- EXT_CLOCK : in std_logic; -- External Clock
-
- -- Buttons and switches
- KEY : in std_logic_vector(3 downto 0); -- Push buttons
- SW : in std_logic_vector(9 downto 0); -- Switches
-
- -- LED displays
- HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
- : out std_logic_vector(6 downto 0);
- LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
- LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
-
- -- RS-232 interface
- UART_TXD : out std_logic; -- UART transmitter
- UART_RXD : in std_logic; -- UART receiver
-
- -- IRDA interface
-
- -- IRDA_TXD : out std_logic; -- IRDA Transmitter
- IRDA_RXD : in std_logic; -- IRDA Receiver
-
- -- SDRAM
- DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
- DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
- DRAM_LDQM, -- Low-byte Data Mask
- DRAM_UDQM, -- High-byte Data Mask
- DRAM_WE_N, -- Write Enable
- DRAM_CAS_N, -- Column Address Strobe
- DRAM_RAS_N, -- Row Address Strobe
- DRAM_CS_N, -- Chip Select
- DRAM_BA_0, -- Bank Address 0
- DRAM_BA_1, -- Bank Address 0
- DRAM_CLK, -- Clock
- DRAM_CKE : out std_logic; -- Clock Enable
-
- -- FLASH
- FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
- FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
- FL_WE_N : out std_logic; -- Write Enable
- FL_RST_N : out std_logic; -- Reset
- FL_OE_N : out std_logic; -- Output Enable
- FL_CE_N : out std_logic; -- Chip Enable
-
- -- SRAM
- SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
- SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
- SRAM_UB_N, -- High-byte Data Mask
- SRAM_LB_N, -- Low-byte Data Mask
- SRAM_WE_N, -- Write Enable
- SRAM_CE_N, -- Chip Enable
- SRAM_OE_N : out std_logic; -- Output Enable
-
- -- SD card interface
- SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
- SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
- SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
- SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
-
- -- USB JTAG link
- TDI, -- CPLD -> FPGA (data in)
- TCK, -- CPLD -> FPGA (clk)
- TCS : in std_logic; -- CPLD -> FPGA (CS)
- TDO : out std_logic; -- FPGA -> CPLD (data out)
-
- -- I2C bus
- I2C_SDAT : inout std_logic; -- I2C Data
- I2C_SCLK : out std_logic; -- I2C Clock
-
- -- PS/2 port
- PS2_DAT, -- Data
- PS2_CLK : inout std_logic; -- Clock
-
- -- VGA output
- VGA_HS, -- H_SYNC
- VGA_VS : out std_logic; -- SYNC
- VGA_R, -- Red[3:0]
- VGA_G, -- Green[3:0]
- VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
-
- -- Audio CODEC
- AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
- AUD_ADCDAT : in std_logic; -- ADC Data
- AUD_DACLRCK : inout std_logic; -- DAC LR Clock
- AUD_DACDAT : out std_logic; -- DAC Data
- AUD_BCLK : inout std_logic; -- Bit-Stream Clock
- AUD_XCK : out std_logic; -- Chip Clock
-
- -- General-purpose I/O
- GPIO_0, -- GPIO Connection 0
- GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
-);
-end TOP_DE1;
-
-architecture rtl of TOP_DE1 is
-
- component T80se
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CLKEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
- end component;
-
-
-
- component Clock_357Mhz
- PORT (
- clock_50Mhz : IN STD_LOGIC;
- clock_357Mhz : OUT STD_LOGIC);
- end component;
-
- component clk_div
- PORT
- (
- clock_25Mhz : IN STD_LOGIC;
- clock_1MHz : OUT STD_LOGIC;
- clock_100KHz : OUT STD_LOGIC;
- clock_10KHz : OUT STD_LOGIC;
- clock_1KHz : OUT STD_LOGIC;
- clock_100Hz : OUT STD_LOGIC;
- clock_10Hz : OUT STD_LOGIC;
- clock_1Hz : OUT STD_LOGIC;
- clock_10sec : OUT STD_LOGIC;
- clock_1min : OUT STD_LOGIC;
- clock_1hr : OUT STD_LOGIC);
- end component;
-
- component decoder_7seg
- port (
- NUMBER : in std_logic_vector(3 downto 0);
- HEX_DISP : out std_logic_vector(6 downto 0));
- end component;
-
-
-
- COMPONENT miniUART
- PORT (
- SysClk : in Std_Logic; -- System Clock
- Reset : in Std_Logic; -- Reset input
- CS_N : in Std_Logic;
- RD_N : in Std_Logic;
- WR_N : in Std_Logic;
- RxD : in Std_Logic;
- TxD : out Std_Logic;
- IntRx_N : out Std_Logic; -- Receive interrupt
- IntTx_N : out Std_Logic; -- Transmit interrupt
- Addr : in Std_Logic_Vector(1 downto 0); --
- DataIn : in Std_Logic_Vector(7 downto 0); --
- DataOut : out Std_Logic_Vector(7 downto 0)); --
- END COMPONENT;
-
-
- signal INT_n : std_logic;
- signal M1_n : std_logic;
- signal MREQ_n : std_logic;
- signal IORQ_n : std_logic;
- signal RD_n : std_logic;
- signal WR_n : std_logic;
- signal MWr_n : std_logic;
- signal Rst_n_s : std_logic;
-
- signal Clk_Z80 : std_logic;
- signal Clk_357Mhz : std_logic;
-
- signal DI_CPU : std_logic_vector(7 downto 0);
- signal DO_CPU : std_logic_vector(7 downto 0);
- signal A : std_logic_vector(15 downto 0);
- signal One : std_logic;
- signal AA : std_logic_vector(21 downto 0);
-
- signal D_ROM : std_logic_vector(7 downto 0);
-
- signal clk25mhz : std_logic;
- signal clk1hz : std_logic;
- signal clk10hz : std_logic;
- signal clk100hz : std_logic;
- signal clk10sec : std_logic;
- --signal clk1min : std_logic;
- --signal clk1hr : std_logic;
-
- signal HEX_DISP0 : std_logic_vector(6 downto 0);
- signal HEX_DISP1 : std_logic_vector(6 downto 0);
- signal HEX_DISP2 : std_logic_vector(6 downto 0);
- signal HEX_DISP3 : std_logic_vector(6 downto 0);
-
- signal NUMBER0 : std_logic_vector(3 downto 0);
- signal NUMBER1 : std_logic_vector(3 downto 0);
- signal NUMBER2 : std_logic_vector(3 downto 0);
- signal NUMBER3 : std_logic_vector(3 downto 0);
-
- --signal GPIO_0_buf_in : std_logic_vector(35 downto 0);
- --signal GPIO_1_buf_in : std_logic_vector(35 downto 0);
-
-
-
-
-
-
- --signal Z80SOC_VERSION : std_logic_vector(2 downto 0); -- "000" = DE1, "001" = S3E
- --signal Z80SOC_STACK : std_logic_vector(15 downto 0); -- Should be set to top of (RAM Memory - 1)
-
-
-
- signal uart0_CS : std_Logic;
- signal uart0_RD : std_Logic;
- signal uart0_WR : std_Logic;
- signal uart0_RxInt : std_Logic;
- signal uart0_TxInt : std_Logic;
- signal uart0_Addr : std_Logic_Vector(1 downto 0);
- signal uart0_DataIn : std_Logic_Vector(7 downto 0);
- signal uart0_DataOut : std_logic_Vector(7 downto 0);
- signal UartIntVector : std_logic_Vector(7 downto 0);
-
-
- --signal FlashReady : std_logic;
- --signal iDataFlash : std_logic_Vector(7 downto 0);
- --signal iCMDFlash : std_logic_Vector(2 downto 0);
-
- --signal FlashAddr : std_logic_Vector(21 downto 0);
-
- --signal LedBlink : std_logic;
-
- --signal SingleShot : std_logic;
-
- signal IntVector : std_logic_Vector(7 downto 0);
-
-
-
- --signal Z80_RAM_ADR : Std_Logic_Vector(15 downto 0);
- --signal Z80_RAM_CE : Std_Logic;
- --signal Z80_RAM_OE : Std_Logic;
- --signal Z80_RAM_WE : Std_Logic;
-
-
- --signal Z80_EE_ADR : Std_Logic_Vector(21 downto 0);
- --signal Z80_EE_0E : Std_Logic;
- --signal Z80_EE_WE : Std_Logic;
- --signal Z80_EE_CE : Std_Logic;
-
- --signal PFA_IOE : Std_Logic;
- --signal PFA_MEX : Std_Logic;
-
- signal LEDRED : std_logic_Vector(7 downto 0);
-
-
-begin
-
-
-
- Rst_n_s <= not SW(9); -- Switch 9 toggles Reset on z80
-
-
- HEX0 <= HEX_DISP0; -- Move Signal to Output Pins
- HEX1 <= HEX_DISP1; -- Move Signal to Output Pins
- HEX2 <= HEX_DISP2; -- Move Signal to Output Pins
- HEX3 <= HEX_DISP3; -- Move Signal to Output Pins
-
- -- SRAM control signals
- SRAM_ADDR(15 downto 0) <= A - x"C000" when (A >= x"C000" and MREQ_n = '0');
- SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A >= x"C000") else (others => 'Z');
- SRAM_WE_N <= Wr_n or MREQ_n when A >= x"C000";
- SRAM_OE_N <= Rd_n or MREQ_n when A >= x"C000"; --Rd_n;
-
- -- ???? Why can't this pin be connected to MREQ_n CPU will not run unless its is connected to zero
- SRAM_CE_N <= '0';
- --------------------------------------------------------------------------------------------------
-
- --1FFFH is used for unlocking ram in future. Auto lock after one read or write.
-
- -- FLASH control signals
-
- --FL_ADDR(15 downto 0) <= A(15 downto 0) when (Clk_Z80 = '1' and A < x"A000");
- FL_ADDR(15 downto 0) <= A(15 downto 0) when (A < x"A000" and MREQ_n = '0');
- --D_ROM(7 downto 0) <= FL_DQ when (Clk_Z80 = '1' and A < x"A000");
- D_ROM(7 downto 0) <= FL_DQ when (A < x"A000" and MREQ_n = '0');
-
- -- ????? Unblock this and CPU will not run
- --FL_DQ <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A < x"A000") else (others => 'Z');
- -----------------------------------------------------------
-
- FL_DQ <= (others => 'Z');
-
- FL_WE_N <= Wr_n; --'1'; -- Write Enable
-
- FL_OE_N <= Rd_n; -- Output Enable
-
- FL_CE_N <= MREQ_n when A < x"A000"; -- Chip Enable
-
-
-
-
- --Buffer Flash Data Lines
- --D_ROM(0) <= '1' when FL_DQ(0) = '1' else '0';
- --D_ROM(1) <= '1' when FL_DQ(1) = '1' else '0';
- --D_ROM(2) <= '1' when FL_DQ(2) = '1' else '0';
- --D_ROM(3) <= '1' when FL_DQ(3) = '1' else '0';
- --D_ROM(4) <= '1' when FL_DQ(4) = '1' else '0';
- --D_ROM(5) <= '1' when FL_DQ(5) = '1' else '0';
- --D_ROM(6) <= '1' when FL_DQ(6) = '1' else '0';
- --D_ROM(7) <= '1' when FL_DQ(7) = '1' else '0';
-
-
-
-
-
- -- UART control signals
- uart0_CS <= IORQ_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
- uart0_RD <= Rd_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
- uart0_WR <= Wr_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
- uart0_Addr <= b"00";
- ----------------------------------------------
- ----------------------------------------------
- --Z80 Interrupt Vectors
- -- IBMVECT
- --0040 AA1C DW COMMBOUT ;CHAN-B TRANSMIT BUFFER EMPTY
- --0042 101B DW COMBCLI ;BSTATUS
- --0044 F21C DW COMMBIN ;BRECEIVE
- --0046 FF1A DW COMBCLII ;BEXTINT
- --0048 281C DW COMMAOUT ;ATRBMTY
- --004A 691C DW COMACLI ;WAS CRTEXINT ;ASTATUS
- --004C 2F1B DW COMMAIN ;WAS CRTINP ;ARECEIVE
- --004E 971C DW COMACLII ;WAS CRTEXIN? ;AEXTINT
- IntVector(7 downto 0) <= x"4C" when (IORQ_n = '0' and MREQ_n = '1' and M1_n = '0' and uart0_RxInt = '1');
- ----------------------------------------------------------
-
-
-
-
-
- -- Depending on bus signals DI_CPU gets loaded with one of these values.
- -- Note: bus signals change while z80 is executing different instructions.
- -- Input to Z80
- DI_CPU <=
- SRAM_DQ(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= x"C000") else
-
- --Input ROM Code
- D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"A000") else
-
- uart0_DataIn(7 downto 0) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"24") else
-
- IntVector(7 downto 0) when (IORQ_n = '0' and MREQ_n = '1' and M1_n = '0' and uart0_RxInt = '1') else
-
- "ZZZZZZZZ";
-
- -- Process to latch leds and hex displays
- pinout_process: process(Clk_Z80)
- variable NUMBER0_sig : std_logic_vector(3 downto 0);
- variable NUMBER1_sig : std_logic_vector(3 downto 0);
- variable NUMBER2_sig : std_logic_vector(3 downto 0);
- variable NUMBER3_sig : std_logic_vector(3 downto 0);
- variable LEDG_sig : std_logic_vector(7 downto 0);
- variable LEDR_sig : std_logic_vector(9 downto 0);
- variable GPIO_0_buf_out: std_logic_vector(35 downto 0);
- variable uart0_buf_DataOut: std_logic_vector(7 downto 0);
- --variable GPIO_1_buf_out: std_logic_vector(35 downto 0);
- begin
- if Clk_Z80'event and Clk_Z80 = '1' then
- if IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' then
- -- LEDG
- if A(7 downto 0) = x"01" then
- -- LEDR
- elsif A(7 downto 0) = x"02" then
- LEDR_sig(7 downto 0) := DO_CPU;
- -- HEX1 and HEX0
- elsif A(7 downto 0) = x"10" then
- NUMBER0_sig := DO_CPU(3 downto 0);
- NUMBER1_sig := DO_CPU(7 downto 4);
- -- HEX3 and HEX2
- elsif A(7 downto 0) = x"11" then
- NUMBER2_sig := DO_CPU(3 downto 0);
- NUMBER3_sig := DO_CPU(7 downto 4);
- elsif A(7 downto 0) = x"24" then
- uart0_buf_DataOut := DO_CPU; --load data to uart output buffer
-
- end if;
- end if;
- end if;
- -- Latches the signals
- NUMBER0 <= NUMBER0_sig;
- NUMBER1 <= NUMBER1_sig;
- NUMBER2 <= NUMBER2_sig;
- NUMBER3 <= NUMBER3_sig;
-
-
- -- ???? Unblock this and CPU will not run
- --LEDRED(7 downto 0) <= LEDR_sig(7 downto 0);
- ---------------------------------------------
-
-
- uart0_DataOut <= uart0_buf_DataOut;
- end process;
-
- One <= '1';
- z80_inst: T80se
- port map (
- M1_n => M1_n,
- MREQ_n => MREQ_n,
- IORQ_n => IORQ_n,
- RD_n => Rd_n,
- WR_n => Wr_n,
- RFSH_n => open,
- HALT_n => open,
- WAIT_n => One,
- INT_n => INT_n,
- NMI_n => clk1hz,
- RESET_n => Rst_n_s,
- BUSRQ_n => One,
- BUSAK_n => open,
- CLK_n => Clk_Z80,
- CLKEN => One,
- A => A,
- DI => DI_CPU,
- DO => DO_CPU
- );
-
-
- clkdiv_inst: clk_div
- port map (
- clock_25Mhz => CLOCK_27,
- clock_1MHz => open,
- clock_100KHz => open,
- clock_10KHz => open,
- clock_1KHz => open,
- clock_100Hz => clk100hz,
- clock_10Hz => clk10hz,
- clock_1Hz => clk1hz,
- clock_10sec => clk10sec,
- clock_1min => open,
- clock_1hr => open
- );
-
- clock_z80_inst : Clock_357Mhz
- port map (
- clock_50Mhz => CLOCK_50,
- clock_357Mhz => Clk_Z80
- );
-
- DISPHEX0 : decoder_7seg PORT MAP (
- NUMBER => NUMBER0,
- HEX_DISP => HEX_DISP0
- );
-
- DISPHEX1 : decoder_7seg PORT MAP (
- NUMBER => NUMBER1,
- HEX_DISP => HEX_DISP1
- );
-
- DISPHEX2 : decoder_7seg PORT MAP (
- NUMBER => NUMBER2,
- HEX_DISP => HEX_DISP2
- );
-
- DISPHEX3 : decoder_7seg PORT MAP (
- NUMBER => NUMBER3,
- HEX_DISP => HEX_DISP3
- );
-
-
- U1 : miniUART PORT MAP (
- SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
- Reset => Key(0), --: in Std_Logic; -- Reset input
- CS_N => uart0_cs, --: in Std_Logic;
- RD_N => uart0_Rd, --: in Std_Logic;
- WR_N => uart0_Wr, --: in Std_Logic;
- RxD => UART_RXD, --: in Std_Logic;
- TxD => UART_TXD, --: out Std_Logic;
- IntRx_N => uart0_RxInt, --: out Std_Logic; -- Received Byte
- IntTx_N => uart0_TxInt, --: out Std_Logic; -- Transmit Buffer Empty
- Addr => uart0_Addr, --: in Std_Logic_Vector(1 downto 0); --
- DataIn => uart0_DataOut, --: in Std_Logic_Vector(7 downto 0); --
- DataOut => uart0_DataIn --: out Std_Logic_Vector(7 downto 0)); --
- );
-
-
-
-
-
-
- LEDR(0) <= '1' when LEDRED(0) = '1' else '0';
- LEDR(1) <= '1' when LEDRED(1) = '1' else '0';
- LEDR(2) <= '1' when LEDRED(2) = '1' else '0';
- LEDR(3) <= '1' when LEDRED(3) = '1' else '0';
- LEDR(4) <= '1' when LEDRED(4) = '1' else '0';
- LEDR(5) <= '1' when LEDRED(5) = '1' else '0';
- LEDR(6) <= '1' when LEDRED(6) = '1' else '0';
- LEDR(7) <= '1' when LEDRED(7) = '1' else '0';
-
-
-
- INT_n <= '0' when uart0_RxInt ='1' else '1';
-
-
- -- Block any of these and CPU will not run -- ?????
- LEDG(0) <= uart0_RxInt;
- LEDG(1) <= uart0_TxInt;
- LEDG(5) <= INT_n;
- ------------------------------------------------------
-
- LEDG(6) <= clk10sec;
- LEDG(7) <= clk1hz;
-
- SRAM_DQ(15 downto 8) <= (others => 'Z');
- SRAM_ADDR(17 downto 16) <= "00";
- SRAM_UB_N <= '1';
- SRAM_LB_N <= '0';
- SRAM_CE_N <= '0';
- --
- UART_TXD <= 'Z';
- DRAM_ADDR <= (others => '0');
- DRAM_LDQM <= '0';
- DRAM_UDQM <= '0';
- DRAM_WE_N <= '1';
- DRAM_CAS_N <= '1';
- DRAM_RAS_N <= '1';
- DRAM_CS_N <= '1';
- DRAM_BA_0 <= '0';
- DRAM_BA_1 <= '0';
- DRAM_CLK <= '0';
- DRAM_CKE <= '0';
-
- FL_ADDR(21 downto 16) <= b"000000";
- FL_RST_N <= '1'; -- Reset
-
- TDO <= '0';
- I2C_SCLK <= '0';
- AUD_DACDAT <= '0';
- AUD_XCK <= '0';
- -- Set all bidirectional ports to tri-state
- DRAM_DQ <= (others => 'Z');
-
- I2C_SDAT <= 'Z';
- AUD_ADCLRCK <= 'Z';
- AUD_DACLRCK <= 'Z';
- AUD_BCLK <= 'Z';
- GPIO_0 <= (others => 'Z');
- GPIO_1 <= (others => 'Z');
-end;
\ No newline at end of file
Index: DE1/rtl/VHDL/clock_357mhz.vhd
===================================================================
--- DE1/rtl/VHDL/clock_357mhz.vhd (revision 8)
+++ DE1/rtl/VHDL/clock_357mhz.vhd (nonexistent)
@@ -1,37 +0,0 @@
--- 3.57 Mhz clock from a 50 Mhz input
--- Ronivon C. costa
--- 03/2008
-------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-ENTITY Clock_357Mhz IS
- PORT (
- clock_50Mhz : IN STD_LOGIC;
- clock_357Mhz : OUT STD_LOGIC);
- END Clock_357Mhz;
-
-ARCHITECTURE rtl OF Clock_357Mhz IS
-
- SIGNAL counter: STD_LOGIC_VECTOR(3 DOWNTO 0);
- SIGNAL clock_357Mhz_int : STD_LOGIC;
-
-BEGIN
-
- PROCESS (clock_50Mhz)
- BEGIN
- IF clock_50Mhz'EVENT and clock_50Mhz = '1' THEN
- IF counter < "1110" THEN
- counter <= counter + 1;
- ELSE
- counter <= "0000";
- clock_357Mhz_int <= not clock_357Mhz_int;
- END IF;
- END IF;
-
- clock_357Mhz <= clock_357Mhz_int;
-
- END PROCESS;
-END rtl;
Index: DE1/rtl/VHDL/RxUnit.vhd
===================================================================
--- DE1/rtl/VHDL/RxUnit.vhd (revision 8)
+++ DE1/rtl/VHDL/RxUnit.vhd (nonexistent)
@@ -1,155 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
---
--- Design units : miniUART core for the OCRP-1
---
--- File name : RxUnit.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 0.1 Ovidiu Lupas 15 January 2000 New model
--- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
--- olupas@opencores.org
--------------------------------------------------------------------------------
--- Description : Implements the receive unit of the miniUART core. Samples
--- 16 times the RxD line and retain the value in the middle of
--- the time interval.
--------------------------------------------------------------------------------
--- Entity for Receive Unit - 9600 baudrate --
--------------------------------------------------------------------------------
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
-library work;
- use work.UART_Def.all;
--------------------------------------------------------------------------------
--- Receive unit
--------------------------------------------------------------------------------
-entity RxUnit is
- port (
- Clk : in Std_Logic; -- system clock signal
- Reset : in Std_Logic; -- Reset input
- Enable : in Std_Logic; -- Enable input
- RxD : in Std_Logic; -- RS-232 data input
- RD : in Std_Logic; -- Read data signal
- FErr : out Std_Logic; -- Status signal
- OErr : out Std_Logic; -- Status signal
- DRdy : out Std_Logic; -- Status signal
- DataIn : out Std_Logic_Vector(7 downto 0));
-end entity; --================== End of entity ==============================--
--------------------------------------------------------------------------------
--- Architecture for receive Unit
--------------------------------------------------------------------------------
-architecture Behaviour of RxUnit is
- -----------------------------------------------------------------------------
- -- Signals
- -----------------------------------------------------------------------------
- signal Start : Std_Logic; -- Syncro signal
- signal tmpRxD : Std_Logic; -- RxD buffer
- signal tmpDRdy : Std_Logic; -- Data ready buffer
- signal outErr : Std_Logic; --
- signal frameErr : Std_Logic; --
- signal BitCnt : Unsigned(3 downto 0); --
- signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
- signal ShtReg : Std_Logic_Vector(7 downto 0); --
- signal DOut : Std_Logic_Vector(7 downto 0); --
-begin
- ---------------------------------------------------------------------
- -- Receiver process
- ---------------------------------------------------------------------
- RcvProc : process(Clk,Reset,Enable,RxD)
- variable tmpBitCnt : Integer range 0 to 15;
- variable tmpSampleCnt : Integer range 0 to 15;
- constant CntOne : Unsigned(3 downto 0):="0001";
- begin
- if Rising_Edge(Clk) then
- tmpBitCnt := ToInteger(BitCnt);
- tmpSampleCnt := ToInteger(SampleCnt);
- if Reset = '0' then
- BitCnt <= "0000";
- SampleCnt <= "0000";
- Start <= '0';
- tmpDRdy <= '0';
- frameErr <= '0';
- outErr <= '0';
-
- ShtReg <= "00000000"; --
- DOut <= "00000000"; --
- else
- if RD = '1' then
- tmpDRdy <= '0'; -- Data was read
- end if;
-
- if Enable = '1' then
- if Start = '0' then
- if RxD = '0' then -- Start bit,
- SampleCnt <= SampleCnt + CntOne;
- Start <= '1';
- end if;
- else
- if tmpSampleCnt = 8 then -- reads the RxD line
- tmpRxD <= RxD;
- SampleCnt <= SampleCnt + CntOne;
- elsif tmpSampleCnt = 15 then
- case tmpBitCnt is
- when 0 =>
- if tmpRxD = '1' then -- Start Bit
- Start <= '0';
- else
- BitCnt <= BitCnt + CntOne;
- end if;
- SampleCnt <= SampleCnt + CntOne;
- when 1|2|3|4|5|6|7|8 =>
- BitCnt <= BitCnt + CntOne;
- SampleCnt <= SampleCnt + CntOne;
- ShtReg <= tmpRxD & ShtReg(7 downto 1);
- when 9 =>
- if tmpRxD = '0' then -- stop bit expected
- frameErr <= '1';
- else
- frameErr <= '0';
- end if;
-
- if tmpDRdy = '1' then --
- outErr <= '1';
- else
- outErr <= '0';
- end if;
-
- tmpDRdy <= '1';
- DOut <= ShtReg;
- BitCnt <= "0000";
- Start <= '0';
- when others =>
- null;
- end case;
- else
- SampleCnt <= SampleCnt + CntOne;
- end if;
- end if;
- end if;
- end if;
- end if;
- end process;
-
- DRdy <= tmpDRdy;
- DataIn <= DOut;
- FErr <= frameErr;
- OErr <= outErr;
-
-end Behaviour; --==================== End of architecture ====================--
\ No newline at end of file
Index: DE1/rtl/VHDL/decoder_7seg.vhd
===================================================================
--- DE1/rtl/VHDL/decoder_7seg.vhd (revision 8)
+++ DE1/rtl/VHDL/decoder_7seg.vhd (nonexistent)
@@ -1,40 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.all;
-USE IEEE.STD_LOGIC_UNSIGNED.all;
-
-entity decoder_7seg is
- port
- (
- NUMBER : in std_logic_vector(3 downto 0);
- HEX_DISP : out std_logic_vector(6 downto 0)
- );
-end decoder_7seg;
-
-architecture rtl of decoder_7seg is
-begin
-process(NUMBER)
-begin
- case NUMBER is
- --0 to 9
- when "0000" => HEX_DISP <= "1000000";
- when "0001" => HEX_DISP <= "1111001";
- when "0010" => HEX_DISP <= "0100100";
- when "0011" => HEX_DISP <= "0110000";
- when "0100" => HEX_DISP <= "0011001";
- when "0101" => HEX_DISP <= "0010010";
- when "0110" => HEX_DISP <= "0000011";
- when "0111" => HEX_DISP <= "1111000";
- when "1000" => HEX_DISP <= "0000000";
- when "1001" => HEX_DISP <= "0011000";
- -- A to F
- when "1010" => HEX_DISP <= "0001000";
- when "1011" => HEX_DISP <= "0000011";
- when "1100" => HEX_DISP <= "1000110";
- when "1101" => HEX_DISP <= "0100001";
- when "1110" => HEX_DISP <= "0000110";
- when "1111" => HEX_DISP <= "0001110";
- when others => HEX_DISP <= "1111111";
- end case;
-end process;
-end rtl;
-
Index: DE1/rtl/VHDL/TxUnit.vhd
===================================================================
--- DE1/rtl/VHDL/TxUnit.vhd (revision 8)
+++ DE1/rtl/VHDL/TxUnit.vhd (nonexistent)
@@ -1,116 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
---
--- Design units : miniUART core for the OCRP-1
---
--- File name : TxUnit.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 0.1 Ovidiu Lupas 15 January 2000 New model
--- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
--- olupas@opencores.org
--------------------------------------------------------------------------------
--- Description :
--------------------------------------------------------------------------------
--- Entity for the Tx Unit --
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.Uart_Def.all;
--------------------------------------------------------------------------------
--- Transmitter unit
--------------------------------------------------------------------------------
-entity TxUnit is
- port (
- Clk : in Std_Logic; -- Clock signal
- Reset : in Std_Logic; -- Reset input
- Enable : in Std_Logic; -- Enable input
- Load : in Std_Logic; -- Load transmit data
- TxD : out Std_Logic; -- RS-232 data output
- TRegE : out Std_Logic; -- Tx register empty
- TBufE : out Std_Logic; -- Tx buffer empty
- DataO : in Std_Logic_Vector(7 downto 0));
-end entity; --================== End of entity ==============================--
--------------------------------------------------------------------------------
--- Architecture for TxUnit
--------------------------------------------------------------------------------
-architecture Behaviour of TxUnit is
- -----------------------------------------------------------------------------
- -- Signals
- -----------------------------------------------------------------------------
- signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
- signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
- signal BitCnt : Unsigned(3 downto 0); -- bit counter
- signal tmpTRegE : Std_Logic; --
- signal tmpTBufE : Std_Logic; --
-begin
- -----------------------------------------------------------------------------
- -- Implements the Tx unit
- -----------------------------------------------------------------------------
- process(Clk,Reset,Enable,Load,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)
- variable tmp_TRegE : Std_Logic;
- constant CntOne : Unsigned(3 downto 0):="0001";
- begin
- if Rising_Edge(Clk) then
- if Reset = '0' then
- tmpTRegE <= '1';
- tmpTBufE <= '1';
- TxD <= '1';
- BitCnt <= "0000";
- elsif Load = '1' then
- TBuff <= DataO;
- tmpTBufE <= '0';
- elsif Enable = '1' then
- if ( tmpTBufE = '0') and (tmpTRegE = '1') then
- TReg <= TBuff;
- tmpTRegE <= '0';
--- tmp_TRegE := '0';
- tmpTBufE <= '1';
--- else
--- tmp_TRegE := tmpTRegE;
- end if;
-
- if tmpTRegE = '0' then
- case BitCnt is
- when "0000" =>
- TxD <= '0';
- BitCnt <= BitCnt + CntOne;
- when "0001" | "0010" | "0011" |
- "0100" | "0101" | "0110" |
- "0111" | "1000" =>
- TxD <= TReg(0);
- TReg <= '1' & TReg(7 downto 1);
- BitCnt <= BitCnt + CntOne;
- when "1001" =>
- TxD <= '1';
- TReg <= '1' & TReg(7 downto 1);
- BitCnt <= "0000";
- tmpTRegE <= '1';
- when others => null;
- end case;
- end if;
- end if;
- end if;
- end process;
-
- TRegE <= tmpTRegE;
- TBufE <= tmpTBufE;
-end Behaviour; --=================== End of architecture ====================--
\ No newline at end of file
Index: DE1/rtl/VHDL/top_de1.vhd
===================================================================
--- DE1/rtl/VHDL/top_de1.vhd (revision 8)
+++ DE1/rtl/VHDL/top_de1.vhd (nonexistent)
@@ -1,616 +0,0 @@
--------------------------------------------------------------------------------------------------
--- Z80 Control Microprocessor
---
--- Version history:
--------------------
--- Version 0.2 Alpha for for Altera DE1
--- Developer: Tyler Pohl
--- Release Date: 2010 / 10 / 01
---
--- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
--- This version developed and tested on: Altera DE1 Development Board
---
--- Peripherals configured (Using Ports):
---
--- 40 KB Internal ROM Read (0x0000h - 0x9FFFh) -- Location 1FFFH will be used to unlock locked RAM in future
---
--- 08 KB Shared Memory Read/Write (0xA000h - 0xBFFFh)
---
--- Locked Supr1 (0xC000h - 0xC7FFh)
--- Supr2 (0xC800h - 0xCFFFh)
--- Supr3 (0xD000h - 0xD7FFh)
--- Supr4 (0xD800h - 0xDFFFh) -- Stack starts at DFEA and goes down initialize this in z80 code
--- Supr5 (0xE000h - 0xE7FFh)
--- Supr6 (0xE800h - 0xEFFFh)
--- Lacoked Pram (0xF000h - 0xF7FFh) -- Switched between 5 banks
--- Sram (0xF800h - 0xF8FFh) -- Switched between 5 banks
--- Ram (0xF900h - 0xFFFFh) -- Switched between 5 banks
-
--- 08 Green Leds Out (Port 0x01h)
--- 08 Red Leds Out (Port 0x02h)
--- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)
-
--- 01 Uart0 In/Out (Port 0x24h)
-
--- 01 Rom Switching Out (Port 0xDDh)
--- 02 Rom Switching Out (Port 0xDDh)
--- 03 Rom Switching Out (Port 0xDDh)
-
--- 00 to 04 Ram Bank Switching Out (Port 0xDCh)
-
--- Future Ports (Registers)
---PRF F0h
---STATS,RTCIN F0h --Brown Out and Pwr Fail Stat 60Hz
---PFKILL F1h
---RTCRST F2h
---SFTPRT F3h
---MEXPON F4h
---MEXPOFF F5h
---IOXPON F6h
---IOXPOFF F7h
---EPPAGE1 FCh
---EPPAGE2 FDh
---
--- Revision history:
---
--- 2010/10/01 - Modified RAM layout to support new and future improvements
--- - Changed ROM to support 16 bit addresses
--- - Serial port Recived works under Interrupt -- Load z80test and data ends up on hex display
---
---
--- Getting Started
- -- Use CII_Starter_USB_API_v1 project to load flash chip - don't forget to erase chip first
- -- Load rom.bin to flash chip starting at address 0
- -- Connect the serial port up to hyperterminal or minicom
- -- Sends data out serial port and displays on hex display data sent
- -- Type chars to send from PC serial port - z80 recieves and displays on hex display under interrupt
---
---
--- TO-DO:
--- - MOST IMPORTANT !!!! - This is halting my progress
--- - Search for this ????? and figure out why it stops the CPU from running
--- -
--- - Serial communication, to download assembly code from PC
--- - SD/MMC card interface to read/store data and programs
--- - Get Flash Write to Work -- Why does the CPU not run when connecting DO_CPU to the FL_DQ pins ?
--- - Figure out why cpu does not run when having LED, and uart enabled in the Port output section
--- - Get all the memory above working and document.
--- - Get the serial Tx Interrupt to work.
--- - Add registers to uart so baudrate, parity, interrupts can be modified.
--- - Document this project in the form of Microprocessor Datasheets.
--- - Design Template of Software to communicate to the Board
--------------------------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_arith.all;
-use IEEE.std_logic_unsigned.all;
-
-entity TOP_DE1 is
- port(
-
- -- Clocks
- CLOCK_27, -- 27 MHz
- CLOCK_50, -- 50 MHz
- EXT_CLOCK : in std_logic; -- External Clock
-
- -- Buttons and switches
- KEY : in std_logic_vector(3 downto 0); -- Push buttons
- SW : in std_logic_vector(9 downto 0); -- Switches
-
- -- LED displays
- HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
- : out std_logic_vector(6 downto 0);
- LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
- LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
-
- -- RS-232 interface
- UART_TXD : out std_logic; -- UART transmitter
- UART_RXD : in std_logic; -- UART receiver
-
- -- IRDA interface
-
- -- IRDA_TXD : out std_logic; -- IRDA Transmitter
- IRDA_RXD : in std_logic; -- IRDA Receiver
-
- -- SDRAM
- DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
- DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
- DRAM_LDQM, -- Low-byte Data Mask
- DRAM_UDQM, -- High-byte Data Mask
- DRAM_WE_N, -- Write Enable
- DRAM_CAS_N, -- Column Address Strobe
- DRAM_RAS_N, -- Row Address Strobe
- DRAM_CS_N, -- Chip Select
- DRAM_BA_0, -- Bank Address 0
- DRAM_BA_1, -- Bank Address 0
- DRAM_CLK, -- Clock
- DRAM_CKE : out std_logic; -- Clock Enable
-
- -- FLASH
- FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
- FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
- FL_WE_N : out std_logic; -- Write Enable
- FL_RST_N : out std_logic; -- Reset
- FL_OE_N : out std_logic; -- Output Enable
- FL_CE_N : out std_logic; -- Chip Enable
-
- -- SRAM
- SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
- SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
- SRAM_UB_N, -- High-byte Data Mask
- SRAM_LB_N, -- Low-byte Data Mask
- SRAM_WE_N, -- Write Enable
- SRAM_CE_N, -- Chip Enable
- SRAM_OE_N : out std_logic; -- Output Enable
-
- -- SD card interface
- SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
- SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
- SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
- SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
-
- -- USB JTAG link
- TDI, -- CPLD -> FPGA (data in)
- TCK, -- CPLD -> FPGA (clk)
- TCS : in std_logic; -- CPLD -> FPGA (CS)
- TDO : out std_logic; -- FPGA -> CPLD (data out)
-
- -- I2C bus
- I2C_SDAT : inout std_logic; -- I2C Data
- I2C_SCLK : out std_logic; -- I2C Clock
-
- -- PS/2 port
- PS2_DAT, -- Data
- PS2_CLK : inout std_logic; -- Clock
-
- -- VGA output
- VGA_HS, -- H_SYNC
- VGA_VS : out std_logic; -- SYNC
- VGA_R, -- Red[3:0]
- VGA_G, -- Green[3:0]
- VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
-
- -- Audio CODEC
- AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
- AUD_ADCDAT : in std_logic; -- ADC Data
- AUD_DACLRCK : inout std_logic; -- DAC LR Clock
- AUD_DACDAT : out std_logic; -- DAC Data
- AUD_BCLK : inout std_logic; -- Bit-Stream Clock
- AUD_XCK : out std_logic; -- Chip Clock
-
- -- General-purpose I/O
- GPIO_0, -- GPIO Connection 0
- GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
-);
-end TOP_DE1;
-
-architecture rtl of TOP_DE1 is
-
- component T80se
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CLKEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
- end component;
-
-
-
- component Clock_357Mhz
- PORT (
- clock_50Mhz : IN STD_LOGIC;
- clock_357Mhz : OUT STD_LOGIC);
- end component;
-
- component clk_div
- PORT
- (
- clock_25Mhz : IN STD_LOGIC;
- clock_1MHz : OUT STD_LOGIC;
- clock_100KHz : OUT STD_LOGIC;
- clock_10KHz : OUT STD_LOGIC;
- clock_1KHz : OUT STD_LOGIC;
- clock_100Hz : OUT STD_LOGIC;
- clock_10Hz : OUT STD_LOGIC;
- clock_1Hz : OUT STD_LOGIC;
- clock_10sec : OUT STD_LOGIC;
- clock_1min : OUT STD_LOGIC;
- clock_1hr : OUT STD_LOGIC);
- end component;
-
- component decoder_7seg
- port (
- NUMBER : in std_logic_vector(3 downto 0);
- HEX_DISP : out std_logic_vector(6 downto 0));
- end component;
-
-
-
- COMPONENT miniUART
- PORT (
- SysClk : in Std_Logic; -- System Clock
- Reset : in Std_Logic; -- Reset input
- CS_N : in Std_Logic;
- RD_N : in Std_Logic;
- WR_N : in Std_Logic;
- RxD : in Std_Logic;
- TxD : out Std_Logic;
- IntRx_N : out Std_Logic; -- Receive interrupt
- IntTx_N : out Std_Logic; -- Transmit interrupt
- Addr : in Std_Logic_Vector(1 downto 0); --
- DataIn : in Std_Logic_Vector(7 downto 0); --
- DataOut : out Std_Logic_Vector(7 downto 0)); --
- END COMPONENT;
-
-
- signal INT_n : std_logic;
- signal M1_n : std_logic;
- signal MREQ_n : std_logic;
- signal IORQ_n : std_logic;
- signal RD_n : std_logic;
- signal WR_n : std_logic;
- signal MWr_n : std_logic;
- signal Rst_n_s : std_logic;
-
- signal Clk_Z80 : std_logic;
- signal Clk_357Mhz : std_logic;
-
- signal DI_CPU : std_logic_vector(7 downto 0);
- signal DO_CPU : std_logic_vector(7 downto 0);
- signal A : std_logic_vector(15 downto 0);
- signal One : std_logic;
- signal AA : std_logic_vector(21 downto 0);
-
- signal D_ROM : std_logic_vector(7 downto 0);
-
- signal clk25mhz : std_logic;
- signal clk1hz : std_logic;
- signal clk10hz : std_logic;
- signal clk100hz : std_logic;
- signal clk10sec : std_logic;
- --signal clk1min : std_logic;
- --signal clk1hr : std_logic;
-
- signal HEX_DISP0 : std_logic_vector(6 downto 0);
- signal HEX_DISP1 : std_logic_vector(6 downto 0);
- signal HEX_DISP2 : std_logic_vector(6 downto 0);
- signal HEX_DISP3 : std_logic_vector(6 downto 0);
-
- signal NUMBER0 : std_logic_vector(3 downto 0);
- signal NUMBER1 : std_logic_vector(3 downto 0);
- signal NUMBER2 : std_logic_vector(3 downto 0);
- signal NUMBER3 : std_logic_vector(3 downto 0);
-
-
-
- signal uart0_CS : std_Logic;
- signal uart0_RD : std_Logic;
- signal uart0_WR : std_Logic;
- signal uart0_RxInt : std_Logic;
- signal uart0_TxInt : std_Logic;
- signal uart0_Addr : std_Logic_Vector(1 downto 0);
- signal uart0_DataIn : std_Logic_Vector(7 downto 0);
- signal uart0_DataOut : std_logic_Vector(7 downto 0);
- signal UartIntVector : std_logic_Vector(7 downto 0);
-
-
-
- signal IntVector : std_logic_Vector(7 downto 0);
-
- signal LEDRED : std_logic_Vector(7 downto 0);
-
-
-begin
-
-
-
- Rst_n_s <= not SW(9); -- Switch 9 toggles Reset on z80
-
-
- HEX0 <= HEX_DISP0; -- Move Signal to Output Pins
- HEX1 <= HEX_DISP1; -- Move Signal to Output Pins
- HEX2 <= HEX_DISP2; -- Move Signal to Output Pins
- HEX3 <= HEX_DISP3; -- Move Signal to Output Pins
-
- -- SRAM control signals
- SRAM_ADDR(15 downto 0) <= A - x"C000" when (A >= x"C000" and MREQ_n = '0');
- SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A >= x"C000") else (others => 'Z');
- SRAM_WE_N <= Wr_n or MREQ_n when A >= x"C000";
- SRAM_OE_N <= Rd_n or MREQ_n when A >= x"C000"; --Rd_n;
-
- -- ???? Why can't this pin be connected to MREQ_n CPU will not run unless its is connected to zero
- SRAM_CE_N <= '0';
- --------------------------------------------------------------------------------------------------
-
- --1FFFH is used for unlocking ram in future. Auto lock after one read or write.
-
- -- FLASH control signals
-
- --FL_ADDR(15 downto 0) <= A(15 downto 0) when (Clk_Z80 = '1' and A < x"A000");
- FL_ADDR(15 downto 0) <= A(15 downto 0) when (A < x"A000" and MREQ_n = '0');
- --D_ROM(7 downto 0) <= FL_DQ when (Clk_Z80 = '1' and A < x"A000");
- D_ROM(7 downto 0) <= FL_DQ when (A < x"A000" and MREQ_n = '0');
-
- -- ????? Unblock this and CPU will not run
- --FL_DQ <= DO_CPU when (Wr_n = '0' and MREQ_n = '0' and A < x"A000") else (others => 'Z');
- -----------------------------------------------------------
-
- FL_DQ <= (others => 'Z');
-
- FL_WE_N <= '1'; --'1'; -- Write Enable
-
- FL_OE_N <= Rd_n; -- Output Enable
-
- FL_CE_N <= MREQ_n when A < x"A000"; -- Chip Enable
-
-
-
-
- --Buffer Flash Data Lines
- --D_ROM(0) <= '1' when FL_DQ(0) = '1' else '0';
- --D_ROM(1) <= '1' when FL_DQ(1) = '1' else '0';
- --D_ROM(2) <= '1' when FL_DQ(2) = '1' else '0';
- --D_ROM(3) <= '1' when FL_DQ(3) = '1' else '0';
- --D_ROM(4) <= '1' when FL_DQ(4) = '1' else '0';
- --D_ROM(5) <= '1' when FL_DQ(5) = '1' else '0';
- --D_ROM(6) <= '1' when FL_DQ(6) = '1' else '0';
- --D_ROM(7) <= '1' when FL_DQ(7) = '1' else '0';
-
-
-
-
-
- -- UART control signals
- uart0_CS <= IORQ_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
- uart0_RD <= Rd_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
- uart0_WR <= Wr_n when (A(7 downto 0) = x"24" and IORQ_n = '0');
- uart0_Addr <= b"00";
- ----------------------------------------------
- ----------------------------------------------
- --Z80 Interrupt Vectors
- -- IBMVECT
- --0040 AA1C DW COMMBOUT ;CHAN-B TRANSMIT BUFFER EMPTY
- --0042 101B DW COMBCLI ;BSTATUS
- --0044 F21C DW COMMBIN ;BRECEIVE
- --0046 FF1A DW COMBCLII ;BEXTINT
- --0048 281C DW COMMAOUT ;ATRBMTY
- --004A 691C DW COMACLI ;WAS CRTEXINT ;ASTATUS
- --004C 2F1B DW COMMAIN ;WAS CRTINP ;ARECEIVE
- --004E 971C DW COMACLII ;WAS CRTEXIN? ;AEXTINT
- IntVector(7 downto 0) <= x"4C" when (IORQ_n = '0' and MREQ_n = '1' and M1_n = '0' and uart0_RxInt = '1');
- ----------------------------------------------------------
-
-
-
-
-
- -- Depending on bus signals DI_CPU gets loaded with one of these values.
- -- Note: bus signals change while z80 is executing different instructions.
- -- Input to Z80
- DI_CPU <=
- SRAM_DQ(7 downto 0) when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A >= x"C000") else
-
- --Input ROM Code
- D_ROM when (Rd_n = '0' and MREQ_n = '0' and IORQ_n = '1' and A < x"A000") else
-
- uart0_DataIn(7 downto 0) when (IORQ_n = '0' and MREQ_n = '1' and Rd_n = '0' and A(7 downto 0) = x"24") else
-
- IntVector(7 downto 0) when (IORQ_n = '0' and MREQ_n = '1' and M1_n = '0' and uart0_RxInt = '1') else
-
- "ZZZZZZZZ";
-
- -- Process to latch leds and hex displays
- pinout_process: process(Clk_Z80)
- variable NUMBER0_sig : std_logic_vector(3 downto 0);
- variable NUMBER1_sig : std_logic_vector(3 downto 0);
- variable NUMBER2_sig : std_logic_vector(3 downto 0);
- variable NUMBER3_sig : std_logic_vector(3 downto 0);
- variable LEDG_sig : std_logic_vector(7 downto 0);
- variable LEDR_sig : std_logic_vector(9 downto 0);
- variable GPIO_0_buf_out: std_logic_vector(35 downto 0);
- variable uart0_buf_DataOut: std_logic_vector(7 downto 0);
- --variable GPIO_1_buf_out: std_logic_vector(35 downto 0);
- begin
- if Clk_Z80'event and Clk_Z80 = '1' then
- if IORQ_n = '0' and MREQ_n = '1' and Wr_n = '0' then
- -- LEDG
- if A(7 downto 0) = x"01" then
- -- LEDR
- elsif A(7 downto 0) = x"02" then
- LEDR_sig(7 downto 0) := DO_CPU;
- -- HEX1 and HEX0
- elsif A(7 downto 0) = x"10" then
- NUMBER0_sig := DO_CPU(3 downto 0);
- NUMBER1_sig := DO_CPU(7 downto 4);
- -- HEX3 and HEX2
- elsif A(7 downto 0) = x"11" then
- NUMBER2_sig := DO_CPU(3 downto 0);
- NUMBER3_sig := DO_CPU(7 downto 4);
- elsif A(7 downto 0) = x"24" then
- uart0_buf_DataOut := DO_CPU; --load data to uart output buffer
-
- end if;
- end if;
- end if;
- -- Latches the signals
- NUMBER0 <= NUMBER0_sig;
- NUMBER1 <= NUMBER1_sig;
- NUMBER2 <= NUMBER2_sig;
- NUMBER3 <= NUMBER3_sig;
-
-
- -- ???? Unblock this and CPU will not run
- -- NOTE it will work if you block uart0_DataOut below
- --LEDRED(7 downto 0) <= LEDR_sig(7 downto 0);
- ---------------------------------------------
-
-
- uart0_DataOut <= uart0_buf_DataOut;
- end process;
-
- One <= '1';
- z80_inst: T80se
- port map (
- M1_n => M1_n,
- MREQ_n => MREQ_n,
- IORQ_n => IORQ_n,
- RD_n => Rd_n,
- WR_n => Wr_n,
- RFSH_n => open,
- HALT_n => open,
- WAIT_n => One,
- INT_n => INT_n,
- NMI_n => clk1hz,
- RESET_n => Rst_n_s,
- BUSRQ_n => One,
- BUSAK_n => open,
- CLK_n => Clk_Z80,
- CLKEN => One,
- A => A,
- DI => DI_CPU,
- DO => DO_CPU
- );
-
-
- clkdiv_inst: clk_div
- port map (
- clock_25Mhz => CLOCK_27,
- clock_1MHz => open,
- clock_100KHz => open,
- clock_10KHz => open,
- clock_1KHz => open,
- clock_100Hz => clk100hz,
- clock_10Hz => clk10hz,
- clock_1Hz => clk1hz,
- clock_10sec => clk10sec,
- clock_1min => open,
- clock_1hr => open
- );
-
- clock_z80_inst : Clock_357Mhz
- port map (
- clock_50Mhz => CLOCK_50,
- clock_357Mhz => Clk_Z80
- );
-
- DISPHEX0 : decoder_7seg PORT MAP (
- NUMBER => NUMBER0,
- HEX_DISP => HEX_DISP0
- );
-
- DISPHEX1 : decoder_7seg PORT MAP (
- NUMBER => NUMBER1,
- HEX_DISP => HEX_DISP1
- );
-
- DISPHEX2 : decoder_7seg PORT MAP (
- NUMBER => NUMBER2,
- HEX_DISP => HEX_DISP2
- );
-
- DISPHEX3 : decoder_7seg PORT MAP (
- NUMBER => NUMBER3,
- HEX_DISP => HEX_DISP3
- );
-
-
- U1 : miniUART PORT MAP (
- SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
- Reset => Key(0), --: in Std_Logic; -- Reset input
- CS_N => uart0_cs, --: in Std_Logic;
- RD_N => uart0_Rd, --: in Std_Logic;
- WR_N => uart0_Wr, --: in Std_Logic;
- RxD => UART_RXD, --: in Std_Logic;
- TxD => UART_TXD, --: out Std_Logic;
- IntRx_N => uart0_RxInt, --: out Std_Logic; -- Received Byte
- IntTx_N => uart0_TxInt, --: out Std_Logic; -- Transmit Buffer Empty
- Addr => uart0_Addr, --: in Std_Logic_Vector(1 downto 0); --
- DataIn => uart0_DataOut, --: in Std_Logic_Vector(7 downto 0); --
- DataOut => uart0_DataIn --: out Std_Logic_Vector(7 downto 0)); --
- );
-
-
-
-
-
-
- LEDR(0) <= '1' when LEDRED(0) = '1' else '0';
- LEDR(1) <= '1' when LEDRED(1) = '1' else '0';
- LEDR(2) <= '1' when LEDRED(2) = '1' else '0';
- LEDR(3) <= '1' when LEDRED(3) = '1' else '0';
- LEDR(4) <= '1' when LEDRED(4) = '1' else '0';
- LEDR(5) <= '1' when LEDRED(5) = '1' else '0';
- LEDR(6) <= '1' when LEDRED(6) = '1' else '0';
- LEDR(7) <= '1' when LEDRED(7) = '1' else '0';
-
-
-
- INT_n <= '0' when uart0_RxInt ='1' else '1';
-
-
- -- Block any of these and CPU will not run -- ?????
- LEDG(0) <= uart0_RxInt;
- LEDG(1) <= uart0_TxInt;
- LEDG(5) <= INT_n;
- ------------------------------------------------------
-
- LEDG(6) <= clk10sec;
- LEDG(7) <= clk1hz;
-
- SRAM_DQ(15 downto 8) <= (others => 'Z');
- SRAM_ADDR(17 downto 16) <= "00";
- SRAM_UB_N <= '1';
- SRAM_LB_N <= '0';
- SRAM_CE_N <= '0';
- --
- UART_TXD <= 'Z';
- DRAM_ADDR <= (others => '0');
- DRAM_LDQM <= '0';
- DRAM_UDQM <= '0';
- DRAM_WE_N <= '1';
- DRAM_CAS_N <= '1';
- DRAM_RAS_N <= '1';
- DRAM_CS_N <= '1';
- DRAM_BA_0 <= '0';
- DRAM_BA_1 <= '0';
- DRAM_CLK <= '0';
- DRAM_CKE <= '0';
-
- FL_ADDR(21 downto 16) <= b"000000";
- FL_RST_N <= '1'; -- Reset
-
- TDO <= '0';
- I2C_SCLK <= '0';
- AUD_DACDAT <= '0';
- AUD_XCK <= '0';
- -- Set all bidirectional ports to tri-state
- DRAM_DQ <= (others => 'Z');
-
- I2C_SDAT <= 'Z';
- AUD_ADCLRCK <= 'Z';
- AUD_DACLRCK <= 'Z';
- AUD_BCLK <= 'Z';
- GPIO_0 <= (others => 'Z');
- GPIO_1 <= (others => 'Z');
-end;
\ No newline at end of file
Index: DE1/rtl/VHDL/t80/T80s.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80s.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80s.vhd (nonexistent)
@@ -1,190 +0,0 @@
---
--- Z80 compatible microprocessor core, synchronous top level
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0210 : Fixed read with wait
---
--- 0211 : Fixed interrupt cycle
---
--- 0235 : Updated for T80 interface change
---
--- 0236 : Added T2Write generic
---
--- 0237 : Fixed T2Write with wait state
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80s is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T80s;
-
-architecture rtl of T80s is
-
- signal CEN : std_logic;
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- CEN <= '1';
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => IOWait)
- port map(
- CEN => CEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- WAIT_n => Wait_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => RESET_n,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK_n,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n);
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK_n'event and CLK_n = '1' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and Wait_n = '0') then
- RD_n <= not IntCycle_n;
- MREQ_n <= not IntCycle_n;
- IORQ_n <= IntCycle_n;
- end if;
- if TState = "011" then
- MREQ_n <= '0';
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
- RD_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- if T2Write = 0 then
- if TState = "010" and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- end if;
- end if;
- if TState = "010" and Wait_n = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/T80_RegX.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80_RegX.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80_RegX.vhd (nonexistent)
@@ -1,176 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- T80 Registers for Xilinx Select RAM
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
--- 0242 : Initial release
---
--- 0244 : Removed UNISIM library and added componet declaration
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
- component RAM16X1D
- port(
- DPO : out std_ulogic;
- SPO : out std_ulogic;
- A0 : in std_ulogic;
- A1 : in std_ulogic;
- A2 : in std_ulogic;
- A3 : in std_ulogic;
- D : in std_ulogic;
- DPRA0 : in std_ulogic;
- DPRA1 : in std_ulogic;
- DPRA2 : in std_ulogic;
- DPRA3 : in std_ulogic;
- WCLK : in std_ulogic;
- WE : in std_ulogic);
- end component;
-
- signal ENH : std_logic;
- signal ENL : std_logic;
-
-begin
-
- ENH <= CEN and WEH;
- ENL <= CEN and WEL;
-
- bG1: for I in 0 to 7 generate
- begin
- Reg1H : RAM16X1D
- port map(
- DPO => DOBH(i),
- SPO => DOAH(i),
- A0 => AddrA(0),
- A1 => AddrA(1),
- A2 => AddrA(2),
- A3 => '0',
- D => DIH(i),
- DPRA0 => AddrB(0),
- DPRA1 => AddrB(1),
- DPRA2 => AddrB(2),
- DPRA3 => '0',
- WCLK => Clk,
- WE => ENH);
- Reg1L : RAM16X1D
- port map(
- DPO => DOBL(i),
- SPO => DOAL(i),
- A0 => AddrA(0),
- A1 => AddrA(1),
- A2 => AddrA(2),
- A3 => '0',
- D => DIL(i),
- DPRA0 => AddrB(0),
- DPRA1 => AddrB(1),
- DPRA2 => AddrB(2),
- DPRA3 => '0',
- WCLK => Clk,
- WE => ENL);
- Reg2H : RAM16X1D
- port map(
- DPO => DOCH(i),
- SPO => open,
- A0 => AddrA(0),
- A1 => AddrA(1),
- A2 => AddrA(2),
- A3 => '0',
- D => DIH(i),
- DPRA0 => AddrC(0),
- DPRA1 => AddrC(1),
- DPRA2 => AddrC(2),
- DPRA3 => '0',
- WCLK => Clk,
- WE => ENH);
- Reg2L : RAM16X1D
- port map(
- DPO => DOCL(i),
- SPO => open,
- A0 => AddrA(0),
- A1 => AddrA(1),
- A2 => AddrA(2),
- A3 => '0',
- D => DIL(i),
- DPRA0 => AddrC(0),
- DPRA1 => AddrC(1),
- DPRA2 => AddrC(2),
- DPRA3 => '0',
- WCLK => Clk,
- WE => ENL);
- end generate;
-
-end;
Index: DE1/rtl/VHDL/t80/T80se.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80se.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80se.vhd (nonexistent)
@@ -1,192 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0240
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0235 : First release
---
--- 0236 : Added T2Write generic
---
--- 0237 : Fixed T2Write with wait state
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80se is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- IOWait : integer := 0 -- 0 => Single cycle I/O, 1 => Std I/O cycle
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CLKEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T80se;
-
-architecture rtl of T80se is
-
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => IOWait)
- port map(
- CEN => CLKEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- WAIT_n => Wait_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => RESET_n,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK_n,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n);
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK_n'event and CLK_n = '1' then
- if CLKEN = '1' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and Wait_n = '0') then
- RD_n <= not IntCycle_n;
- MREQ_n <= not IntCycle_n;
- IORQ_n <= IntCycle_n;
- end if;
- if TState = "011" then
- MREQ_n <= '0';
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
- RD_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- if T2Write = 0 then
- if TState = "010" and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- else
- if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- end if;
- end if;
- if TState = "010" and Wait_n = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/T16450.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T16450.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T16450.vhd (nonexistent)
@@ -1,459 +0,0 @@
---
--- 16450 compatible UART with synchronous bus interface
--- RClk/BaudOut is XIn enable instead of actual clock
---
--- Version : 0249b
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First release
---
--- 0249 : Fixed interrupt and baud rate bugs found by Andy Dyer
--- Added modem status and break detection
--- Added support for 1.5 and 2 stop bits
---
--- 0249b : Fixed loopback break generation bugs found by Andy Dyer
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T16450 is
- port(
- MR_n : in std_logic;
- XIn : in std_logic;
- RClk : in std_logic;
- CS_n : in std_logic;
- Rd_n : in std_logic;
- Wr_n : in std_logic;
- A : in std_logic_vector(2 downto 0);
- D_In : in std_logic_vector(7 downto 0);
- D_Out : out std_logic_vector(7 downto 0);
- SIn : in std_logic;
- CTS_n : in std_logic;
- DSR_n : in std_logic;
- RI_n : in std_logic;
- DCD_n : in std_logic;
- SOut : out std_logic;
- RTS_n : out std_logic;
- DTR_n : out std_logic;
- OUT1_n : out std_logic;
- OUT2_n : out std_logic;
- BaudOut : out std_logic;
- Intr : out std_logic
- );
-end T16450;
-
-architecture rtl of T16450 is
-
- signal RBR : std_logic_vector(7 downto 0); -- Reciever Buffer Register
- signal THR : std_logic_vector(7 downto 0); -- Transmitter Holding Register
- signal IER : std_logic_vector(7 downto 0); -- Interrupt Enable Register
- signal IIR : std_logic_vector(7 downto 0); -- Interrupt Ident. Register
- signal LCR : std_logic_vector(7 downto 0); -- Line Control Register
- signal MCR : std_logic_vector(7 downto 0); -- MODEM Control Register
- signal LSR : std_logic_vector(7 downto 0); -- Line Status Register
- signal MSR : std_logic_vector(7 downto 0); -- MODEM Status Register
- signal SCR : std_logic_vector(7 downto 0); -- Scratch Register
- signal DLL : std_logic_vector(7 downto 0); -- Divisor Latch (LS)
- signal DLM : std_logic_vector(7 downto 0); -- Divisor Latch (MS)
-
- signal DM0 : std_logic_vector(7 downto 0);
- signal DM1 : std_logic_vector(7 downto 0);
-
- signal MSR_In : std_logic_vector(3 downto 0);
-
- signal Bit_Phase : unsigned(3 downto 0);
- signal Brk_Cnt : unsigned(3 downto 0);
- signal RX_Filtered : std_logic;
- signal RX_ShiftReg : std_logic_vector(7 downto 0);
- signal RX_Bit_Cnt : integer range 0 to 11;
- signal RX_Parity : std_logic;
- signal RXD : std_logic;
-
- signal TX_Tick : std_logic;
- signal TX_ShiftReg : std_logic_vector(7 downto 0);
- signal TX_Bit_Cnt : integer range 0 to 11;
- signal TX_Parity : std_logic;
- signal TX_Next_Is_Stop : std_logic;
- signal TX_Stop_Bit : std_logic;
- signal TXD : std_logic;
-
-begin
-
- DTR_n <= MCR(4) or not MCR(0);
- RTS_n <= MCR(4) or not MCR(1);
- OUT1_n <= MCR(4) or not MCR(2);
- OUT2_n <= MCR(4) or not MCR(3);
- SOut <= MCR(4) or (TXD and not LCR(6));
- RXD <= SIn when MCR(4) = '0' else (TXD and not LCR(6));
-
- Intr <= not IIR(0);
-
- -- Registers
- DM0 <= DLL when LCR(7) = '1' else RBR;
- DM1 <= DLM when LCR(7) = '1' else IER;
- with A select
- D_Out <=
- DM0 when "000",
- DM1 when "001",
- IIR when "010",
- LCR when "011",
- MCR when "100",
- LSR when "101",
- MSR when "110",
- SCR when others;
- process (MR_n, XIn)
- begin
- if MR_n = '0' then
- THR <= "00000000";
- IER <= "00000000";
- LCR <= "00000000";
- MCR <= "00000000";
- MSR(3 downto 0) <= "0000";
- SCR <= "00000000"; -- ??
- DLL <= "00000000"; -- ??
- DLM <= "00000000"; -- ??
- elsif XIn'event and XIn = '1' then
- if Wr_n = '0' and CS_n = '0' then
- case A is
- when "000" =>
- if LCR(7) = '1' then
- DLL <= D_In;
- else
- THR <= D_In;
- end if;
- when "001" =>
- if LCR(7) = '1' then
- DLM <= D_In;
- else
- IER(3 downto 0) <= D_In(3 downto 0);
- end if;
- when "011" =>
- LCR <= D_In;
- when "100" =>
- MCR <= D_In;
- when "111" =>
- SCR <= D_In;
- when others =>
- end case;
- end if;
- if Rd_n = '0' and CS_n = '0' and A = "110" then
- MSR(3 downto 0) <= "0000";
- end if;
- if MSR(4) /= MSR_In(0) then
- MSR(0) <= '1';
- end if;
- if MSR(5) /= MSR_In(1) then
- MSR(1) <= '1';
- end if;
- if MSR(6) = '0' and MSR_In(2) = '1' then
- MSR(2) <= '1';
- end if;
- if MSR(7) /= MSR_In(3) then
- MSR(3) <= '1';
- end if;
- end if;
- end process;
- process (XIn)
- begin
- if XIn'event and XIn = '1' then
- if MCR(4) = '0' then
- MSR(4) <= MSR_In(0);
- MSR(5) <= MSR_In(1);
- MSR(6) <= MSR_In(2);
- MSR(7) <= MSR_In(3);
- else
- MSR(4) <= MCR(1);
- MSR(5) <= MCR(0);
- MSR(6) <= MCR(2);
- MSR(7) <= MCR(3);
- end if;
- MSR_In(0) <= CTS_n;
- MSR_In(1) <= DSR_n;
- MSR_In(2) <= RI_n;
- MSR_In(3) <= DCD_n;
- end if;
- end process;
-
- IIR(7 downto 3) <= "00000";
- IIR(2 downto 0) <=
- "110" when IER(2) = '1' and LSR(4 downto 1) /= "0000" else
- "100" when (IER(0) and LSR(0)) = '1' else
- "010" when (IER(1) and LSR(5)) = '1' else
- "000" when IER(3) = '1' and ((MCR(4) = '0' and MSR(3 downto 0) /= "0000") or
- (MCR(4) = '1' and MCR(3 downto 0) /= "0000")) else
- "001";
-
- -- Baud x 16 clock generator
- process (MR_n, XIn)
- variable Baud_Cnt : unsigned(15 downto 0);
- begin
- if MR_n = '0' then
- Baud_Cnt := "0000000000000000";
- BaudOut <= '0';
- elsif XIn'event and XIn = '1' then
- if Baud_Cnt(15 downto 1) = "000000000000000" or (Wr_n = '0' and CS_n = '0' and A(2 downto 1) = "00" and LCR(7) = '1') then
- Baud_Cnt(15 downto 8) := unsigned(DLM);
- Baud_Cnt(7 downto 0) := unsigned(DLL);
- BaudOut <= '1';
- else
- Baud_Cnt := Baud_Cnt - 1;
- BaudOut <= '0';
- end if;
- end if;
- end process;
-
- -- Input filter
- process (MR_n, XIn)
- variable Samples : std_logic_vector(1 downto 0);
- begin
- if MR_n = '0' then
- Samples := "11";
- RX_Filtered <= '1';
- elsif XIn'event and XIn = '1' then
- if RClk = '1' then
- Samples(1) := Samples(0);
- Samples(0) := RXD;
- end if;
- if Samples = "00" then
- RX_Filtered <= '0';
- end if;
- if Samples = "11" then
- RX_Filtered <= '1';
- end if;
- end if;
- end process;
-
- -- Receive state machine
- process (MR_n, XIn)
- begin
- if MR_n = '0' then
- RBR <= "00000000";
- LSR(4 downto 0) <= "00000";
- Bit_Phase <= "0000";
- Brk_Cnt <= "0000";
- RX_ShiftReg(7 downto 0) <= "00000000";
- RX_Bit_Cnt <= 0;
- RX_Parity <= '0';
- elsif XIn'event and XIn = '1' then
- if A = "000" and LCR(7) = '0' and Rd_n = '0' and CS_n = '0' then
- LSR(0) <= '0'; -- DR
- end if;
- if A = "101" and Rd_n = '0' and CS_n = '0' then
- LSR(4) <= '0'; -- BI
- LSR(3) <= '0'; -- FE
- LSR(2) <= '0'; -- PE
- LSR(1) <= '0'; -- OE
- end if;
- if RClk = '1' then
- if RX_Bit_Cnt = 0 and (RX_Filtered = '1' or Bit_Phase = "0111") then
- Bit_Phase <= "0000";
- else
- Bit_Phase <= Bit_Phase + 1;
- end if;
- if Bit_Phase = "1111" then
- if RX_Filtered = '1' then
- Brk_Cnt <= "0000";
- else
- Brk_Cnt <= Brk_Cnt + 1;
- end if;
- if Brk_Cnt = "1100" then
- LSR(4) <= '1'; -- BI
- end if;
- end if;
- if RX_Bit_Cnt = 0 then
- if Bit_Phase = "0111" then
- RX_Bit_Cnt <= RX_Bit_Cnt + 1;
- RX_Parity <= not LCR(4); -- EPS
- end if;
- elsif Bit_Phase = "1111" then
- RX_Bit_Cnt <= RX_Bit_Cnt + 1;
- if RX_Bit_Cnt = 10 then -- Parity stop bit
- RX_Bit_Cnt <= 0;
- LSR(0) <= '1'; -- UART Receive complete
- LSR(3) <= not RX_Filtered; -- Framing error
- elsif (RX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
- (RX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
- (RX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
- (RX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then -- Stop bit/Parity
- RX_Bit_Cnt <= 0;
- if LCR(3) = '1' then -- PEN
- RX_Bit_Cnt <= 10;
- if LCR(5) = '1' then -- Stick parity
- if RX_Filtered = LCR(4) then
- LSR(2) <= '1';
- end if;
- else
- if RX_Filtered /= RX_Parity then
- LSR(2) <= '1';
- end if;
- end if;
- else
- LSR(0) <= '1'; -- UART Receive complete
- LSR(3) <= not RX_Filtered; -- Framing error
- end if;
- RBR <= RX_ShiftReg(7 downto 0);
- LSR(1) <= LSR(0);
- if A = "101" and Rd_n = '0' and CS_n = '0' then
- LSR(1) <= '0';
- end if;
- else
- RX_ShiftReg(6 downto 0) <= RX_ShiftReg(7 downto 1);
- RX_ShiftReg(7) <= RX_Filtered;
- if LCR(1 downto 0) = "10" then
- RX_ShiftReg(7) <= '0';
- RX_ShiftReg(6) <= RX_Filtered;
- end if;
- if LCR(1 downto 0) = "01" then
- RX_ShiftReg(7) <= '0';
- RX_ShiftReg(6) <= '0';
- RX_ShiftReg(5) <= RX_Filtered;
- end if;
- if LCR(1 downto 0) = "00" then
- RX_ShiftReg(7) <= '0';
- RX_ShiftReg(6) <= '0';
- RX_ShiftReg(5) <= '0';
- RX_ShiftReg(4) <= RX_Filtered;
- end if;
- RX_Parity <= RX_Filtered xor RX_Parity;
- end if;
- end if;
- end if;
- end if;
- end process;
-
- -- Transmit bit tick
- process (MR_n, XIn)
- variable TX_Cnt : unsigned(4 downto 0);
- begin
- if MR_n = '0' then
- TX_Cnt := "00000";
- TX_Tick <= '0';
- elsif XIn'event and XIn = '1' then
- TX_Tick <= '0';
- if RClk = '1' then
- TX_Cnt := TX_Cnt + 1;
- if LCR(2) = '1' and TX_Stop_Bit = '1' then
- if LCR(1 downto 0) = "00" then
- if TX_Cnt = "10111" then
- TX_Tick <= '1';
- TX_Cnt(3 downto 0) := "0000";
- end if;
- else
- if TX_Cnt = "11111" then
- TX_Tick <= '1';
- TX_Cnt(3 downto 0) := "0000";
- end if;
- end if;
- else
- TX_Cnt(4) := '1';
- if TX_Cnt(3 downto 0) = "1111" then
- TX_Tick <= '1';
- end if;
- end if;
- end if;
- end if;
- end process;
-
- -- Transmit state machine
- process (MR_n, XIn)
- begin
- if MR_n = '0' then
- LSR(7 downto 5) <= "011";
- TX_Bit_Cnt <= 0;
- TX_ShiftReg <= (others => '0');
- TXD <= '1';
- TX_Parity <= '0';
- TX_Next_Is_Stop <= '0';
- TX_Stop_Bit <= '0';
- elsif XIn'event and XIn = '1' then
- if TX_Tick = '1' then
- TX_Next_Is_Stop <= '0';
- TX_Stop_Bit <= TX_Next_Is_Stop;
- case TX_Bit_Cnt is
- when 0 =>
- if LSR(5) <= '0' then -- THRE
- TX_Bit_Cnt <= 1;
- end if;
- TXD <= '1';
- when 1 => -- Start bit
- TX_ShiftReg(7 downto 0) <= THR;
- LSR(5) <= '1'; -- THRE
- TXD <= '0';
- TX_Parity <= not LCR(4); -- EPS
- TX_Bit_Cnt <= TX_Bit_Cnt + 1;
- when 10 => -- Parity bit
- TXD <= TX_Parity;
- if LCR(5) = '1' then -- Stick parity
- TXD <= not LCR(4);
- end if;
- TX_Bit_Cnt <= 0;
- TX_Next_Is_Stop <= '1';
- when others =>
- TX_Bit_Cnt <= TX_Bit_Cnt + 1;
- if (TX_Bit_Cnt = 9 and LCR(1 downto 0) = "11") or
- (TX_Bit_Cnt = 8 and LCR(1 downto 0) = "10") or
- (TX_Bit_Cnt = 7 and LCR(1 downto 0) = "01") or
- (TX_Bit_Cnt = 6 and LCR(1 downto 0) = "00") then
- TX_Bit_Cnt <= 0;
- if LCR(3) = '1' then -- PEN
- TX_Bit_Cnt <= 10;
- else
- TX_Next_Is_Stop <= '1';
- end if;
- LSR(6) <= '1'; -- TEMT
- end if;
- TXD <= TX_ShiftReg(0);
- TX_ShiftReg(6 downto 0) <= TX_ShiftReg(7 downto 1);
- TX_Parity <= TX_ShiftReg(0) xor TX_Parity;
- end case;
- end if;
- if Wr_n = '0' and CS_n = '0' and A = "000" and LCR(7) = '0' then
- LSR(5) <= '0'; -- THRE
- LSR(6) <= '0'; -- TEMT
- end if;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/DebugSystemXR.vhd
===================================================================
--- DE1/rtl/VHDL/t80/DebugSystemXR.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/DebugSystemXR.vhd (nonexistent)
@@ -1,185 +0,0 @@
--- Z80, Monitor ROM, external SRAM interface and two 16450 UARTs
--- that can be synthesized and used with
--- the NoICE debugger that can be found at
--- http://www.noicedebugger.com/
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DebugSystemXR is
- port(
- Reset_n : in std_logic;
- Clk : in std_logic;
- NMI_n : in std_logic;
- OE_n : out std_logic;
- WE_n : out std_logic;
- RAMCS_n : out std_logic;
- ROMCS_n : out std_logic;
- PGM_n : out std_logic;
- A : out std_logic_vector(16 downto 0);
- D : inout std_logic_vector(7 downto 0);
- RXD0 : in std_logic;
- CTS0 : in std_logic;
- DSR0 : in std_logic;
- RI0 : in std_logic;
- DCD0 : in std_logic;
- RXD1 : in std_logic;
- CTS1 : in std_logic;
- DSR1 : in std_logic;
- RI1 : in std_logic;
- DCD1 : in std_logic;
- TXD0 : out std_logic;
- RTS0 : out std_logic;
- DTR0 : out std_logic;
- TXD1 : out std_logic;
- RTS1 : out std_logic;
- DTR1 : out std_logic
- );
-end entity DebugSystemXR;
-
-architecture struct of DebugSystemXR is
-
- signal M1_n : std_logic;
- signal MREQ_n : std_logic;
- signal IORQ_n : std_logic;
- signal RD_n : std_logic;
- signal WR_n : std_logic;
- signal RFSH_n : std_logic;
- signal HALT_n : std_logic;
- signal WAIT_n : std_logic;
- signal INT_n : std_logic;
- signal RESET_s : std_logic;
- signal BUSRQ_n : std_logic;
- signal BUSAK_n : std_logic;
- signal A_i : std_logic_vector(15 downto 0);
- signal D_i : std_logic_vector(7 downto 0);
- signal ROM_D : std_logic_vector(7 downto 0);
- signal UART0_D : std_logic_vector(7 downto 0);
- signal UART1_D : std_logic_vector(7 downto 0);
- signal CPU_D : std_logic_vector(7 downto 0);
-
- signal Mirror : std_logic;
-
- signal IOWR_n : std_logic;
- signal RAMCS_n_i : std_logic;
- signal UART0CS_n : std_logic;
- signal UART1CS_n : std_logic;
-
- signal BaudOut0 : std_logic;
- signal BaudOut1 : std_logic;
-
-begin
-
- Wait_n <= '1';
- BusRq_n <= '1';
- INT_n <= '1';
-
- OE_n <= RD_n;
- WE_n <= WR_n;
- RAMCS_n <= RAMCS_n_i;
- ROMCS_n <= '1';
- PGM_n <= '1';
- A(14 downto 0) <= A_i(14 downto 0);
- A(16 downto 15) <= "00";
- D <= D_i when WR_n = '0' else "ZZZZZZZZ";
-
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- Reset_s <= '0';
- Mirror <= '0';
- elsif Clk'event and Clk = '1' then
- Reset_s <= '1';
- if IORQ_n = '0' and A_i(7 downto 4) = "1111" then
- Mirror <= D_i(0);
- end if;
- end if;
- end process;
-
- IOWR_n <= WR_n or IORQ_n;
- RAMCS_n_i <= (not Mirror and not A_i(15)) or MREQ_n;
- UART0CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "00000" else '1';
- UART1CS_n <= '0' when IORQ_n = '0' and A_i(7 downto 3) = "10000" else '1';
-
- CPU_D <=
- D when RAMCS_n_i = '0' else
- UART0_D when UART0CS_n = '0' else
- UART1_D when UART1CS_n = '0' else
- ROM_D;
-
- u0 : entity work.T80s
- generic map(Mode => 1, T2Write => 1, IOWait => 0)
- port map(
- RESET_n => RESET_s,
- CLK_n => Clk,
- WAIT_n => WAIT_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- BUSRQ_n => BUSRQ_n,
- M1_n => M1_n,
- MREQ_n => MREQ_n,
- IORQ_n => IORQ_n,
- RD_n => RD_n,
- WR_n => WR_n,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- BUSAK_n => BUSAK_n,
- A => A_i,
- DI => CPU_D,
- DO => D_i);
-
- u1 : entity work.MonZ80
- port map(
- Clk => Clk,
- A => A_i(10 downto 0),
- D => ROM_D);
-
- u3 : entity work.T16450
- port map(
- MR_n => Reset_s,
- XIn => Clk,
- RClk => BaudOut0,
- CS_n => UART0CS_n,
- Rd_n => RD_n,
- Wr_n => IOWR_n,
- A => A_i(2 downto 0),
- D_In => D_i,
- D_Out => UART0_D,
- SIn => RXD0,
- CTS_n => CTS0,
- DSR_n => DSR0,
- RI_n => RI0,
- DCD_n => DCD0,
- SOut => TXD0,
- RTS_n => RTS0,
- DTR_n => DTR0,
- OUT1_n => open,
- OUT2_n => open,
- BaudOut => BaudOut0,
- Intr => open);
-
- u4 : entity work.T16450
- port map(
- MR_n => Reset_s,
- XIn => Clk,
- RClk => BaudOut1,
- CS_n => UART1CS_n,
- Rd_n => RD_n,
- Wr_n => IOWR_n,
- A => A_i(2 downto 0),
- D_In => D_i,
- D_Out => UART1_D,
- SIn => RXD1,
- CTS_n => CTS1,
- DSR_n => DSR1,
- RI_n => RI1,
- DCD_n => DCD1,
- SOut => TXD1,
- RTS_n => RTS1,
- DTR_n => DTR1,
- OUT1_n => open,
- OUT2_n => open,
- BaudOut => BaudOut1,
- Intr => open);
-
-end;
Index: DE1/rtl/VHDL/t80/SSRAM2.vhd
===================================================================
--- DE1/rtl/VHDL/t80/SSRAM2.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/SSRAM2.vhd (nonexistent)
@@ -1,92 +0,0 @@
---
--- Inferrable Synchronous SRAM for Leonardo synthesis, no write through!
---
--- Version : 0236
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity SSRAM is
- generic(
- AddrWidth : integer := 16;
- DataWidth : integer := 8
- );
- port(
- Clk : in std_logic;
- CE_n : in std_logic;
- WE_n : in std_logic;
- A : in std_logic_vector(AddrWidth - 1 downto 0);
- DIn : in std_logic_vector(DataWidth - 1 downto 0);
- DOut : out std_logic_vector(DataWidth - 1 downto 0)
- );
-end SSRAM;
-
-architecture behaviour of SSRAM is
-
- type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
- signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
--- signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
--- pragma translate_off
- if not is_x(A) then
--- pragma translate_on
- DOut <= RAM(to_integer(unsigned(A(AddrWidth - 1 downto 0))));
--- pragma translate_off
- end if;
--- pragma translate_on
- if CE_n = '0' and WE_n = '0' then
- RAM(to_integer(unsigned(A))) <= DIn;
- end if;
--- A_r <= A;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/T80_Reg.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80_Reg.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80_Reg.vhd (nonexistent)
@@ -1,105 +0,0 @@
---
--- T80 Registers, technology independent
---
--- Version : 0244
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
--- 0242 : Initial release
---
--- 0244 : Changed to single register file
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_Reg is
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
-end T80_Reg;
-
-architecture rtl of T80_Reg is
-
- type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
- signal RegsH : Register_Image(0 to 7);
- signal RegsL : Register_Image(0 to 7);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if CEN = '1' then
- if WEH = '1' then
- RegsH(to_integer(unsigned(AddrA))) <= DIH;
- end if;
- if WEL = '1' then
- RegsL(to_integer(unsigned(AddrA))) <= DIL;
- end if;
- end if;
- end if;
- end process;
-
- DOAH <= RegsH(to_integer(unsigned(AddrA)));
- DOAL <= RegsL(to_integer(unsigned(AddrA)));
- DOBH <= RegsH(to_integer(unsigned(AddrB)));
- DOBL <= RegsL(to_integer(unsigned(AddrB)));
- DOCH <= RegsH(to_integer(unsigned(AddrC)));
- DOCL <= RegsL(to_integer(unsigned(AddrC)));
-
-end;
Index: DE1/rtl/VHDL/t80/T80_Pack.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80_Pack.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80_Pack.vhd (nonexistent)
@@ -1,217 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package T80_Pack is
-
- component T80
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
- end component;
-
- component T80_Reg
- port(
- Clk : in std_logic;
- CEN : in std_logic;
- WEH : in std_logic;
- WEL : in std_logic;
- AddrA : in std_logic_vector(2 downto 0);
- AddrB : in std_logic_vector(2 downto 0);
- AddrC : in std_logic_vector(2 downto 0);
- DIH : in std_logic_vector(7 downto 0);
- DIL : in std_logic_vector(7 downto 0);
- DOAH : out std_logic_vector(7 downto 0);
- DOAL : out std_logic_vector(7 downto 0);
- DOBH : out std_logic_vector(7 downto 0);
- DOBL : out std_logic_vector(7 downto 0);
- DOCH : out std_logic_vector(7 downto 0);
- DOCL : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component T80_MCode
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
- end component;
-
- component T80_ALU
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
- end component;
-
-end;
Index: DE1/rtl/VHDL/t80/T8080se.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T8080se.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T8080se.vhd (nonexistent)
@@ -1,185 +0,0 @@
---
--- 8080 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original 8080
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0242
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
--- STACK status output not supported
---
--- File history :
---
--- 0237 : First version
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T8080se is
- generic(
- Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
- );
- port(
- RESET_n : in std_logic;
- CLK : in std_logic;
- CLKEN : in std_logic;
- READY : in std_logic;
- HOLD : in std_logic;
- INT : in std_logic;
- INTE : out std_logic;
- DBIN : out std_logic;
- SYNC : out std_logic;
- VAIT : out std_logic;
- HLDA : out std_logic;
- WR_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T8080se;
-
-architecture rtl of T8080se is
-
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal INT_n : std_logic;
- signal HALT_n : std_logic;
- signal BUSRQ_n : std_logic;
- signal BUSAK_n : std_logic;
- signal DO_i : std_logic_vector(7 downto 0);
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
- signal One : std_logic;
-
-begin
-
- INT_n <= not INT;
- BUSRQ_n <= HOLD;
- HLDA <= not BUSAK_n;
- SYNC <= '1' when TState = "001" else '0';
- VAIT <= '1' when TState = "010" else '0';
- One <= '1';
-
- DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
- DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
- DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
- DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
- DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
- DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
- DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
- DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => 0)
- port map(
- CEN => CLKEN,
- M1_n => open,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => open,
- HALT_n => HALT_n,
- WAIT_n => READY,
- INT_n => INT_n,
- NMI_n => One,
- RESET_n => RESET_n,
- BUSRQ_n => One,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO_i,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n,
- IntE => INTE);
-
- process (RESET_n, CLK)
- begin
- if RESET_n = '0' then
- DBIN <= '0';
- WR_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK'event and CLK = '1' then
- if CLKEN = '1' then
- DBIN <= '0';
- WR_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and READY = '0') then
- DBIN <= IntCycle_n;
- end if;
- else
- if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
- DBIN <= '1';
- end if;
- if T2Write = 0 then
- if TState = "010" and Write = '1' then
- WR_n <= '0';
- end if;
- else
- if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
- WR_n <= '0';
- end if;
- end if;
- end if;
- if TState = "010" and READY = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/T80.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80.vhd (nonexistent)
@@ -1,1080 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
---
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0210 : Fixed wait and halt
---
--- 0211 : Fixed Refresh addition and IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
---
--- 0235 : Added clock enable and IM 2 fix by Mike Johnson
---
--- 0237 : Changed 8080 I/O address output, added IntE output
---
--- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
---
--- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
---
--- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
---
--- 0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80 is
- generic(
- Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- IORQ : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DInst : in std_logic_vector(7 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0);
- MC : out std_logic_vector(2 downto 0);
- TS : out std_logic_vector(2 downto 0);
- IntCycle_n : out std_logic;
- IntE : out std_logic;
- Stop : out std_logic
- );
-end T80;
-
-architecture rtl of T80 is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- -- Registers
- signal ACC, F : std_logic_vector(7 downto 0);
- signal Ap, Fp : std_logic_vector(7 downto 0);
- signal I : std_logic_vector(7 downto 0);
- signal R : unsigned(7 downto 0);
- signal SP, PC : unsigned(15 downto 0);
-
- signal RegDIH : std_logic_vector(7 downto 0);
- signal RegDIL : std_logic_vector(7 downto 0);
- signal RegBusA : std_logic_vector(15 downto 0);
- signal RegBusB : std_logic_vector(15 downto 0);
- signal RegBusC : std_logic_vector(15 downto 0);
- signal RegAddrA_r : std_logic_vector(2 downto 0);
- signal RegAddrA : std_logic_vector(2 downto 0);
- signal RegAddrB_r : std_logic_vector(2 downto 0);
- signal RegAddrB : std_logic_vector(2 downto 0);
- signal RegAddrC : std_logic_vector(2 downto 0);
- signal RegWEH : std_logic;
- signal RegWEL : std_logic;
- signal Alternate : std_logic;
-
- -- Help Registers
- signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
- signal IR : std_logic_vector(7 downto 0); -- Instruction register
- signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
- signal RegBusA_r : std_logic_vector(15 downto 0);
-
- signal ID16 : signed(15 downto 0);
- signal Save_Mux : std_logic_vector(7 downto 0);
-
- signal TState : unsigned(2 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal IntE_FF1 : std_logic;
- signal IntE_FF2 : std_logic;
- signal Halt_FF : std_logic;
- signal BusReq_s : std_logic;
- signal BusAck : std_logic;
- signal ClkEn : std_logic;
- signal NMI_s : std_logic;
- signal INT_s : std_logic;
- signal IStatus : std_logic_vector(1 downto 0);
-
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal T_Res : std_logic;
- signal XY_State : std_logic_vector(1 downto 0);
- signal Pre_XY_F_M : std_logic_vector(2 downto 0);
- signal NextIs_XY_Fetch : std_logic;
- signal XY_Ind : std_logic;
- signal No_BTR : std_logic;
- signal BTR_r : std_logic;
- signal Auto_Wait : std_logic;
- signal Auto_Wait_t1 : std_logic;
- signal Auto_Wait_t2 : std_logic;
- signal IncDecZ : std_logic;
-
- -- ALU signals
- signal BusB : std_logic_vector(7 downto 0);
- signal BusA : std_logic_vector(7 downto 0);
- signal ALU_Q : std_logic_vector(7 downto 0);
- signal F_Out : std_logic_vector(7 downto 0);
-
- -- Registered micro code outputs
- signal Read_To_Reg_r : std_logic_vector(4 downto 0);
- signal Arith16_r : std_logic;
- signal Z16_r : std_logic;
- signal ALU_Op_r : std_logic_vector(3 downto 0);
- signal Save_ALU_r : std_logic;
- signal PreserveC_r : std_logic;
- signal MCycles : std_logic_vector(2 downto 0);
-
- -- Micro code outputs
- signal MCycles_d : std_logic_vector(2 downto 0);
- signal TStates : std_logic_vector(2 downto 0);
- signal IntCycle : std_logic;
- signal NMICycle : std_logic;
- signal Inc_PC : std_logic;
- signal Inc_WZ : std_logic;
- signal IncDec_16 : std_logic_vector(3 downto 0);
- signal Prefix : std_logic_vector(1 downto 0);
- signal Read_To_Acc : std_logic;
- signal Read_To_Reg : std_logic;
- signal Set_BusB_To : std_logic_vector(3 downto 0);
- signal Set_BusA_To : std_logic_vector(3 downto 0);
- signal ALU_Op : std_logic_vector(3 downto 0);
- signal Save_ALU : std_logic;
- signal PreserveC : std_logic;
- signal Arith16 : std_logic;
- signal Set_Addr_To : std_logic_vector(2 downto 0);
- signal Jump : std_logic;
- signal JumpE : std_logic;
- signal JumpXY : std_logic;
- signal Call : std_logic;
- signal RstP : std_logic;
- signal LDZ : std_logic;
- signal LDW : std_logic;
- signal LDSPHL : std_logic;
- signal IORQ_i : std_logic;
- signal Special_LD : std_logic_vector(2 downto 0);
- signal ExchangeDH : std_logic;
- signal ExchangeRp : std_logic;
- signal ExchangeAF : std_logic;
- signal ExchangeRS : std_logic;
- signal I_DJNZ : std_logic;
- signal I_CPL : std_logic;
- signal I_CCF : std_logic;
- signal I_SCF : std_logic;
- signal I_RETN : std_logic;
- signal I_BT : std_logic;
- signal I_BC : std_logic;
- signal I_BTR : std_logic;
- signal I_RLD : std_logic;
- signal I_RRD : std_logic;
- signal I_INRC : std_logic;
- signal SetDI : std_logic;
- signal SetEI : std_logic;
- signal IMode : std_logic_vector(1 downto 0);
- signal Halt : std_logic;
-
-begin
-
- mcode : T80_MCode
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- IR => IR,
- ISet => ISet,
- MCycle => MCycle,
- F => F,
- NMICycle => NMICycle,
- IntCycle => IntCycle,
- MCycles => MCycles_d,
- TStates => TStates,
- Prefix => Prefix,
- Inc_PC => Inc_PC,
- Inc_WZ => Inc_WZ,
- IncDec_16 => IncDec_16,
- Read_To_Acc => Read_To_Acc,
- Read_To_Reg => Read_To_Reg,
- Set_BusB_To => Set_BusB_To,
- Set_BusA_To => Set_BusA_To,
- ALU_Op => ALU_Op,
- Save_ALU => Save_ALU,
- PreserveC => PreserveC,
- Arith16 => Arith16,
- Set_Addr_To => Set_Addr_To,
- IORQ => IORQ_i,
- Jump => Jump,
- JumpE => JumpE,
- JumpXY => JumpXY,
- Call => Call,
- RstP => RstP,
- LDZ => LDZ,
- LDW => LDW,
- LDSPHL => LDSPHL,
- Special_LD => Special_LD,
- ExchangeDH => ExchangeDH,
- ExchangeRp => ExchangeRp,
- ExchangeAF => ExchangeAF,
- ExchangeRS => ExchangeRS,
- I_DJNZ => I_DJNZ,
- I_CPL => I_CPL,
- I_CCF => I_CCF,
- I_SCF => I_SCF,
- I_RETN => I_RETN,
- I_BT => I_BT,
- I_BC => I_BC,
- I_BTR => I_BTR,
- I_RLD => I_RLD,
- I_RRD => I_RRD,
- I_INRC => I_INRC,
- SetDI => SetDI,
- SetEI => SetEI,
- IMode => IMode,
- Halt => Halt,
- NoRead => NoRead,
- Write => Write);
-
- alu : T80_ALU
- generic map(
- Mode => Mode,
- Flag_C => Flag_C,
- Flag_N => Flag_N,
- Flag_P => Flag_P,
- Flag_X => Flag_X,
- Flag_H => Flag_H,
- Flag_Y => Flag_Y,
- Flag_Z => Flag_Z,
- Flag_S => Flag_S)
- port map(
- Arith16 => Arith16_r,
- Z16 => Z16_r,
- ALU_Op => ALU_Op_r,
- IR => IR(5 downto 0),
- ISet => ISet,
- BusA => BusA,
- BusB => BusB,
- F_In => F,
- Q => ALU_Q,
- F_Out => F_Out);
-
- ClkEn <= CEN and not BusAck;
-
- T_Res <= '1' when TState = unsigned(TStates) else '0';
-
- NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
- ((Set_Addr_To = aXY) or
- (MCycle = "001" and IR = "11001011") or
- (MCycle = "001" and IR = "00110110")) else '0';
-
- Save_Mux <= BusB when ExchangeRp = '1' else
- DI_Reg when Save_ALU_r = '0' else
- ALU_Q;
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- PC <= (others => '0'); -- Program Counter
- A <= (others => '0');
- TmpAddr <= (others => '0');
- IR <= "00000000";
- ISet <= "00";
- XY_State <= "00";
- IStatus <= "00";
- MCycles <= "000";
- DO <= "00000000";
-
- ACC <= (others => '1');
- F <= (others => '1');
- Ap <= (others => '1');
- Fp <= (others => '1');
- I <= (others => '0');
- R <= (others => '0');
- SP <= (others => '1');
- Alternate <= '0';
-
- Read_To_Reg_r <= "00000";
- F <= (others => '1');
- Arith16_r <= '0';
- BTR_r <= '0';
- Z16_r <= '0';
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- PreserveC_r <= '0';
- XY_Ind <= '0';
-
- elsif CLK_n'event and CLK_n = '1' then
-
- if ClkEn = '1' then
-
- ALU_Op_r <= "0000";
- Save_ALU_r <= '0';
- Read_To_Reg_r <= "00000";
-
- MCycles <= MCycles_d;
-
- if IMode /= "11" then
- IStatus <= IMode;
- end if;
-
- Arith16_r <= Arith16;
- PreserveC_r <= PreserveC;
- if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
- Z16_r <= '1';
- else
- Z16_r <= '0';
- end if;
-
- if MCycle = "001" and TState(2) = '0' then
- -- MCycle = 1 and TState = 1, 2, or 3
-
- if TState = 2 and Wait_n = '1' then
- if Mode < 2 then
- A(7 downto 0) <= std_logic_vector(R);
- A(15 downto 8) <= I;
- R(6 downto 0) <= R(6 downto 0) + 1;
- end if;
-
- if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
- PC <= PC + 1;
- end if;
-
- if IntCycle = '1' and IStatus = "01" then
- IR <= "11111111";
- elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
- IR <= "00000000";
- else
- IR <= DInst;
- end if;
-
- ISet <= "00";
- if Prefix /= "00" then
- if Prefix = "11" then
- if IR(5) = '1' then
- XY_State <= "10";
- else
- XY_State <= "01";
- end if;
- else
- if Prefix = "10" then
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- ISet <= Prefix;
- end if;
- else
- XY_State <= "00";
- XY_Ind <= '0';
- end if;
- end if;
-
- else
- -- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
-
- if MCycle = "110" then
- XY_Ind <= '1';
- if Prefix = "01" then
- ISet <= "01";
- end if;
- end if;
-
- if T_Res = '1' then
- BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
- if Jump = '1' then
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(DI_Reg);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- elsif JumpXY = '1' then
- A <= RegBusC;
- PC <= unsigned(RegBusC);
- elsif Call = '1' or RstP = '1' then
- A <= TmpAddr;
- PC <= unsigned(TmpAddr);
- elsif MCycle = MCycles and NMICycle = '1' then
- A <= "0000000001100110";
- PC <= "0000000001100110";
- elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
- A(15 downto 8) <= I;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- PC(15 downto 8) <= unsigned(I);
- PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
- else
- case Set_Addr_To is
- when aXY =>
- if XY_State = "00" then
- A <= RegBusC;
- else
- if NextIs_XY_Fetch = '1' then
- A <= std_logic_vector(PC);
- else
- A <= TmpAddr;
- end if;
- end if;
- when aIOA =>
- if Mode = 3 then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- elsif Mode = 2 then
- -- Duplicate I/O address on 8080
- A(15 downto 8) <= DI_Reg;
- else
- A(15 downto 8) <= ACC;
- end if;
- A(7 downto 0) <= DI_Reg;
- when aSP =>
- A <= std_logic_vector(SP);
- when aBC =>
- if Mode = 3 and IORQ_i = '1' then
- -- Memory map I/O on GBZ80
- A(15 downto 8) <= (others => '1');
- A(7 downto 0) <= RegBusC(7 downto 0);
- else
- A <= RegBusC;
- end if;
- when aDE =>
- A <= RegBusC;
- when aZI =>
- if Inc_WZ = '1' then
- A <= std_logic_vector(unsigned(TmpAddr) + 1);
- else
- A(15 downto 8) <= DI_Reg;
- A(7 downto 0) <= TmpAddr(7 downto 0);
- end if;
- when others =>
- A <= std_logic_vector(PC);
- end case;
- end if;
-
- Save_ALU_r <= Save_ALU;
- ALU_Op_r <= ALU_Op;
-
- if I_CPL = '1' then
- -- CPL
- ACC <= not ACC;
- F(Flag_Y) <= not ACC(5);
- F(Flag_H) <= '1';
- F(Flag_X) <= not ACC(3);
- F(Flag_N) <= '1';
- end if;
- if I_CCF = '1' then
- -- CCF
- F(Flag_C) <= not F(Flag_C);
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= F(Flag_C);
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- if I_SCF = '1' then
- -- SCF
- F(Flag_C) <= '1';
- F(Flag_Y) <= ACC(5);
- F(Flag_H) <= '0';
- F(Flag_X) <= ACC(3);
- F(Flag_N) <= '0';
- end if;
- end if;
-
- if TState = 2 and Wait_n = '1' then
- if ISet = "01" and MCycle = "111" then
- IR <= DInst;
- end if;
- if JumpE = '1' then
- PC <= unsigned(signed(PC) + signed(DI_Reg));
- elsif Inc_PC = '1' then
- PC <= PC + 1;
- end if;
- if BTR_r = '1' then
- PC <= PC - 2;
- end if;
- if RstP = '1' then
- TmpAddr <= (others =>'0');
- TmpAddr(5 downto 3) <= IR(5 downto 3);
- end if;
- end if;
- if TState = 3 and MCycle = "110" then
- TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
- end if;
-
- if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
- if IncDec_16(2 downto 0) = "111" then
- if IncDec_16(3) = '1' then
- SP <= SP - 1;
- else
- SP <= SP + 1;
- end if;
- end if;
- end if;
-
- if LDSPHL = '1' then
- SP <= unsigned(RegBusC);
- end if;
- if ExchangeAF = '1' then
- Ap <= ACC;
- ACC <= Ap;
- Fp <= F;
- F <= Fp;
- end if;
- if ExchangeRS = '1' then
- Alternate <= not Alternate;
- end if;
- end if;
-
- if TState = 3 then
- if LDZ = '1' then
- TmpAddr(7 downto 0) <= DI_Reg;
- end if;
- if LDW = '1' then
- TmpAddr(15 downto 8) <= DI_Reg;
- end if;
-
- if Special_LD(2) = '1' then
- case Special_LD(1 downto 0) is
- when "00" =>
- ACC <= I;
- F(Flag_P) <= IntE_FF2;
- when "01" =>
- ACC <= std_logic_vector(R);
- F(Flag_P) <= IntE_FF2;
- when "10" =>
- I <= ACC;
- when others =>
- R <= unsigned(ACC);
- end case;
- end if;
- end if;
-
- if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
- if Mode = 3 then
- F(6) <= F_Out(6);
- F(5) <= F_Out(5);
- F(7) <= F_Out(7);
- if PreserveC_r = '0' then
- F(4) <= F_Out(4);
- end if;
- else
- F(7 downto 1) <= F_Out(7 downto 1);
- if PreserveC_r = '0' then
- F(Flag_C) <= F_Out(0);
- end if;
- end if;
- end if;
- if T_Res = '1' and I_INRC = '1' then
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- if DI_Reg(7 downto 0) = "00000000" then
- F(Flag_Z) <= '1';
- else
- F(Flag_Z) <= '0';
- end if;
- F(Flag_S) <= DI_Reg(7);
- F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
- DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
- end if;
-
- if TState = 1 then
- DO <= BusB;
- if I_RLD = '1' then
- DO(3 downto 0) <= BusA(3 downto 0);
- DO(7 downto 4) <= BusB(3 downto 0);
- end if;
- if I_RRD = '1' then
- DO(3 downto 0) <= BusB(7 downto 4);
- DO(7 downto 4) <= BusA(3 downto 0);
- end if;
- end if;
-
- if T_Res = '1' then
- Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
- Read_To_Reg_r(4) <= Read_To_Reg;
- if Read_To_Acc = '1' then
- Read_To_Reg_r(3 downto 0) <= "0111";
- Read_To_Reg_r(4) <= '1';
- end if;
- end if;
-
- if TState = 1 and I_BT = '1' then
- F(Flag_X) <= ALU_Q(3);
- F(Flag_Y) <= ALU_Q(1);
- F(Flag_H) <= '0';
- F(Flag_N) <= '0';
- end if;
- if I_BC = '1' or I_BT = '1' then
- F(Flag_P) <= IncDecZ;
- end if;
-
- if (TState = 1 and Save_ALU_r = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10111" =>
- ACC <= Save_Mux;
- when "10110" =>
- DO <= Save_Mux;
- when "11000" =>
- SP(7 downto 0) <= unsigned(Save_Mux);
- when "11001" =>
- SP(15 downto 8) <= unsigned(Save_Mux);
- when "11011" =>
- F <= Save_Mux;
- when others =>
- end case;
- end if;
-
- end if;
-
- end if;
-
- end process;
-
----------------------------------------------------------------------------
---
--- BC('), DE('), HL('), IX and IY
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- -- Bus A / Write
- RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
- RegAddrA_r <= XY_State(1) & "11";
- end if;
-
- -- Bus B
- RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
- if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
- RegAddrB_r <= XY_State(1) & "11";
- end if;
-
- -- Address from register
- RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
- -- Jump (HL), LD SP,HL
- if (JumpXY = '1' or LDSPHL = '1') then
- RegAddrC <= Alternate & "10";
- end if;
- if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
- RegAddrC <= XY_State(1) & "11";
- end if;
-
- if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
- IncDecZ <= F_Out(Flag_Z);
- end if;
- if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
- if ID16 = 0 then
- IncDecZ <= '0';
- else
- IncDecZ <= '1';
- end if;
- end if;
-
- RegBusA_r <= RegBusA;
- end if;
- end if;
- end process;
-
- RegAddrA <=
- -- 16 bit increment/decrement
- Alternate & IncDec_16(1 downto 0) when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
- XY_State(1) & "11" when (TState = 2 or
- (TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
- -- EX HL,DL
- Alternate & "10" when ExchangeDH = '1' and TState = 3 else
- Alternate & "01" when ExchangeDH = '1' and TState = 4 else
- -- Bus A / Write
- RegAddrA_r;
-
- RegAddrB <=
- -- EX HL,DL
- Alternate & "01" when ExchangeDH = '1' and TState = 3 else
- -- Bus B
- RegAddrB_r;
-
- ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
- signed(RegBusA) + 1;
-
- process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegWEH <= '0';
- RegWEL <= '0';
- if (TState = 1 and Save_ALU_r = '0') or
- (Save_ALU_r = '1' and ALU_OP_r /= "0111") then
- case Read_To_Reg_r is
- when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
- RegWEH <= not Read_To_Reg_r(0);
- RegWEL <= Read_To_Reg_r(0);
- when others =>
- end case;
- end if;
-
- if ExchangeDH = '1' and (TState = 3 or TState = 4) then
- RegWEH <= '1';
- RegWEL <= '1';
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- case IncDec_16(1 downto 0) is
- when "00" | "01" | "10" =>
- RegWEH <= '1';
- RegWEL <= '1';
- when others =>
- end case;
- end if;
- end process;
-
- process (Save_Mux, RegBusB, RegBusA_r, ID16,
- ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
- begin
- RegDIH <= Save_Mux;
- RegDIL <= Save_Mux;
-
- if ExchangeDH = '1' and TState = 3 then
- RegDIH <= RegBusB(15 downto 8);
- RegDIL <= RegBusB(7 downto 0);
- end if;
- if ExchangeDH = '1' and TState = 4 then
- RegDIH <= RegBusA_r(15 downto 8);
- RegDIL <= RegBusA_r(7 downto 0);
- end if;
-
- if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
- RegDIH <= std_logic_vector(ID16(15 downto 8));
- RegDIL <= std_logic_vector(ID16(7 downto 0));
- end if;
- end process;
-
- Regs : T80_Reg
- port map(
- Clk => CLK_n,
- CEN => ClkEn,
- WEH => RegWEH,
- WEL => RegWEL,
- AddrA => RegAddrA,
- AddrB => RegAddrB,
- AddrC => RegAddrC,
- DIH => RegDIH,
- DIL => RegDIL,
- DOAH => RegBusA(15 downto 8),
- DOAL => RegBusA(7 downto 0),
- DOBH => RegBusB(15 downto 8),
- DOBL => RegBusB(7 downto 0),
- DOCH => RegBusC(15 downto 8),
- DOCL => RegBusC(7 downto 0));
-
----------------------------------------------------------------------------
---
--- Buses
---
----------------------------------------------------------------------------
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '1' then
- if ClkEn = '1' then
- case Set_BusB_To is
- when "0111" =>
- BusB <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusB_To(0) = '1' then
- BusB <= RegBusB(7 downto 0);
- else
- BusB <= RegBusB(15 downto 8);
- end if;
- when "0110" =>
- BusB <= DI_Reg;
- when "1000" =>
- BusB <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusB <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusB <= "00000001";
- when "1011" =>
- BusB <= F;
- when "1100" =>
- BusB <= std_logic_vector(PC(7 downto 0));
- when "1101" =>
- BusB <= std_logic_vector(PC(15 downto 8));
- when "1110" =>
- BusB <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
-
- case Set_BusA_To is
- when "0111" =>
- BusA <= ACC;
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
- if Set_BusA_To(0) = '1' then
- BusA <= RegBusA(7 downto 0);
- else
- BusA <= RegBusA(15 downto 8);
- end if;
- when "0110" =>
- BusA <= DI_Reg;
- when "1000" =>
- BusA <= std_logic_vector(SP(7 downto 0));
- when "1001" =>
- BusA <= std_logic_vector(SP(15 downto 8));
- when "1010" =>
- BusA <= "00000000";
- when others =>
- BusB <= "--------";
- end case;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------------
---
--- Generate external control signals
---
----------------------------------------------------------------------------
- process (RESET_n,CLK_n)
- begin
- if RESET_n = '0' then
- RFSH_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
- RFSH_n <= '0';
- else
- RFSH_n <= '1';
- end if;
- end if;
- end if;
- end process;
-
- MC <= std_logic_vector(MCycle);
- TS <= std_logic_vector(TState);
- DI_Reg <= DI;
- HALT_n <= not Halt_FF;
- BUSAK_n <= not BusAck;
- IntCycle_n <= not IntCycle;
- IntE <= IntE_FF1;
- IORQ <= IORQ_i;
- Stop <= I_DJNZ;
-
--------------------------------------------------------------------------
---
--- Syncronise inputs
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- variable OldNMI_n : std_logic;
- begin
- if RESET_n = '0' then
- BusReq_s <= '0';
- INT_s <= '0';
- NMI_s <= '0';
- OldNMI_n := '0';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- BusReq_s <= not BUSRQ_n;
- INT_s <= not INT_n;
- if NMICycle = '1' then
- NMI_s <= '0';
- elsif NMI_n = '0' and OldNMI_n = '1' then
- NMI_s <= '1';
- end if;
- OldNMI_n := NMI_n;
- end if;
- end if;
- end process;
-
--------------------------------------------------------------------------
---
--- Main state machine
---
--------------------------------------------------------------------------
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- MCycle <= "001";
- TState <= "000";
- Pre_XY_F_M <= "000";
- Halt_FF <= '0';
- BusAck <= '0';
- NMICycle <= '0';
- IntCycle <= '0';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- No_BTR <= '0';
- Auto_Wait_t1 <= '0';
- Auto_Wait_t2 <= '0';
- M1_n <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- if CEN = '1' then
- Auto_Wait_t1 <= Auto_Wait;
- Auto_Wait_t2 <= Auto_Wait_t1;
- No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
- (I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
- (I_BTR and (not IR(4) or F(Flag_Z)));
- if TState = 2 then
- if SetEI = '1' then
- IntE_FF1 <= '1';
- IntE_FF2 <= '1';
- end if;
- if I_RETN = '1' then
- IntE_FF1 <= IntE_FF2;
- end if;
- end if;
- if TState = 3 then
- if SetDI = '1' then
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- end if;
- if IntCycle = '1' or NMICycle = '1' then
- Halt_FF <= '0';
- end if;
- if MCycle = "001" and TState = 2 and Wait_n = '1' then
- M1_n <= '1';
- end if;
- if BusReq_s = '1' and BusAck = '1' then
- else
- BusAck <= '0';
- if TState = 2 and Wait_n = '0' then
- elsif T_Res = '1' then
- if Halt = '1' then
- Halt_FF <= '1';
- end if;
- if BusReq_s = '1' then
- BusAck <= '1';
- else
- TState <= "001";
- if NextIs_XY_Fetch = '1' then
- MCycle <= "110";
- Pre_XY_F_M <= MCycle;
- if IR = "00110110" and Mode = 0 then
- Pre_XY_F_M <= "010";
- end if;
- elsif (MCycle = "111") or
- (MCycle = "110" and Mode = 1 and ISet /= "01") then
- MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
- elsif (MCycle = MCycles) or
- No_BTR = '1' or
- (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
- M1_n <= '0';
- MCycle <= "001";
- IntCycle <= '0';
- NMICycle <= '0';
- if NMI_s = '1' and Prefix = "00" then
- NMICycle <= '1';
- IntE_FF1 <= '0';
- elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
- IntCycle <= '1';
- IntE_FF1 <= '0';
- IntE_FF2 <= '0';
- end if;
- else
- MCycle <= std_logic_vector(unsigned(MCycle) + 1);
- end if;
- end if;
- else
- if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
-
- TState <= TState + 1;
- end if;
- end if;
- end if;
- if TState = 0 then
- M1_n <= '0';
- end if;
- end if;
- end if;
- end process;
-
- process (IntCycle, NMICycle, MCycle)
- begin
- Auto_Wait <= '0';
- if IntCycle = '1' or NMICycle = '1' then
- if MCycle = "001" then
- Auto_Wait <= '1';
- end if;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/T80a.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80a.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80a.vhd (nonexistent)
@@ -1,253 +0,0 @@
---
--- Z80 compatible microprocessor core, asynchronous top level
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0211 : Fixed interrupt cycle
---
--- 0235 : Updated for T80 interface change
---
--- 0238 : Updated for T80 interface change
---
--- 0240 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
--- 0247 : Fixed bus req/ack cycle
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80a is
- generic(
- Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
- );
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- D : inout std_logic_vector(7 downto 0)
- );
-end T80a;
-
-architecture rtl of T80a is
-
- signal CEN : std_logic;
- signal Reset_s : std_logic;
- signal IntCycle_n : std_logic;
- signal IORQ : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal MREQ : std_logic;
- signal MReq_Inhibit : std_logic;
- signal Req_Inhibit : std_logic;
- signal RD : std_logic;
- signal MREQ_n_i : std_logic;
- signal IORQ_n_i : std_logic;
- signal RD_n_i : std_logic;
- signal WR_n_i : std_logic;
- signal RFSH_n_i : std_logic;
- signal BUSAK_n_i : std_logic;
- signal A_i : std_logic_vector(15 downto 0);
- signal DO : std_logic_vector(7 downto 0);
- signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
- signal Wait_s : std_logic;
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- CEN <= '1';
-
- BUSAK_n <= BUSAK_n_i;
- MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
- RD_n_i <= not RD or Req_Inhibit;
-
- MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
- IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
- RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
- WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
- RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
- A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
- D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- Reset_s <= '0';
- elsif CLK_n'event and CLK_n = '1' then
- Reset_s <= '1';
- end if;
- end process;
-
- u0 : T80
- generic map(
- Mode => Mode,
- IOWait => 1)
- port map(
- CEN => CEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n_i,
- HALT_n => HALT_n,
- WAIT_n => Wait_s,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => Reset_s,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n_i,
- CLK_n => CLK_n,
- A => A_i,
- DInst => D,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n);
-
- process (CLK_n)
- begin
- if CLK_n'event and CLK_n = '0' then
- Wait_s <= WAIT_n;
- if TState = "011" and BUSAK_n_i = '1' then
- DI_Reg <= to_x01(D);
- end if;
- end if;
- end process;
-
- process (Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- WR_n_i <= '1';
- elsif CLK_n'event and CLK_n = '1' then
- WR_n_i <= '1';
- if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
- WR_n_i <= not Write;
- end if;
- end if;
- end process;
-
- process (Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- Req_Inhibit <= '0';
- elsif CLK_n'event and CLK_n = '1' then
- if MCycle = "001" and TState = "010" then
- Req_Inhibit <= '1';
- else
- Req_Inhibit <= '0';
- end if;
- end if;
- end process;
-
- process (Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- MReq_Inhibit <= '0';
- elsif CLK_n'event and CLK_n = '0' then
- if MCycle = "001" and TState = "010" then
- MReq_Inhibit <= '1';
- else
- MReq_Inhibit <= '0';
- end if;
- end if;
- end process;
-
- process(Reset_s,CLK_n)
- begin
- if Reset_s = '0' then
- RD <= '0';
- IORQ_n_i <= '1';
- MREQ <= '0';
- elsif CLK_n'event and CLK_n = '0' then
-
- if MCycle = "001" then
- if TState = "001" then
- RD <= IntCycle_n;
- MREQ <= IntCycle_n;
- IORQ_n_i <= IntCycle_n;
- end if;
- if TState = "011" then
- RD <= '0';
- IORQ_n_i <= '1';
- MREQ <= '1';
- end if;
- if TState = "100" then
- MREQ <= '0';
- end if;
- else
- if TState = "001" and NoRead = '0' then
- RD <= not Write;
- IORQ_n_i <= not IORQ;
- MREQ <= not IORQ;
- end if;
- if TState = "011" then
- RD <= '0';
- IORQ_n_i <= '1';
- MREQ <= '0';
- end if;
- end if;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/T80_ALU.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80_ALU.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80_ALU.vhd (nonexistent)
@@ -1,371 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0247
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0238 : Fixed zero flag for 16 bit SBC and ADC
---
--- 0240 : Added GB operations
---
--- 0242 : Cleanup
---
--- 0247 : Cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity T80_ALU is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- Arith16 : in std_logic;
- Z16 : in std_logic;
- ALU_Op : in std_logic_vector(3 downto 0);
- IR : in std_logic_vector(5 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- BusA : in std_logic_vector(7 downto 0);
- BusB : in std_logic_vector(7 downto 0);
- F_In : in std_logic_vector(7 downto 0);
- Q : out std_logic_vector(7 downto 0);
- F_Out : out std_logic_vector(7 downto 0)
- );
-end T80_ALU;
-
-architecture rtl of T80_ALU is
-
- procedure AddSub(A : std_logic_vector;
- B : std_logic_vector;
- Sub : std_logic;
- Carry_In : std_logic;
- signal Res : out std_logic_vector;
- signal Carry : out std_logic) is
-
- variable B_i : unsigned(A'length - 1 downto 0);
- variable Res_i : unsigned(A'length + 1 downto 0);
- begin
- if Sub = '1' then
- B_i := not unsigned(B);
- else
- B_i := unsigned(B);
- end if;
-
- Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
- Carry <= Res_i(A'length + 1);
- Res <= std_logic_vector(Res_i(A'length downto 1));
- end;
-
- -- AddSub variables (temporary signals)
- signal UseCarry : std_logic;
- signal Carry7_v : std_logic;
- signal Overflow_v : std_logic;
- signal HalfCarry_v : std_logic;
- signal Carry_v : std_logic;
- signal Q_v : std_logic_vector(7 downto 0);
-
- signal BitMask : std_logic_vector(7 downto 0);
-
-begin
-
- with IR(5 downto 3) select BitMask <= "00000001" when "000",
- "00000010" when "001",
- "00000100" when "010",
- "00001000" when "011",
- "00010000" when "100",
- "00100000" when "101",
- "01000000" when "110",
- "10000000" when others;
-
- UseCarry <= not ALU_Op(2) and ALU_Op(0);
- AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
- AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
- AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-
- -- bug fix - parity flag is just parity for 8080, also overflow for Z80
- process (Carry_v, Carry7_v, Q_v)
- begin
- if(Mode=2) then
- OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
- Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
- OverFlow_v <= Carry_v xor Carry7_v;
- end if;
- end process;
-
- process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
- variable Q_t : std_logic_vector(7 downto 0);
- variable DAA_Q : unsigned(8 downto 0);
- begin
- Q_t := "--------";
- F_Out <= F_In;
- DAA_Q := "---------";
- case ALU_Op is
- when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
- F_Out(Flag_N) <= '0';
- F_Out(Flag_C) <= '0';
- case ALU_OP(2 downto 0) is
- when "000" | "001" => -- ADD, ADC
- Q_t := Q_v;
- F_Out(Flag_C) <= Carry_v;
- F_Out(Flag_H) <= HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "010" | "011" | "111" => -- SUB, SBC, CP
- Q_t := Q_v;
- F_Out(Flag_N) <= '1';
- F_Out(Flag_C) <= not Carry_v;
- F_Out(Flag_H) <= not HalfCarry_v;
- F_Out(Flag_P) <= OverFlow_v;
- when "100" => -- AND
- Q_t(7 downto 0) := BusA and BusB;
- F_Out(Flag_H) <= '1';
- when "101" => -- XOR
- Q_t(7 downto 0) := BusA xor BusB;
- F_Out(Flag_H) <= '0';
- when others => -- OR "110"
- Q_t(7 downto 0) := BusA or BusB;
- F_Out(Flag_H) <= '0';
- end case;
- if ALU_Op(2 downto 0) = "111" then -- CP
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- else
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- end if;
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- if Z16 = '1' then
- F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
- end if;
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- case ALU_Op(2 downto 0) is
- when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
- when others =>
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- end case;
- if Arith16 = '1' then
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- F_Out(Flag_P) <= F_In(Flag_P);
- end if;
- when "1100" =>
- -- DAA
- F_Out(Flag_H) <= F_In(Flag_H);
- F_Out(Flag_C) <= F_In(Flag_C);
- DAA_Q(7 downto 0) := unsigned(BusA);
- DAA_Q(8) := '0';
- if F_In(Flag_N) = '0' then
- -- After addition
- -- Alow > 9 or H = 1
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if (DAA_Q(3 downto 0) > 9) then
- F_Out(Flag_H) <= '1';
- else
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q := DAA_Q + 6;
- end if;
- -- new Ahigh > 9 or C = 1
- if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q + 96; -- 0x60
- end if;
- else
- -- After subtraction
- if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
- if DAA_Q(3 downto 0) > 5 then
- F_Out(Flag_H) <= '0';
- end if;
- DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
- end if;
- if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
- DAA_Q := DAA_Q - 352; -- 0x160
- end if;
- end if;
- F_Out(Flag_X) <= DAA_Q(3);
- F_Out(Flag_Y) <= DAA_Q(5);
- F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
- Q_t := std_logic_vector(DAA_Q(7 downto 0));
- if DAA_Q(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= DAA_Q(7);
- F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
- DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
- when "1101" | "1110" =>
- -- RLD, RRD
- Q_t(7 downto 4) := BusA(7 downto 4);
- if ALU_Op(0) = '1' then
- Q_t(3 downto 0) := BusB(7 downto 4);
- else
- Q_t(3 downto 0) := BusB(3 downto 0);
- end if;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_S) <= Q_t(7);
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- when "1001" =>
- -- BIT
- Q_t(7 downto 0) := BusB and BitMask;
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- F_Out(Flag_P) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- F_Out(Flag_P) <= '0';
- end if;
- F_Out(Flag_H) <= '1';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= '0';
- F_Out(Flag_Y) <= '0';
- if IR(2 downto 0) /= "110" then
- F_Out(Flag_X) <= BusB(3);
- F_Out(Flag_Y) <= BusB(5);
- end if;
- when "1010" =>
- -- SET
- Q_t(7 downto 0) := BusB or BitMask;
- when "1011" =>
- -- RES
- Q_t(7 downto 0) := BusB and not BitMask;
- when "1000" =>
- -- ROT
- case IR(5 downto 3) is
- when "000" => -- RLC
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := BusA(7);
- F_Out(Flag_C) <= BusA(7);
- when "010" => -- RL
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(7);
- when "001" => -- RRC
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(0);
- F_Out(Flag_C) <= BusA(0);
- when "011" => -- RR
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := F_In(Flag_C);
- F_Out(Flag_C) <= BusA(0);
- when "100" => -- SLA
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '0';
- F_Out(Flag_C) <= BusA(7);
- when "110" => -- SLL (Undocumented) / SWAP
- if Mode = 3 then
- Q_t(7 downto 4) := BusA(3 downto 0);
- Q_t(3 downto 0) := BusA(7 downto 4);
- F_Out(Flag_C) <= '0';
- else
- Q_t(7 downto 1) := BusA(6 downto 0);
- Q_t(0) := '1';
- F_Out(Flag_C) <= BusA(7);
- end if;
- when "101" => -- SRA
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := BusA(7);
- F_Out(Flag_C) <= BusA(0);
- when others => -- SRL
- Q_t(6 downto 0) := BusA(7 downto 1);
- Q_t(7) := '0';
- F_Out(Flag_C) <= BusA(0);
- end case;
- F_Out(Flag_H) <= '0';
- F_Out(Flag_N) <= '0';
- F_Out(Flag_X) <= Q_t(3);
- F_Out(Flag_Y) <= Q_t(5);
- F_Out(Flag_S) <= Q_t(7);
- if Q_t(7 downto 0) = "00000000" then
- F_Out(Flag_Z) <= '1';
- else
- F_Out(Flag_Z) <= '0';
- end if;
- F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
- Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
- if ISet = "00" then
- F_Out(Flag_P) <= F_In(Flag_P);
- F_Out(Flag_S) <= F_In(Flag_S);
- F_Out(Flag_Z) <= F_In(Flag_Z);
- end if;
- when others =>
- null;
- end case;
- Q <= Q_t;
- end process;
-end;
Index: DE1/rtl/VHDL/t80/SSRAMX.vhd
===================================================================
--- DE1/rtl/VHDL/t80/SSRAMX.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/SSRAMX.vhd (nonexistent)
@@ -1,132 +0,0 @@
---
--- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
---
--- Version : 0247
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
---
--- 0240 : Initial release
---
--- 0242 : Changed RAMB4_S8 to map by name
---
--- 0247 : Added RAMB4_S8 component declaration
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity SSRAM is
- generic(
- AddrWidth : integer := 11;
- DataWidth : integer := 8
- );
- port(
- Clk : in std_logic;
- CE_n : in std_logic;
- WE_n : in std_logic;
- A : in std_logic_vector(AddrWidth - 1 downto 0);
- DIn : in std_logic_vector(DataWidth - 1 downto 0);
- DOut : out std_logic_vector(DataWidth - 1 downto 0)
- );
-end SSRAM;
-
-architecture rtl of SSRAM is
-
- component RAMB4_S8
- port(
- DO : out std_logic_vector(7 downto 0);
- ADDR : in std_logic_vector(8 downto 0);
- CLK : in std_ulogic;
- DI : in std_logic_vector(7 downto 0);
- EN : in std_ulogic;
- RST : in std_ulogic;
- WE : in std_ulogic);
- end component;
-
- constant RAMs : integer := (2 ** AddrWidth) / 512;
-
- type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
-
- signal bRAMOut : bRAMOut_a;
- signal biA_r : integer;
- signal A_r : unsigned(A'left downto 0);
--- signal A_i : std_logic_vector(8 downto 0);
- signal WEA : std_logic_vector(RAMs - 1 downto 0);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- A_r <= unsigned(A);
- end if;
- end process;
-
- biA_r <= to_integer(A_r(A'left downto 9));
--- A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0);
-
- bG1: for I in 0 to RAMs - 1 generate
- begin
- WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
- BSSRAM : RAMB4_S8
- port map(
- DI => DIn,
- EN => '1',
- WE => WEA(I),
- RST => '0',
- CLK => Clk,
- ADDR => A,
- DO => bRAMOut(I));
- end generate;
-
- process (biA_r, bRAMOut)
- begin
- DOut <= bRAMOut(0);
- for I in 1 to RAMs - 1 loop
- if biA_r = I then
- DOut <= bRAMOut(I);
- end if;
- end loop;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/T80_MCode.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80_MCode.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80_MCode.vhd (nonexistent)
@@ -1,1944 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
---
--- Z80 compatible microprocessor core
---
--- Version : 0242
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0208 : First complete release
---
--- 0211 : Fixed IM 1
---
--- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
---
--- 0235 : Added IM 2 fix by Mike Johnson
---
--- 0238 : Added NoRead signal
---
--- 0238b: Fixed instruction timing for POP and DJNZ
---
--- 0240 : Added (IX/IY+d) states, removed op-codes from mode 2 and added all remaining mode 3 op-codes
-
--- 0240mj1 fix for HL inc/dec for INI, IND, INIR, INDR, OUTI, OUTD, OTIR, OTDR
---
--- 0242 : Fixed I/O instruction timing, cleanup
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80_MCode is
- generic(
- Mode : integer := 0;
- Flag_C : integer := 0;
- Flag_N : integer := 1;
- Flag_P : integer := 2;
- Flag_X : integer := 3;
- Flag_H : integer := 4;
- Flag_Y : integer := 5;
- Flag_Z : integer := 6;
- Flag_S : integer := 7
- );
- port(
- IR : in std_logic_vector(7 downto 0);
- ISet : in std_logic_vector(1 downto 0);
- MCycle : in std_logic_vector(2 downto 0);
- F : in std_logic_vector(7 downto 0);
- NMICycle : in std_logic;
- IntCycle : in std_logic;
- MCycles : out std_logic_vector(2 downto 0);
- TStates : out std_logic_vector(2 downto 0);
- Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
- Inc_PC : out std_logic;
- Inc_WZ : out std_logic;
- IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
- Read_To_Reg : out std_logic;
- Read_To_Acc : out std_logic;
- Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
- Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
- ALU_Op : out std_logic_vector(3 downto 0);
- -- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
- Save_ALU : out std_logic;
- PreserveC : out std_logic;
- Arith16 : out std_logic;
- Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
- IORQ : out std_logic;
- Jump : out std_logic;
- JumpE : out std_logic;
- JumpXY : out std_logic;
- Call : out std_logic;
- RstP : out std_logic;
- LDZ : out std_logic;
- LDW : out std_logic;
- LDSPHL : out std_logic;
- Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
- ExchangeDH : out std_logic;
- ExchangeRp : out std_logic;
- ExchangeAF : out std_logic;
- ExchangeRS : out std_logic;
- I_DJNZ : out std_logic;
- I_CPL : out std_logic;
- I_CCF : out std_logic;
- I_SCF : out std_logic;
- I_RETN : out std_logic;
- I_BT : out std_logic;
- I_BC : out std_logic;
- I_BTR : out std_logic;
- I_RLD : out std_logic;
- I_RRD : out std_logic;
- I_INRC : out std_logic;
- SetDI : out std_logic;
- SetEI : out std_logic;
- IMode : out std_logic_vector(1 downto 0);
- Halt : out std_logic;
- NoRead : out std_logic;
- Write : out std_logic
- );
-end T80_MCode;
-
-architecture rtl of T80_MCode is
-
- constant aNone : std_logic_vector(2 downto 0) := "111";
- constant aBC : std_logic_vector(2 downto 0) := "000";
- constant aDE : std_logic_vector(2 downto 0) := "001";
- constant aXY : std_logic_vector(2 downto 0) := "010";
- constant aIOA : std_logic_vector(2 downto 0) := "100";
- constant aSP : std_logic_vector(2 downto 0) := "101";
- constant aZI : std_logic_vector(2 downto 0) := "110";
-
- function is_cc_true(
- F : std_logic_vector(7 downto 0);
- cc : bit_vector(2 downto 0)
- ) return boolean is
- begin
- if Mode = 3 then
- case cc is
- when "000" => return F(7) = '0'; -- NZ
- when "001" => return F(7) = '1'; -- Z
- when "010" => return F(4) = '0'; -- NC
- when "011" => return F(4) = '1'; -- C
- when "100" => return false;
- when "101" => return false;
- when "110" => return false;
- when "111" => return false;
- end case;
- else
- case cc is
- when "000" => return F(6) = '0'; -- NZ
- when "001" => return F(6) = '1'; -- Z
- when "010" => return F(0) = '0'; -- NC
- when "011" => return F(0) = '1'; -- C
- when "100" => return F(2) = '0'; -- PO
- when "101" => return F(2) = '1'; -- PE
- when "110" => return F(7) = '0'; -- P
- when "111" => return F(7) = '1'; -- M
- end case;
- end if;
- end;
-
-begin
-
- process (IR, ISet, MCycle, F, NMICycle, IntCycle)
- variable DDD : std_logic_vector(2 downto 0);
- variable SSS : std_logic_vector(2 downto 0);
- variable DPair : std_logic_vector(1 downto 0);
- variable IRB : bit_vector(7 downto 0);
- begin
- DDD := IR(5 downto 3);
- SSS := IR(2 downto 0);
- DPair := IR(5 downto 4);
- IRB := to_bitvector(IR);
-
- MCycles <= "001";
- if MCycle = "001" then
- TStates <= "100";
- else
- TStates <= "011";
- end if;
- Prefix <= "00";
- Inc_PC <= '0';
- Inc_WZ <= '0';
- IncDec_16 <= "0000";
- Read_To_Acc <= '0';
- Read_To_Reg <= '0';
- Set_BusB_To <= "0000";
- Set_BusA_To <= "0000";
- ALU_Op <= "0" & IR(5 downto 3);
- Save_ALU <= '0';
- PreserveC <= '0';
- Arith16 <= '0';
- IORQ <= '0';
- Set_Addr_To <= aNone;
- Jump <= '0';
- JumpE <= '0';
- JumpXY <= '0';
- Call <= '0';
- RstP <= '0';
- LDZ <= '0';
- LDW <= '0';
- LDSPHL <= '0';
- Special_LD <= "000";
- ExchangeDH <= '0';
- ExchangeRp <= '0';
- ExchangeAF <= '0';
- ExchangeRS <= '0';
- I_DJNZ <= '0';
- I_CPL <= '0';
- I_CCF <= '0';
- I_SCF <= '0';
- I_RETN <= '0';
- I_BT <= '0';
- I_BC <= '0';
- I_BTR <= '0';
- I_RLD <= '0';
- I_RRD <= '0';
- I_INRC <= '0';
- SetDI <= '0';
- SetEI <= '0';
- IMode <= "11";
- Halt <= '0';
- NoRead <= '0';
- Write <= '0';
-
- case ISet is
- when "00" =>
-
-------------------------------------------------------------------------------
---
--- Unprefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
--- 8 BIT LOAD GROUP
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- LD r,r'
- Set_BusB_To(2 downto 0) <= SSS;
- ExchangeRp <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when "00000110"|"00001110"|"00010110"|"00011110"|"00100110"|"00101110"|"00111110" =>
- -- LD r,n
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01111110" =>
- -- LD r,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- when others => null;
- end case;
- when "01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111" =>
- -- LD (HL),r
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110110" =>
- -- LD (HL),n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aXY;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00001010" =>
- -- LD A,(BC)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00011010" =>
- -- LD A,(DE)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- when 2 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "00111010" =>
- if Mode = 3 then
- -- LDD A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end if;
- when "00000010" =>
- -- LD (BC),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00010010" =>
- -- LD (DE),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aDE;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- when others => null;
- end case;
- when "00110010" =>
- if Mode = 3 then
- -- LDD (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1110";
- when others => null;
- end case;
- else
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 16 BIT LOAD GROUP
- when "00000001"|"00010001"|"00100001"|"00110001" =>
- -- LD dd,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1000";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1001";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "00101010" =>
- if Mode = 3 then
- -- LDI A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Acc <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD HL,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end if;
- when "00100010" =>
- if Mode = 3 then
- -- LDI (HL),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "0110";
- when others => null;
- end case;
- else
- -- LD (nn),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "0101"; -- L
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "0100"; -- H
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- end if;
- when "11111001" =>
- -- LD SP,HL
- TStates <= "110";
- LDSPHL <= '1';
- when "11000101"|"11010101"|"11100101"|"11110101" =>
- -- PUSH qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "0111";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 2 =>
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- if DPAIR = "11" then
- Set_BusB_To <= "1011";
- else
- Set_BusB_To(2 downto 1) <= DPAIR;
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- Write <= '1';
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "11000001"|"11010001"|"11100001"|"11110001" =>
- -- POP qq
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "1011";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '1';
- end if;
- when 3 =>
- IncDec_16 <= "0111";
- Read_To_Reg <= '1';
- if DPAIR = "11" then
- Set_BusA_To(3 downto 0) <= "0111";
- else
- Set_BusA_To(2 downto 1) <= DPAIR;
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
-
--- EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
- when "11101011" =>
- if Mode /= 3 then
- -- EX DE,HL
- ExchangeDH <= '1';
- end if;
- when "00001000" =>
- if Mode = 3 then
- -- LD (nn),SP
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- Set_BusB_To <= "1000";
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- Set_BusB_To <= "1001";
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EX AF,AF'
- ExchangeAF <= '1';
- end if;
- when "11011001" =>
- if Mode = 3 then
- -- RETI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- SetEI <= '1';
- when others => null;
- end case;
- elsif Mode < 2 then
- -- EXX
- ExchangeRS <= '1';
- end if;
- when "11100011" =>
- if Mode /= 3 then
- -- EX (SP),HL
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aSP;
- when 2 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0101";
- Set_BusB_To <= "0101";
- Set_Addr_To <= aSP;
- when 3 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- Set_BusA_To <= "0100";
- Set_BusB_To <= "0100";
- Set_Addr_To <= aSP;
- when 5 =>
- IncDec_16 <= "1111";
- TStates <= "101";
- Write <= '1';
- when others => null;
- end case;
- end if;
-
--- 8 BIT ARITHMETIC AND LOGICAL GROUP
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- ADD A,r
- -- ADC A,r
- -- SUB A,r
- -- SBC A,r
- -- AND A,r
- -- OR A,r
- -- XOR A,r
- -- CP A,r
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- ADD A,(HL)
- -- ADC A,(HL)
- -- SUB A,(HL)
- -- SBC A,(HL)
- -- AND A,(HL)
- -- OR A,(HL)
- -- XOR A,(HL)
- -- CP A,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- when others => null;
- end case;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- ADD A,n
- -- ADC A,n
- -- SUB A,n
- -- SBC A,n
- -- AND A,n
- -- OR A,n
- -- XOR A,n
- -- CP A,n
- MCycles <= "010";
- if MCycle = "010" then
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusA_To(2 downto 0) <= "111";
- end if;
- when "00000100"|"00001100"|"00010100"|"00011100"|"00100100"|"00101100"|"00111100" =>
- -- INC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- when "00110100" =>
- -- INC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0000";
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "00000101"|"00001101"|"00010101"|"00011101"|"00100101"|"00101101"|"00111101" =>
- -- DEC r
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- ALU_Op <= "0010";
- when "00110101" =>
- -- DEC (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- when 2 =>
- TStates <= "100";
- Set_Addr_To <= aXY;
- ALU_Op <= "0010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- PreserveC <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= DDD;
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
-
--- GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
- when "00100111" =>
- -- DAA
- Set_BusA_To(2 downto 0) <= "111";
- Read_To_Reg <= '1';
- ALU_Op <= "1100";
- Save_ALU <= '1';
- when "00101111" =>
- -- CPL
- I_CPL <= '1';
- when "00111111" =>
- -- CCF
- I_CCF <= '1';
- when "00110111" =>
- -- SCF
- I_SCF <= '1';
- when "00000000" =>
- if NMICycle = '1' then
- -- NMI
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when others => null;
- end case;
- elsif IntCycle = '1' then
- -- INT (IM 2)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- LDZ <= '1';
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- TStates <= "100";
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- TStates <= "100";
- Write <= '1';
- when 4 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 5 =>
- Jump <= '1';
- when others => null;
- end case;
- else
- -- NOP
- end if;
- when "01110110" =>
- -- HALT
- Halt <= '1';
- when "11110011" =>
- -- DI
- SetDI <= '1';
- when "11111011" =>
- -- EI
- SetEI <= '1';
-
--- 16 BIT ARITHMETIC GROUP
- when "00001001"|"00011001"|"00101001"|"00111001" =>
- -- ADD HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- Arith16 <= '1';
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- Arith16 <= '1';
- when others =>
- end case;
- when "00000011"|"00010011"|"00100011"|"00110011" =>
- -- INC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "01";
- IncDec_16(1 downto 0) <= DPair;
- when "00001011"|"00011011"|"00101011"|"00111011" =>
- -- DEC ss
- TStates <= "110";
- IncDec_16(3 downto 2) <= "11";
- IncDec_16(1 downto 0) <= DPair;
-
--- ROTATE AND SHIFT GROUP
- when "00000111"
- -- RLCA
- |"00010111"
- -- RLA
- |"00001111"
- -- RRCA
- |"00011111" =>
- -- RRA
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
-
--- JUMP GROUP
- when "11000011" =>
- -- JP nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- Jump <= '1';
- when others => null;
- end case;
- when "11000010"|"11001010"|"11010010"|"11011010"|"11100010"|"11101010"|"11110010"|"11111010" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+C),A
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "0111";
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "01" =>
- -- LD (nn),A
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- Set_BusB_To <= "0111";
- when 4 =>
- Write <= '1';
- when others => null;
- end case;
- when "10" =>
- -- LD A,($FF00+C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "11" =>
- -- LD A,(nn)
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- when 4 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- end case;
- else
- -- JP cc,nn
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Jump <= '1';
- end if;
- when others => null;
- end case;
- end if;
- when "00011000" =>
- if Mode /= 2 then
- -- JR e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00111000" =>
- if Mode /= 2 then
- -- JR C,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00110000" =>
- if Mode /= 2 then
- -- JR NC,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_C) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00101000" =>
- if Mode /= 2 then
- -- JR Z,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '0' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "00100000" =>
- if Mode /= 2 then
- -- JR NZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- if F(Flag_Z) = '1' then
- MCycles <= "010";
- end if;
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
- when "11101001" =>
- -- JP (HL)
- JumpXY <= '1';
- when "00010000" =>
- if Mode = 3 then
- I_DJNZ <= '1';
- elsif Mode < 2 then
- -- DJNZ,e
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- I_DJNZ <= '1';
- Set_BusB_To <= "1010";
- Set_BusA_To(2 downto 0) <= "000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- I_DJNZ <= '1';
- Inc_PC <= '1';
- when 3 =>
- NoRead <= '1';
- JumpE <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end if;
-
--- CALL AND RETURN GROUP
- when "11001101" =>
- -- CALL nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- IncDec_16 <= "1111";
- Inc_PC <= '1';
- TStates <= "100";
- Set_Addr_To <= aSP;
- LDW <= '1';
- Set_BusB_To <= "1101";
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
- if IR(5) = '0' or Mode /= 3 then
- -- CALL cc,nn
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Inc_PC <= '1';
- LDW <= '1';
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- IncDec_16 <= "1111";
- Set_Addr_TO <= aSP;
- TStates <= "100";
- Set_BusB_To <= "1101";
- else
- MCycles <= "011";
- end if;
- when 4 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 5 =>
- Write <= '1';
- Call <= '1';
- when others => null;
- end case;
- end if;
- when "11001001" =>
- -- RET
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
- if IR(5) = '1' and Mode = 3 then
- case IRB(4 downto 3) is
- when "00" =>
- -- LD ($FF00+nn),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "01" =>
- -- ADD SP,n
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- ALU_Op <= "0000";
- Inc_PC <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To <= "1000";
- Set_BusB_To <= "0110";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To <= "1001";
- Set_BusB_To <= "1110"; -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
- when others =>
- end case;
- when "10" =>
- -- LD A,($FF00+nn)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- when others => null;
- end case;
- when "11" =>
- -- LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Set_BusA_To(2 downto 0) <= "101"; -- L
- Read_To_Reg <= '1';
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Set_BusA_To(2 downto 0) <= "100"; -- H
- Read_To_Reg <= '1';
- when others => null;
- end case;
- end case;
- else
- -- RET cc
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
- Set_Addr_TO <= aSP;
- else
- MCycles <= "001";
- end if;
- TStates <= "101";
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- when others => null;
- end case;
- end if;
- when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
- -- RST p
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1101";
- when 2 =>
- Write <= '1';
- IncDec_16 <= "1111";
- Set_Addr_To <= aSP;
- Set_BusB_To <= "1100";
- when 3 =>
- Write <= '1';
- RstP <= '1';
- when others => null;
- end case;
-
--- INPUT AND OUTPUT GROUP
- when "11011011" =>
- if Mode /= 3 then
- -- IN A,(n)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- when 3 =>
- Read_To_Acc <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
- when "11010011" =>
- if Mode /= 3 then
- -- OUT (n),A
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- Set_Addr_To <= aIOA;
- Set_BusB_To <= "0111";
- when 3 =>
- Write <= '1';
- IORQ <= '1';
- when others => null;
- end case;
- end if;
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--- MULTIBYTE INSTRUCTIONS
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
- when "11001011" =>
- if Mode /= 2 then
- Prefix <= "01";
- end if;
-
- when "11101101" =>
- if Mode < 2 then
- Prefix <= "10";
- end if;
-
- when "11011101"|"11111101" =>
- if Mode < 2 then
- Prefix <= "11";
- end if;
-
- end case;
-
- when "01" =>
-
-------------------------------------------------------------------------------
---
--- CB prefixed instructions
---
-------------------------------------------------------------------------------
-
- Set_BusA_To(2 downto 0) <= IR(2 downto 0);
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111111" =>
- -- RLC r
- -- RL r
- -- RRC r
- -- RR r
- -- SLA r
- -- SRA r
- -- SRL r
- -- SLL r (Undocumented) / SWAP r
- if MCycle = "001" then
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "00000110"|"00010110"|"00001110"|"00011110"|"00101110"|"00111110"|"00100110"|"00110110" =>
- -- RLC (HL)
- -- RL (HL)
- -- RRC (HL)
- -- RR (HL)
- -- SRA (HL)
- -- SRL (HL)
- -- SLA (HL)
- -- SLL (HL) (Undocumented) / SWAP (HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others =>
- end case;
- when "01000000"|"01000001"|"01000010"|"01000011"|"01000100"|"01000101"|"01000111"
- |"01001000"|"01001001"|"01001010"|"01001011"|"01001100"|"01001101"|"01001111"
- |"01010000"|"01010001"|"01010010"|"01010011"|"01010100"|"01010101"|"01010111"
- |"01011000"|"01011001"|"01011010"|"01011011"|"01011100"|"01011101"|"01011111"
- |"01100000"|"01100001"|"01100010"|"01100011"|"01100100"|"01100101"|"01100111"
- |"01101000"|"01101001"|"01101010"|"01101011"|"01101100"|"01101101"|"01101111"
- |"01110000"|"01110001"|"01110010"|"01110011"|"01110100"|"01110101"|"01110111"
- |"01111000"|"01111001"|"01111010"|"01111011"|"01111100"|"01111101"|"01111111" =>
- -- BIT b,r
- if MCycle = "001" then
- Set_BusB_To(2 downto 0) <= IR(2 downto 0);
- ALU_Op <= "1001";
- end if;
- when "01000110"|"01001110"|"01010110"|"01011110"|"01100110"|"01101110"|"01110110"|"01111110" =>
- -- BIT b,(HL)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7=>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1001";
- TStates <= "100";
- when others => null;
- end case;
- when "11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111111" =>
- -- SET b,r
- if MCycle = "001" then
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "11000110"|"11001110"|"11010110"|"11011110"|"11100110"|"11101110"|"11110110"|"11111110" =>
- -- SET b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7=>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1010";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- when "10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011111"
- |"10100000"|"10100001"|"10100010"|"10100011"|"10100100"|"10100101"|"10100111"
- |"10101000"|"10101001"|"10101010"|"10101011"|"10101100"|"10101101"|"10101111"
- |"10110000"|"10110001"|"10110010"|"10110011"|"10110100"|"10110101"|"10110111"
- |"10111000"|"10111001"|"10111010"|"10111011"|"10111100"|"10111101"|"10111111" =>
- -- RES b,r
- if MCycle = "001" then
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- end if;
- when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
- -- RES b,(HL)
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 | 7 =>
- Set_Addr_To <= aXY;
- when 2 =>
- ALU_Op <= "1011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_Addr_To <= aXY;
- TStates <= "100";
- when 3 =>
- Write <= '1';
- when others => null;
- end case;
- end case;
-
- when others =>
-
-------------------------------------------------------------------------------
---
--- ED prefixed instructions
---
-------------------------------------------------------------------------------
-
- case IRB is
- when "00000000"|"00000001"|"00000010"|"00000011"|"00000100"|"00000101"|"00000110"|"00000111"
- |"00001000"|"00001001"|"00001010"|"00001011"|"00001100"|"00001101"|"00001110"|"00001111"
- |"00010000"|"00010001"|"00010010"|"00010011"|"00010100"|"00010101"|"00010110"|"00010111"
- |"00011000"|"00011001"|"00011010"|"00011011"|"00011100"|"00011101"|"00011110"|"00011111"
- |"00100000"|"00100001"|"00100010"|"00100011"|"00100100"|"00100101"|"00100110"|"00100111"
- |"00101000"|"00101001"|"00101010"|"00101011"|"00101100"|"00101101"|"00101110"|"00101111"
- |"00110000"|"00110001"|"00110010"|"00110011"|"00110100"|"00110101"|"00110110"|"00110111"
- |"00111000"|"00111001"|"00111010"|"00111011"|"00111100"|"00111101"|"00111110"|"00111111"
-
-
- |"10000000"|"10000001"|"10000010"|"10000011"|"10000100"|"10000101"|"10000110"|"10000111"
- |"10001000"|"10001001"|"10001010"|"10001011"|"10001100"|"10001101"|"10001110"|"10001111"
- |"10010000"|"10010001"|"10010010"|"10010011"|"10010100"|"10010101"|"10010110"|"10010111"
- |"10011000"|"10011001"|"10011010"|"10011011"|"10011100"|"10011101"|"10011110"|"10011111"
- | "10100100"|"10100101"|"10100110"|"10100111"
- | "10101100"|"10101101"|"10101110"|"10101111"
- | "10110100"|"10110101"|"10110110"|"10110111"
- | "10111100"|"10111101"|"10111110"|"10111111"
- |"11000000"|"11000001"|"11000010"|"11000011"|"11000100"|"11000101"|"11000110"|"11000111"
- |"11001000"|"11001001"|"11001010"|"11001011"|"11001100"|"11001101"|"11001110"|"11001111"
- |"11010000"|"11010001"|"11010010"|"11010011"|"11010100"|"11010101"|"11010110"|"11010111"
- |"11011000"|"11011001"|"11011010"|"11011011"|"11011100"|"11011101"|"11011110"|"11011111"
- |"11100000"|"11100001"|"11100010"|"11100011"|"11100100"|"11100101"|"11100110"|"11100111"
- |"11101000"|"11101001"|"11101010"|"11101011"|"11101100"|"11101101"|"11101110"|"11101111"
- |"11110000"|"11110001"|"11110010"|"11110011"|"11110100"|"11110101"|"11110110"|"11110111"
- |"11111000"|"11111001"|"11111010"|"11111011"|"11111100"|"11111101"|"11111110"|"11111111" =>
- null; -- NOP, undocumented
- when "01111110"|"01111111" =>
- -- NOP, undocumented
- null;
--- 8 BIT LOAD GROUP
- when "01010111" =>
- -- LD A,I
- Special_LD <= "100";
- TStates <= "101";
- when "01011111" =>
- -- LD A,R
- Special_LD <= "101";
- TStates <= "101";
- when "01000111" =>
- -- LD I,A
- Special_LD <= "110";
- TStates <= "101";
- when "01001111" =>
- -- LD R,A
- Special_LD <= "111";
- TStates <= "101";
--- 16 BIT LOAD GROUP
- when "01001011"|"01011011"|"01101011"|"01111011" =>
- -- LD dd,(nn)
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- when 4 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1000";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '1';
- end if;
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- when 5 =>
- Read_To_Reg <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusA_To <= "1001";
- else
- Set_BusA_To(2 downto 1) <= IR(5 downto 4);
- Set_BusA_To(0) <= '0';
- end if;
- when others => null;
- end case;
- when "01000011"|"01010011"|"01100011"|"01110011" =>
- -- LD (nn),dd
- MCycles <= "101";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Inc_PC <= '1';
- LDZ <= '1';
- when 3 =>
- Set_Addr_To <= aZI;
- Inc_PC <= '1';
- LDW <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1000";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- Set_BusB_To(3) <= '0';
- end if;
- when 4 =>
- Inc_WZ <= '1';
- Set_Addr_To <= aZI;
- Write <= '1';
- if IR(5 downto 4) = "11" then
- Set_BusB_To <= "1001";
- else
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- Set_BusB_To(3) <= '0';
- end if;
- when 5 =>
- Write <= '1';
- when others => null;
- end case;
- when "10100000" | "10101000" | "10110000" | "10111000" =>
- -- LDI, LDD, LDIR, LDDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0000";
- Set_Addr_To <= aDE;
- if IR(3) = '0' then
- IncDec_16 <= "0110"; -- IX
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- I_BT <= '1';
- TStates <= "101";
- Write <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0101"; -- DE
- else
- IncDec_16 <= "1101";
- end if;
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100001" | "10101001" | "10110001" | "10111001" =>
- -- CPI, CPD, CPIR, CPDR
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aXY;
- IncDec_16 <= "1100"; -- BC
- when 2 =>
- Set_BusB_To <= "0110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "0111";
- Save_ALU <= '1';
- PreserveC <= '1';
- if IR(3) = '0' then
- IncDec_16 <= "0110";
- else
- IncDec_16 <= "1110";
- end if;
- when 3 =>
- NoRead <= '1';
- I_BC <= '1';
- TStates <= "101";
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "01000100"|"01001100"|"01010100"|"01011100"|"01100100"|"01101100"|"01110100"|"01111100" =>
- -- NEG
- Alu_OP <= "0010";
- Set_BusB_To <= "0111";
- Set_BusA_To <= "1010";
- Read_To_Acc <= '1';
- Save_ALU <= '1';
- when "01000110"|"01001110"|"01100110"|"01101110" =>
- -- IM 0
- IMode <= "00";
- when "01010110"|"01110110" =>
- -- IM 1
- IMode <= "01";
- when "01011110"|"01110111" =>
- -- IM 2
- IMode <= "10";
--- 16 bit arithmetic
- when "01001010"|"01011010"|"01101010"|"01111010" =>
- -- ADC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0001";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0001";
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '0';
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01000010"|"01010010"|"01100010"|"01110010" =>
- -- SBC HL,ss
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "101";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- Set_BusB_To(0) <= '1';
- when others =>
- Set_BusB_To <= "1000";
- end case;
- TStates <= "100";
- when 3 =>
- NoRead <= '1';
- ALU_Op <= "0011";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- Set_BusA_To(2 downto 0) <= "100";
- case to_integer(unsigned(IR(5 downto 4))) is
- when 0|1|2 =>
- Set_BusB_To(2 downto 1) <= IR(5 downto 4);
- when others =>
- Set_BusB_To <= "1001";
- end case;
- when others =>
- end case;
- when "01101111" =>
- -- RLD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- NoRead <= '1';
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1101";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RLD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01100111" =>
- -- RRD
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 2 =>
- Set_Addr_To <= aXY;
- when 3 =>
- Read_To_Reg <= '1';
- Set_BusB_To(2 downto 0) <= "110";
- Set_BusA_To(2 downto 0) <= "111";
- ALU_Op <= "1110";
- TStates <= "100";
- Set_Addr_To <= aXY;
- Save_ALU <= '1';
- when 4 =>
- I_RRD <= '1';
- Write <= '1';
- when others =>
- end case;
- when "01000101"|"01001101"|"01010101"|"01011101"|"01100101"|"01101101"|"01110101"|"01111101" =>
- -- RETI, RETN
- MCycles <= "011";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_TO <= aSP;
- when 2 =>
- IncDec_16 <= "0111";
- Set_Addr_To <= aSP;
- LDZ <= '1';
- when 3 =>
- Jump <= '1';
- IncDec_16 <= "0111";
- I_RETN <= '1';
- when others => null;
- end case;
- when "01000000"|"01001000"|"01010000"|"01011000"|"01100000"|"01101000"|"01110000"|"01111000" =>
- -- IN r,(C)
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- when 2 =>
- IORQ <= '1';
- if IR(5 downto 3) /= "110" then
- Read_To_Reg <= '1';
- Set_BusA_To(2 downto 0) <= IR(5 downto 3);
- end if;
- I_INRC <= '1';
- when others =>
- end case;
- when "01000001"|"01001001"|"01010001"|"01011001"|"01100001"|"01101001"|"01110001"|"01111001" =>
- -- OUT (C),r
- -- OUT (C),0
- MCycles <= "010";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To(2 downto 0) <= IR(5 downto 3);
- if IR(5 downto 3) = "110" then
- Set_BusB_To(3) <= '1';
- end if;
- when 2 =>
- Write <= '1';
- IORQ <= '1';
- when others =>
- end case;
- when "10100010" | "10101010" | "10110010" | "10111010" =>
- -- INI, IND, INIR, INDR
- -- note B is decremented AFTER being put on the bus
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- Set_Addr_To <= aBC;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- IORQ <= '1';
- Set_BusB_To <= "0110";
- Set_Addr_To <= aXY;
- when 3 =>
- if IR(3) = '0' then
- --IncDec_16 <= "0010";
- IncDec_16 <= "0110";
- else
- --IncDec_16 <= "1010";
- IncDec_16 <= "1110";
- end if;
- TStates <= "100";
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- when "10100011" | "10101011" | "10110011" | "10111011" =>
- -- OUTI, OUTD, OTIR, OTDR
- -- note B is decremented BEFORE being put on the bus.
- -- mikej fix for hl inc
- MCycles <= "100";
- case to_integer(unsigned(MCycle)) is
- when 1 =>
- TStates <= "101";
- Set_Addr_To <= aXY;
- Set_BusB_To <= "1010";
- Set_BusA_To <= "0000";
- Read_To_Reg <= '1';
- Save_ALU <= '1';
- ALU_Op <= "0010";
- when 2 =>
- Set_BusB_To <= "0110";
- Set_Addr_To <= aBC;
- when 3 =>
- if IR(3) = '0' then
- IncDec_16 <= "0110"; -- mikej
- else
- IncDec_16 <= "1110"; -- mikej
- end if;
- IORQ <= '1';
- Write <= '1';
- I_BTR <= '1';
- when 4 =>
- NoRead <= '1';
- TStates <= "101";
- when others => null;
- end case;
- end case;
-
- end case;
-
- if Mode = 1 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "011";
- end if;
- end if;
-
- if Mode = 3 then
- if MCycle = "001" then
--- TStates <= "100";
- else
- TStates <= "100";
- end if;
- end if;
-
- if Mode < 2 then
- if MCycle = "110" then
- Inc_PC <= '1';
- if Mode = 1 then
- Set_Addr_To <= aXY;
- TStates <= "100";
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- end if;
- if IRB = "00110110" or IRB = "11001011" then
- Set_Addr_To <= aNone;
- end if;
- end if;
- if MCycle = "111" then
- if Mode = 0 then
- TStates <= "101";
- end if;
- if ISet /= "01" then
- Set_Addr_To <= aXY;
- end if;
- Set_BusB_To(2 downto 0) <= SSS;
- Set_BusB_To(3) <= '0';
- if IRB = "00110110" or ISet = "01" then
- -- LD (HL),n
- Inc_PC <= '1';
- else
- NoRead <= '1';
- end if;
- end if;
- end if;
-
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/SSRAM.vhd
===================================================================
--- DE1/rtl/VHDL/t80/SSRAM.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/SSRAM.vhd (nonexistent)
@@ -1,92 +0,0 @@
---
--- Inferrable Synchronous SRAM for XST synthesis
---
--- Version : 0220
---
--- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t51/
---
--- Limitations :
---
--- File history :
--- 0208 : Initial release
--- 0218 : Fixed data out at write
--- 0220 : Added support for XST
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity SSRAM is
- generic(
- AddrWidth : integer := 11;
- DataWidth : integer := 8
- );
- port(
- Clk : in std_logic;
- CE_n : in std_logic;
- WE_n : in std_logic;
- A : in std_logic_vector(AddrWidth - 1 downto 0);
- DIn : in std_logic_vector(DataWidth - 1 downto 0);
- DOut : out std_logic_vector(DataWidth - 1 downto 0)
- );
-end SSRAM;
-
-architecture behaviour of SSRAM is
-
- type Memory_Image is array (natural range <>) of std_logic_vector(DataWidth - 1 downto 0);
- signal RAM : Memory_Image(0 to 2 ** AddrWidth - 1);
- signal A_r : std_logic_vector(AddrWidth - 1 downto 0);
-
-begin
-
- process (Clk)
- begin
- if Clk'event and Clk = '1' then
- if (CE_n nor WE_n) = '1' then
- RAM(to_integer(unsigned(A))) <= DIn;
- end if;
- A_r <= A;
- end if;
- end process;
-
- DOut <= RAM(to_integer(unsigned(A_r)))
--- pragma translate_off
- when not is_x(A_r) else (others => '-')
--- pragma translate_on
- ;
-end;
Index: DE1/rtl/VHDL/t80/T80set.vhd
===================================================================
--- DE1/rtl/VHDL/t80/T80set.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/T80set.vhd (nonexistent)
@@ -1,179 +0,0 @@
--- ****
--- T80(b) core. In an effort to merge and maintain bug fixes ....
---
---
--- Ver 300 started tidyup
--- MikeJ March 2005
--- Latest version from www.fpgaarcade.com (original www.opencores.org)
---
--- ****
--- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
---
--- Z80 compatible microprocessor core, synchronous top level with clock enable
--- Different timing than the original z80
--- Inputs needs to be synchronous and outputs may glitch
---
--- Version : 0238
---
--- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- Redistributions of source code must retain the above copyright notice,
--- this list of conditions and the following disclaimer.
---
--- Redistributions in synthesized form must reproduce the above copyright
--- notice, this list of conditions and the following disclaimer in the
--- documentation and/or other materials provided with the distribution.
---
--- Neither the name of the author nor the names of other contributors may
--- be used to endorse or promote products derived from this software without
--- specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
--- Please report bugs to the author, but before you do so, please
--- make sure that this is not a derivative work and that
--- you have the latest version of this file.
---
--- The latest version of this file can be found at:
--- http://www.opencores.org/cvsweb.shtml/t80/
---
--- Limitations :
---
--- File history :
---
--- 0235 : First release
---
--- 0236 : Added T2Write generic
---
--- 0237 : Fixed T2Write with wait state
---
--- 0238 : Updated for T80 interface change
---
--- 0242 : Updated for T80 interface change
---
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use work.T80_Pack.all;
-
-entity T80sed is
- port(
- RESET_n : in std_logic;
- CLK_n : in std_logic;
- CLKEN : in std_logic;
- WAIT_n : in std_logic;
- INT_n : in std_logic;
- NMI_n : in std_logic;
- BUSRQ_n : in std_logic;
- M1_n : out std_logic;
- MREQ_n : out std_logic;
- IORQ_n : out std_logic;
- RD_n : out std_logic;
- WR_n : out std_logic;
- RFSH_n : out std_logic;
- HALT_n : out std_logic;
- BUSAK_n : out std_logic;
- A : out std_logic_vector(15 downto 0);
- DI : in std_logic_vector(7 downto 0);
- DO : out std_logic_vector(7 downto 0)
- );
-end T80sed;
-
-architecture rtl of T80sed is
-
- signal IntCycle_n : std_logic;
- signal NoRead : std_logic;
- signal Write : std_logic;
- signal IORQ : std_logic;
- signal DI_Reg : std_logic_vector(7 downto 0);
- signal MCycle : std_logic_vector(2 downto 0);
- signal TState : std_logic_vector(2 downto 0);
-
-begin
-
- u0 : T80
- generic map(
- Mode => 0,
- IOWait => 1)
- port map(
- CEN => CLKEN,
- M1_n => M1_n,
- IORQ => IORQ,
- NoRead => NoRead,
- Write => Write,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- WAIT_n => Wait_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- RESET_n => RESET_n,
- BUSRQ_n => BUSRQ_n,
- BUSAK_n => BUSAK_n,
- CLK_n => CLK_n,
- A => A,
- DInst => DI,
- DI => DI_Reg,
- DO => DO,
- MC => MCycle,
- TS => TState,
- IntCycle_n => IntCycle_n);
-
- process (RESET_n, CLK_n)
- begin
- if RESET_n = '0' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- DI_Reg <= "00000000";
- elsif CLK_n'event and CLK_n = '1' then
- if CLKEN = '1' then
- RD_n <= '1';
- WR_n <= '1';
- IORQ_n <= '1';
- MREQ_n <= '1';
- if MCycle = "001" then
- if TState = "001" or (TState = "010" and Wait_n = '0') then
- RD_n <= not IntCycle_n;
- MREQ_n <= not IntCycle_n;
- IORQ_n <= IntCycle_n;
- end if;
- if TState = "011" then
- MREQ_n <= '0';
- end if;
- else
- if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
- RD_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- if ((TState = "001") or (TState = "010")) and Write = '1' then
- WR_n <= '0';
- IORQ_n <= not IORQ;
- MREQ_n <= IORQ;
- end if;
- end if;
- if TState = "010" and Wait_n = '1' then
- DI_Reg <= DI;
- end if;
- end if;
- end if;
- end process;
-
-end;
Index: DE1/rtl/VHDL/t80/DebugSystem.vhd
===================================================================
--- DE1/rtl/VHDL/t80/DebugSystem.vhd (revision 8)
+++ DE1/rtl/VHDL/t80/DebugSystem.vhd (nonexistent)
@@ -1,181 +0,0 @@
--- Z80, Monitor ROM, 4k RAM and two 16450 UARTs
--- that can be synthesized and used with
--- the NoICE debugger that can be found at
--- http://www.noicedebugger.com/
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DebugSystem is
- port(
- Reset_n : in std_logic;
- Clk : in std_logic;
- NMI_n : in std_logic;
- RXD0 : in std_logic;
- CTS0 : in std_logic;
- DSR0 : in std_logic;
- RI0 : in std_logic;
- DCD0 : in std_logic;
- RXD1 : in std_logic;
- CTS1 : in std_logic;
- DSR1 : in std_logic;
- RI1 : in std_logic;
- DCD1 : in std_logic;
- TXD0 : out std_logic;
- RTS0 : out std_logic;
- DTR0 : out std_logic;
- TXD1 : out std_logic;
- RTS1 : out std_logic;
- DTR1 : out std_logic
- );
-end DebugSystem;
-
-architecture struct of DebugSystem is
-
- signal M1_n : std_logic;
- signal MREQ_n : std_logic;
- signal IORQ_n : std_logic;
- signal RD_n : std_logic;
- signal WR_n : std_logic;
- signal RFSH_n : std_logic;
- signal HALT_n : std_logic;
- signal WAIT_n : std_logic;
- signal INT_n : std_logic;
- signal RESET_s : std_logic;
- signal BUSRQ_n : std_logic;
- signal BUSAK_n : std_logic;
- signal A : std_logic_vector(15 downto 0);
- signal D : std_logic_vector(7 downto 0);
- signal ROM_D : std_logic_vector(7 downto 0);
- signal SRAM_D : std_logic_vector(7 downto 0);
- signal UART0_D : std_logic_vector(7 downto 0);
- signal UART1_D : std_logic_vector(7 downto 0);
- signal CPU_D : std_logic_vector(7 downto 0);
-
- signal Mirror : std_logic;
-
- signal IOWR_n : std_logic;
- signal RAMCS_n : std_logic;
- signal UART0CS_n : std_logic;
- signal UART1CS_n : std_logic;
-
- signal BaudOut0 : std_logic;
- signal BaudOut1 : std_logic;
-
-begin
-
- Wait_n <= '1';
- BusRq_n <= '1';
- INT_n <= '1';
-
- process (Reset_n, Clk)
- begin
- if Reset_n = '0' then
- Reset_s <= '0';
- Mirror <= '0';
- elsif Clk'event and Clk = '1' then
- Reset_s <= '1';
- if IORQ_n = '0' and A(7 downto 4) = "1111" then
- Mirror <= D(0);
- end if;
- end if;
- end process;
-
- IOWR_n <= WR_n or IORQ_n;
- RAMCS_n <= (not Mirror and not A(15)) or MREQ_n;
- UART0CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
- UART1CS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "10000" else '1';
-
- CPU_D <=
- SRAM_D when RAMCS_n = '0' else
- UART0_D when UART0CS_n = '0' else
- UART1_D when UART1CS_n = '0' else
- ROM_D;
-
- u0 : entity work.T80s
- generic map(Mode => 1, T2Write => 1, IOWait => 0)
- port map(
- RESET_n => RESET_s,
- CLK_n => Clk,
- WAIT_n => WAIT_n,
- INT_n => INT_n,
- NMI_n => NMI_n,
- BUSRQ_n => BUSRQ_n,
- M1_n => M1_n,
- MREQ_n => MREQ_n,
- IORQ_n => IORQ_n,
- RD_n => RD_n,
- WR_n => WR_n,
- RFSH_n => RFSH_n,
- HALT_n => HALT_n,
- BUSAK_n => BUSAK_n,
- A => A,
- DI => CPU_D,
- DO => D);
-
- u1 : entity work.MonZ80
- port map(
- Clk => Clk,
- A => A(10 downto 0),
- D => ROM_D);
-
- u2 : entity work.SSRAM
- generic map(
- AddrWidth => 12)
- port map(
- Clk => Clk,
- CE_n => RAMCS_n,
- WE_n => WR_n,
- A => A(11 downto 0),
- DIn => D,
- DOut => SRAM_D);
-
- u3 : entity work.T16450
- port map(
- MR_n => Reset_s,
- XIn => Clk,
- RClk => BaudOut0,
- CS_n => UART0CS_n,
- Rd_n => RD_n,
- Wr_n => IOWR_n,
- A => A(2 downto 0),
- D_In => D,
- D_Out => UART0_D,
- SIn => RXD0,
- CTS_n => CTS0,
- DSR_n => DSR0,
- RI_n => RI0,
- DCD_n => DCD0,
- SOut => TXD0,
- RTS_n => RTS0,
- DTR_n => DTR0,
- OUT1_n => open,
- OUT2_n => open,
- BaudOut => BaudOut0,
- Intr => open);
-
- u4 : entity work.T16450
- port map(
- MR_n => Reset_s,
- XIn => Clk,
- RClk => BaudOut1,
- CS_n => UART1CS_n,
- Rd_n => RD_n,
- Wr_n => IOWR_n,
- A => A(2 downto 0),
- D_In => D,
- D_Out => UART1_D,
- SIn => RXD1,
- CTS_n => CTS1,
- DSR_n => DSR1,
- RI_n => RI1,
- DCD_n => DCD1,
- SOut => TXD1,
- RTS_n => RTS1,
- DTR_n => DTR1,
- OUT1_n => open,
- OUT2_n => open,
- BaudOut => BaudOut1,
- Intr => open);
-
-end;
Index: DE1/rtl/VHDL/uart/uart_lib.vhd
===================================================================
--- DE1/rtl/VHDL/uart/uart_lib.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/uart_lib.vhd (nonexistent)
@@ -1,62 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
---
--- Design units : UART_Def
---
--- File name : uart_lib.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 0.1 Ovidiu Lupas 15 January 2000 New model
--- olupas@opencores.org
--------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- package UART_Def
---------------------------------------------------------------------------------
-library IEEE,STD;
-use IEEE.Std_Logic_1164.all;
-use IEEE.Numeric_Std.all;
---**--
-package UART_Def is
- -----------------------------------------------------------------------------
- -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB
- -- Error message for unknowns (U, X, W, Z, -), converted to 0
- -- Verifies whether vector is too long (> 16 bits)
- -----------------------------------------------------------------------------
- function ToInteger (
- Invector : in Unsigned(3 downto 0))
- return Integer;
-end UART_Def; --==================== End of package header ======================--
-package body UART_Def is
- function ToInteger (
- InVector : in Unsigned(3 downto 0))
- return Integer is
- constant HeaderMsg : String := "To_Integer:";
- constant MsgSeverity : Severity_Level := Warning;
- variable Value : Integer := 0;
- begin
- for i in 0 to 3 loop
- if (InVector(i) = '1') then
- Value := Value + (2**I);
- end if;
- end loop;
- return Value;
- end ToInteger;
-end UART_Def; --================ End of package body ================--
-
-
Index: DE1/rtl/VHDL/uart/miniUART.vhd
===================================================================
--- DE1/rtl/VHDL/uart/miniUART.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/miniUART.vhd (nonexistent)
@@ -1,210 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
---
--- Design units : miniUART core for the OCRP-1
---
--- File name : miniuart.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
--- Simulator : ModelSim PE/PLUS version 4.7b on a Windows95 PC
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 0.1 Ovidiu Lupas 15 January 2000 New model
--- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
--- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
--- the RSBusCtrl did not process all possible situations
---
--- olupas@opencores.org
--------------------------------------------------------------------------------
--- Description : The memory consists of a dual-port memory addressed by
--- two counters (RdCnt & WrCnt). The third counter (StatCnt)
--- sets the status signals and keeps a track of the data flow.
--------------------------------------------------------------------------------
--- Entity for miniUART Unit - 9600 baudrate --
--------------------------------------------------------------------------------
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
-library work;
- use work.UART_Def.all;
-
-entity miniUART is
- port (
- SysClk : in Std_Logic; -- System Clock
- Reset : in Std_Logic; -- Reset input
- CS_N : in Std_Logic;
- RD_N : in Std_Logic;
- WR_N : in Std_Logic;
- RxD : in Std_Logic;
- TxD : out Std_Logic;
- IntRx_N : out Std_Logic; -- Receive interrupt
- IntTx_N : out Std_Logic; -- Transmit interrupt
- Addr : in Std_Logic_Vector(1 downto 0); --
- DataIn : in Std_Logic_Vector(7 downto 0); --
- DataOut : out Std_Logic_Vector(7 downto 0)); --
-end entity; --================== End of entity ==============================--
--------------------------------------------------------------------------------
--- Architecture for miniUART Controller Unit
--------------------------------------------------------------------------------
-architecture uart of miniUART is
- -----------------------------------------------------------------------------
- -- Signals
- -----------------------------------------------------------------------------
- signal RxData : Std_Logic_Vector(7 downto 0); --
- signal TxData : Std_Logic_Vector(7 downto 0); --
- signal CSReg : Std_Logic_Vector(7 downto 0); -- Ctrl & status register
- -- CSReg detailed
- -----------+--------+--------+--------+--------+--------+--------+--------+
- -- CSReg(7)|CSReg(6)|CSReg(5)|CSReg(4)|CSReg(3)|CSReg(2)|CSReg(1)|CSReg(0)|
- -- Res | Res | Res | Res | UndRun | OvrRun | FErr | OErr |
- -----------+--------+--------+--------+--------+--------+--------+--------+
- signal EnabRx : Std_Logic; -- Enable RX unit
- signal EnabTx : Std_Logic; -- Enable TX unit
- signal DRdy : Std_Logic; -- Receive Data ready
- signal TRegE : Std_Logic; -- Transmit register empty
- signal TBufE : Std_Logic; -- Transmit buffer empty
- signal FErr : Std_Logic; -- Frame error
- signal OErr : Std_Logic; -- Output error
- signal Read : Std_Logic; -- Read receive buffer
- signal Load : Std_Logic; -- Load transmit buffer
- -----------------------------------------------------------------------------
- -- Baud rate Generator
- -----------------------------------------------------------------------------
- component ClkUnit is
- port (
- SysClk : in Std_Logic; -- System Clock
- EnableRX : out Std_Logic; -- Control signal
- EnableTX : out Std_Logic; -- Control signal
- Reset : in Std_Logic); -- Reset input
- end component;
- -----------------------------------------------------------------------------
- -- Receive Unit
- -----------------------------------------------------------------------------
- component RxUnit is
- port (
- Clk : in Std_Logic; -- Clock signal
- Reset : in Std_Logic; -- Reset input
- Enable : in Std_Logic; -- Enable input
- RxD : in Std_Logic; -- RS-232 data input
- RD : in Std_Logic; -- Read data signal
- FErr : out Std_Logic; -- Status signal
- OErr : out Std_Logic; -- Status signal
- DRdy : out Std_Logic; -- Status signal
- DataIn : out Std_Logic_Vector(7 downto 0));
- end component;
- -----------------------------------------------------------------------------
- -- Transmitter Unit
- -----------------------------------------------------------------------------
- component TxUnit is
- port (
- Clk : in Std_Logic; -- Clock signal
- Reset : in Std_Logic; -- Reset input
- Enable : in Std_Logic; -- Enable input
- Load : in Std_Logic; -- Load transmit data
- TxD : out Std_Logic; -- RS-232 data output
- TRegE : out Std_Logic; -- Tx register empty
- TBufE : out Std_Logic; -- Tx buffer empty
- DataO : in Std_Logic_Vector(7 downto 0));
- end component;
-begin
- -----------------------------------------------------------------------------
- -- Instantiation of internal components
- -----------------------------------------------------------------------------
- ClkDiv : ClkUnit port map (SysClk,EnabRX,EnabTX,Reset);
- TxDev : TxUnit port map (SysClk,Reset,EnabTX,Load,TxD,TRegE,TBufE,TxData);
- RxDev : RxUnit port map (SysClk,Reset,EnabRX,RxD,Read,FErr,OErr,DRdy,RxData);
-
- --IntRx_N <= DRdy;
- --IntTx_N <= TBufE;
- -----------------------------------------------------------------------------
- -- Implements the controller for Rx&Tx units
- -----------------------------------------------------------------------------
- RSBusCtrl : process(SysClk,Reset,Read,Load)
- variable StatM : Std_Logic_Vector(4 downto 0);
- begin
- if Rising_Edge(SysClk) then
- if Reset = '0' then
- StatM := "00000";
- --IntTx_N <= '0';
- --IntRx_N <= '0';
- CSReg <= "11110000";
- else
- StatM(0) := DRdy;
- StatM(1) := FErr;
- StatM(2) := OErr;
- StatM(3) := TBufE;
- StatM(4) := TRegE;
- end if;
- --case StatM is
- --when "00001" =>
- -- IntRx_N <= '1';
- -- CSReg(2) <= '1';
- --when "10001" =>
- -- IntRx_N <= '1';
- -- CSReg(2) <= '1';
- --when "01000" =>
- -- IntTx_N <= '1';
- --when "10000" =>
- -- IntTx_N <= '1';
- -- CSReg(3) <= '1';
- --when others => null;
- --end case;
-
- IntRx_N <= DRdy;
- IntTx_N <= TRegE;
-
- --if Read = '1' then
- -- CSReg(2) <= '0';
- -- IntRx_N <= '0';
- --end if;
-
- --if Load = '1' then
- -- CSReg(3) <= '0';
- -- IntTx_N <= '0';
- --end if;
- end if;
- end process;
- -----------------------------------------------------------------------------
- -- Combinational section
- -----------------------------------------------------------------------------
- process(SysClk)
- begin
- if (CS_N = '0' and RD_N = '0') then
- Read <= '1';
- else Read <= '0';
- end if;
-
- if (CS_N = '0' and WR_N = '0') then
- Load <= '1';
- else Load <= '0';
- end if;
-
- if Read = '0' then
- DataOut <= "ZZZZZZZZ";
- elsif (Read = '1' and Addr = "00") then
- DataOut <= RxData;
- elsif (Read = '1' and Addr = "01") then
- DataOut <= CSReg;
- end if;
-
- if Load = '0' then
- TxData <= "ZZZZZZZZ";
- elsif (Load = '1' and Addr = "00") then
- TxData <= DataIn;
- end if;
- end process;
-end uart; --===================== End of architecture =======================--
\ No newline at end of file
Index: DE1/rtl/VHDL/uart/DOCS/MiniUART.doc
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: DE1/rtl/VHDL/uart/DOCS/MiniUART.doc
===================================================================
--- DE1/rtl/VHDL/uart/DOCS/MiniUART.doc (revision 8)
+++ DE1/rtl/VHDL/uart/DOCS/MiniUART.doc (nonexistent)
DE1/rtl/VHDL/uart/DOCS/MiniUART.doc
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: DE1/rtl/VHDL/uart/clkUnit.vhd
===================================================================
--- DE1/rtl/VHDL/uart/clkUnit.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/clkUnit.vhd (nonexistent)
@@ -1,135 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
-
--- Design units : miniUART core for the OCRP-1
---
--- File name : clkUnit.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 1.0 Ovidiu Lupas 15 January 2000 New model
--- 1.1 Ovidiu Lupas 28 May 2000 EnableRx/EnableTx ratio corrected
--- olupas@opencores.org
--------------------------------------------------------------------------------
--- Description : Generates the Baud clock and enable signals for RX & TX
--- units.
--------------------------------------------------------------------------------
--- Entity for Baud rate generator Unit - 9600 baudrate --
--------------------------------------------------------------------------------
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
-library work;
- use work.UART_Def.all;
--------------------------------------------------------------------------------
--- Baud rate generator
--------------------------------------------------------------------------------
-entity ClkUnit is
- port (
- SysClk : in Std_Logic; -- System Clock
- EnableRx : out Std_Logic; -- Control signal
- EnableTx : out Std_Logic; -- Control signal
- Reset : in Std_Logic); -- Reset input
-end entity; --================== End of entity ==============================--
--------------------------------------------------------------------------------
--- Architecture for Baud rate generator Unit
--------------------------------------------------------------------------------
-architecture Behaviour of ClkUnit is
- -----------------------------------------------------------------------------
- -- Signals
- -----------------------------------------------------------------------------
- signal ClkDiv26 : Std_Logic;
- signal tmpEnRX : Std_Logic;
- signal tmpEnTX : Std_Logic;
-begin
- -----------------------------------------------------------------------------
- -- Divides the system clock of 50 MHz by 32
- -----------------------------------------------------------------------------
- DivClk26 : process(SysClk,Reset)
- constant CntOne : unsigned(4 downto 0) := "00001";
- variable Cnt26 : unsigned(5 downto 0);
- begin
- if Rising_Edge(SysClk) then
- if Reset = '0' then
- Cnt26 := "000000";
- ClkDiv26 <= '0';
- else
- Cnt26 := Cnt26 + CntOne;
- case Cnt26 is
- when "100000" =>
- ClkDiv26 <= '1';
- Cnt26 := "000000";
- when others =>
- ClkDiv26 <= '0';
- end case;
- end if;
- end if;
- end process;
- -----------------------------------------------------------------------------
- -- Provides the EnableRX signal, at ~ 155 KHz
- -----------------------------------------------------------------------------
- DivClk10 : process(SysClk,Reset,Clkdiv26)
- constant CntOne : unsigned(3 downto 0) := "0001";
- variable Cnt10 : unsigned(3 downto 0);
- begin
- if Rising_Edge(SysClk) then
- if Reset = '0' then
- Cnt10 := "0000";
- tmpEnRX <= '0';
- elsif ClkDiv26 = '1' then
- Cnt10 := Cnt10 + CntOne;
- end if;
- case Cnt10 is
- when "1010" =>
- tmpEnRX <= '1';
- Cnt10 := "0000";
- when others =>
- tmpEnRX <= '0';
- end case;
- end if;
- end process;
- -----------------------------------------------------------------------------
- -- Provides the EnableTX signal, at 9.6 KHz
- -----------------------------------------------------------------------------
- DivClk16 : process(SysClk,Reset,tmpEnRX)
- constant CntOne : unsigned(4 downto 0) := "00001";
- variable Cnt16 : unsigned(4 downto 0);
- begin
- if Rising_Edge(SysClk) then
- if Reset = '0' then
- Cnt16 := "00000";
- tmpEnTX <= '0';
- elsif tmpEnRX = '1' then
- Cnt16 := Cnt16 + CntOne;
- end if;
- case Cnt16 is
- when "01111" =>
- tmpEnTX <= '1';
- Cnt16 := Cnt16 + CntOne;
- when "10001" =>
- Cnt16 := "00000";
- tmpEnTX <= '0';
- when others =>
- tmpEnTX <= '0';
- end case;
- end if;
- end process;
-
- EnableRX <= tmpEnRX;
- EnableTX <= tmpEnTX;
-end Behaviour; --==================== End of architecture ===================--
\ No newline at end of file
Index: DE1/rtl/VHDL/uart/RxUnit.vhd
===================================================================
--- DE1/rtl/VHDL/uart/RxUnit.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/RxUnit.vhd (nonexistent)
@@ -1,155 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
---
--- Design units : miniUART core for the OCRP-1
---
--- File name : RxUnit.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 0.1 Ovidiu Lupas 15 January 2000 New model
--- 2.0 Ovidiu Lupas 17 April 2000 samples counter cleared for bit 0
--- olupas@opencores.org
--------------------------------------------------------------------------------
--- Description : Implements the receive unit of the miniUART core. Samples
--- 16 times the RxD line and retain the value in the middle of
--- the time interval.
--------------------------------------------------------------------------------
--- Entity for Receive Unit - 9600 baudrate --
--------------------------------------------------------------------------------
-library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
-library work;
- use work.UART_Def.all;
--------------------------------------------------------------------------------
--- Receive unit
--------------------------------------------------------------------------------
-entity RxUnit is
- port (
- Clk : in Std_Logic; -- system clock signal
- Reset : in Std_Logic; -- Reset input
- Enable : in Std_Logic; -- Enable input
- RxD : in Std_Logic; -- RS-232 data input
- RD : in Std_Logic; -- Read data signal
- FErr : out Std_Logic; -- Status signal
- OErr : out Std_Logic; -- Status signal
- DRdy : out Std_Logic; -- Status signal
- DataIn : out Std_Logic_Vector(7 downto 0));
-end entity; --================== End of entity ==============================--
--------------------------------------------------------------------------------
--- Architecture for receive Unit
--------------------------------------------------------------------------------
-architecture Behaviour of RxUnit is
- -----------------------------------------------------------------------------
- -- Signals
- -----------------------------------------------------------------------------
- signal Start : Std_Logic; -- Syncro signal
- signal tmpRxD : Std_Logic; -- RxD buffer
- signal tmpDRdy : Std_Logic; -- Data ready buffer
- signal outErr : Std_Logic; --
- signal frameErr : Std_Logic; --
- signal BitCnt : Unsigned(3 downto 0); --
- signal SampleCnt : Unsigned(3 downto 0); -- samples on one bit counter
- signal ShtReg : Std_Logic_Vector(7 downto 0); --
- signal DOut : Std_Logic_Vector(7 downto 0); --
-begin
- ---------------------------------------------------------------------
- -- Receiver process
- ---------------------------------------------------------------------
- RcvProc : process(Clk,Reset,Enable,RxD)
- variable tmpBitCnt : Integer range 0 to 15;
- variable tmpSampleCnt : Integer range 0 to 15;
- constant CntOne : Unsigned(3 downto 0):="0001";
- begin
- if Rising_Edge(Clk) then
- tmpBitCnt := ToInteger(BitCnt);
- tmpSampleCnt := ToInteger(SampleCnt);
- if Reset = '0' then
- BitCnt <= "0000";
- SampleCnt <= "0000";
- Start <= '0';
- tmpDRdy <= '0';
- frameErr <= '0';
- outErr <= '0';
-
- ShtReg <= "00000000"; --
- DOut <= "00000000"; --
- else
- if RD = '1' then
- tmpDRdy <= '0'; -- Data was read
- end if;
-
- if Enable = '1' then
- if Start = '0' then
- if RxD = '0' then -- Start bit,
- SampleCnt <= SampleCnt + CntOne;
- Start <= '1';
- end if;
- else
- if tmpSampleCnt = 8 then -- reads the RxD line
- tmpRxD <= RxD;
- SampleCnt <= SampleCnt + CntOne;
- elsif tmpSampleCnt = 15 then
- case tmpBitCnt is
- when 0 =>
- if tmpRxD = '1' then -- Start Bit
- Start <= '0';
- else
- BitCnt <= BitCnt + CntOne;
- end if;
- SampleCnt <= SampleCnt + CntOne;
- when 1|2|3|4|5|6|7|8 =>
- BitCnt <= BitCnt + CntOne;
- SampleCnt <= SampleCnt + CntOne;
- ShtReg <= tmpRxD & ShtReg(7 downto 1);
- when 9 =>
- if tmpRxD = '0' then -- stop bit expected
- frameErr <= '1';
- else
- frameErr <= '0';
- end if;
-
- if tmpDRdy = '1' then --
- outErr <= '1';
- else
- outErr <= '0';
- end if;
-
- tmpDRdy <= '1';
- DOut <= ShtReg;
- BitCnt <= "0000";
- Start <= '0';
- when others =>
- null;
- end case;
- else
- SampleCnt <= SampleCnt + CntOne;
- end if;
- end if;
- end if;
- end if;
- end if;
- end process;
-
- DRdy <= tmpDRdy;
- DataIn <= DOut;
- FErr <= frameErr;
- OErr <= outErr;
-
-end Behaviour; --==================== End of architecture ====================--
\ No newline at end of file
Index: DE1/rtl/VHDL/uart/uart.vhd
===================================================================
--- DE1/rtl/VHDL/uart/uart.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/uart.vhd (nonexistent)
@@ -1,148 +0,0 @@
--------------------------------------------------------------------------------
--- Title : UART
--- Project : UART
--------------------------------------------------------------------------------
--- File : MiniUart.vhd
--- Author : Philippe CARTON
--- (philippe.carton2@libertysurf.fr)
--- Organization:
--- Created : 15/12/2001
--- Last update : 8/1/2003
--- Platform : Foundation 3.1i
--- Simulators : ModelSim 5.5b
--- Synthesizers: Xilinx Synthesis
--- Targets : Xilinx Spartan
--- Dependency : IEEE std_logic_1164, Rxunit.vhd, Txunit.vhd, utils.vhd
--------------------------------------------------------------------------------
--- Description: Uart (Universal Asynchronous Receiver Transmitter) for SoC.
--- Wishbone compatable.
--------------------------------------------------------------------------------
--- Copyright (c) notice
--- This core adheres to the GNU public license
---
--------------------------------------------------------------------------------
--- Revisions :
--- Revision Number :
--- Version :
--- Date :
--- Modifier : name
--- Description :
---
-------------------------------------------------------------------------------
-
-library ieee;
- use ieee.std_logic_1164.all;
-
-entity UART is
- generic(BRDIVISOR: INTEGER range 0 to 65535 := 1302); -- Baud rate divisor 130
- port (
--- Wishbone signals
- WB_CLK_I : in std_logic; -- clock
- WB_RST_I : in std_logic; -- Reset input
- WB_ADR_I : in std_logic_vector(1 downto 0); -- Adress bus
- WB_DAT_I : in std_logic_vector(7 downto 0); -- DataIn Bus
- WB_DAT_O : out std_logic_vector(7 downto 0); -- DataOut Bus
- WB_WE_I : in std_logic; -- Write Enable
- WB_STB_I : in std_logic; -- Strobe
- WB_ACK_O : out std_logic; -- Acknowledge
--- process signals
- IntTx_O : out std_logic; -- Transmit interrupt: indicate waiting for Byte
- IntRx_O : out std_logic; -- Receive interrupt: indicate Byte received
- BR_Clk_I : in std_logic; -- Clock used for Transmit/Receive
- TxD_PAD_O: out std_logic; -- Tx RS232 Line
- RxD_PAD_I: in std_logic); -- Rx RS232 Line
-end UART;
-
--- Architecture for UART for synthesis
-architecture Behaviour of UART is
-
- component Counter
- generic(COUNT: INTEGER range 0 to 65535); -- Count revolution
- port (
- Clk : in std_logic; -- Clock
- Reset : in std_logic; -- Reset input
- CE : in std_logic; -- Chip Enable
- O : out std_logic); -- Output
- end component;
-
- component RxUnit
- port (
- Clk : in std_logic; -- system clock signal
- Reset : in std_logic; -- Reset input
- Enable : in std_logic; -- Enable input
- ReadA : in Std_logic; -- Async Read Received Byte
- RxD : in std_logic; -- RS-232 data input
- RxAv : out std_logic; -- Byte available
- DataO : out std_logic_vector(7 downto 0)); -- Byte received
- end component;
-
- component TxUnit
- port (
- Clk : in std_logic; -- Clock signal
- Reset : in std_logic; -- Reset input
- Enable : in std_logic; -- Enable input
- LoadA : in std_logic; -- Asynchronous Load
- TxD : out std_logic; -- RS-232 data output
- Busy : out std_logic; -- Tx Busy
- DataI : in std_logic_vector(7 downto 0)); -- Byte to transmit
- end component;
-
- signal RxData : std_logic_vector(7 downto 0); -- Last Byte received
- signal TxData : std_logic_vector(7 downto 0); -- Last bytes transmitted
- signal SReg : std_logic_vector(7 downto 0); -- Status register
- signal EnabRx : std_logic; -- Enable RX unit
- signal EnabTx : std_logic; -- Enable TX unit
- signal RxAv : std_logic; -- Data Received
- signal TxBusy : std_logic; -- Transmiter Busy
- signal ReadA : std_logic; -- Async Read receive buffer
- signal LoadA : std_logic; -- Async Load transmit buffer
- signal Sig0 : std_logic; -- gnd signal
- signal Sig1 : std_logic; -- vcc signal
- --signal Counter : std_logic_vector(2 downto 0);
-
-
- begin
- sig0 <= '0';
- sig1 <= '1';
- Uart_Rxrate : Counter -- Baud Rate adjust
- generic map (COUNT => BRDIVISOR)
- port map (BR_CLK_I, sig0, sig1, EnabRx);
- Uart_Txrate : Counter -- 4 Divider for Tx
- generic map (COUNT => 4)
- port map (BR_CLK_I, Sig0, EnabRx, EnabTx);
- Uart_TxUnit : TxUnit port map (BR_CLK_I, WB_RST_I, EnabTX, LoadA, TxD_PAD_O, TxBusy, TxData);
- Uart_RxUnit : RxUnit port map (BR_CLK_I, WB_RST_I, EnabRX, ReadA, RxD_PAD_I, RxAv, RxData);
- IntTx_O <= not TxBusy;
- IntRx_O <= RxAv;
- SReg(0) <= not TxBusy;
- SReg(1) <= RxAv;
- SReg(7 downto 2) <= "000000";
-
- -- Implements WishBone data exchange.
- -- Clocked on rising edge. Synchronous Reset RST_I
- WBctrl : process(WB_CLK_I, WB_RST_I, WB_STB_I, WB_WE_I, WB_ADR_I)
- variable StatM : std_logic_vector(4 downto 0);
- begin
- if Rising_Edge(WB_CLK_I) then
- if (WB_RST_I = '1') then
- ReadA <= '0';
- LoadA <= '0';
- else
- if (WB_STB_I = '1' and WB_WE_I = '1' and WB_ADR_I = "00") then -- Write Byte to Tx
- TxData <= WB_DAT_I;
- LoadA <= '1'; -- Load signal
- else LoadA <= '0';
- end if;
- if (WB_STB_I = '1' and WB_WE_I = '0' and WB_ADR_I = "00") then -- Read Byte from Rx
- ReadA <= '1'; -- Read signal
- else ReadA <= '0';
- end if;
- end if;
- end if;
- end process;
- WB_ACK_O <= WB_STB_I;
- WB_DAT_O <=
- RxData when WB_ADR_I = "00" else -- Read Byte from Rx
- SReg when WB_ADR_I = "01" else -- Read Status Reg
- "00000000";
-end Behaviour;
Index: DE1/rtl/VHDL/uart/clk_div.vhd
===================================================================
--- DE1/rtl/VHDL/uart/clk_div.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/clk_div.vhd (nonexistent)
@@ -1,174 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-
-ENTITY clk_div IS
-
- PORT
- (
- clock_25Mhz : IN STD_LOGIC;
- clock_1MHz : OUT STD_LOGIC;
- clock_100KHz : OUT STD_LOGIC;
- clock_10KHz : OUT STD_LOGIC;
- clock_1KHz : OUT STD_LOGIC;
- clock_100Hz : OUT STD_LOGIC;
- clock_10Hz : OUT STD_LOGIC;
- clock_1Hz : OUT STD_LOGIC;
- clock_10sec : OUT STD_LOGIC;
- clock_1min : OUT STD_LOGIC;
- clock_1hr : OUT STD_LOGIC);
-
-END clk_div;
-
-ARCHITECTURE a OF clk_div IS
-
- SIGNAL count_1Mhz: STD_LOGIC_VECTOR(4 DOWNTO 0);
- SIGNAL count_100Khz, count_10Khz, count_1Khz : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL count_100hz, count_10hz, count_1hz : STD_LOGIC_VECTOR(2 DOWNTO 0);
- SIGNAL count_10sec, count_1min, count_1hr : STD_LOGIC_VECTOR(2 DOWNTO 0);
-
- SIGNAL clock_1Mhz_int, clock_100Khz_int, clock_10Khz_int, clock_1Khz_int: STD_LOGIC;
- SIGNAL clock_100hz_int, clock_10Hz_int, clock_1Hz_int : STD_LOGIC;
- SIGNAL clock_10sec_int, clock_1min_int, clock_1hr_int : STD_LOGIC;
-
-BEGIN
- PROCESS
- BEGIN
--- Divide by 25
- WAIT UNTIL clock_25Mhz'EVENT and clock_25Mhz = '1';
- IF count_1Mhz < 24 THEN
- count_1Mhz <= count_1Mhz + 1;
- ELSE
- count_1Mhz <= "00000";
- END IF;
- IF count_1Mhz < 12 THEN
- clock_1Mhz_int <= '0';
- ELSE
- clock_1Mhz_int <= '1';
- END IF;
-
--- Ripple clocks are used in this code to save prescalar hardware
--- Sync all clock prescalar outputs back to master clock signal
- clock_1Mhz <= clock_1Mhz_int;
- clock_100Khz <= clock_100Khz_int;
- clock_10Khz <= clock_10Khz_int;
- clock_1Khz <= clock_1Khz_int;
- clock_100hz <= clock_100hz_int;
- clock_10hz <= clock_10hz_int;
- clock_1hz <= clock_1hz_int;
- clock_10sec <= clock_10sec_int;
- clock_1min <= clock_1min_int;
- clock_1hr <= clock_1hr_int;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_1Mhz_int'EVENT and clock_1Mhz_int = '1';
- IF count_100Khz /= 4 THEN
- count_100Khz <= count_100Khz + 1;
- ELSE
- count_100khz <= "000";
- clock_100Khz_int <= NOT clock_100Khz_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_100Khz_int'EVENT and clock_100Khz_int = '1';
- IF count_10Khz /= 4 THEN
- count_10Khz <= count_10Khz + 1;
- ELSE
- count_10khz <= "000";
- clock_10Khz_int <= NOT clock_10Khz_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_10Khz_int'EVENT and clock_10Khz_int = '1';
- IF count_1Khz /= 4 THEN
- count_1Khz <= count_1Khz + 1;
- ELSE
- count_1khz <= "000";
- clock_1Khz_int <= NOT clock_1Khz_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_1Khz_int'EVENT and clock_1Khz_int = '1';
- IF count_100hz /= 4 THEN
- count_100hz <= count_100hz + 1;
- ELSE
- count_100hz <= "000";
- clock_100hz_int <= NOT clock_100hz_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_100hz_int'EVENT and clock_100hz_int = '1';
- IF count_10hz /= 4 THEN
- count_10hz <= count_10hz + 1;
- ELSE
- count_10hz <= "000";
- clock_10hz_int <= NOT clock_10hz_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_10hz_int'EVENT and clock_10hz_int = '1';
- IF count_1hz /= 4 THEN
- count_1hz <= count_1hz + 1;
- ELSE
- count_1hz <= "000";
- clock_1hz_int <= NOT clock_1hz_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_1hz_int'EVENT and clock_1hz_int = '1';
- IF count_10sec /= 4 THEN
- count_10sec <= count_10sec + 1;
- ELSE
- count_10sec <= "000";
- clock_10sec_int <= NOT clock_10sec_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_10sec_int'EVENT and clock_10sec_int = '1';
- IF count_1min /= 4 THEN
- count_1min <= count_1min + 1;
- ELSE
- count_1min <= "000";
- clock_1min_int <= NOT clock_1min_int;
- END IF;
- END PROCESS;
-
--- Divide by 10
- PROCESS
- BEGIN
- WAIT UNTIL clock_1min_int'EVENT and clock_1min_int = '1';
- IF count_1hr /= 4 THEN
- count_1hr <= count_1hr + 1;
- ELSE
- count_1hr <= "000";
- clock_1hr_int <= NOT clock_1hr_int;
- END IF;
- END PROCESS;
-
-END a;
-
Index: DE1/rtl/VHDL/uart/TxUnit.vhd
===================================================================
--- DE1/rtl/VHDL/uart/TxUnit.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/TxUnit.vhd (nonexistent)
@@ -1,116 +0,0 @@
---===========================================================================--
---
--- S Y N T H E Z I A B L E miniUART C O R E
---
--- www.OpenCores.Org - January 2000
--- This core adheres to the GNU public license
---
--- Design units : miniUART core for the OCRP-1
---
--- File name : TxUnit.vhd
---
--- Purpose : Implements an miniUART device for communication purposes
--- between the OR1K processor and the Host computer through
--- an RS-232 communication protocol.
---
--- Library : uart_lib.vhd
---
--- Dependencies : IEEE.Std_Logic_1164
---
---===========================================================================--
--------------------------------------------------------------------------------
--- Revision list
--- Version Author Date Changes
---
--- 0.1 Ovidiu Lupas 15 January 2000 New model
--- 2.0 Ovidiu Lupas 17 April 2000 unnecessary variable removed
--- olupas@opencores.org
--------------------------------------------------------------------------------
--- Description :
--------------------------------------------------------------------------------
--- Entity for the Tx Unit --
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library work;
-use work.Uart_Def.all;
--------------------------------------------------------------------------------
--- Transmitter unit
--------------------------------------------------------------------------------
-entity TxUnit is
- port (
- Clk : in Std_Logic; -- Clock signal
- Reset : in Std_Logic; -- Reset input
- Enable : in Std_Logic; -- Enable input
- Load : in Std_Logic; -- Load transmit data
- TxD : out Std_Logic; -- RS-232 data output
- TRegE : out Std_Logic; -- Tx register empty
- TBufE : out Std_Logic; -- Tx buffer empty
- DataO : in Std_Logic_Vector(7 downto 0));
-end entity; --================== End of entity ==============================--
--------------------------------------------------------------------------------
--- Architecture for TxUnit
--------------------------------------------------------------------------------
-architecture Behaviour of TxUnit is
- -----------------------------------------------------------------------------
- -- Signals
- -----------------------------------------------------------------------------
- signal TBuff : Std_Logic_Vector(7 downto 0); -- transmit buffer
- signal TReg : Std_Logic_Vector(7 downto 0); -- transmit register
- signal BitCnt : Unsigned(3 downto 0); -- bit counter
- signal tmpTRegE : Std_Logic; --
- signal tmpTBufE : Std_Logic; --
-begin
- -----------------------------------------------------------------------------
- -- Implements the Tx unit
- -----------------------------------------------------------------------------
- process(Clk,Reset,Enable,Load,DataO,TBuff,TReg,tmpTRegE,tmpTBufE)
- variable tmp_TRegE : Std_Logic;
- constant CntOne : Unsigned(3 downto 0):="0001";
- begin
- if Rising_Edge(Clk) then
- if Reset = '0' then
- tmpTRegE <= '1';
- tmpTBufE <= '1';
- TxD <= '1';
- BitCnt <= "0000";
- elsif Load = '1' then
- TBuff <= DataO;
- tmpTBufE <= '0';
- elsif Enable = '1' then
- if ( tmpTBufE = '0') and (tmpTRegE = '1') then
- TReg <= TBuff;
- tmpTRegE <= '0';
--- tmp_TRegE := '0';
- tmpTBufE <= '1';
--- else
--- tmp_TRegE := tmpTRegE;
- end if;
-
- if tmpTRegE = '0' then
- case BitCnt is
- when "0000" =>
- TxD <= '0';
- BitCnt <= BitCnt + CntOne;
- when "0001" | "0010" | "0011" |
- "0100" | "0101" | "0110" |
- "0111" | "1000" =>
- TxD <= TReg(0);
- TReg <= '1' & TReg(7 downto 1);
- BitCnt <= BitCnt + CntOne;
- when "1001" =>
- TxD <= '1';
- TReg <= '1' & TReg(7 downto 1);
- BitCnt <= "0000";
- tmpTRegE <= '1';
- when others => null;
- end case;
- end if;
- end if;
- end if;
- end process;
-
- TRegE <= tmpTRegE;
- TBufE <= tmpTBufE;
-end Behaviour; --=================== End of architecture ====================--
\ No newline at end of file
Index: DE1/rtl/VHDL/uart/top_uart.vhd
===================================================================
--- DE1/rtl/VHDL/uart/top_uart.vhd (revision 8)
+++ DE1/rtl/VHDL/uart/top_uart.vhd (nonexistent)
@@ -1,181 +0,0 @@
--------------------------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_arith.all;
-use IEEE.std_logic_unsigned.all;
-
-entity TOP_UART is
- port(
-
- -- Clocks
- CLOCK_27, -- 27 MHz
- CLOCK_50, -- 50 MHz
- EXT_CLOCK : in std_logic; -- External Clock
-
- -- Buttons and switches
- KEY : in std_logic_vector(3 downto 0); -- Push buttons
- SW : in std_logic_vector(9 downto 0); -- Switches
-
- -- LED displays
- HEX0, HEX1, HEX2, HEX3 -- 7-segment displays
- : out std_logic_vector(6 downto 0);
- LEDG : out std_logic_vector(7 downto 0); -- Green LEDs
- LEDR : out std_logic_vector(9 downto 0); -- Red LEDs
-
- -- RS-232 interface
- UART_TXD : out std_logic; -- UART transmitter
- UART_RXD : in std_logic; -- UART receiver
-
- -- IRDA interface
-
- -- IRDA_TXD : out std_logic; -- IRDA Transmitter
- IRDA_RXD : in std_logic; -- IRDA Receiver
-
- -- SDRAM
- DRAM_DQ : inout std_logic_vector(15 downto 0); -- Data Bus
- DRAM_ADDR : out std_logic_vector(11 downto 0); -- Address Bus
- DRAM_LDQM, -- Low-byte Data Mask
- DRAM_UDQM, -- High-byte Data Mask
- DRAM_WE_N, -- Write Enable
- DRAM_CAS_N, -- Column Address Strobe
- DRAM_RAS_N, -- Row Address Strobe
- DRAM_CS_N, -- Chip Select
- DRAM_BA_0, -- Bank Address 0
- DRAM_BA_1, -- Bank Address 0
- DRAM_CLK, -- Clock
- DRAM_CKE : out std_logic; -- Clock Enable
-
- -- FLASH
- FL_DQ : inout std_logic_vector(7 downto 0); -- Data bus
- FL_ADDR : out std_logic_vector(21 downto 0); -- Address bus
- FL_WE_N, -- Write Enable
- FL_RST_N, -- Reset
- FL_OE_N, -- Output Enable
- FL_CE_N : out std_logic; -- Chip Enable
-
- -- SRAM
- SRAM_DQ : inout std_logic_vector(15 downto 0); -- Data bus 16 Bits
- SRAM_ADDR : out std_logic_vector(17 downto 0); -- Address bus 18 Bits
- SRAM_UB_N, -- High-byte Data Mask
- SRAM_LB_N, -- Low-byte Data Mask
- SRAM_WE_N, -- Write Enable
- SRAM_CE_N, -- Chip Enable
- SRAM_OE_N : out std_logic; -- Output Enable
-
- -- SD card interface
- SD_DAT : in std_logic; -- SD Card Data SD pin 7 "DAT 0/DataOut"
- SD_DAT3 : out std_logic; -- SD Card Data 3 SD pin 1 "DAT 3/nCS"
- SD_CMD : out std_logic; -- SD Card Command SD pin 2 "CMD/DataIn"
- SD_CLK : out std_logic; -- SD Card Clock SD pin 5 "CLK"
-
- -- USB JTAG link
- TDI, -- CPLD -> FPGA (data in)
- TCK, -- CPLD -> FPGA (clk)
- TCS : in std_logic; -- CPLD -> FPGA (CS)
- TDO : out std_logic; -- FPGA -> CPLD (data out)
-
- -- I2C bus
- I2C_SDAT : inout std_logic; -- I2C Data
- I2C_SCLK : out std_logic; -- I2C Clock
-
- -- PS/2 port
- PS2_DAT, -- Data
- PS2_CLK : inout std_logic; -- Clock
-
- -- VGA output
- VGA_HS, -- H_SYNC
- VGA_VS : out std_logic; -- SYNC
- VGA_R, -- Red[3:0]
- VGA_G, -- Green[3:0]
- VGA_B : out std_logic_vector(3 downto 0); -- Blue[3:0]
-
- -- Audio CODEC
- AUD_ADCLRCK : inout std_logic; -- ADC LR Clock
- AUD_ADCDAT : in std_logic; -- ADC Data
- AUD_DACLRCK : inout std_logic; -- DAC LR Clock
- AUD_DACDAT : out std_logic; -- DAC Data
- AUD_BCLK : inout std_logic; -- Bit-Stream Clock
- AUD_XCK : out std_logic; -- Chip Clock
-
- -- General-purpose I/O
- GPIO_0, -- GPIO Connection 0
- GPIO_1 : inout std_logic_vector(35 downto 0) -- GPIO Connection 1
-);
-end TOP_UART;
-
-architecture rtl of TOP_UART is
-
- component miniUART
- port (
- SysClk : in Std_Logic; -- System Clock
- Reset : in Std_Logic; -- Reset input
- CS_N : in Std_Logic;
- RD_N : in Std_Logic;
- WR_N : in Std_Logic;
- RxD : in Std_Logic;
- TxD : out Std_Logic;
- IntRx_N : out Std_Logic; -- Receive interrupt
- IntTx_N : out Std_Logic; -- Transmit interrupt
- Addr : in Std_Logic_Vector(1 downto 0); --
- DataIn : in Std_Logic_Vector(7 downto 0); --
- DataOut : out Std_Logic_Vector(7 downto 0)); --
- end component;
-
-begin
-
- U1 : miniUART PORT MAP (
- SysClk => CLOCK_50, --: in Std_Logic; -- System Clock
- Reset => KEY(0), --: in Std_Logic; -- Reset input
- CS_N => SW(0), --: in Std_Logic;
- RD_N => SW(1), --: in Std_Logic;
- WR_N => SW(2), --: in Std_Logic;
- RxD => UART_RXD, --: in Std_Logic;
- TxD => UART_TXD, --: out Std_Logic;
- IntRx_N => LEDG(0), --: out Std_Logic; -- Receive interrupt
- IntTx_N => LEDG(1), --: out Std_Logic; -- Transmit interrupt
- Addr => SW(8 downto 7), --: in Std_Logic_Vector(1 downto 0); --
- DataIn => x"69", --: in Std_Logic_Vector(7 downto 0); --
- DataOut => LEDR(7 downto 0)--: out Std_Logic_Vector(7 downto 0)); --
- );
-
- --
- SRAM_DQ(15 downto 8) <= (others => 'Z');
- SRAM_ADDR(17 downto 16) <= "00";
- SRAM_UB_N <= '1';
- SRAM_LB_N <= '0';
- SRAM_CE_N <= '0';
- --
- UART_TXD <= 'Z';
- DRAM_ADDR <= (others => '0');
- DRAM_LDQM <= '0';
- DRAM_UDQM <= '0';
- DRAM_WE_N <= '1';
- DRAM_CAS_N <= '1';
- DRAM_RAS_N <= '1';
- DRAM_CS_N <= '1';
- DRAM_BA_0 <= '0';
- DRAM_BA_1 <= '0';
- DRAM_CLK <= '0';
- DRAM_CKE <= '0';
- FL_ADDR <= (others => '0');
- FL_WE_N <= '1';
- FL_RST_N <= '0';
- FL_OE_N <= '1';
- FL_CE_N <= '1';
- TDO <= '0';
- I2C_SCLK <= '0';
- AUD_DACDAT <= '0';
- AUD_XCK <= '0';
- -- Set all bidirectional ports to tri-state
- DRAM_DQ <= (others => 'Z');
- FL_DQ <= (others => 'Z');
- I2C_SDAT <= 'Z';
- AUD_ADCLRCK <= 'Z';
- AUD_DACLRCK <= 'Z';
- AUD_BCLK <= 'Z';
- GPIO_0 <= (others => 'Z');
- GPIO_1 <= (others => 'Z');
-end;
\ No newline at end of file
Index: DE1/z80soc.pof
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: DE1/z80soc.pof
===================================================================
--- DE1/z80soc.pof (revision 8)
+++ DE1/z80soc.pof (nonexistent)
DE1/z80soc.pof
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property