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Rev 4 → Rev 7
/spectrum_48k_for_digilent_spartan3_starter_kit/ram.v
22,17 → 22,17
/* |
This module generates a high level on "isfalling" when "a" changes from high to low. |
*/ |
module getfedge ( |
input clk, |
input a, |
output isfalling |
); |
|
reg sh = 1'b1; |
assign isfalling = sh & ~a; |
always @(posedge clk) |
sh <= a; |
endmodule |
module getfedge ( |
input clk, |
input a, |
output isfalling |
); |
|
reg sh = 1'b1; |
assign isfalling = sh & ~a; |
always @(posedge clk) |
sh <= a; |
endmodule |
|
|
/* |
52,45 → 52,45
activated at the same edge) |
|
*/ |
module ram_controller ( |
input clk, |
// Bank 1 (VRAM) |
input [15:0] a1, |
input cs1_n, |
input oe1_n, |
input we1_n, |
input [7:0] din1, |
output [7:0] dout1, |
// Bank 2 (upper RAM) |
input [15:0] a2, |
input cs2_n, |
input oe2_n, |
input we2_n, |
input [7:0] din2, |
output [7:0] dout2, |
// Outputs to actual SRAM on board |
output [17:0] sa, |
inout [7:0] sd, |
output sramce, |
output sramub, |
output sramlb, |
output sramoe, |
output sramwe |
); |
|
module ram_controller ( |
input clk, |
// Bank 1 (VRAM) |
input [15:0] a1, |
input cs1_n, |
input oe1_n, |
input we1_n, |
input [7:0] din1, |
output [7:0] dout1, |
// Bank 2 (upper RAM) |
input [15:0] a2, |
input cs2_n, |
input oe2_n, |
input we2_n, |
input [7:0] din2, |
output [7:0] dout2, |
// Outputs to actual SRAM on board |
output [17:0] sa, |
inout [7:0] sd, |
output sramce, |
output sramub, |
output sramlb, |
output sramoe, |
output sramwe |
); |
|
// Permanently enable SRAM and set it to use only LSB |
assign sramub = 1; |
assign sramub = 1; |
assign sramlb = 0; |
assign sramce = 0; |
assign sramoe = 0; |
|
reg rsramwe = 1; |
assign sramwe = rsramwe; |
|
reg [17:0] rsa; |
reg [7:0] rsd; |
assign sa = rsa; |
assign sd = rsd; |
reg rsramwe = 1; |
assign sramwe = rsramwe; |
|
reg [17:0] rsa; |
reg [7:0] rsd; |
assign sa = rsa; |
assign sd = rsd; |
|
// set when there has been a high to low transition in the corresponding signal |
wire bank1read, bank1write, bank2read, bank2write; |